A laser array structure and its fabrication method

Abstract

This invention discloses a laser array structure and its fabrication method. The structure includes m laser array units, each laser array unit comprising: an insulating substrate; an epitaxial layer located on one side surface of the insulating substrate, with n steps arranged at predetermined intervals along a first direction; each step includes a first surface and a second surface, with an N-contact electrode disposed on the first surface and a P-contact electrode disposed on the second surface; along the first direction, the N-contact electrodes and P-contact electrodes are arranged sequentially, with the (n-1)th P-contact electrode electrically connected to the nth N-contact electrode; along a second direction, the first column of the m N-contact electrodes is connected together, and the nth column of the m P-contact electrodes is connected together, the second direction being perpendicular to the first direction, the first direction being the long axis direction of the epitaxial layer, n>1, m≥1 or n≥1, m>1, where m and n are both positive integers, to realize a high-power laser chip at the chip level.

Description

Technical Field

[0001] This invention relates to the field of laser technology, and in particular to a laser array structure and its fabrication method. Background Technology

[0002] Existing VCSEL laser chips are relatively small, with mainstream chips on the market ranging from 1-2mm in size and 3-10W in power. To achieve higher power levels, such as hundreds of kilowatts, serial-parallel interconnection of the chips needs to be implemented at the packaging level. The current limitations and shortcomings are as follows:

[0003] The packaging process is significantly more complex because it requires handling multiple chips and designing complex packaging substrates to achieve series and parallel connections between them. The yield rate of the packaging process directly impacts the final yield rate of the high-power packaged array. It also requires more additional gold wires or wiring interconnects, increasing cost and process complexity. Furthermore, the extra gold wires introduce additional inductance, reducing the product's response rate and hindering applications that prioritize high response speeds. Large array packages have lower integration, requiring more space for interconnection between each chip, reducing optical density, and causing dark spots between close-range beams, thus limiting the application range of high-power VCSEL laser chips. Achieving high power through series and parallel connections at the packaging level presents additional challenges for market applications. Driver design requires calculations and matching based on individual chip parameters, and it also places higher demands on the multi-chip packaging capabilities. Summary of the Invention

[0004] This invention provides a laser array structure and its fabrication method to realize high-power laser chips at the chip level.

[0005] To achieve the above objectives, one embodiment of the present invention proposes a laser array structure, comprising:

[0006] m laser array units, each laser array unit including: an insulating substrate;

[0007] An epitaxial layer is located on one side surface of the insulating substrate, and along a first direction, the epitaxial layer is arranged with n steps at predetermined intervals;

[0008] Each step includes a first surface and a second surface, wherein an N-contact electrode is disposed on the first surface and a P-contact electrode is disposed on the second surface;

[0009] Wherein, along the first direction, the n N-contact electrodes and the n P-contact electrodes are arranged alternately in sequence, and the (n-1)th P-contact electrode is electrically connected to the nth N-contact electrode;

[0010] Along the second direction, the first column of N-contact electrodes in the m laser array units are all connected together, and the nth column of P-contact electrodes in the m laser array units are all connected together. The second direction is perpendicular to the first direction, and the first direction is the long axis direction of the epitaxial layer. n>1, m≥1 or n≥1, m>1, where m and n are both positive integers.

[0011] According to the laser array structure proposed in the embodiments of the present invention, an epitaxial layer is formed on an insulating substrate, and n steps are arranged at a predetermined distance on the epitaxial layer. N-contact electrodes are provided on the first surface of each step, and P-contact electrodes are provided on the second surface of each step. The n N-contact electrodes and n P-contact electrodes are arranged alternately along a first direction, and the (n-1)th P-contact electrode is electrically connected to the nth N-contact electrode. Along a second direction, the first column of m N-contact electrodes is connected together, and the nth column of m P-contact electrodes is connected together. The second direction is perpendicular to the first direction, and the first direction is the long axis direction of the epitaxial layer. This enables the realization of a high-power laser chip at the chip level, improves the yield and high-speed response performance of such a high-power laser array, improves the spot quality, reduces the difficulty of realizing the laser array at the packaging level, and facilitates subsequent market use.

[0012] Optionally, along the second direction, at least one of the remaining n-1 columns of N-contact electrodes in the m laser array units are connected together, and / or each P-contact electrode electrically connected to at least one column of the N-contact electrodes is connected together, the second direction being perpendicular to the first direction, the first direction being the long axis direction of the epitaxial layer, n>1, m>1, and m and n are both positive integers.

[0013] Optionally, in the laser array structure, each laser array unit further includes: a bonding layer, the bonding layer being located on one side surface of the insulating substrate, and the epitaxial layer being located on the side surface of the bonding layer opposite to the insulating substrate.

[0014] Optionally, the vertical projection of the first surface on the insulating substrate is smaller than the vertical projection of the second surface on the insulating substrate.

[0015] Optionally, each P-contact electrode is provided with multiple arrayed through holes, each through hole being used to emit light emitted from the light-emitting point of the laser chip.

[0016] Optionally, a first insulating passivation region is formed between one side of the nth N-contact electrode and one side of the nth P-contact electrode.

[0017] Optionally, a second insulating passivation region is formed between the other side of the (n-1)th P contact electrode and the other side of the nth N contact electrode.

[0018] Optionally, in the laser array structure, each laser array unit further includes: a third insulating passivation region, the third insulating passivation region being located on the surface of each P-contact electrode adjacent to the second insulating passivation region on the side away from the epitaxial layer, the vertical projection area of ​​the third insulating passivation region on the P-contact electrode being smaller than the area of ​​the P-contact electrode, and not overlapping with the vertical projection of the via on the P-contact electrode. Optionally, in the laser array structure, each laser array unit further includes: n first conductive metal layers and n second conductive metal layers, each first conductive metal layer filling between the first insulating passivation region and the second insulating passivation region; each second conductive metal layer filling between the second insulating passivation region and the third insulating passivation region, wherein the (n-1)th second conductive metal layer is electrically connected to the nth first conductive metal layer.

[0019] To achieve the above objectives, another embodiment of the present invention proposes a method for fabricating a laser array structure, wherein the laser array structure comprises m laser array units, and includes the following steps:

[0020] Forming an insulating substrate;

[0021] An epitaxial layer is formed on one side surface of the insulating substrate;

[0022] Along a first direction, n steps are arranged at preset distances on the epitaxial layer, wherein each step includes a first surface and a second surface;

[0023] An N-contact electrode is formed on the first surface;

[0024] A P-contact electrode is formed on the second surface;

[0025] The (n-1)th P-contact electrode is electrically connected to the nth N-contact electrode;

[0026] Along the second direction, the first column of the m N-contact electrodes is connected together, and the nth column of the m P-contact electrodes is connected together. The second direction is perpendicular to the first direction, and the first direction is the long axis direction of the epitaxial layer. n>1, m≥1 or n≥1, m>1, where m and n are both positive integers.

[0027] According to the method for fabricating a laser array structure proposed in the embodiments of the present invention, firstly, an insulating substrate is formed; then, an epitaxial layer is formed on one side surface of the insulating substrate; then, along a first direction, n steps are arranged at a predetermined distance on the epitaxial layer, wherein each step includes a first surface and a second surface; then, an N-contact electrode is formed on the first surface; and a P-contact electrode is formed on the second surface; then, the (n-1)th P-contact electrode is electrically connected to the nth N-contact electrode; then, along a second direction, the first column of m N-contact electrodes is connected together, and the nth column of m P-contact electrodes is connected together, wherein the second direction is perpendicular to the first direction, and the first direction is the long axis direction of the epitaxial layer, thereby realizing a high-power laser chip at the chip level, improving the yield and high-speed response performance of such a high-power laser array, improving the spot quality, reducing the difficulty of realizing the laser array at the packaging level, and facilitating subsequent market use.

[0028] Optionally, the electrical connection between the (n-1)th P contact electrode and the nth N contact electrode includes:

[0029] A first insulating passivation region is formed between one side of the nth N-contact electrode and one side of the nth P-contact electrode;

[0030] A second insulating passivation region is formed between the other side of the (n-1)th P contact electrode and the other side of the nth N contact electrode;

[0031] A third insulating passivation region is formed on the surface of each P-contact electrode on the side opposite to the epitaxial layer;

[0032] A first conductive metal layer is filled between the first insulating passivation region and the second insulating passivation region, and a second conductive metal layer is filled between the second insulating passivation region and the third insulating passivation region, wherein the (n-1)th second conductive metal layer is electrically connected to the nth first conductive metal layer.

[0033] Optionally, before arranging n steps at preset distances on the epitaxial layer, the method further includes:

[0034] The epitaxial layer is deposited on the first substrate;

[0035] The epitaxial layer is transferred onto the second substrate;

[0036] Strip the first substrate;

[0037] A bonding layer is formed on the epitaxial layer;

[0038] The bonding layer and the epitaxial layer are transferred onto the insulating substrate, and the second substrate is peeled off, wherein the bonding layer is adjacent to the insulating substrate;

[0039] Each laser chip is made independent.

[0040] Compared with existing technologies, this application has the following beneficial effects: It increases the power level of lasers, expanding their application range, such as high-power long-range radar; it improves the yield of laser arrays by utilizing the high yield of chip manufacturing processes, i.e., improving the yield of laser arrays at the chip manufacturing level. Since the automation level of chip manufacturing processes is significantly higher than that of packaging processes, the yield of chip manufacturing can be significantly improved, and defects can be significantly reduced; laser arrays manufactured at the chip level can significantly reduce non-light-emitting areas between chips, increase the density of light-emitting areas on the chips, increase optical density, and significantly improve dark spots between close-range light spots. Achieving series and parallel connection of chips at the chip manufacturing level allows for the customization of high-power arrays that directly meet market needs based on customers' real-time voltage and current drive requirements, and significantly reduces the requirements for subsequent packaging capabilities, facilitating market packaging and use. Furthermore, regarding the substrate secondary transfer scheme, the secondary transfer epitaxial layer method proposed in this invention can effectively alleviate the thermal stress introduced during the growth of the epitaxial layer on the first substrate, reduce the non-radiative recombination centers introduced by stress in the light-emitting area, reduce non-radiative recombination of charge carriers, enhance the luminescent recombination effect, and effectively improve the photoelectric conversion efficiency of the laser. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of a laser array structure according to an embodiment of the present invention;

[0042] Figure 2 This is a top view of a laser array structure according to an embodiment of the present invention;

[0043] Figure 3 This is a top view of a laser array structure according to another embodiment of the present invention;

[0044] Figure 4 This is a schematic diagram of a laser array structure according to another embodiment of the present invention;

[0045] Figure 5 This is a schematic diagram of a laser array structure according to another embodiment of the present invention;

[0046] Figure 6 This is a schematic diagram of a laser array structure according to another embodiment of the present invention;

[0047] Figure 7 This is a schematic diagram of a laser array structure according to another embodiment of the present invention;

[0048] Figure 8 This is a flowchart of a method for fabricating a laser array structure according to an embodiment of the present invention;

[0049] Figure 9This is a flowchart of a method for fabricating a laser array structure according to an embodiment of the present invention;

[0050] Figure 10 This is a flowchart of a method for fabricating a laser array structure according to another embodiment of the present invention;

[0051] Figures 11 to 21 This is a process step diagram of a method for fabricating a laser array structure according to a specific embodiment of the present invention. Detailed Implementation

[0052] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0053] The laser array structure and its fabrication method proposed in the embodiments of the present invention will be described below with reference to the accompanying drawings. Figure 1 This is a schematic diagram of the laser array structure according to an embodiment of the present invention. Figure 2 This is a top view of a laser array structure according to an embodiment of the present invention. Figure 1-2 As shown, the laser array structure 100 includes:

[0054] m laser array units 101, each laser array unit 101 including: an insulating substrate 102;

[0055] An epitaxial layer 103 is located on one side surface of an insulating substrate 102. Along a first direction, n steps 104 are arranged in the epitaxial layer 103 at preset distances. The preset distance is the width of a single laser chip and can be set according to actual conditions.

[0056] Each step 104 includes a first surface 104A and a second surface 104B. An N-contact electrode 105 is disposed on the first surface 104A and a P-contact electrode 106 is disposed on the second surface 104B.

[0057] In this configuration, along the first direction, n N-contact electrodes 105 and n P-contact electrodes 106 are arranged alternately in sequence, and the (n-1)th P-contact electrode 106 is electrically connected to the nth N-contact electrode 105.

[0058] Along the second direction, the first column of N contact electrodes 105 in m laser array units 101 are connected together, and the nth column of P contact electrodes 106 in m laser array units 101 are connected together. The second direction is perpendicular to the first direction, which is the long axis direction of the epitaxial layer. n>1, m≥1 or n≥1, m>1, where m and n are both positive integers.

[0059] Optionally, along the second direction, at least one of the remaining n-1 columns of N-contact electrodes 105 in the m laser array units 101 are connected together, and / or each P-contact electrode 106 electrically connected to the at least one column of N-contact electrodes is connected together. The second direction is perpendicular to the first direction, which is the long axis direction of the epitaxial layer, where n>1, m>1, and m and n are both positive integers. The following explanation uses n=2 and m=2 as an example.

[0060] Combination Figure 1 and Figure 2 As shown, Figure 1 yes Figure 2 A cross-sectional view along the A-A' direction. Each laser array unit includes two laser chips. An epitaxial layer 103 is formed on an insulating substrate 102 along a first direction, and two steps 104 are formed on the epitaxial layer 103. An N-contact electrode 105 is disposed on the first surface 104A of each step 104, and a P-contact electrode 106 is disposed on the second surface 104B of each step 104. In the first direction, the P-contact electrode 106 of the preceding laser chip is electrically connected to the N-contact electrode 105 of the following laser chip, i.e., the two laser chips are connected in series. The N-contact electrode 105 of the preceding laser chip serves as the main N-electrode 107 of the laser array unit, and the P-contact electrode 106 of the following laser chip serves as the main P-electrode 108 of the laser array unit.

[0061] Along the second direction, such as Figure 2 As shown, the two aforementioned laser array units are arranged sequentially. The two main N-electrodes are connected together, serving as the main N-electrodes of the entire laser array structure, and the two main P-electrodes are connected together, serving as the main P-electrodes of the entire laser array structure. When one of the series-connected laser chips is not working, all the laser chips in the row connected in series with it will also be inactive.

[0062] Along the second direction, such as Figure 3 As shown, it is similar to Figure 2 The difference lies in the following: the two aforementioned laser array units are arranged sequentially, the two N-contact electrodes in the second column are connected together, and the two P-contact electrodes electrically connected to the N-contact electrodes in the second column are also connected together. The failure of any one laser chip does not affect the operation of the other laser chips.

[0063] It should be noted that the insulating substrate can be gallium arsenide, aluminum nitride, sapphire, silicon carbide, or unintentionally doped silicon substrate.

[0064] The epitaxial layer is mainly composed of GaAs, AlGaAs, InP, and GaN materials.

[0065] The N-contact and P-contact electrodes of the laser chip are mainly TiPtAu, AuGeNiAu electrodes.

[0066] Optionally, such as Figure 4 As shown, in the laser array structure 100, each laser array unit 101 further includes a bonding layer 109, which is located on one side surface of the insulating substrate 102, and an epitaxial layer 103 is located on the side surface of the bonding layer 109 facing away from the insulating substrate 102. The bonding layer 109 facilitates the adhesion of the epitaxial layer 103 to the insulating substrate 102.

[0067] Optionally, such as Figure 1 and Figure 4 As shown, the vertical projection of the first surface 104A onto the insulating substrate 102 is smaller than the vertical projection of the second surface 104B onto the insulating substrate 102. That is, the area of ​​the N contact electrode 105 is smaller than the area of ​​the P contact electrode.

[0068] Optionally, such as Figure 5 As shown, a first insulating passivation region 110 is formed between one side of the nth N-contact electrode 105 and one side of the nth P-contact electrode 106. The first insulating passivation region 110 is provided to isolate the N-contact electrodes and P-contact electrodes in a single laser chip.

[0069] Optionally, such as Figure 5 As shown, a second insulating passivation region 111 is formed between the other side of the (n-1)th P contact electrode 106 and the other side of the nth N contact electrode 105. The second insulating passivation region 111 is provided to isolate the P contact electrode 106 in the previous laser chip from the N contact electrode 105 in the next laser chip.

[0070] Optionally, such as Figure 5 As shown, in the laser array structure 100, each laser array unit 101 further includes a third insulating passivation region 112. The third insulating passivation region 112 is located on the surface of each P contact electrode 106 on the side away from the epitaxial layer 103. The vertical projection area of ​​the third insulating passivation region 112 on the P contact electrode 106 is smaller than the area of ​​the P contact electrode 106.

[0071] The insulating passivation region can be made of insulating materials such as aluminum nitride, silicon nitride, and silicon oxide.

[0072] Optionally, such as Figure 6As shown, in the laser array structure 100, each laser array unit 101 further includes: n first conductive metal layers 113 and n second conductive metal layers 114, each first conductive metal layer 113 filling between the first insulating passivation region 110 and the second insulating passivation region 111; each second conductive metal layer 114 filling between the second insulating passivation region 111 and the third insulating passivation region 112, wherein the (n-1)th second conductive metal layer 113 and the nth first conductive metal layer 114 are electrically connected.

[0073] In other words, the N-contact electrodes and P-contact electrodes of two adjacent laser chips are electrically connected. A first conductive metal layer 113 is arranged on the N-contact electrode, and a second conductive metal layer 114 is arranged on the P-contact electrode. The first conductive metal layer 113 and the second conductive metal layer 114 are electrically connected, thereby realizing the series connection of two adjacent laser chips.

[0074] Optionally, such as Figure 7 As shown, each P-contact electrode 106 is provided with a plurality of arrayed vias 115, each via 115 being used to emit light emitted from the light-emitting point of the laser chip. Furthermore, a third insulating passivation region 112 is located on the surface of each P-contact electrode 106 adjacent to the second insulating passivation region, on the side facing away from the epitaxial layer 103. The vertical projection area of ​​the third insulating passivation region 112 on the P-contact electrode 106 is smaller than the area of ​​the P-contact electrode 106, and does not overlap with the vertical projection of the vias 115 on the P-contact electrode 106.

[0075] It should be noted that each laser chip includes multiple light-emitting points, and the number of through holes on each P contact electrode 106 corresponds to the number of multiple light-emitting points.

[0076] In summary, the laser array structure proposed in this embodiment of the invention, by forming an epitaxial layer on an insulating substrate and arranging n steps at predetermined intervals on the epitaxial layer, provides N-contact electrodes on the first surface of each step and P-contact electrodes on the second surface of each step, wherein the n N-contact electrodes and n P-contact electrodes are arranged sequentially and alternately along a first direction, and the (n-1)th P-contact electrode is electrically connected to the nth N-contact electrode; along a second direction, the first column of m N-contact electrodes is connected together, and the nth column of m P-contact electrodes is connected together, the second direction is perpendicular to the first direction, the first direction is the long axis direction of the epitaxial layer, n>1, m≥1 or n≥1, m>1, thereby realizing a high-power laser chip at the chip level, improving the yield and high-speed response performance of such a high-power laser array, improving the spot quality, reducing the difficulty of realizing the laser array at the packaging level, and facilitating subsequent market use.

[0077] Figure 8This is a flowchart illustrating a method for fabricating a laser array structure according to an embodiment of the present invention. The laser array structure includes m laser array units, such as... Figure 8 As shown, the fabrication method for each laser array unit includes the following steps:

[0078] S101, forming an insulating substrate;

[0079] S102, an epitaxial layer is formed on one side surface of the insulating substrate;

[0080] The epitaxial layers include: a highly reflective n-DBR layer, a multi-quantum-well layer, and a P-DBR layer.

[0081] It should be noted that an epitaxial layer can be deposited on an insulating substrate using organic chemical vapor deposition (MOCVD) technology.

[0082] S103, along the first direction, n steps are arranged at preset distances on the epitaxial layer, wherein each step includes a first surface and a second surface;

[0083] It should be noted that each independent epitaxial layer can be etched into the N-shaped doped layer through an etching process, forming a step.

[0084] S104, an N-contact electrode is formed on the first surface;

[0085] An N-type contact electrode is formed on the surface of the N-type doped layer by a coating process.

[0086] S105, a P-contact electrode is formed on the second surface;

[0087] Laser emission points are formed through oxidation or ion implantation processes, and P-contact electrodes are formed on the second surface (i.e., the surface of the P-type doped layer) through a coating process.

[0088] S106, the (n-1)th P contact electrode is electrically connected to the nth N contact electrode;

[0089] S107, along the second direction, the first column of m N contact electrodes is connected together, and the nth column of m P contact electrodes is connected together. The second direction is perpendicular to the first direction, and the first direction is the long axis direction of the epitaxial layer. n>1, m≥1 or n≥1, m>1, where m and n are both positive integers.

[0090] On the aforementioned structural surface, a passivation insulating film is deposited, and the areas where the first and second conductive metal layers need to be plated are exposed through an etching process. Finally, laser chips are connected in series through a metal plating process to form a laser array unit. The first column N-contact electrodes of multiple laser array units are connected together to form the N-electrode of the entire laser chip, and the nth column P-contact electrodes of multiple laser array units are connected together to form the P-electrode of the entire laser chip.

[0091] Optionally, such as Figure 9 As shown, step S106 includes: the electrical connection between the (n-1)th P contact electrode and the nth N contact electrode includes:

[0092] S1061, a first insulating passivation region is formed between one side of the nth N contact electrode and one side of the nth P contact electrode.

[0093] S1062, a second insulating passivation region is formed between the other side of the (n-1)th P contact electrode and the other side of the nth N contact electrode;

[0094] S1063, a third insulating passivation region is formed on the surface of each P contact electrode on the side away from the epitaxial layer;

[0095] S1064, a first conductive metal layer is filled between the first insulating passivation region and the second insulating passivation region, and a second conductive metal layer is filled between the second insulating passivation region and the third insulating passivation region, wherein the (n-1)th second conductive metal layer is electrically connected to the nth first conductive metal layer.

[0096] Optionally, such as Figure 10 As shown, before step S103, the method further includes: that is, before arranging n steps at preset distances on the epitaxial layer, the method further includes:

[0097] S108, deposit an epitaxial layer on the first substrate;

[0098] The first substrate is a gallium arsenide substrate. An epitaxial layer can be deposited on the gallium arsenide substrate using a metal-organic chemical vapor deposition (MOCVD) process.

[0099] S109, the epitaxial layer is transferred onto the second substrate;

[0100] The second substrate is a transition substrate. The epitaxial layer can be transferred onto the transition substrate using an organic bonding process. Transition substrates are mainly made of aluminum nitride, sapphire, silicon carbide, or undoped silicon.

[0101] S110, peel off the first substrate;

[0102] Gallium arsenide substrates can be removed using wet methods, dry methods, or laser lift-off techniques.

[0103] S111, forming a bonding layer on the epitaxial layer;

[0104] S112, the bonding layer and the epitaxial layer are transferred onto the insulating substrate, wherein the bonding layer is adjacent to the insulating substrate, and the second substrate is peeled off;

[0105] Then, the intermediate is transferred to the insulating substrate using wafer Au-Au or AuSn bonding processes for chip manufacturing, and the transition substrate (i.e., the second substrate) is removed.

[0106] S113, which makes each laser chip independent.

[0107] Each laser chip is made independent through an etching process.

[0108] In the above embodiments, the laser chip can be a VCSEL laser chip. It mainly achieves the series and parallel connection of multiple VCSEL chips at the chip level through chip technology, so as to make up for the fact that the power of a single VCSEL cannot reach hundreds of kilowatts. Its working principle is the same as that of a single laser. It mainly introduces positive and negative currents into the chip through positive and negative electrodes, and then causes the positive load carriers to undergo stimulated emission recombination and light emission. The laser output is further increased through N-DBR and P-DBR resonant cavities.

[0109] The high-power VCSEL chip of the chip level of this invention is mainly used in fields such as lidar, solid-state and fiber laser pump sources, medical aesthetics, industrial applications, and scientific research applications.

[0110] Specifically, such as Figure 11-21 The diagram shows a flowchart of a specific embodiment of a laser array fabrication method. Where m = 1 and n = 3.

[0111] S201, an epitaxial layer 201 is deposited on a gallium arsenide substrate 200.

[0112] S202, the epitaxial layer 201 is transferred to the transition substrate 202.

[0113] S203, stripping gallium arsenide substrate 200.

[0114] S204, forming a bonding layer 203 on the epitaxial layer 201.

[0115] S205, the epitaxial layer 201 is transferred to the insulating substrate 204 through the bonding layer 203, and the transition substrate 202 is peeled off.

[0116] S206 makes each laser chip independent.

[0117] S207 forms various steps.

[0118] S208 forms the P-contact electrode 205.

[0119] S209 forms the N-contact electrode 206.

[0120] S210, deposited passivated insulating film.

[0121] S211 connects multiple laser chips in series and forms the main N electrode 208 and the main P electrode 207.

[0122] In summary, the method for fabricating a laser array structure according to the embodiments of the present invention firstly forms an insulating substrate; then, an epitaxial layer is formed on one side surface of the insulating substrate; next, n steps are arranged at predetermined intervals along a first direction on the epitaxial layer, wherein each step includes a first surface and a second surface; then, an N-contact electrode is formed on the first surface; and a P-contact electrode is formed on the second surface; then, the (n-1)th P-contact electrode is electrically connected to the nth N-contact electrode; then, along a second direction, the first column of m N-contact electrodes is connected together, and the nth column of m P-contact electrodes is connected together, wherein the second direction is perpendicular to the first direction, and the first direction is the long axis direction of the epitaxial layer. This allows for the realization of a high-power laser chip at the chip level, improving the yield and high-speed response performance of such a high-power laser array, improving the beam quality, reducing the difficulty of realizing the laser array at the packaging level, and facilitating subsequent market use.

[0123] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A laser array structure, characterized in that, include: m laser array units, each laser array unit comprising: an insulating substrate; An epitaxial layer is located on one side surface of the insulating substrate, and along a first direction, the epitaxial layer is arranged with n steps at predetermined intervals; Each step includes a first surface and a second surface, wherein an N-contact electrode is disposed on the first surface and a P-contact electrode is disposed on the second surface; In this configuration, along the first direction, n N-contact electrodes and n P-contact electrodes are arranged alternately in sequence, the (n-1)th P-contact electrode is electrically connected to the nth N-contact electrode, and the preceding laser chip is connected in series with the following laser chip. Along the second direction, the first column of N-contact electrodes in the m laser array units are all connected together, and the nth column of P-contact electrodes in the m laser array units are all connected together. The second direction is perpendicular to the first direction, and the first direction is the major axis direction of the epitaxial layer. Wherein, n>1, m>1, and m and n are both positive integers. Along the second direction, at least one of the remaining n-1 columns of N-contact electrodes in the m laser array units are connected together, and / or each P-contact electrode electrically connected to the at least one column of said N-contact electrodes is connected together. The second direction is perpendicular to the first direction, which is the long axis direction of the epitaxial layer. A first insulating passivation region is formed between one side of the nth N-contact electrode and one side of the nth P-contact electrode; A second insulating passivation region is formed between the other side of the (n-1)th P contact electrode and the other side of the nth N contact electrode; Each of the P contact electrodes is provided with a plurality of through holes arranged in an array; The third insulating passivation region is located on the surface of each P contact electrode adjacent to the second insulating passivation region on the side away from the epitaxial layer. The vertical projection area of ​​the third insulating passivation region on the P contact electrode is smaller than the area of ​​the P contact electrode and does not overlap with the vertical projection of the via on the P contact electrode. There are n first conductive metal layers and n second conductive metal layers, each of the first conductive metal layers filling the space between the first insulating passivation region and the second insulating passivation region; each of the second conductive metal layers filling the space between the second insulating passivation region and the third insulating passivation region, wherein the (n-1)th second conductive metal layer is electrically connected to the nth first conductive metal layer.

2. The laser array structure according to claim 1, characterized in that, Also includes: A bonding layer is located on one side surface of the insulating substrate, and an epitaxial layer is located on the side surface of the bonding layer opposite to the insulating substrate.

3. The laser array structure according to claim 1, characterized in that, The vertical projection of the first surface onto the insulating substrate is smaller than the vertical projection of the second surface onto the insulating substrate.

4. The laser array structure according to claim 1, characterized in that, Each of the vias is used to emit light emitted from the light-emitting point of the laser chip.

5. A method for fabricating a laser array structure, characterized in that, The laser array structure comprises m laser array units, and includes the following steps: Forming an insulating substrate; An epitaxial layer is formed on one side surface of the insulating substrate; Along a first direction, n steps are arranged at preset distances on the epitaxial layer, wherein each step includes a first surface and a second surface; An N-contact electrode is formed on the first surface; A P-contact electrode is formed on the second surface; The (n-1)th P-contact electrode is electrically connected to the nth N-contact electrode; the preceding laser chip is connected in series with the following laser chip; Along the second direction, the first column of the m N-contact electrodes is connected together, and the nth column of the m P-contact electrodes is connected together. The second direction is perpendicular to the first direction, and the first direction is the major axis direction of the epitaxial layer. Where n>1, m≥1, and m and n are both positive integers. The electrical connection between the (n-1)th P contact electrode and the nth N contact electrode includes: A first insulating passivation region is formed between one side of the nth N-contact electrode and one side of the nth P-contact electrode; A second insulating passivation region is formed between the other side of the (n-1)th P contact electrode and the other side of the nth N contact electrode; A third insulating passivation region is formed on the surface of each P-contact electrode on the side opposite to the epitaxial layer; A first conductive metal layer is filled between the first insulating passivation region and the second insulating passivation region, and a second conductive metal layer is filled between the second insulating passivation region and the third insulating passivation region, wherein the (n-1)th second conductive metal layer is electrically connected to the nth first conductive metal layer.

6. The method for fabricating a laser array structure according to claim 5, characterized in that, Before arranging n steps at preset distances on the epitaxial layer, the following is also included: The epitaxial layer is deposited on the first substrate; The epitaxial layer is transferred onto the second substrate; Strip the first substrate; A bonding layer is formed on the epitaxial layer; The bonding layer and the epitaxial layer are transferred onto the insulating substrate, wherein the bonding layer is adjacent to the insulating substrate, and the second substrate is peeled off; Each laser chip is made independent.

Images