Hash algorithm and circuits, electronic equipment

Abstract

The present disclosure provides a hash algorithm circuit, hash algorithm, and electronic device. The hash algorithm circuit is used to reduce fixed-length parallel data. The reduced identifier can be used as an index reference, ID, address extension bit, message digest, and so on. The hash algorithm circuit features low power consumption and low cost, and can be integrated into digital circuits.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technology, and in particular to a hash algorithm, circuit, and electronic equipment. Background Art

[0002] A hash algorithm, also known as a hashing algorithm or a hashing algorithm, transforms an input of arbitrary length into an output of fixed length, known as a hash value. This conversion is a compression mapping; that is, the space of hash values ​​is typically much smaller than the space of inputs. Different inputs may hash to the same output, making it impossible to determine a unique input value from the hash value. Simply put, it's a function that compresses a message of arbitrary length into a message digest of a fixed length.

[0003] The hash algorithm (or hash algorithm) in the prior art is generally implemented using software, does not have physical isolation characteristics, and has the risk of being deciphered. Summary of the Invention

[0004] In view of this, the purpose of the present disclosure is to provide a hash algorithm, circuit, and electronic device.

[0005] Based on the above objectives, a first aspect of the present disclosure provides a hash algorithm circuit, comprising:

[0006] The input circuit unit is configured to: receive data to be processed;

[0007] at least one hash circuit unit electrically coupled to the input circuit unit, the hash circuit unit having a circuit structure arranged according to a preset hash algorithm and configured to: form the to-be-processed data passing through the hash circuit unit into target data; wherein the data length of the to-be-processed data is greater than the data length of the target data;

[0008] The output circuit unit is electrically coupled to at least one of the hash circuit units and is configured to output the target data.

[0009] In some embodiments, the preset hash algorithm is selected from at least one of the following methods: direct addressing method, digital analysis method, square median method, folding method, random number method, and division remainder method.

[0010] In some embodiments, the hash algorithm circuit includes a first hash circuit unit and a second hash circuit unit;

[0011] The first hash circuit unit is electrically coupled to the input circuit unit, has a circuit structure arranged according to a first preset hash algorithm, and is configured to: form the data to be processed into intermediate data; wherein the data length of the data to be processed is greater than the data length of the intermediate data;

[0012] The second hash circuit unit is electrically coupled to the first hash circuit unit, has a circuit structure arranged according to a second preset hash algorithm, and is configured to: form the intermediate data into target data; wherein the data length of the intermediate data is greater than the data length of the target data.

[0013] In some embodiments, the data to be processed is divided into n sequences;

[0014] The first hash circuit unit is configured to: generate k sequences of intermediate data according to the first preset hash algorithm through its circuit structure, wherein n and k are both natural numbers, and n>k;

[0015] The second hash circuit unit is configured to: transform the k sequences into target data having u sequences according to the second preset hash algorithm through its circuit structure, where u is a natural number and k>u.

[0016] In some embodiments, the first hash circuit unit includes at least one of an exclusive OR circuit, a sum circuit, and a shift circuit.

[0017] In some embodiments, the second hash circuit unit includes at least one of an exclusive OR circuit, a sum circuit, and a shift circuit.

[0018] In some embodiments, the number of the XOR circuits and the summing circuits is determined according to the difference between the numbers of n and u.

[0019] In some embodiments, the data to be processed is divided into 8 sequences; the first hash circuit unit includes:

[0020] a first XOR circuit configured to perform an XOR operation on the first sequence and the second sequence of the data to be processed to form a second intermediate sequence of the intermediate data;

[0021] a first summing circuit configured to perform a summing operation on the third sequence and the fourth sequence of the data to be processed to form a fifth intermediate sequence of the intermediate data;

[0022] a first left shift circuit, configured to left shift the fifth sequence of data to be processed to form a fourth intermediate sequence of intermediate data;

[0023] a second XOR circuit configured to perform an XOR operation on the sixth sequence and the eighth sequence of the data to be processed to form a third intermediate sequence of the intermediate data;

[0024] The first right shift circuit is configured to right shift the seventh sequence of the to-be-processed data to form a first intermediate sequence of the intermediate data.

[0025] In some embodiments, the second hash circuit unit includes:

[0026] a third XOR circuit, electrically coupled to the first right shift circuit and the first XOR circuit, and configured to perform an XOR operation on the first intermediate sequence and the second intermediate sequence to form a first temporary sequence;

[0027] a second summing circuit electrically coupled to the second XOR circuit and the first left shift circuit, and configured to perform a summing operation on the third intermediate sequence and the fourth intermediate sequence to form a second temporary sequence;

[0028] a second right shift circuit electrically coupled to the second summing circuit and configured to right shift the second temporary sequence by a first predetermined number of bits to form a third temporary sequence;

[0029] a second left shift circuit electrically coupled to the first summing circuit and configured to left-shift the fifth intermediate sequence by a second predetermined number of bits to form a fourth temporary sequence;

[0030] a fourth XOR circuit, electrically coupled to the third XOR circuit and the second left shift circuit, and configured to perform an XOR operation on the first temporary sequence and a fourth temporary sequence to form a fifth temporary sequence;

[0031] The fifth XOR circuit is electrically coupled to the fourth XOR circuit and the second right shift circuit respectively, and is configured to perform an XOR operation on the third temporary sequence and the fifth temporary sequence to form the target data.

[0032] A second aspect of the present disclosure provides a hash algorithm implemented using a hash algorithm circuit, the hash algorithm circuit comprising an input circuit unit, at least one hash circuit unit, and an output circuit unit electrically coupled in sequence, the hash algorithm comprising:

[0033] receiving data to be processed by utilizing the input circuit unit;

[0034] Using the at least one hash circuit unit, the data to be processed that has passed through the hash circuit unit is transformed into target data according to a preset hash algorithm; wherein the data length of the data to be processed is greater than the data length of the target data;

[0035] The target data is outputted using the output circuit unit.

[0036] In some embodiments, the preset hash algorithm is selected from at least one of the following methods: direct addressing method, digital analysis method, square median method, folding method, random number method, and division remainder method.

[0037] In some embodiments, the hash algorithm circuit includes a first hash circuit unit electrically coupled to the input circuit unit and a second hash circuit unit electrically coupled to the first hash circuit unit; the hash algorithm further includes:

[0038] Using the first hash circuit unit, the data to be processed is converted into intermediate data according to a first preset hash algorithm; wherein the data length of the data to be processed is greater than the data length of the intermediate data;

[0039] The second hash circuit unit is used to transform the intermediate data into target data according to a second preset hash algorithm; wherein the data length of the intermediate data is greater than the data length of the target data.

[0040] In some embodiments, the data to be processed is divided into n sequences; and the hash algorithm further includes:

[0041] Using the first hash circuit unit, through its circuit structure, the n sequences are transformed into intermediate data having k sequences according to the first preset hash algorithm, where n and k are both natural numbers, and n>k;

[0042] The second hash circuit unit is used to transform the k sequences into target data having u sequences according to the second preset hash algorithm through its circuit structure, wherein u is a natural number and k>u.

[0043] In some embodiments, the first hash circuit unit includes at least one of an exclusive OR circuit, a sum circuit, and a shift circuit.

[0044] In some embodiments, the second hash circuit unit includes at least one of an exclusive OR circuit, a sum circuit, and a shift circuit.

[0045] In some embodiments, the hashing algorithm further includes:

[0046] The number of the XOR circuits and the summing circuits is determined according to the difference between the numbers of n and u.

[0047] In some embodiments, the data to be processed is divided into 8 sequences; the first hash circuit unit includes a first XOR circuit, a first summation circuit, a first left shift circuit, a second XOR circuit and a first right shift circuit;

[0048] The hash algorithm also includes:

[0049] Using the first XOR circuit, performing an XOR operation on the first sequence of the to-be-processed data and the second sequence to form a second intermediate sequence of the intermediate data;

[0050] using the first summing circuit to sum the third sequence and the fourth sequence of the data to be processed to form a fifth intermediate sequence of the intermediate data;

[0051] Using the first left shift circuit, left-shifting the fifth sequence of data to be processed to form a fourth intermediate sequence of intermediate data;

[0052] Using a second XOR circuit, performing an XOR operation on the sixth sequence and the eighth sequence of the data to be processed to form a third intermediate sequence of the intermediate data;

[0053] The first right shift circuit is used to right shift the seventh sequence of the data to be processed to form a first intermediate sequence of the intermediate data.

[0054] In some embodiments, the second hash circuit unit includes a third XOR circuit, a second summing circuit, a second right shift circuit, a second left shift circuit, a fourth XOR circuit, and a fifth XOR circuit; the third XOR circuit is electrically coupled to the first right shift circuit and the first XOR circuit, respectively; the second summing circuit is electrically coupled to the second XOR circuit and the first left shift circuit, respectively; the second right shift circuit is electrically coupled to the second summing circuit; the second left shift circuit is electrically coupled to the first summing circuit; the fourth XOR circuit is electrically coupled to the third XOR circuit and the second left shift circuit, respectively; and the fifth XOR circuit is electrically coupled to the fourth XOR circuit and the second right shift circuit, respectively.

[0055] The hash algorithm also includes:

[0056] Using the third XOR circuit, performing an XOR operation on the first intermediate sequence and the second intermediate sequence to form a first temporary sequence;

[0057] using the second summing circuit to sum the third intermediate sequence and the fourth intermediate sequence to form a second temporary sequence;

[0058] Utilizing the second right shift circuit, right-shifting the second temporary sequence by a first predetermined number of bits to form a third temporary sequence;

[0059] Utilizing the second left shift circuit, shifting the fifth intermediate sequence left by a second predetermined number of bits to form a fourth temporary sequence;

[0060] Using the fourth XOR circuit, performing an XOR operation on the first temporary sequence and the fourth temporary sequence to form a fifth temporary sequence;

[0061] The fifth XOR circuit is used to perform an XOR operation on the third temporary sequence and the fifth temporary sequence to form the target data.

[0062] A third aspect of the present disclosure provides an electronic device, comprising the hash algorithm circuit described in the first aspect.

[0063] As can be seen from the foregoing, the hash algorithm, circuit, and electronic device provided herein utilize hardware architecture to physically reduce fixed-length parallel data. The reduced identifiers can be used as index references, IDs, address extension bits, message digests, and more, while also exhibiting high security. The hash algorithm circuit exhibits low power consumption and low cost, and can be integrated into digital circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the present disclosure or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only for the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0065] Figure 1 FIG2 shows an exemplary circuit structure diagram of a hash algorithm circuit according to an embodiment of the present disclosure;

[0066] Figure 2 An exemplary structural diagram of a hash algorithm circuit according to an embodiment of the present disclosure is shown;

[0067] Figure 3 FIG2 shows an exemplary circuit structure diagram of a hash circuit unit group according to an embodiment of the present disclosure;

[0068] Figure 4 A flowchart of an exemplary method according to an embodiment of the present disclosure is shown;

[0069] Figure 5 FIG. 5 shows a more specific hardware structure diagram of an electronic device 500 provided in this embodiment. DETAILED DESCRIPTION

[0070] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0071] It should be noted that, unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0072] A key tool in cryptography is the hash algorithm, sometimes called a digital fingerprint. Like the summary of an article, it's also known as a digest algorithm. The rapid development of the Internet of Things (IoT) has rapidly exposed numerous information security issues. International, national, and corporate organizations are beginning to prioritize security. The future of IoT security will require integrated, diversified solutions. Hash algorithms play a crucial role in hardware, software, and application security.

[0073] Currently, there are a variety of hash algorithms, including direct addressing, digital analysis, squaring the middle, and division with remainder. Hash algorithms have a wide range of applications, including file verification, digital signatures, authentication protocols, secure boot, and fast addressing. These applications are generally implemented using software, primarily to address trust issues in communications.

[0074] However, hash algorithms implemented in software are prone to security issues once the software code is deciphered. In light of this, the present disclosure provides a hash algorithm circuit, hash algorithm, and electronic device. This hash algorithm circuit, through a hardware structure, physically reduces fixed-length parallel data. The reduced identifiers can be used as index references, IDs, address extension bits, message digests, and more, while also providing high security. This hash algorithm circuit features low power consumption and low cost, and can be integrated into digital circuits.

[0075] Figure 1 FIG. 1 shows an exemplary circuit structure diagram of a hash algorithm circuit 100 according to an embodiment of the present disclosure.

[0076] The hash algorithm circuit 100 includes an input circuit unit 102 , at least one hash circuit unit 104 , and an output circuit unit 106 .

[0077] like Figure 1As shown, the input circuit unit 102 can receive data to be processed 108 from an external device (not shown). The external device can be another module of the electronic device to which the hash algorithm circuit 100 belongs (for example, a processor of the electronic device to which the hash algorithm circuit 100 belongs), or it can be another terminal device other than the electronic device to which the hash algorithm circuit 100 belongs. The data to be processed 108 can be a message of any length. The data to be processed 108 can be, for example, a key index address, device identity information, etc.

[0078] The hash circuit unit 104 is electrically coupled to the input circuit unit 102 and has a circuit structure configured according to a preset hash algorithm. For example, after the data to be processed 108 passes through the hash circuit unit 104, it is converted into target data 110. Because the hash circuit unit 104 has a circuit structure configured according to the preset hash algorithm, the target data 110 formed after the data to be processed 108 passes through the hash circuit unit 104 has a data length that is shorter than the data length of the data to be processed 108. This reduces resource consumption and increases processing speed when processing or storing the target data 110 compared to the data to be processed 108. Furthermore, because the hash circuit unit 104 has a circuit structure configured according to the preset hash algorithm, the target data 110 formed after passing through the hash circuit unit 104 is difficult to reverse-decrypt to obtain the data to be processed 108.

[0079] In some embodiments, the preset hash algorithm can be selected from at least one of the following methods: direct addressing method, digital analysis method, square median method, folding method, random number method, and division remainder method.

[0080] Direct addressing uses a hash function to generate a key or a linear function of the key. This is done by using H(key) = key or H(key) = a·key + b, where a and b are constants. This hash function is also called a self-function.

[0081] Digital analysis analyzes a set of data to identify numerical patterns and then uses this data to construct hash addresses with a low probability of collision. For example, if the first few digits of a group of employees' birth dates are roughly the same, the probability of a collision is high. However, if the last few digits representing the month and day differ significantly, using these digits to construct the hash address will significantly reduce the probability of a collision.

[0082] The middle digits of the squared keyword are used as the hash address.

[0083] The folding method is to divide the keyword into several parts with the same number of bits, and the number of bits in the last part can be different. Then the sum of these parts (excluding the carry) is taken as the hash address.

[0084] The random number method selects a random function and uses the keyword as the seed of the random function to generate a random value as the hash address. It is usually used in situations where the keyword lengths are different.

[0085] The remainder method uses the remainder obtained by dividing the key by a number p that is no greater than the hash table length m as the hash address. Specifically, H(key) = key MOD p, where p ≤ m. This method can be applied modulo the key directly or after operations like folding or squaring. The choice of p is crucial; it is typically a prime number or m. A poorly chosen p can easily lead to collisions.

[0086] In some embodiments, the number of the hash circuit units may be two or more. Figure 2 FIG. 2 shows an exemplary structural diagram of a hash algorithm circuit 200 according to an embodiment of the present disclosure.

[0087] The hash algorithm circuit 200 includes an input circuit unit 202 , a first hash circuit unit 204 , a second hash circuit unit 206 , and an output circuit unit 208 .

[0088] The first hash circuit unit 204 is electrically coupled to the input circuit unit 202. In some embodiments, the first hash circuit unit 204 may have a circuit structure arranged according to a first preset hash algorithm, and is configured to convert the to-be-processed data 210 into intermediate data 212. In some embodiments, the first preset hash algorithm may be selected from at least one of the following methods: direct addressing, digital analysis, square median, folding, random number, and division-with-remainder.

[0089] Because the first hash circuit unit 204 has a circuit structure configured according to the first preset hash algorithm, the data length of the intermediate data 212 generated after the data to be processed 210 passes through the first hash circuit unit 204 is shorter than the data length of the data to be processed 210. Because the first hash circuit unit 204 has a circuit structure configured according to the first preset hash algorithm, the intermediate data 212 generated after passing through the first hash circuit unit 204 increases the difficulty of reverse decryption of the data to be processed 210.

[0090] The second hash circuit unit 206 is electrically coupled to the first hash circuit unit 206 and the output circuit unit 208. In some embodiments, the second hash circuit unit 206 may have a circuit structure arranged according to a second preset hash algorithm and is used to convert the intermediate data 212 into the target data 214. In some embodiments, the second preset hash algorithm may be selected from at least one of the following methods: direct addressing, digital analysis, square median, folding, random number, and division with remainder.

[0091] Because the second hash circuit unit 206 has a circuit structure configured according to the second preset hash algorithm, the target data 214 formed after the intermediate data 212 passes through the second hash circuit unit 206 has a data length that is shorter than the data length of the intermediate data 212. This reduces resource consumption and improves processing speed when processing or storing the target data 214, compared to the data to be processed 210. Furthermore, because the intermediate data 212 is the data to be processed 210 processed by the first hash circuit unit 204, and the second hash circuit unit 206 has a circuit structure configured according to the second preset hash algorithm, the target data 214 formed after the intermediate data 212 passes through the second hash circuit unit 206 further increases the difficulty of reverse decrypting the data to be processed 210.

[0092] In some embodiments, the first hash circuit unit includes at least one of an exclusive-OR circuit, a summing circuit, and a shifting circuit; and the second hash circuit unit includes at least one of an exclusive-OR circuit, a summing circuit, and a shifting circuit.

[0093] The XOR circuit obtains a new data sequence by performing XOR processing on two data sequences, thereby shortening the two data sequences into one data sequence.

[0094] The summing circuit obtains a new data sequence by summing two data sequences, thereby shortening the two data sequences into one data sequence.

[0095] The shift circuit shifts part of the data sequence in the complete data, so that the position of some data sequences in the complete data is disrupted, thereby increasing the difficulty of deciphering the data.

[0096] Figure 3 FIG. 4 shows an exemplary circuit structure diagram of a hash circuit unit group 300 according to an embodiment of the present disclosure.

[0097] The data to be processed 306 input to the hash circuit unit group 300 can be divided into several sequences. For example, if the data length of the data to be processed 306 is n×L, the data to be processed 306 can be divided into n sequences, each of which has a length of L. Figure 3 In the example shown, the data to be processed 306 is divided into 8 sequences s1 to s8, that is, n=8, and the length of each sequence is L.

[0098] In some embodiments, the step of splitting the data to be processed 306 can be completed by other modules of the electronic device to which the hash algorithm circuit 100 belongs (for example, the processor of the electronic device to which the hash algorithm circuit 100 belongs), and then passed through the input circuit unit ( Figure 3 ) is input into the hash circuit unit group 300.

[0099] like Figure 3 As shown, the first hash circuit unit 302 includes a first XOR circuit 30202 , a first summation circuit 30204 , a first left shift circuit 30206 , a second XOR circuit 30208 and a first right shift circuit 30210 .

[0100] The first XOR circuit 30202 is configured to perform an XOR operation on the first sequence s1 and the second sequence s2 of the data to be processed 306 to obtain a second intermediate sequence m2 of the intermediate data 308 by position replacement, with a length of L;

[0101] A first summing circuit 30204 is configured to sum the third sequence s3 and the fourth sequence s4 of the to-be-processed data 306 to obtain a fifth intermediate sequence m5 of the intermediate data 308 by position replacement, with a length of L;

[0102] A first left shift circuit 30206 is configured to left-shift the fifth sequence s5 of the to-be-processed data 306 (e.g., by 3 bits) to obtain a fourth intermediate sequence m4 of the intermediate data 308 by position replacement, the length of which is L.

[0103] The second XOR circuit 30208 is configured to perform an XOR operation on the sixth sequence s6 and the eighth sequence s8 of the data to be processed 306 to obtain a third intermediate sequence m3 of the intermediate data 308 by position replacement, with a length of L;

[0104] The first right shift circuit 30210 is configured to right shift the seventh sequence s7 of the data to be processed 306 (for example, right shift by 3 bits), and obtain the first intermediate sequence m1 of the intermediate data 308 by position replacement, with a length of L.

[0105] It can be seen that the intermediate data 308 includes intermediate sequences m1-m5, and the data length of each intermediate sequence is equal to the data length of the initial sequences s1-s8. Therefore, the intermediate data 308 obtained after passing through the first hash circuit unit 302 is shorter than the data to be processed 306. The XOR, summation, and shifting processes increase the difficulty of reverse decryption of the intermediate data 308.

[0106] Furthermore, the intermediate data 308 may be processed by the second hash circuit unit 304 to obtain target data 310 .

[0107] The second hash circuit unit 304 includes a third XOR circuit 30402 , a second summing circuit 30404 , a second right shift circuit 30406 , a second left shift circuit 30408 ​​, a fourth XOR circuit 30410 , and a fifth XOR circuit 30412 .

[0108] a third XOR circuit 30402 electrically coupled to the first right shift circuit 30210 and the first XOR circuit 30202, and configured to perform an XOR operation on the first intermediate sequence m1 and the second intermediate sequence m2 to form a first temporary sequence t1 having a length of L;

[0109] a second summing circuit 30404 electrically coupled to the second XOR circuit 30208 and the first left shift circuit 30206, and configured to sum the third intermediate sequence m3 and the fourth intermediate sequence m4 to form a second temporary sequence t2 having a length of L;

[0110] a second right shift circuit 30406 electrically coupled to the second summing circuit 30404 and configured to right shift the second temporary sequence t2 by a first predetermined number of bits (e.g., 5 bits) to form a third temporary sequence t3 having a length of L;

[0111] a second left shift circuit 30408, electrically coupled to the first summing circuit 30204, and configured to left-shift the fifth intermediate sequence m5 by a second predetermined number of bits (e.g., 7 bits) to form a fourth temporary sequence t4 with a length of L;

[0112] a fourth XOR circuit 30410 , electrically coupled to the third XOR circuit 30402 and the second left shift circuit 30406 , and configured to perform an XOR operation on the first temporary sequence t1 and the fourth temporary sequence t4 to form a fifth temporary sequence t5 with a length of L;

[0113] The fifth XOR circuit 30412 is electrically coupled to the fourth XOR circuit 30410 and the second right shift circuit 30406 respectively, and is configured to perform an XOR operation on the third temporary sequence t3 and the fifth temporary sequence t5 to form the target data 310 with a length of L.

[0114] After passing through the first hash circuit unit 302 and the second hash circuit unit 304, the length of the data to be processed 306 is reduced from n×L to the length of the target data 310, L. The mathematical relationship is described as follows:

[0115] m1=s7>>3

[0116] m2=s1⊕s2

[0117] m3=s6⊕s8

[0118] m4=s5<<3

[0119] m5=(s3+s4)mod2 L

[0120]

[0121] It can be seen that the hash circuit unit group 300 finally completes the following mapping:

[0122] H(s)=d

[0123] S={s1,s2,s3,…,sn}

[0124] Here, d is the final target data 310, with a length of L; S is the data to be processed 306, with a length of n×L, and the length of S is n times that of d. s1~sn are sequences obtained by segmenting S, with a length of L, which is consistent with the length of d.

[0125] It can be seen that the target data 310 includes only one sequence, and the data length of this sequence is equal to the data length of the initial sequences s1 to s8. Therefore, after being processed again by the second hash circuit unit 304, the length of the target data 310 is further shortened. In addition, the intermediate data 308 is further processed by XOR, summation, and shifting, which further increases the difficulty of reverse decryption of the target data 310.

[0126] It can be seen from the above embodiments that after processing by the XOR circuit or the summing circuit, two sequences can be combined into one sequence, that is, the data length is shortened by the length of one sequence. Therefore, according to actual needs, the number of XOR circuits, summing circuits, or circuits with similar functions included in the hash circuit unit can be designed to further form the data to be processed into target data of a required length.

[0127] For example, in the aforementioned embodiment, to-be-processed data of length 8×L is converted into target data of length L, and the total number of XOR circuits and summing circuits used is 7. In other words, if the length of the to-be-processed data is n×L, then to achieve a target data length of L, a total of n-1 XOR circuits and summing circuits (or circuits with similar functions) are required. Thus, the number of XOR circuits and summing circuits needs to be determined based on the difference between the number n of sequences into which the to-be-processed data is divided and the number u of sequences of the target data. Furthermore, when allocating the number of XOR circuits and summing circuits to different hash circuit units, the number of XOR circuits and summing circuits in each hash circuit unit can also be determined based on the number k of sequences of the intermediate data.

[0128] It should be noted that hash circuit unit group 300 is merely an exemplary structure. It should be understood that the number of hash circuit units included in a hash algorithm circuit can be selected based on the complexity of the circuit design. Furthermore, the specific circuits used in the hash circuit units are not limited to XOR circuits, summation circuits, and shift circuits; other circuits can also be selected based on actual needs.

[0129] The output circuit unit 106 is electrically coupled to the hash circuit unit 104 and is configured to output the target data 110 to an external device (not shown). The external device may be another module of the electronic device to which the hash algorithm circuit 100 belongs (e.g., a processor of the electronic device to which the hash algorithm circuit 100 belongs), or another terminal device other than the electronic device to which the hash algorithm circuit 100 belongs.

[0130] The hash algorithm circuit proposed in the present disclosure can be used to shorten fixed-length parallel data to generate a new index address or identifier. The hash algorithm circuit can increase the randomness and complexity of security circuits such as random number generators or physical non-cloning functions, preventing hackers from directly accessing core modules and conducting modeling attacks.

[0131] For example, the original input is a certain index address, and the original input address can generate a new index address through the hash algorithm circuit. Since the hash algorithm circuit is a hardware structure, its specific circuit structure cannot be known through software deciphering. Therefore, even if the original input address is deciphered, the information corresponding to the actual index address (new index address) (such as the key) cannot be obtained, thereby providing device security through the hash algorithm circuit.

[0132] At the same time, the hash algorithm circuit proposed in the present disclosure has the characteristics of small footprint, low power consumption, low cost, etc., and is easy to be integrated into digital circuits.

[0133] The hash algorithm circuit can be used as an address expansion. For example, if an address is IDX, it will be reduced to IDX / n after passing through the circuit, and the new addressing address can be formed as follows:

[0134] IDX new ={IDX,H(IDX)}

[0135] After the above expansion, the address bits are expanded, allowing this circuit to be used in instruction set compression or physical address mapping. Furthermore, for example, if an address is IDX, it can be reduced to IDX / n after hashing. After being left-shifted L bits and then passed through the hash algorithm again, it can be right-reduced to IDX / n. This means that the same address can be used to generate multiple addressing addresses. There are many other applications.

[0136] Figure 4 A flowchart of an exemplary method 400 according to an embodiment of the present disclosure is shown.

[0137] The hash algorithm 400 may be implemented using a hash algorithm circuit. Figure 1 As shown, the hash algorithm circuit 100 includes an input circuit unit 102, at least one hash circuit unit 104, and an output circuit unit 106 electrically coupled in sequence. The hash algorithm 400 includes the following steps.

[0138] In step 402, the input circuit unit (eg, Figure 1 The input circuit unit 102 receives the data to be processed (for example, Figure 1 data to be processed 108).

[0139] In step 404, the at least one hash circuit unit (eg, Figure 1 The hash circuit unit 104) forms the data to be processed after passing through the hash circuit unit into target data (for example, Figure 1 target data 110); wherein, the data length of the data to be processed is greater than the data length of the target data.

[0140] In some embodiments, the preset hash algorithm is selected from at least one of the following methods: direct addressing method, digital analysis method, square median method, folding method, random number method, and division remainder method.

[0141] In some embodiments, the hash algorithm circuit includes a first hash circuit unit (eg, Figure 2 a first hash circuit unit 204) and a second hash circuit unit (eg, Figure 2 The second hash circuit unit 206); the hash algorithm further includes:

[0142] The first hash circuit unit is used to convert the data to be processed into intermediate data (for example, Figure 2 intermediate data 212); wherein the data length of the data to be processed is greater than the data length of the intermediate data;

[0143] The second hash circuit unit is used to transform the intermediate data into target data (eg, Figure 2 target data 214); wherein, the data length of the intermediate data is greater than the data length of the target data.

[0144] In some embodiments, the first hash circuit unit includes at least one of an exclusive OR circuit, a summing circuit, and a shift circuit; the second hash circuit unit includes at least one of an exclusive OR circuit, a summing circuit, and a shift circuit.

[0145] In some embodiments, the data to be processed is divided into 8 sequences; the first hash circuit unit (eg, Figure 3 The first hash circuit unit 302 includes a first XOR circuit (eg, Figure 3 a first XOR circuit 30202), a first summing circuit (eg, Figure 3 a first summing circuit 30204), a first left shifting circuit (eg, Figure 3 The first left shift circuit 30206), the second XOR circuit (for example, Figure 3 The second XOR circuit 30208) and the first right shift circuit (eg, Figure 3 first right shift circuit 30210);

[0146] The hash algorithm also includes:

[0147] The first XOR circuit is used to convert the data to be processed (for example, Figure 3 The first sequence of data to be processed 306) (for example, Figure 3 The first sequence t1) and the second sequence (e.g., Figure 3 The second sequence t2) is XORed to form the intermediate data (for example, Figure 3 The second intermediate sequence of intermediate data 308) (eg, Figure 3 a second intermediate sequence m2);

[0148] The first summing circuit is used to sum the third sequence of the data to be processed (for example, Figure 3 The third sequence t3) and the fourth sequence (e.g., Figure 3 The fourth sequence t4) is summed to form a fifth intermediate sequence of the intermediate data (eg, Figure 3The fifth intermediate sequence m5);

[0149] The first left shift circuit is used to shift the fifth sequence of the data to be processed (for example, Figure 3 The fifth sequence t5) is shifted left to form a fourth intermediate sequence of the intermediate data (eg, Figure 3 The fourth intermediate sequence m4);

[0150] The sixth sequence of the data to be processed (for example, Figure 3 The sixth sequence t6) and the eighth sequence (e.g., Figure 3 The eighth sequence t8) is XORed to form a third intermediate sequence of the intermediate data (eg, Figure 3 The third intermediate sequence m3);

[0151] The first right shift circuit is used to shift the seventh sequence of the data to be processed (for example, Figure 3 The seventh sequence t7) is right-shifted to form a first intermediate sequence of the intermediate data (eg, Figure 3 The first intermediate sequence m1).

[0152] In some embodiments, the second hash circuit unit (eg, Figure 3 The second hash circuit unit 304 includes a third XOR circuit (eg, Figure 3 The third XOR circuit 30402), the second summing circuit (for example, Figure 3 The second summing circuit 30404), the second right shift circuit (eg, Figure 3 The second right shift circuit 30406), the second left shift circuit (for example, Figure 3 The second left shift circuit 30408), the fourth XOR circuit (for example, Figure 3 The fourth XOR circuit 30410), the fifth XOR circuit (for example, Figure 3 the fifth XOR circuit 30412); the third XOR circuit is electrically coupled to the first right shift circuit and the first XOR circuit, respectively; the second summing circuit is electrically coupled to the second XOR circuit and the first left shift circuit, respectively; the second right shift circuit is electrically coupled to the second summing circuit; the second left shift circuit is electrically coupled to the first summing circuit; the fourth XOR circuit is electrically coupled to the third XOR circuit and the second left shift circuit, respectively; the fifth XOR circuit is electrically coupled to the fourth XOR circuit and the second right shift circuit, respectively;

[0153] The hash algorithm also includes:

[0154] Using the third XOR circuit, the first intermediate sequence and the second intermediate sequence are XORed to form a first temporary sequence (eg, Figure 3 The first temporary sequence t1);

[0155] The third intermediate sequence and the fourth intermediate sequence are XORed using the second summing circuit to form a second temporary sequence (eg, Figure 3 A second temporary sequence t2);

[0156] The second temporary sequence is right-shifted by a first predetermined number of bits using the second right-shift circuit to form a third temporary sequence (eg, Figure 3 A third temporary sequence t3);

[0157] The second left shift circuit is used to left shift the fifth intermediate sequence by a second predetermined number of bits to form a fourth temporary sequence (eg, Figure 3 A fourth temporary sequence t4);

[0158] Using the fourth XOR circuit, the first temporary sequence and the fourth temporary sequence are XORed to form a fifth temporary sequence (eg, Figure 3 A fifth temporary sequence t5);

[0159] Using the fifth XOR circuit, the third temporary sequence and the fifth temporary sequence are XORed to form the target data (eg, Figure 3 target data 310).

[0160] In step 406, the output circuit unit (eg, Figure 1 The output circuit unit 106) outputs the target data.

[0161] The hash algorithm implemented by the hash algorithm circuit provided in the present disclosure is used to reduce parallel data of fixed length. The reduced identifier can be used as an index reference, a flag ID, an address extension bit, an information summary, etc.

[0162] It should be noted that the above description is of specific embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in an order different from that described in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order shown or the sequential order to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0163] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments and methods, the present disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the hash algorithm described in any of the above embodiments when executing the program.

[0164] Figure 5 Schematic diagram of the hardware structure of a more specific electronic device 500 provided in this embodiment is shown. The device 500 may include: a processor 502, a memory 504, an input / output interface 506, a communication interface 508, and a bus 510. The processor 502, the memory 504, the input / output interface 506, and the communication interface 508 are connected to each other within the device via the bus 510.

[0165] The processor 502 can be implemented using a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided by the embodiments of the present disclosure.

[0166] The memory 504 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage devices, dynamic storage devices, etc. The memory 504 can store an operating system and other application programs. When the technical solutions provided by the embodiments of the present disclosure are implemented through software or firmware, the relevant program codes are stored in the memory 504 and called and executed by the processor 502.

[0167] The input / output interface 506 is used to connect to an input / output module to implement information input and output. The input / output module can be configured as a component in the device (not shown in the figure) or can be externally connected to the device to provide corresponding functions. Input devices may include a keyboard, mouse, touch screen, microphone, various sensors, etc., and output devices may include a display, speaker, vibrator, indicator light, etc.

[0168] In some embodiments, the input / output interface 506 can also be connected to the hash algorithm circuit (eg, Figure 1 Hash algorithm circuit 100, Figure 2 Hash algorithm circuit 200, or Figure 3 The hash algorithm circuit 300 is electrically coupled to the processor and uses the hash algorithm circuit to process the input or output data before performing subsequent operations.

[0169] The communication interface 508 is used to connect to a communication module (not shown) to enable communication between the device and other devices. The communication module can communicate via a wired method (such as USB, network cable, etc.) or a wireless method (such as mobile network, WIFI, Bluetooth, etc.).

[0170] The bus 510 comprises a pathway for transmitting information between the various components of the device, such as the processor 502 , the memory 504 , the input / output interface 506 , and the communication interface 508 .

[0171] It should be noted that although the above device only shows the processor 502, memory 504, input / output interface 506, communication interface 508, and bus 510, in a specific implementation, the device may also include other components necessary for normal operation. In addition, those skilled in the art will understand that the above device may only include the components necessary to implement the embodiments of the present disclosure, and does not necessarily include all the components shown in the figure.

[0172] The electronic device of the above embodiment is used to implement the corresponding hash algorithm in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0173] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Within the scope of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0174] In addition, to simplify the description and discussion, and in order not to obscure the present disclosure, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, devices may be shown in the form of block diagrams to avoid obscuring the present disclosure, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the present disclosure is to be implemented (i.e., these details should be fully within the purview of those skilled in the art). Where specific details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that the present disclosure may be implemented without these specific details or with variations in these specific details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0175] Although the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0176] The present disclosure is intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A hash algorithm circuit comprising: The input circuit unit is configured to: receive data to be processed; at least one hash circuit unit electrically coupled to the input circuit unit, the hash circuit unit having a circuit structure arranged according to a preset hash algorithm and configured to: form the to-be-processed data passing through the hash circuit unit into target data; wherein the data length of the to-be-processed data is greater than the data length of the target data; an output circuit unit, electrically coupled to at least one of the hash circuit units, and configured to: output the target data; Wherein, the at least one hash circuit unit includes a first hash circuit unit and a second hash circuit unit; The first hash circuit unit is electrically coupled to the input circuit unit, has a circuit structure arranged according to a first preset hash algorithm, and is configured to: form the data to be processed into intermediate data; wherein the data length of the data to be processed is greater than the data length of the intermediate data; The second hash circuit unit is electrically coupled to the first hash circuit unit, has a circuit structure arranged according to a second preset hash algorithm, and is configured to: form the intermediate data into target data; wherein the data length of the intermediate data is greater than the data length of the target data.

2. The hash algorithm circuit according to claim 1, wherein: The preset hash algorithm is selected from at least one of the following methods: direct addressing method, digital analysis method, square median method, folding method, random number method, and division remainder method.

3. The hash algorithm circuit according to claim 1, wherein: The data to be processed is divided into n sequences; The first hash circuit unit is configured to: generate k sequences of intermediate data according to the first preset hash algorithm through its circuit structure, wherein n and k are both natural numbers, and n>k; The second hash circuit unit is configured to: transform the k sequences into target data having u sequences according to the second preset hash algorithm through its circuit structure, where u is a natural number and k>u.

4. The hash algorithm circuit according to claim 3, wherein: The first hash circuit unit includes at least one of an XOR circuit, a summation circuit, and a shift circuit; The second hash circuit unit includes at least one of an XOR circuit, a summation circuit, and a shift circuit; The number of the XOR circuits and the summing circuits is determined according to the difference between n and u.

5. The hash algorithm circuit according to claim 4, wherein: The data to be processed is divided into 8 sequences; The first hash circuit unit includes: a first XOR circuit configured to perform an XOR operation on the first sequence and the second sequence of the data to be processed to form a second intermediate sequence of the intermediate data; a first summing circuit configured to perform a summing operation on the third sequence and the fourth sequence of the data to be processed to form a fifth intermediate sequence of the intermediate data; a first left shift circuit, configured to left shift the fifth sequence of data to be processed to form a fourth intermediate sequence of intermediate data; a second XOR circuit configured to perform an XOR operation on the sixth sequence and the eighth sequence of the data to be processed to form a third intermediate sequence of the intermediate data; The first right shift circuit is configured to right shift the seventh sequence of the to-be-processed data to form a first intermediate sequence of the intermediate data.

6. The hash algorithm circuit according to claim 5, wherein: The second hash circuit unit includes: a third XOR circuit, electrically coupled to the first right shift circuit and the first XOR circuit, and configured to perform an XOR operation on the first intermediate sequence and the second intermediate sequence to form a first temporary sequence; a second summing circuit electrically coupled to the second XOR circuit and the first left shift circuit, and configured to perform a summing operation on the third intermediate sequence and the fourth intermediate sequence to form a second temporary sequence; a second right shift circuit electrically coupled to the second summing circuit and configured to right shift the second temporary sequence by a first predetermined number of bits to form a third temporary sequence; a second left shift circuit electrically coupled to the first summing circuit and configured to left-shift the fifth intermediate sequence by a second predetermined number of bits to form a fourth temporary sequence; a fourth XOR circuit, electrically coupled to the third XOR circuit and the second left shift circuit, and configured to perform an XOR operation on the first temporary sequence and a fourth temporary sequence to form a fifth temporary sequence; The fifth XOR circuit is electrically coupled to the fourth XOR circuit and the second right shift circuit respectively, and is configured to perform an XOR operation on the third temporary sequence and the fifth temporary sequence to form the target data.

7. A hash algorithm implemented using a hash algorithm circuit, the hash algorithm circuit comprising an input circuit unit, at least one hash circuit unit, and an output circuit unit electrically coupled in sequence, the hash algorithm comprising: receiving data to be processed by utilizing the input circuit unit; Using the at least one hash circuit unit, the data to be processed that has passed through the hash circuit unit is transformed into target data according to a preset hash algorithm; wherein the data length of the data to be processed is greater than the data length of the target data; outputting the target data using the output circuit unit; The at least one hash circuit unit includes a first hash circuit unit electrically coupled to the input circuit unit and a second hash circuit unit electrically coupled to the first hash circuit unit; and the hash algorithm further includes: Using the first hash circuit unit, the data to be processed is converted into intermediate data according to a first preset hash algorithm; wherein the data length of the data to be processed is greater than the data length of the intermediate data; The second hash circuit unit is used to transform the intermediate data into target data according to a second preset hash algorithm; wherein the data length of the intermediate data is greater than the data length of the target data.

8. The hash algorithm according to claim 7, wherein: The preset hash algorithm is selected from at least one of the following methods: direct addressing method, digital analysis method, square median method, folding method, random number method, and division remainder method.

9. The hash algorithm according to claim 8, wherein: The data to be processed is divided into n sequences; the hash algorithm further includes: Using the first hash circuit unit, through its circuit structure, the n sequences are transformed into intermediate data having k sequences according to the first preset hash algorithm, where n and k are both natural numbers, and n>k; The second hash circuit unit is used to transform the k sequences into target data having u sequences according to the second preset hash algorithm through its circuit structure, wherein u is a natural number and k>u.

10. The hash algorithm according to claim 9, wherein: The first hash circuit unit includes at least one of an XOR circuit, a summation circuit, and a shift circuit; The second hash circuit unit includes at least one of an XOR circuit, a summation circuit, and a shift circuit; The hash algorithm further includes: The number of the XOR circuits and the summing circuits is determined according to the difference between the numbers of n and u.

11. The hash algorithm according to claim 10, wherein: The data to be processed is divided into 8 sequences; the first hash circuit unit includes a first XOR circuit, a first summation circuit, a first left shift circuit, a second XOR circuit and a first right shift circuit; The hash algorithm also includes: Using the first XOR circuit, performing an XOR operation on the first sequence of the to-be-processed data and the second sequence to form a second intermediate sequence of the intermediate data; using the first summing circuit to sum the third sequence and the fourth sequence of the data to be processed to form a fifth intermediate sequence of the intermediate data; Using the first left shift circuit, left-shifting the fifth sequence of data to be processed to form a fourth intermediate sequence of intermediate data; Using a second XOR circuit, performing an XOR operation on the sixth sequence and the eighth sequence of the data to be processed to form a third intermediate sequence of the intermediate data; The first right shift circuit is used to right shift the seventh sequence of the data to be processed to form a first intermediate sequence of the intermediate data.

12. The hash algorithm according to claim 11, wherein: The second hash circuit unit includes a third XOR circuit, a second summing circuit, a second right shift circuit, a second left shift circuit, a fourth XOR circuit, and a fifth XOR circuit; the third XOR circuit is electrically coupled to the first right shift circuit and the first XOR circuit, respectively; the second summing circuit is electrically coupled to the second XOR circuit and the first left shift circuit, respectively; and the second right shift circuit is electrically coupled to the second summing circuit; The second left shift circuit is electrically coupled to the first summing circuit; The fourth XOR circuit is electrically coupled to the third XOR circuit and the second left shift circuit respectively; The fifth XOR circuit is electrically coupled to the fourth XOR circuit and the second right shift circuit respectively; The hash algorithm also includes: Using the third XOR circuit, performing an XOR operation on the first intermediate sequence and the second intermediate sequence to form a first temporary sequence; using the second summing circuit to sum the third intermediate sequence and the fourth intermediate sequence to form a second temporary sequence; Utilizing the second right shift circuit, right-shifting the second temporary sequence by a first predetermined number of bits to form a third temporary sequence; Utilizing the second left shift circuit, shifting the fifth intermediate sequence left by a second predetermined number of bits to form a fourth temporary sequence; Using the fourth XOR circuit, performing an XOR operation on the first temporary sequence and the fourth temporary sequence to form a fifth temporary sequence; The fifth XOR circuit is used to perform an XOR operation on the third temporary sequence and the fifth temporary sequence to form the target data.

13. An electronic device comprising the hash algorithm circuit according to any one of claims 1 to 6.

Images