High-speed low-power potential translation circuit
By introducing a dynamic current generation module into the potential shift circuit, additional current is provided only at the moment of signal change, thus solving the balance problem between conversion speed and static power consumption and realizing high-speed, low-power potential shift.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-01-27
- Publication Date
- 2026-03-20
AI Technical Summary
Existing potential shifting circuits struggle to balance switching speed and static power consumption. A small bias current results in a slow switching speed, while a large bias current increases static power consumption.
A dynamic current generation module is used to provide additional current at the moment of signal change, and combined with a bias module to provide a stable bias current. The dynamic current only increases at the moment of conversion, reducing static power consumption.
This improves the switching speed of the potential shift circuit, reduces static power consumption, and maintains the circuit's reliability and response performance.
Smart Images
Figure CN114499491B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application relates to the technical field of power switch control, in particular to a high-speed low-power potential translation circuit. BACKGROUND
[0002] The potential translation circuit is widely applied to various high-voltage power switch control applications and is used for converting a logic level from a low side to a high side. The potential translation circuit is an indispensable component in a DCDC switch voltage converter, a motor drive or a ClassD audio power amplifier.
[0003] In a commonly used potential translation circuit, the bias current of the potential translation circuit is an indispensable factor for maintaining a high-side output level. The selection of the bias current size determines the conversion performance of the potential translation circuit. If the bias current is small, the conversion speed of the potential translation circuit will be slow, and the delay time between the input signal and the output signal will be long. Therefore, it is necessary to increase the bias current to shorten the delay time between the input signal and the output signal. However, increasing the bias current will increase the static power consumption of the chip. Therefore, a high-speed low-power potential translation circuit is urgently needed. SUMMARY
[0004] In order to improve the conversion speed of the potential translation and reduce the static power consumption, the application provides a high-speed low-power potential translation circuit.
[0005] The high-speed low-power potential translation circuit provided by the application adopts the following technical scheme: a high-speed low-power potential translation circuit, comprising a current comparator module, a bias module, a dynamic current generation module, a first inverter IV1, a first power supply end VCC, a signal input end IN and a signal output end OUT; the current comparator module comprises a first input end a1, a second input end a2, a bias current input end a3, a power supply end e and an output end f, the first input end a1 is connected to the signal input end IN, the signal input end IN is also connected to the input end of the first inverter IV1, the output end of the first inverter IV1 is connected to the second input end a2, the bias current input end a3 is connected to the bias module and the dynamic current generation module respectively, the power supply end e is connected to the first power supply end VCC, and the output end f is connected to the signal output end OUT;
[0006] The dynamic current generation module comprises a third input end d1, a fourth input end d2 and a dynamic current output end d3; the third input end d1 is connected to the input end of the first inverter IV1, the fourth input end d2 is connected to the output end of the first inverter IV1, and the dynamic current output end d3 is connected to the bias current input end a3;
[0007] The bias module is configured to provide a bias current.
[0008] The dynamic current generation module is configured to provide additional transient dynamic current for the potential translation circuit when the input signal changes.
[0009] When the current comparator module performs potential conversion according to the control signal of the signal input terminal IN, the bias module provides a bias current for the current comparator module. Compared with the original potential translation circuit, by increasing the dynamic current generation module, only the dynamic current of the potential translation circuit is increased at the moment when the input signal changes. The dynamic current generation module provides additional current for the current comparator module, which can improve the response speed of the current comparator module, so that the potential translation circuit quickly converts. At the same time, in the process of high-speed conversion, the bias module does not need to provide all the working current, thereby reducing the bias current and reducing the static power consumption of the potential translation circuit.
[0010] Optionally, the dynamic current generation module comprises a second inverter IV2 and a first energy storage element, an input end of the second inverter IV2 is connected to the third input end d1, a power supply end of the second inverter IV2 is connected to the dynamic current output end d3, an output end of the second inverter IV2 is connected to one end of the first energy storage element, and the other end of the first energy storage element is connected to the dynamic current output end d3.
[0011] Optionally, the second inverter IV2 comprises a MOS tube M6A and a MOS tube M6B, a gate of the MOS tube M6A and a gate of the MOS tube M6B are connected to the third input end d1, a source of the MOS tube M6A is connected to a ground end GND, a drain of the MOS tube M6A is connected to a drain of the MOS tube M6B, the drain of the MOS tube M6A and the drain of the MOS tube M6B are connected to the first energy storage element, and a source of the MOS tube M6B is connected to the dynamic current output end d3.
[0012] By adopting the technical scheme, when the signal input end IN is converted from low level to high level, the input signal of the signal input end IN is input into the second inverter IV2, at this time, the MOS tube M6A is turned on, the first energy storage element stores energy, and the current for storing energy of the first energy storage element also flows through the current comparator module to provide dynamic current for the current comparator module; when the signal input end IN is converted from high level to low level, the MOS tube M6B is turned on, and the first energy storage element is in a discharging state, at this time, the current discharged by the first energy storage element only flows through the MOS tube M6B, and does not affect the working of the potential translation circuit; by controlling the size of the first energy storage element, the duration of the pulse current is widened, the reliability is improved, the energy provided in each potential translation process can be controlled, the dynamic current required by the potential translation circuit during signal conversion is increased, and the conversion speed of the potential translation circuit is increased, and the instantaneous dynamic current is increased, the static bias current provided by the bias module is reduced, and the static power consumption of the potential translation circuit is reduced.
[0013] Optionally, the dynamic current generating module further comprises a third inverter IV3 and a second energy storage element, an input end of the third inverter IV3 is connected to the fourth input end d2, a power supply end of the third inverter IV3 is connected to the dynamic current output end d3, an output end of the third inverter IV3 is connected to one end of the second energy storage element, and the other end of the second energy storage element is connected to the dynamic current output end d3.
[0014] Optionally, the third inverter IV3 comprises a MOS tube M7A and a MOS tube M7B, a gate of the MOS tube M7A and a gate of the MOS tube M7B are connected to the fourth input end d2, a source of the MOS tube M7A is connected to the ground end GND, a drain of the MOS tube M7A is connected to a drain of the MOS tube M7B, the drain of the MOS tube M7A and the drain of the MOS tube M7B are connected to the second energy storage element, and a source of the MOS tube M7B is connected to the dynamic current output end d3.
[0015] By adopting the technical scheme, when the signal input end IN is converted from high level to low level, the first inverter IV1 generates an inverted signal opposite to the input signal and inputs the inverted signal into the third inverter IV3, at this time, the MOS tube M7A is turned on, the second energy storage element is in a charging state, and the current flowing through the second energy storage element provides dynamic current for the current comparator module, when the signal input end IN is converted from low level to high level, the MOS tube M7B is turned on, the second energy storage element is in a discharging state, at this time, the current discharged by the second energy storage element only flows through the MOS tube M7B and does not affect the operation of the potential translation circuit, the dynamic current generation module only provides dynamic current for the current comparator module at the moment of potential translation, and after the potential conversion is completed, the dynamic current for the current comparator module is no longer needed.
[0016] Optionally, the current comparator module comprises a differential input submodule, a first mirror submodule, a second mirror submodule and a shaping submodule; the differential input submodule comprises the first input end a1, the second input end a2, the bias current input end a3, a first differential current output end a4 and a second differential current output end a5, the first mirror submodule comprises a first differential current input end b1 and a first mirror current output end b2, the second mirror submodule comprises a second differential current input end c1 and a second mirror current output end c2, the first differential current output end a4 is connected to the first differential current input end b1, the first mirror current output end b2 is connected to an input end of the shaping submodule, the second differential current output end a5 is connected to the second differential current input end c1, the second mirror current output end c2 is connected to an input end of the shaping submodule, and an output end of the shaping submodule is connected to the output end f.
[0017] By adopting the technical scheme, when the input signal of the signal input end IN and the inverted signal opposite to the input signal are low side levels and are both input into the differential input submodule, the differential input submodule converts the inverted signal into a first differential current, the differential input submodule converts the input signal into a second differential current, the first differential current is input into the first mirror submodule, the second differential current is input into the second mirror submodule, the first mirror submodule generates a first mirror current according to the first differential current, the second mirror submodule generates a second mirror current according to the second differential current, the first mirror current and the second mirror current determine the high and low of the level of the input end of the shaping submodule, the first mirror current and the second mirror current are shaped by the shaping submodule and then a high side level is output through the signal output end OUT, and the conversion from the low side level to the high side level is completed.
[0018] Optionally, the circuit further comprises an external current input terminal Iin, the biasing module comprises a third mirroring sub-module, a reference current input terminal g1 and a biasing current output terminal g2, the reference current input terminal g1 is connected to the external current input terminal Iin, the biasing current output terminal g2 is connected to the biasing current input terminal a3, an input terminal of the third mirroring sub-module is connected to the reference current input terminal g1, and an output terminal of the third mirroring sub-module is connected to the biasing current output terminal g2.
[0019] Optionally, the third mirroring sub-module further comprises a MOS tube M1A and a MOS tube M1B, a drain of the MOS tube M1A is connected to the reference current input terminal g1, a source of the MOS tube M1A is connected to a ground terminal GND, a gate of the MOS tube M1A is connected to a gate of the M1B, a source of the MOS tube M1B is connected to the ground terminal GND, and a drain of the MOS tube M1B is connected to the biasing current output terminal g2.
[0020] By using the above technical solution, when the reference current is input by the external current input terminal Iin and the MOS tube M1A is turned on, the current flowing through the drain of the MOS tube M1A is mirrored to the drain of the MOS tube M1B, and the current flowing through the drain of the MOS tube M1B provides the biasing current for the potential translation circuit, the MOS tube M1A and the MOS tube M1B constitute a mirroring current source, the current flowing through the drain of the MOS tube M1B is not affected by the external load, and the current flowing through the drain of the MOS tube M1B provides the stable biasing current for the current comparator module.
[0021] In summary, the present application has at least one of the following beneficial technical effects: 1. When the current comparator module performs potential conversion according to the control signal of the signal input terminal IN, the biasing module provides the biasing current for the current comparator module, compared with the original potential translation circuit, by increasing the dynamic current generation module, only the dynamic current of the potential translation circuit is increased at the moment when the input signal changes; the dynamic current generation module provides additional current for the current comparator module, which can improve the response speed of the current comparator module, so that the potential translation circuit quickly converts, and at the same time in the process of high-speed conversion, the biasing module does not need to provide all the working current, thereby the biasing current can be reduced, and the static power consumption of the potential translation circuit can be reduced;
[0022] 2. When the signal input IN is converted from low to high, the input signal of the signal input IN is input into the second inverter IV2, at this time the MOS transistor M6A is turned on, the first energy storage element stores energy, the current flowing through the first energy storage element also flows through the current comparator module, and the dynamic current is provided for the current comparator module. When the signal input IN is converted from high to low, the MOS transistor M6B is turned on, and the first energy storage element is in a discharging state. At this time, the current discharged by the first energy storage element only flows through the MOS transistor M6B, and does not affect the operation of the potential translation circuit. By controlling the size of the first energy storage element, the duration of the pulse current is widened, the reliability is improved, and the energy provided in each potential translation process can be controlled. By increasing the dynamic current required by the potential translation circuit during signal conversion, the conversion speed of the potential translation circuit is increased. Increasing the instantaneous dynamic current can reduce the static bias current provided by the bias module, and further reduce the static power consumption of the potential translation circuit;
[0023] 3. When the signal input IN is converted from high to low, the first inverter IV1 generates an inverted signal opposite to the input signal and inputs the inverted signal into the third inverter IV3. At this time, the MOS transistor M7A is turned on, and the second energy storage element is in a charging state. The current flowing through the second energy storage element provides dynamic current for the current comparator module. When the signal input IN is converted from low to high, the MOS transistor M7B is turned on, and the second energy storage element is in a discharging state. At this time, the current discharged by the second energy storage element only flows through the MOS transistor M7B, and does not affect the operation of the potential translation circuit. The dynamic current generation module only provides dynamic current for the current comparator module at the moment of potential translation. After the potential conversion is completed, there is no need to provide dynamic current for the current comparator module.
[0024] 4. The dynamic current generation module can very conveniently adjust the parameters of its electrical elements to improve the response performance of the potential translation circuit. BRIEF DESCRIPTION OF DRAWINGS
[0025] Figure 1 is a structural block diagram of an embodiment of the application;
[0026] Figure 2 is a circuit principle diagram of the current comparator module in the embodiment of the application;
[0027] Figure 3 is a circuit principle diagram of the bias module and the dynamic current generation module in the embodiment of the application.
[0028] EXPLANATION OF REFERENCE NUMERALS: 1, current comparator module; 11, differential input submodule; 12, first mirror submodule; 13, second mirror submodule; 14, shaping submodule; 2, bias module; 21, third mirror submodule; 3, dynamic current generation module. DETAILED DESCRIPTION
[0029] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.
[0030] The embodiment of the present application discloses a high-speed low-power potential translation circuit. Referring to Figure 1 and Figure 2 The high-speed low-power potential translation circuit comprises a current comparator module 1, a bias module 2, a dynamic current generation module 3, a first inverter IV1, a first power supply end VCC, a signal input end IN and a signal output end OUT. The current comparator module 1 comprises a first input end a1, a second input end a2, a bias current input end a3, a power supply end e and an output end f. The signal input end IN is connected to the input end of the first inverter IV1 and the first input end a1 respectively. The output end of the first inverter IV1 is connected to the second input end a2. The bias current input end a3 is connected to the bias module 2 and the dynamic current generation module 3 respectively. The power supply end e is connected to the first power supply end VCC. The output end f is connected to the signal output end OUT.
[0031] The bias module 2 is used to provide a bias current during the potential translation process. The dynamic current generation module 3 is used to provide an additional transient dynamic current for the potential translation circuit when the input signal changes.
[0032] When the control signal is input by the signal input end IN, the current comparator module 1 receives the input signal and the inverted signal of the input signal. The bias module 2 provides a bias current for the current comparator module 1. The dynamic current generation module 3 compensates the bias current, thereby improving the conversion speed of the potential translation. By controlling the size of the compensation current, the bias current can be indirectly reduced, and the static power consumption of the potential translation circuit can be further reduced.
[0033] Referring to Figure 1 In the embodiment, the current comparator module 1 comprises a differential input sub-module 11, a first mirror sub-module 12, a second mirror sub-module 13 and a shaping sub-module 14. The differential input sub-module 11 is connected to the first mirror sub-module 12 and the second mirror sub-module 13 respectively. The power supply end of the first mirror sub-module 12 and the power supply end of the second mirror sub-module 13 are both connected to the first power supply end VCC. The output end of the first mirror sub-module 12 and the output end of the second mirror sub-module 13 are both connected to the input end of the shaping sub-module 14. The output end of the shaping sub-module 14 is connected to the signal output end OUT.
[0034] Specifically, the first differential input sub-module 11 comprises a first input terminal a1, a second input terminal a2, a bias current output terminal a3, a first differential current output terminal a4 and a second differential current output terminal a5, the first mirror sub-module 12 comprises a first differential current input terminal b1 and a first mirror current output terminal b2, the second mirror sub-module 13 comprises a second differential current input terminal c1 and a second mirror current output terminal c2, the first differential current output terminal a4 is connected to the first differential current input terminal b1, the first mirror current output terminal b2 is connected to an input terminal of the shaping sub-module 14, the second differential current output terminal a5 is connected to the second differential current input terminal c1, the second mirror current output terminal c2 is connected to an input terminal of the shaping sub-module 14, and an output terminal of the shaping sub-module 14 is connected to the output terminal f.
[0035] Further, the differential input sub-module 11 further comprises a MOS transistor M2A and a MOS transistor M2B, a gate of the MOS transistor M2A is connected to the second input terminal a2, a source of the MOS transistor M2A is connected to the bias current input terminal a3, and a drain of the MOS transistor M2A is connected to the first differential current output terminal a4; a gate of the MOS transistor M2B is connected to the first input terminal a1, a source of the MOS transistor M2B is connected to the bias current input terminal a3, and a drain of the MOS transistor M2B is connected to the second differential current output terminal a5.
[0036] Among them, the MOS transistor M2A and the MOS transistor M2B constitute a MOS differential pair.
[0037] In the embodiment, the first mirror sub-module comprises a MOS transistor M3A and a MOS transistor M3B, a drain of the MOS transistor M3A is connected to the first differential current input terminal b1, a source of the MOS transistor M3A is connected to the power supply terminal e, a gate of the MOS transistor M3A is connected to the first differential current input terminal b1 and a gate of the MOS transistor M3B respectively, a source of the MOS transistor M3B is connected to the power supply terminal e, and a drain of the MOS transistor M3B is connected to the first mirror current output terminal b2. Among them, the MOS transistor M3A and the MOS transistor M3B constitute a first current mirror.
[0038] In the embodiment, the high-speed low-power potential translation circuit further comprises a second power supply end VCC5V, and the second mirror sub-module comprises MOS transistor M4A, MOS transistor M4B, MOS transistor M5A and MOS transistor M5B. The drain of the MOS transistor M4A is connected to the second differential current input end c1, the source of the MOS transistor M4A is connected to the power supply end e, the gate of the MOS transistor M4A is connected to the second differential current input end c1 and the gate of the MOS transistor M4B respectively, the source of the MOS transistor M4B is connected to the power supply end e, the drain of the MOS transistor M4B is connected to the drain of the MOS transistor M5A, the source of the MOS transistor M5A is connected to the second power supply end VCC5V, the gate of the MOS transistor M5B is connected to the gate of the MOS transistor M5A, the drain of the MOS transistor M5B is connected to the second mirror current output end c2, and the source of the MOS transistor M5B is connected to the second power supply end VCC5V. The MOS transistor M4A and the MOS transistor M4B constitute a second current mirror, and the MOS transistor M5A and the MOS transistor M5B constitute a third current mirror.
[0039] In the embodiment, the shaping sub-module 14 comprises a Schmitt trigger G, the input ends of the Schmitt trigger G are connected to the first mirror current output end b2 and the second mirror current output end c2 respectively, and the output end of the Schmitt trigger G is connected to the output end f.
[0040] In the embodiment, the first power supply end VCC supplies power for the first current mirror and the second current mirror, the second power supply end VCC5V supplies power for the third current mirror, and the first power supply end VCC and the second power supply end VCC5V also supply power for the Schmitt trigger G. The Schmitt trigger G is used for shaping the current or voltage signal flowing through the MOS transistor M5B and the MOS transistor M3B.
[0041] When the input signal is input to the gate of the MOS transistor M2B through the first input end a1, and the inverted signal is input to the MOS transistor M2A through the second input end a2, the MOS transistor M2A generates a first differential current according to the inverted signal, and inputs the first differential current to the first mirror sub-module 12 through the first differential current output end a4. The first differential current passes through the first current mirror to generate a stable first mirror current. The MOS transistor M2B generates a second differential current according to the input signal, and inputs the second differential current to the second mirror sub-module 13 through the second differential current output end a5, and generates a stable second mirror current through the second current mirror and the third current mirror respectively. Then, the first mirror current and the second mirror current are input to the Schmitt trigger G, and are output through the signal output end OUT after being shaped by the Schmitt trigger G.
[0042] The first mirror current and the second mirror current determine the high or low of the logic level of the input end of the Schmitt trigger G, and then the input logic signal is shaped by the Schmitt trigger G, and is output via the signal output end OUT. When the logic level of the input signal is low side logic of 0V-5V, and the supply voltage of the first current mirror, the second current mirror, the third current mirror and the Schmitt trigger G is high side logic voltage, the low side logic level input by the current comparator module 1 is converted into high side logic level output, that is, the voltage is converted from 0V-5V of the signal input end IN to (VCC5)-VCC of the signal output end OUT.
[0043] In the embodiment, the MOS tube M3A, the MOS tube M3B, the MOS tube M4A and the MOS tube M4B are P-channel MOS tubes, and the MOS tube M2A, the MOS tube M2B, the MOS tube M5A and the MOS tube M5B are N-channel MOS tubes.
[0044] Reference Figure 3 In the embodiment, the potential translation circuit further includes an external current input end Iin, the biasing module 2 includes a third mirror sub-module 21, a reference current input end g1 and a biasing current output end g2; the reference current input end g1 is connected to the external current input end Iin, the biasing current output end g2 is connected to the biasing current input end a3, the input end of the third mirror sub-module 21 is connected to the reference current input end g1, and the output end of the third mirror sub-module 21 is connected to the biasing current output end g2.
[0045] Further, the third mirror sub-module further includes a MOS tube M1A and a MOS tube M1B. The drain of the MOS tube M1A is connected to the reference current input end g1, the source of the MOS tube M1A is connected to the ground end GND, the gate of the MOS tube M1A is connected to the reference current input end g1 and the gate of the MOS tube M1B respectively, the source of the MOS tube M1B is connected to the ground end GND, and the drain of the MOS tube M1B is connected to the biasing current output end g2. Among them, the MOS tube M1A and the MOS tube M1B constitute a fourth current mirror, and the MOS tube M1A and the MOS tube M1B are both N-channel MOS tubes and have the same parameters.
[0046] When the biasing module 2 provides biasing current for the current comparator module 1, the external current input end Iin provides reference current for the fourth current mirror, and then the reference current enters the MOS tube M1A via the reference current input end g1; then the biasing current is generated by the fourth current mirror and is input to the current comparator module 1 by the biasing current output end g2.
[0047] In the embodiment, the dynamic current generating module 3 comprises a third input end d1, a fourth input end d2 and a dynamic current output end d3; the third input end d1 is connected to the input end of the first inverter IV1, the fourth input end d2 is connected to the output end of the first inverter IV1, and the dynamic current output end d3 is connected to the bias current input end a3; specifically, the dynamic current generating module 3 further comprises a second inverter IV2, a third inverter IV3, a first energy storage element and a second energy storage element; the input end of the second inverter IV2 is connected to the third input end d1, the output end of the second inverter IV2 is connected to one end of the first energy storage element, and the power supply end of the second inverter IV2 and the other end of the first energy storage element are both connected to the bias current input end a3; the input end of the third inverter IV3 is connected to the fourth input end d2, the output end of the third inverter IV3 is connected to one end of the second energy storage element, and the power supply end of the third inverter IV3 and the other end of the second energy storage element are both connected to the bias current input end a3.
[0048] In the embodiment, the first energy storage element is a capacitor C1, and the second energy storage element is a capacitor C2.
[0049] Specifically, the second inverter IV2 comprises a MOS tube M6B and a MOS tube M6A; the gate of the MOS tube M6A and the gate of the MOS tube M6B are both connected to the third input end d1, the source of the MOS tube M6A is connected to the ground end GND, the drain of the MOS tube M6A is connected to the drain of the MOS tube M6B, the source of the MOS tube M6B is connected to the dynamic current output end d3, and the source of the MOS tube M6B is further connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to the dynamic current output end d3.
[0050] The third inverter IV3 comprises a MOS tube M7B and a MOS tube M7A; the gate of the MOS tube M7A and the gate of the MOS tube M7B are both connected to the third input end d1, the source of the MOS tube M7A is connected to the ground end GND, the drain of the MOS tube M7A is connected to the drain of the MOS tube M7B, the source of the MOS tube M7B is connected to the dynamic current output end d3, and the source of the MOS tube M7B is further connected to one end of the capacitor C2, and the other end of the capacitor C2 is connected to the dynamic current output end d3.
[0051] In the embodiment, the MOS tube M6A and the MOS tube M7A are both N-channel MOS tubes, and the MOS tube M6B and the MOS tube M7B are both P-channel MOS tubes.
[0052] When the input signal of the signal input terminal IN is converted from low level to high level, at this time, the MOS transistor M6A and the MOS transistor M7B are turned on, the MOS transistor M6B and the MOS transistor M7A are turned off, the capacitor C1 is in a charging state, the capacitor C2 is in a discharging state, the current for charging the capacitor C1 flows through the current comparator module 1, so that the current flowing through the differential pair M2AM2B is increased; the current for discharging the capacitor C2 flows through the MOS transistor M7A, which is almost equal to the switching current of the MOS transistor M7A, and does not affect the current flowing through the differential pair M2AM2B, so that the amplitude and duration of the current can be controlled by controlling the capacity of the capacitor C1, and then the bias current provided by the biasing module 2 is indirectly reduced, so that the static loss of the current comparator module 1 is reduced.
[0053] When the input signal of the signal input terminal IN is converted from high level to low level, at this time, the MOS transistor M6B and the MOS transistor M7A are turned on, the MOS transistor M7B and the MOS transistor M6A are turned off, the capacitor C2 is in a charging state, the capacitor C1 is in a discharging state, the current for charging the capacitor C2 flows through the current comparator module 1, so that the current flowing through the differential pair M2AM2B is increased; the current for discharging the capacitor C1 flows through the MOS transistor M6A, which is almost equal to the switching current of the MOS transistor M6A, and does not affect the current flowing through the differential pair M2AM2B.
[0054] From the above principle, it can be seen that the dynamic current generating module 3 only provides dynamic current for the current comparator module 1 at the moment of input signal change, compared with the previous bias current provided by the biasing module 2, the conversion speed is improved, and the dynamic current generating module 3 does not generate any loss after the conversion is completed, and at the same time, the bias current can be reduced, so as to reduce the static power consumption.
[0055] The above are preferred embodiments of the present application, and are not intended to limit the protection scope of the present application, any feature disclosed in the specification (including the abstract and the drawings) can be replaced by other equivalent or similar features, unless specifically described. That is, each feature is only an example of a series of equivalent or similar features, unless specifically described.
Claims
1. A high-speed, low-power potential shifting circuit, characterized in that, The system includes a current comparator module (1), a bias module (2), a dynamic current generation module (3), a first inverter IV1, a first power supply terminal VCC, a signal input terminal IN, and a signal output terminal OUT. The current comparator module (1) includes a first input terminal a1, a second input terminal a2, a bias current input terminal a3, a power supply terminal e, and an output terminal f. The first input terminal a1 is connected to the signal input terminal IN, and the signal input terminal IN is also connected to the input terminal of the first inverter IV1. The output terminal of the first inverter IV1 is connected to the second input terminal a2. The bias current input terminal a3 is connected to the bias module (2) and the dynamic current generation module (3) respectively. The power supply terminal e is connected to the first power supply terminal VCC, and the output terminal f is connected to the signal output terminal OUT. The dynamic current generation module (3) includes a third input terminal d1, a fourth input terminal d2, and a dynamic current output terminal d3; The third input terminal d1 is connected to the input terminal of the first inverter IV1, the fourth input terminal d2 is connected to the output terminal of the first inverter IV1, and the dynamic current output terminal d3 is connected to the bias current input terminal a3. The bias module (2) is used to provide bias current; The dynamic current generation module (3) includes a second inverter IV2 and a first energy storage element. The input terminal of the second inverter IV2 is connected to the third input terminal d1. The power supply terminal of the second inverter IV2 is connected to the dynamic current output terminal d3. The output terminal of the second inverter IV2 is connected to one end of the first energy storage element. The other end of the first energy storage element is connected to the dynamic current output terminal d3. The dynamic current generation module (3) further includes a third inverter IV3 and a second energy storage element. The input terminal of the third inverter IV3 is connected to the fourth input terminal d2. The power supply terminal of the third inverter IV3 is connected to the dynamic current output terminal d3. The output terminal of the third inverter IV3 is connected to one end of the second energy storage element, and the other end of the second energy storage element is connected to the dynamic current output terminal d3. The dynamic current generation module (3) is used to control the charging and discharging of the first energy storage element and the second energy storage element through the second inverter IV2 and the third inverter IV3 when the input signal changes, so as to provide instantaneous dynamic current for the current comparator module (1) to improve the potential shift speed and reduce static power consumption.
2. The high-speed, low-power potential shifting circuit according to claim 1, characterized in that, The second inverter IV2 includes MOSFETs M6A and M6B. The gates of MOSFETs M6A and M6B are both connected to the third input terminal d1. The source of MOSFET M6A is connected to ground terminal GND. The drain of MOSFET M6A is connected to the drain of MOSFET M6B. The drains of MOSFETs M6A and M6B are both connected to the first energy storage element. The source of MOSFET M6B is connected to the dynamic current output terminal d3.
3. The high-speed, low-power potential shifting circuit according to claim 1, characterized in that, The third inverter IV3 includes MOSFETs M7A and M7B. The gates of MOSFETs M7A and M7B are both connected to the fourth input terminal d2. The source of MOSFET M7A is connected to ground terminal GND. The drain of MOSFET M7A is connected to the drain of MOSFET M7B. The drains of MOSFETs M7A and M7B are both connected to the second energy storage element. The source of MOSFET M7B is connected to the dynamic current output terminal d3.
4. The high-speed, low-power potential shifting circuit according to claim 1, characterized in that, The current comparator module (1) includes a differential input submodule (11), a first mirror submodule (12), a second mirror submodule (13), and a shaping submodule (14). The differential input submodule (11) includes a first input terminal a1, a second input terminal a2, a bias current input terminal a3, a first differential current output terminal a4, and a second differential current output terminal a5. The first mirror submodule (12) includes a first differential current input terminal b1 and a first mirror current output terminal b2. The second mirror submodule (13) includes a second differential current input terminal c1 and a second mirror current output terminal c2. The first differential current output terminal a4 is connected to the first differential current input terminal b1. The first mirror current output terminal b2 is connected to the input terminal of the shaping submodule (14). The second differential current output terminal a5 is connected to the second differential current input terminal c1. The second mirror current output terminal c2 is connected to the input terminal of the shaping submodule (14). The output terminal of the shaping submodule (14) is connected to the output terminal f.
5. The high-speed, low-power potential shifting circuit according to claim 1, characterized in that, The circuit also includes an external current input terminal Iin. The bias module (2) includes a third mirror submodule (21), a reference current input terminal g1, and a bias current output terminal g2. The reference current input terminal g1 is connected to the external current input terminal Iin. The bias current output terminal g2 is connected to the bias current input terminal a3. The input terminal of the third mirror submodule (21) is connected to the reference current input terminal g1. The output terminal of the third mirror submodule (21) is connected to the bias current output terminal g2.
6. The high-speed, low-power potential shifting circuit according to claim 5, characterized in that, The third mirror submodule (21) further includes MOS transistor M1A and MOS transistor M1B. The drain of MOS transistor M1A is connected to the reference current input terminal g1, the source of MOS transistor M1A is connected to the ground terminal GND, the gate of MOS transistor M1A is connected to the gate of M1B, the source of MOS transistor M1B is connected to the ground terminal GND, and the drain of MOS transistor M1B is connected to the bias current output terminal g2.
Citation Information
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