A phase-locked loop circuit and circuit board assembly with interruption-free switching

Abstract

Embodiments of the present invention relate to the field of electronic circuits and disclose a phase-locked loop circuit and circuit board assembly with interruptionless switching. The circuit includes a phase detector circuit, a charge pump, a filter, a voltage-controlled oscillator, and a frequency divider. The phase detector circuit is used to determine a reference clock signal corresponding to the control signal based on a control signal received from a control terminal of the phase detector circuit. The phase detector circuit is also used to calculate the phase error width between the reference clock signal corresponding to the control signal and a feedback signal input to the frequency divider. When the phase error width is greater than a preset time width, the phase detector circuit outputs a signal with a width of the preset time width; when the phase error width is less than or equal to the preset time width, the phase detector circuit outputs a signal with a width of the phase error width. In this embodiment, by configuring the phase detector circuit to only output signals with a width less than or equal to the preset time width to the charge pump, the phase-locked loop is controlled to gradually adjust the phase of the phase-locked loop output in a certain step, effectively improving the stability of the data communication function.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of electronic circuits, and in particular to a phase-locked loop circuit and a circuit board assembly with interruption-free switching. Background Art

[0002] With the development of microelectronics technology, the frequency and performance of microprocessors and workstation systems have increased, placing increasingly higher demands on the design of system clock generation circuits. Phase-locked loops (PLLs), as a common design technology, are widely used in system-on-chip (SOC) clock generation circuits.

[0003] Usually a selector is also provided in the phase-locked loop circuit. Technicians can control the selector to select the required reference clock signal as the output reference signal, or switch to the required reference clock signal as the output reference signal, and input the output reference signal into the phase-locked loop through the phase detector.

[0004] During the switching process of the reference clock signal, the phase error between the switched reference clock signal and the feedback signal of the phase-locked loop may be large, which will cause the input voltage of the voltage-controlled oscillator (VCO) in the phase-locked loop to attenuate oscillation, and then cause the output phase of the VCO to change dramatically in a short period of time. In some applications, this change will seriously affect the data communication function. Summary of the Invention

[0005] The purpose of the embodiments of the present invention is to provide a phase-locked loop circuit and circuit board assembly with uninterrupted switching, which greatly reduces the amplitude of the output phase change of the voltage-controlled oscillator and effectively improves the stability of the data communication function.

[0006] To solve the above technical problems, an embodiment of the present invention provides a phase-locked loop circuit with interruptionless switching, comprising: a phase detector circuit, a charge pump, a filter, a voltage-controlled oscillator, and a frequency divider. The phase detector circuit has N first input terminals serving as input terminals of the phase-locked loop circuit, where N is an integer greater than 1. The output terminal of the phase detector circuit is connected to the charge pump, which is connected to the filter, which is connected to the input terminal of the voltage-controlled oscillator. The output terminal of the voltage-controlled oscillator serves as the output terminal of the phase-locked loop circuit. The output terminal of the voltage-controlled oscillator is also connected to the input terminal of the frequency divider, and the output terminal of the frequency divider is connected to a second input terminal of the phase detector circuit. The N first input terminals of the phase detector circuit are configured to receive a reference clock signal. The phase detector circuit is configured to determine a reference clock signal corresponding to the control signal based on a control signal received from a control terminal of the phase detector circuit. The phase detector circuit is further configured to calculate a phase error width between the reference clock signal corresponding to the control signal and a feedback signal input to the frequency divider, and output a signal having a width of the preset time width when the phase error width is greater than a preset time width; and output a signal having a width of the phase error width when the phase error width is less than or equal to the preset time width.

[0007] An embodiment of the present invention further provides a phase-locked loop circuit with interruptionless switching, comprising: N phase-detection modules, N charge pumps, a selector, a filter, a voltage-controlled oscillator, and a frequency divider, wherein N is an integer greater than 1; a first input end of the phase-detection module serves as an input end of the phase-locked loop circuit, an output end of the phase-detection module is connected to the charge pump, an output end of the charge pump is connected to the selector, an output end of the selector is connected to the filter, the filter is connected to an input end of the voltage-controlled oscillator, an output end of the voltage-controlled oscillator serves as an output end of the phase-locked loop circuit, an output end of the voltage-controlled oscillator is further connected to an input end of the frequency divider, an output end of the frequency divider is connected to a second input end of the phase-detection module, and the first input end of the phase-detection module is used to receive a reference clock signal; the phase-detection module is used to calculate a phase error width between the reference clock signal and a feedback signal input by the frequency divider, and output a signal having a width of the preset time width when the phase error width is greater than a preset time width; and output a signal having a width of the phase error width when the phase error width is less than or equal to the preset time width; and the selector is used to output a signal corresponding to the control signal based on a control signal received from a control end of the selector.

[0008] An embodiment of the present invention further provides a circuit board assembly, comprising any of the above-mentioned interruption-free switching phase-locked loop circuits.

[0009] In the embodiment of the present invention, a phase-detection circuit is provided to calculate the phase error width between the reference clock signal and the feedback signal after switching. When the phase error width used for adjustment is too large, specifically when the phase error width is greater than a preset time width, only a signal with a width of the preset time width is output to the charge pump. Technicians can control the phase-locked loop to gradually adjust the phase of the phase-locked loop output in a certain step by setting the preset time width, thereby greatly reducing the amplitude of the output phase change of the voltage-controlled oscillator and effectively improving the stability of the data communication function.

[0010] In some embodiments, a phase detection circuit includes a selector and a phase detection module; the N first input terminals of the selector serve as the N first input terminals of the phase detection circuit, the control terminal of the selector serves as the control terminal of the phase detection circuit, the output terminal of the selector is connected to the first input terminal of the phase detection module, the second input terminal of the phase detection module serves as the second input terminal of the phase detection circuit, and the output terminal of the phase detection module serves as the output terminal of the phase detection circuit; the selector is configured to determine a reference clock signal corresponding to the output control signal based on a control signal received from the control terminal of the selector; the phase detection module is configured to calculate the phase error width between the reference clock signal corresponding to the control signal and a feedback signal, and output a signal with a width of the preset time width when the phase error width is greater than a preset time width; and output a signal with a width of the phase error width when the phase error width is less than or equal to the preset time width. This embodiment provides a specific circuit structure of a phase detection circuit.

[0011] In some embodiments, a phase detection circuit includes a selector and N phase detection modules; a first input terminal of each phase detection module serves as the first input terminal of the phase detection circuit, a second input terminal of each phase detection module serves as the second input terminal of the phase detection circuit, an output terminal of each phase detection module is connected to the N input terminals of the selector, and a control terminal of the selector serves as a control terminal of the phase detection circuit; the phase detection module is configured to calculate the phase error width between a reference clock signal and a feedback signal, and output a signal having a preset time width when the phase error width is greater than a preset time width; and output a signal having a phase error width when the phase error width is less than or equal to the preset time width; the selector is configured to output a signal corresponding to the control signal based on a control signal received from the control terminal of the phase detection circuit. This embodiment provides another specific circuit structure of a phase detection circuit.

[0012] In some embodiments, the phase detector module includes: a phase detector, a first delay module, a second delay module, a first NOT gate, a second NOT gate, a first AND gate, and a second AND gate; the first input end of the phase detector serves as the first input end of the phase detector module, the second input end of the phase detector serves as the second input end of the phase detector module, the uplink output end of the phase detector is connected to the input end of the first delay module, the output end of the first delay module is connected to the first NOT gate, the first NOT gate is connected to the first input end of the first AND gate, the uplink output end of the phase detector is also connected to the second input end of the first AND gate, the downlink output end of the phase detector is connected to the input end of the second delay module, the output end of the second delay module is connected to the second NOT gate, the second NOT gate is connected to the first input end of the second AND gate, the downlink output end of the phase detector is also connected to the second input end of the second AND gate, the output end of the first AND gate and the output end of the second AND gate serve as the output end of the phase detector module; the first delay module is configured to output the signal received from the input end of the first delay module after a preset time width; the second delay module is configured to output the signal received from the input end of the second delay module after a preset time width. In this embodiment, a specific circuit structure of a phase detection module is provided.

[0013] In some embodiments, the phase detector module includes: a first phase detector, a second phase detector, a third delay module, a fourth delay module, a third NOT gate, a fourth NOT gate, a third AND gate, and a fourth AND gate; the first input end of the first phase detector serves as the first input end of the phase detector module, the second input end of the first phase detector serves as the second input end of the phase detector module, the uplink output end of the first phase detector is connected to the third NOT gate, the third NOT gate is connected to the first input end of the third AND gate, the downlink output end of the first phase detector is connected to the fourth NOT gate, the fourth NOT gate is connected to the first input end of the fourth AND gate, the input end of the third delay module is connected to the first input end of the first phase detector, and the output end of the third delay module is connected to the first input end of the first phase detector. The output end is connected to the first input end of the second phase detector, the input end of the fourth delay module is connected to the second input end of the first phase detector, the output end of the fourth delay module is connected to the second input end of the second phase detector, the upstream output end of the second phase detector is connected to the second input end of the third AND gate, the downstream output end of the second phase detector is connected to the second input end of the fourth AND gate, and the output end of the third AND gate and the output end of the fourth AND gate serve as the output end of the phase detector module; the third delay module is configured to output the signal received from the input end of the third delay module after a preset time width; and the fourth delay module is configured to output the signal received from the input end of the fourth delay module after a preset time width. This embodiment provides another specific circuit structure of the phase detector module. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0015] Figure 1 is a structural diagram of a phase-locked loop circuit according to the related technology of this application;

[0016] Figure 2 Schematic diagram of input or output waveforms corresponding to various components in a phase-locked loop circuit according to the related technology of this application;

[0017] Figure 3 This is a schematic diagram of the structure of a phase-locked loop circuit for interruption-free switching according to an embodiment of the present application. Figure 1 ;

[0018] Figure 4 1 is a schematic diagram of input or output waveforms corresponding to various components in a phase-locked loop circuit with interruptionless switching according to an embodiment of the present application;

[0019] Figure 5 This is a schematic diagram of the structure of a phase-locked loop circuit for interruption-free switching according to an embodiment of the present application. Figure 2 ;

[0020] Figure 6 This is a schematic diagram of the structure of the phase detection module in the phase-locked loop circuit with uninterrupted switching according to an embodiment of the present application. Figure 1 ;

[0021] Figure 7 In a phase-locked loop circuit for interruption-free switching according to an embodiment of the present application Figure 6 The waveform diagram of the corresponding phase detection module;

[0022] Figure 8 This is a schematic diagram of the structure of the phase detection module in the phase-locked loop circuit with uninterrupted switching according to an embodiment of the present application. Figure 2 ;

[0023] Figure 9 In a phase-locked loop circuit for interruption-free switching according to an embodiment of the present application Figure 8 The waveform diagram of the corresponding phase detection module;

[0024] Figure 10 This is a schematic diagram of the structure of a phase-locked loop circuit for interruption-free switching according to an embodiment of the present application. Figure 3 . DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with each other and referenced to each other under the premise that there is no contradiction.

[0026] With the development of microelectronics technology, the frequency and performance of microprocessors and workstation systems have increased, placing increasingly higher demands on the design of system clock generation circuits. Phase-locked loops (PLLs), as a common design technology, are widely used in system-on-chip (SOC) clock generation circuits.

[0027] Usually a selector is also provided in the phase-locked loop circuit. Technicians can control the selector to select the required reference clock signal as the output reference signal, or switch to the required reference clock signal as the output reference signal, and input the output reference signal into the phase-locked loop through the phase detector.

[0028] The inventors discovered that in the process of switching the reference clock signal, the phase error between the switched reference clock signal and the feedback signal fed back by the phase-locked loop may be large, which will cause the input voltage of the voltage-controlled oscillator in the phase-locked loop to exhibit attenuated oscillations, and in turn cause the output phase of the voltage-controlled oscillator to change dramatically in a short period of time. This is mainly because the phase-locked loop adjusts the output phase based on the phase error between the currently input reference clock signal and the feedback signal. The larger the phase error, the faster the adjustment speed, and the greater the change in the output phase of the voltage-controlled oscillator. In some applications, this change will seriously affect the data communication function.

[0029] For example, see Figure 1 The structure of the phase-locked loop circuit of the related art includes a selector 01, a phase detector 02, a charge pump 03, a filter 04, a voltage-controlled oscillator 05 and a frequency divider 06. When the reference clock signal input to the phase detector 02 is switched by the selector 01, the input or output waveforms corresponding to each component are shown in the figure below. Figure 2 shown.

[0030] exist Figure 2In the figure, sw_ref is the signal received by the control end of the selector 01, which is used to select the corresponding reference clock signal and output it to the phase detector 02 according to the signal. Both clk_ref0 and clk_ref1 are reference clock signals. clk_ref is the reference clock signal actually output to the phase detector 02. up / dn is the signal output by the phase detector 02 to the charge pump 03. vtune is the signal received by the input end of the voltage-controlled oscillator 05. clk_vco is the clock signal output by the voltage-controlled oscillator 05. phi_vco is the phase of the clock signal output by the voltage-controlled oscillator 05. clk_fb is the feedback signal input to the phase detector 02 by the frequency divider 06.

[0031] When sw_ref is low, it is considered that clk_ref = clk_ref0. After the phase-locked loop circuit is stable, it is considered that the feedback signal clk_fb = clk_ref0. When sw_ref is switched to a high level, it is considered that clk_ref = clk_ref1. However, clk_fb is still equal to clk_ref0. The signal up / dn is positively correlated with the phase error between clk_ref1 and clk_fb. If the phase error between clk_ref1 and clk_fb is too large, the time width of up / dn being at a high level will also be longer, and the input vtune of the voltage-controlled oscillator 05 will change significantly, which will cause a significant change in the output phase phi_vco of the voltage-controlled oscillator. Please refer to Figure 2 The waveform diagram of phi_vco shows that when phi_vco changes within the preset slope range, it can be considered that the phase-locked loop circuit is currently in an uninterrupted switching state. It can be seen that phi_vco in the related art has exceeded the preset slope range, that is, the phase-locked loop circuit in the related art is not currently in a non-switching state. In some applications, this change will seriously affect the data communication function.

[0032] In response to the above technical problems, the present application proposes the following technical concept: a phase-locked loop is set up to calculate the phase error width between the switched reference clock signal and the feedback signal, and when the phase error width used for adjustment is too large, specifically when the phase error width is greater than a preset time width, only a signal with a width of the preset time width is output to the charge pump. Technicians can control the phase-locked loop to gradually adjust the phase of the phase-locked loop output in a certain step by setting the preset time width, which greatly weakens the amplitude of the output phase of the voltage-controlled oscillator and effectively improves the stability of the data communication function.

[0033] One embodiment of the present invention relates to a phase-locked loop circuit with interruption-free switching. Figure 3 The circuit includes a phase detection circuit 1, a charge pump 2, a filter 3, a voltage-controlled oscillator 4 and a frequency divider 5.

[0034] The circuit structure is as follows: the N first input terminals of the phase detection circuit 1 serve as the input terminals of the phase-locked loop circuit, where N is an integer greater than 1. Figure 3 In the figure, the phase detection circuit 1 has two first input terminals as an example. The output terminal of the phase detection circuit 1 is connected to the charge pump 2, the charge pump 2 is connected to the filter 3, the filter 3 is connected to the input terminal of the voltage-controlled oscillator 4, the output terminal of the voltage-controlled oscillator 4 serves as the output terminal of the phase-locked loop circuit, the output terminal of the voltage-controlled oscillator 4 is also connected to the input terminal of the frequency divider 5, and the output terminal of the frequency divider 5 is connected to the second input terminal of the phase detection circuit 1. The N first input terminals of the phase detection circuit 1 are used to receive a reference clock signal.

[0035] The phase detection circuit 1 will determine the reference clock signal corresponding to the control signal based on the control signal received from the control end of the phase detection circuit 1. The phase detection circuit 1 will also calculate the phase error width between the reference clock signal corresponding to the control signal and the feedback signal input by the frequency divider 5, and when the phase error width is greater than the preset time width, the phase detection circuit 1 outputs a signal with a width of the preset time width; when the phase error width is less than or equal to the preset time width, the phase detection circuit 1 outputs a signal with a width of the phase error width.

[0036] In this embodiment, a phase-detection circuit is provided to calculate the phase error width between the switched reference clock signal and the feedback signal. When the phase error width used for adjustment is too large, specifically when the phase error width is greater than a preset time width, only a signal with a width of the preset time width is output to the charge pump. Technicians can control the phase-locked loop to gradually adjust the phase of the phase-locked loop output in a certain step by setting the preset time width, thereby greatly reducing the amplitude of the output phase change of the voltage-controlled oscillator and effectively improving the stability of the data communication function.

[0037] The following is a detailed description of the implementation details of the interruption-free switching phase-locked loop circuit of this embodiment. The following content is only provided for easy understanding of the implementation details and is not necessary for implementing this solution.

[0038] The charge pump 2 can be used to convert the voltage signal output by the phase detection circuit 1 into a current signal.

[0039] The filter 3 is a loop filter, which may be an RC integral filter, a proportional integral filter, an active integral filter, etc., and is used to integrate and filter the current signal to complete the conversion from the current signal to the voltage signal.

[0040] The voltage controlled oscillator 4 is configured to output a clock signal clk_vco according to the voltage signal input by the filter 3 . The clock signal clk_vco includes frequency information freq_vco and phase information phi_vco.

[0041] The frequency divider 5 is used to divide the input clock signal clk_vco according to a set frequency division ratio, and output the divided clock signal clk_fb.

[0042] In some embodiments, the reference clock signals received by the N first input terminals of the phase detection circuit 1 have the same frequency and only differ in phase.

[0043] In some embodiments, a specific circuit structure of the phase detection circuit 1 is provided. Please refer to Figure 3 The phase detection circuit 1 includes a selector 11 and a phase detection module 12.

[0044] The N first input terminals of the selector 11 serve as the N first input terminals of the phase detection circuit 1, the control terminal of the selector 11 serves as the control terminal of the phase detection circuit 1, the output terminal of the selector 11 is connected to the first input terminal of the phase detection module 12, the second input terminal of the phase detection module 12 serves as the second input terminal of the phase detection circuit 1, and the output terminal of the phase detection module 12 serves as the output terminal of the phase detection circuit 1.

[0045] The selector 11 determines to output a reference clock signal corresponding to the control signal according to the control signal received from the control terminal of the selector 11 .

[0046] Specifically, there is a preset correspondence between different input terminals of the selector 11 and the control signals. Taking the case where two input terminals are provided on the selector 11 as an example, one of the input terminals receives the reference clock signal clk_ref0, and the other input terminal receives the reference clock signal clk_ref1. When the control signal sw_ref received by the control terminal of the selector 11 is 0, the selector 11 outputs the reference clock signal clk_ref=clk_ref0; when the control signal sw_ref received by the control terminal of the selector 11 is 1, the selector 11 outputs the reference clock signal clk_ref=clk_ref1, wherein the corresponding relationship can be set as needed.

[0047] Phase detector module 12 calculates the phase error width between reference clock signal clk_ref, corresponding to the control signal, and feedback signal clk_fb. When the phase error width is greater than a preset time width t_del, it outputs a signal with a width equal to the preset time width t_del. When the phase error width is less than or equal to the preset time width t_del, it outputs a signal with a width equal to the phase error width. Thus, phase detector module 12 acts as a module that limits the output signal width, outputting only signals with a width less than or equal to the preset time width t_del. This allows for relatively slow adjustment of the output phase of the entire phase-locked loop to ensure seamless switching of the output phase.

[0048] To more clearly compare the differences between the related art and the solution provided in the embodiment of the present application, please refer to Figure 2 As shown in the waveform diagram of the related art, when the control signal sw_ref = 0, the selector 11 determines that the current reference clock signal clk_ref = clk_ref0 and outputs clk_ref0 to the phase detector module 12. When the switching control signal sw_ref = 1, the selector 11 determines that the current reference clock signal clk_ref = clk_ref1 and outputs clk_ref1 to the phase detector module 12. Due to the hysteresis of the feedback loop, at the moment the reference clock signal is switched, the feedback signal clk_fb output by the frequency divider 5 to the phase detector module 12 is still clk_ref0. At this time, the signals input to the two input terminals of the phase detector module 12 are clk_ref1 and clk_ref0 respectively. The feedback loop will adjust according to the difference between clk_ref1 and clk_ref0 until the signals input to the two input terminals of the phase detector module 12 are both the switched clk_ref1, that is, the phase difference between clk_ref1 and clk_ref0 is adjusted until the phase difference is zero.

[0049] The up / dn signals in the waveform diagram represent the signals output by phase detector circuit 1 to charge pump 2. As can be seen from the waveform diagram, after the reference clock signal is switched, the output up / dn is a wide positive pulse signal. As the reference clock signal is adjusted, this positive pulse signal decreases. Due to over-adjustment, the up / dn output of phase detector circuit 1 may even output a negative pulse signal to adjust the reference clock signal so that both inputs of phase detector module 12 are fed with the switched clk_ref1. As the up / dn signals change, the signal vtune input to voltage-controlled oscillator 4 by filter 3 also changes accordingly. Because up / dn is a wide positive pulse signal in the initial switching phase, this signal causes a significant change in vtune, leading to significant changes in the frequency clk_vco and phase phi_vco of the voltage-controlled oscillator 4's output signal. For a phase-locked loop circuit, significant changes in the output phase phi_vco during the reference clock signal switching process can seriously impact data communication functionality.

[0050] Please refer to Figure 4The waveform diagram of the embodiment of the present application is compared with the related art. After switching the reference clock signal, a positive pulse signal with a large width will be output as up / dn. The phase detection circuit 1 of the present application, specifically the phase detection module 12, will limit the output up / dn, so that the output up / dn is always less than or equal to the preset time width t_del. Specifically, the phase detection module 12 will calculate the phase error width between the reference clock signal clk_ref and the feedback signal clk_fb, and when the phase error width is greater than the preset time width t_del, the output width is a signal of the preset time width t_del; when the phase error width is less than or equal to the preset time width t_del, the output width is a signal of the phase error width. Technicians can control the phase-locked loop to gradually adjust the phase of the phase-locked loop output in a certain step by setting the preset time width, which greatly weakens the amplitude of the output phase of the voltage-controlled oscillator and effectively improves the stability of the data communication function. Please refer to Figure 4 Since the pulse width of the output up / dn is small, the variation of vtune is also small, and thus the variation of the frequency clk_vco and phase phi_vco of the output signal of the voltage-controlled oscillator 4 is also small. It can be roughly considered that the phase-locked loop circuit can achieve uninterrupted switching during the switching of the reference clock signal, effectively improving the stability of the data communication function.

[0051] In some embodiments, another specific circuit structure of the phase detection circuit 1 is provided. Figure 5 The phase detection circuit 1 includes a selector 11 and N phase detection modules 12.

[0052] The first input end of the phase detection module 12 serves as the first input end of the phase detection circuit 1, the second input end of the phase detection module 12 serves as the second input end of the phase detection circuit 1, the output end of the phase detection module 12 is connected to the N input ends of the selector 11, and the control end of the selector 11 serves as the control end of the phase detection circuit 1. Figure 5 In the figure, the phase detection circuit 1 includes two phase detection modules 12 and the selector 11 includes two input terminals.

[0053] The phase detection module 12 calculates the phase error width between the reference clock signal and the feedback signal, and outputs a signal with a width of the preset time width when the phase error width is greater than the preset time width; when the phase error width is less than or equal to the preset time width, it outputs a signal with a width of the phase error width. The selector 11 outputs a signal corresponding to the control signal based on the control signal received from the control end of the phase detection circuit 1.

[0054] In some embodiments, a specific circuit structure of the phase detection module 12 is provided. Figure 6The phase detector module 12 includes: a phase detector 121, a first delay module 122, a second delay module 123, a first NOT gate 124, a second NOT gate 125, a first AND gate 126 and a second AND gate 127.

[0055] The circuit structure is as follows: the first input end of the phase detector 121 serves as the first input end of the phase detector module 12, the second input end of the phase detector 121 serves as the second input end of the phase detector module 12, the uplink output end of the phase detector 121 is connected to the input end of the first delay module 122, the output end of the first delay module 122 is connected to the first NOT gate 124, the first NOT gate 124 is connected to the first input end of the first AND gate 126, the uplink output end of the phase detector 121 is also connected to the second input end of the first AND gate 126, the downlink output end of the phase detector 121 is connected to the input end of the second delay module 123, the output end of the second delay module 123 is connected to the second NOT gate 125, the second NOT gate 125 is connected to the first input end of the second AND gate 127, the downlink output end of the phase detector 121 is also connected to the second input end of the second AND gate 127, the output end of the first AND gate 126 and the output end of the second AND gate 127 serve as the output end of the phase detector module 12.

[0056] The first delay module 122 outputs the signal received from the input end of the first delay module 122 after a preset time width, and the second delay module 123 outputs the signal received from the input end of the second delay module 123 after a preset time width.

[0057] The working principle of the phase detection module 12 is described below in conjunction with the specific circuit structure of the phase detection module 12. Figure 7 , wherein up_e and dn_e refer to the signals output from the uplink output terminal and the downlink output terminal of the phase detector 121, respectively, up_d refers to the signal output from the first delay module 122, dn_d refers to the signal output from the second delay module 123, up is the signal output from the first AND gate 126, and dn is the signal output from the second AND gate 127. Figure 7 The waveform on the left is the waveform of up_e, dn_e, up_d, dn_d, up, and dn when clk_ref leads clk_fb and the phase error is greater than the preset time width t_del; Figure 7 The middle waveform is the waveform of up_e, dn_e, up_d, dn_d, up, and dn when clk_ref lags clk_fb and the phase error is greater than the preset time width t_del; Figure 7The waveforms on the right show the waveforms of up_e, dn_e, up_d, dn_d, up, and dn when clk_ref lags clk_fb and the phase error is less than the preset time width t_del. It should be noted that for phase detector 121, both the uplink and downlink output terminals require a time width ton for the output level to reach a low level. However, for up and dn, the time width ton exists simultaneously, thus offsetting the effect of the time width ton on up and dn.

[0058] In some embodiments, another specific circuit structure of the phase detector module 12 is provided. Figure 8 The phase detector module 12 includes: a first phase detector 128, a second phase detector 129, a third delay module 130, a fourth delay module 131, a third NOT gate 132, a fourth NOT gate 133, a third AND gate 134 and a fourth AND gate 135.

[0059] The circuit structure is as follows: the first input end of the first phase detector 128 serves as the first input end of the phase detector module 12, the second input end of the first phase detector 128 serves as the second input end of the phase detector module 12, the uplink output end of the first phase detector 128 is connected to the third NOT gate 132, the third NOT gate 132 is connected to the first input end of the third AND gate 134, the downlink output end of the first phase detector 128 is connected to the fourth NOT gate 133, the fourth NOT gate 133 is connected to the first input end of the fourth AND gate 135, and the input end of the third delay module 130 is connected to the first input end of the first phase detector 128. The output end of the third delay module 130 is connected to the first input end of the second phase detector 129, the input end of the fourth delay module 131 is connected to the second input end of the first phase detector 128, the output end of the fourth delay module 131 is connected to the second input end of the second phase detector 129, the uplink output end of the second phase detector 129 is connected to the second input end of the third AND gate 134, the downlink output end of the second phase detector 129 is connected to the second input end of the fourth AND gate 135, and the output end of the third AND gate 134 and the output end of the fourth AND gate 135 serve as the output end of the phase detector module 12.

[0060] The third delay module 130 outputs the signal received from the input end of the third delay module 130 after a preset time width, and the fourth delay module 131 outputs the signal received from the input end of the fourth delay module 131 after a preset time width.

[0061] The working principle of the phase detection module 12 is described below in conjunction with the specific circuit structure of the phase detection module 12. Figure 9, wherein up_e and dn_e refer to the signals output from the uplink output terminal and the downlink output terminal of the first phase detector 128, respectively, up_d and dn_d refer to the signals output from the uplink output terminal and the downlink output terminal of the second phase detector 129, respectively, up is the signal output from the third AND gate 134, and dn is the signal output from the fourth AND gate 135. Figure 9 The waveform on the left is the waveform of up_e, dn_e, up_d, dn_d, up, and dn when clk_ref leads clk_fb and the phase error is greater than the preset time width t_del; Figure 9 The waveform on the right is the waveform of up_e, dn_e, up_d, dn_d, up and dn when clk_ref lags clk_fb and the phase error is greater than the preset time width t_del. Figure 9 The waveform diagram when the phase error is less than the preset time width t_del is not shown in the figure, but the waveform pattern is the same as above. It should be noted that for the first phase detector 128 and the second phase detector 129, when outputting pulse signals from both the uplink output terminal and the downlink output terminal, the output level needs to change to a low level after a time width ton has passed. However, for up and dn, the time width ton exists simultaneously, thus canceling out the effect of the time width ton on up and dn.

[0062] In some embodiments, the phase detector may be replaced by a phase frequency detector, which can not only identify the phase difference between reference clock signals with the same frequency but different phases, but also identify the frequency sequence of reference clock signals with different frequencies.

[0063] Another embodiment of the present invention relates to a phase-locked loop circuit with interruption-free switching. Figure 10 , comprising: N phase detection modules 12, N charge pumps 2, a selector 11, a filter 3, a voltage controlled oscillator 4 and a frequency divider 5, wherein N is an integer greater than 1, Figure 10 In the figure, N=2 is taken as an example.

[0064] The circuit structure is as follows: a first input end of the phase detection module 12 serves as an input end of the phase-locked loop circuit; an output end of the phase detection module 12 is connected to the charge pump 2; an output end of the charge pump 2 is connected to the selector 11; an output end of the selector 11 is connected to the filter 3; the filter 3 is connected to an input end of a voltage-controlled oscillator 4; an output end of the voltage-controlled oscillator 4 serves as an output end of the phase-locked loop circuit; an output end of the voltage-controlled oscillator 4 is further connected to an input end of a frequency divider 5; an output end of the frequency divider 5 is connected to a second input end of the phase detection module 12; and a first input end of the phase detection module 12 is used to receive a reference clock signal.

[0065] The phase detection module 12 calculates the phase error width between the reference clock signal and the feedback signal input by the frequency divider, and outputs a signal with a width of the preset time width when the phase error width is greater than the preset time width; when the phase error width is less than or equal to the preset time width, it outputs a signal with a width of the phase error width. The selector 11 outputs a signal corresponding to the control signal based on the control signal received from the control end of the selector.

[0066] In this embodiment, the charge pump can also be arranged between the phase detection module and the selector. The phase detection circuit will calculate the phase error width between the reference clock signal and the feedback signal after switching, and when the phase error width used for adjustment is too large, specifically when the phase error width is greater than the preset time width, only a signal with a width of the preset time width is output to the charge pump. Technicians can control the phase-locked loop to gradually adjust the phase of the phase-locked loop output in a certain step by setting the preset time width, which greatly weakens the output phase variation of the voltage-controlled oscillator and effectively improves the stability of the data communication function.

[0067] In some embodiments, a specific circuit structure of a phase detection module is provided, which includes a phase detector, a first delay module, a second delay module, a first NOT gate, a second NOT gate, a first AND gate, and a second AND gate.

[0068] It should be noted that this embodiment is different from Figure 6 The corresponding embodiments are corresponding, Figure 6 The specific details in the corresponding embodiments are also applicable to this embodiment.

[0069] In some embodiments, another specific circuit structure of a phase detector module is provided, which includes a first phase detector, a second phase detector, a third delay module, a fourth delay module, a third NOT gate, a fourth NOT gate, a third AND gate, and a fourth AND gate.

[0070] It should be noted that this embodiment is different from Figure 8 The corresponding embodiments are corresponding, Figure 8 The specific details in the corresponding embodiments are also applicable to this embodiment.

[0071] It is worth noting that all modules involved in this embodiment are logical modules. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovations of the present invention, this embodiment does not include units that are not closely related to solving the technical problems proposed by the present invention. However, this does not mean that other units do not exist in this embodiment.

[0072] One embodiment of the present invention relates to a circuit board assembly, comprising any one of the above-mentioned interruption-free switching phase-locked loop circuits.

[0073] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present invention, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A phase-locked loop circuit with interruption-free switching, characterized in that: include: Phase detector circuit, charge pump, filter, voltage controlled oscillator and frequency divider; The N first input terminals of the phase detector circuit serve as input terminals of the phase-locked loop circuit, where N is an integer greater than 1; the output terminal of the phase detector circuit is connected to the charge pump, which is connected to the filter, which is connected to the input terminal of the voltage-controlled oscillator; the output terminal of the voltage-controlled oscillator serves as the output terminal of the phase-locked loop circuit; the output terminal of the voltage-controlled oscillator is further connected to the input terminal of the frequency divider, and the output terminal of the frequency divider is connected to the second input terminal of the phase detector circuit; wherein the N first input terminals of the phase detector circuit are used to receive a reference clock signal; The phase detection circuit is used to determine the reference clock signal corresponding to the control signal according to the control signal received from the control end of the phase detection circuit; The phase detection circuit is further configured to calculate a phase error width between the reference clock signal corresponding to the control signal and the feedback signal input by the frequency divider, and output a signal having a width of the preset time width when the phase error width is greater than a preset time width; and output a signal having a width of the phase error width when the phase error width is less than or equal to the preset time width; The phase detection circuit includes a selector and a phase detection module; or the phase detection circuit includes a selector and N phase detection modules; The phase detector module includes: a first phase detector, a second phase detector, a third delay module, a fourth delay module, a third NOT gate, a fourth NOT gate, a third AND gate and a fourth AND gate; the first input end of the first phase detector serves as the first input end of the phase detector module, the second input end of the first phase detector serves as the second input end of the phase detector module, the uplink output end of the first phase detector is connected to the third NOT gate, the third NOT gate is connected to the first input end of the third AND gate, the downlink output end of the first phase detector is connected to the fourth NOT gate, the fourth NOT gate is connected to the first input end of the fourth AND gate, the input end of the third delay module is connected to the first input end of the first phase detector, and the output end of the third delay module is connected to the fourth AND gate. The first input end of the second phase detector, the input end of the fourth delay module is connected to the second input end of the first phase detector, the output end of the fourth delay module is connected to the second input end of the second phase detector, the uplink output end of the second phase detector is connected to the second input end of the third AND gate, the downlink output end of the second phase detector is connected to the second input end of the fourth AND gate, the output end of the third AND gate and the output end of the fourth AND gate serve as the output end of the phase detector module; the third delay module is used to output the signal received from the input end of the third delay module after the preset time width; the fourth delay module is used to output the signal received from the input end of the fourth delay module after the preset time width.

2. The phase-locked loop circuit with interruption-free switching according to claim 1, wherein: When the phase detection circuit includes the selector and the phase detection module, the N first input terminals of the selector serve as the N first input terminals of the phase detection circuit, the control terminal of the selector serves as the control terminal of the phase detection circuit, the output terminal of the selector is connected to the first input terminal of the phase detection module, the second input terminal of the phase detection module serves as the second input terminal of the phase detection circuit, and the output terminal of the phase detection module serves as the output terminal of the phase detection circuit; The selector is configured to determine, based on the control signal received from the control terminal of the selector, to output the reference clock signal corresponding to the control signal; The phase detection module is used to calculate the phase error width between the reference clock signal corresponding to the control signal and the feedback signal, and when the phase error width is greater than the preset time width, output a signal with a width of the preset time width; when the phase error width is less than or equal to the preset time width, output a signal with a width of the phase error width.

3. The phase-locked loop circuit with interruption-free switching according to claim 1, wherein: When the phase detection circuit includes a selector and N phase detection modules, the first input end of the phase detection module serves as the first input end of the phase detection circuit, the second input end of the phase detection module serves as the second input end of the phase detection circuit, the output end of the phase detection module is connected to the N input ends of the selector, and the control end of the selector serves as the control end of the phase detection circuit; The phase detection module is used to calculate the phase error width between the reference clock signal and the feedback signal, and output a signal with a width of the preset time width when the phase error width is greater than the preset time width; and output a signal with a width of the phase error width when the phase error width is less than or equal to the preset time width; The selector is used to output a signal corresponding to the control signal according to the control signal received from the control end of the phase detection circuit.

4. The phase-locked loop circuit with interruption-free switching according to claim 1, wherein: The phase detector is replaced by a phase frequency detector.

5. A phase-locked loop circuit with interruption-free switching, characterized in that: include: N phase detection modules, N charge pumps, a selector, a filter, a voltage controlled oscillator, and a frequency divider, wherein N is an integer greater than 1; The first input end of the phase detection module serves as the input end of the phase-locked loop circuit, the output end of the phase detection module is connected to the charge pump, the output end of the charge pump is connected to the selector, the output end of the selector is connected to the filter, the filter is connected to the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator serves as the output end of the phase-locked loop circuit, the output end of the voltage-controlled oscillator is also connected to the input end of the frequency divider, the output end of the frequency divider is connected to the second input end of the phase detection module, and the first input end of the phase detection module is used to receive a reference clock signal; The phase detection module is used to calculate the phase error width between the reference clock signal and the feedback signal input by the frequency divider, and output a signal with a width of the preset time width when the phase error width is greater than the preset time width; and output a signal with a width of the phase error width when the phase error width is less than or equal to the preset time width; The selector is configured to output a signal corresponding to a control signal received from a control terminal of the selector; The phase detector module includes: a first phase detector, a second phase detector, a third delay module, a fourth delay module, a third NOT gate, a fourth NOT gate, a third AND gate and a fourth AND gate; the first input end of the first phase detector serves as the first input end of the phase detector module, the second input end of the first phase detector serves as the second input end of the phase detector module, the uplink output end of the first phase detector is connected to the third NOT gate, the third NOT gate is connected to the first input end of the third AND gate, the downlink output end of the first phase detector is connected to the fourth NOT gate, the fourth NOT gate is connected to the first input end of the fourth AND gate, the input end of the third delay module is connected to the first input end of the first phase detector, and the output end of the third delay module is connected to the fourth AND gate. The first input end of the second phase detector, the input end of the fourth delay module is connected to the second input end of the first phase detector, the output end of the fourth delay module is connected to the second input end of the second phase detector, the uplink output end of the second phase detector is connected to the second input end of the third AND gate, the downlink output end of the second phase detector is connected to the second input end of the fourth AND gate, the output end of the third AND gate and the output end of the fourth AND gate serve as the output end of the phase detector module; the third delay module is used to output the signal received from the input end of the third delay module after the preset time width; the fourth delay module is used to output the signal received from the input end of the fourth delay module after the preset time width.

6. A circuit board assembly, characterized in that: A phase-locked loop circuit comprising the interruption-free switching according to any one of claims 1 to 5.

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