A Capacitor Array System for SAR ADC

Abstract

The present invention discloses a capacitor array system for SAR ADC. For an N-bit SAR ADC, the positive and negative ends of the capacitor array only need 2 N‑2 The capacitor with unit capacitance value greatly reduces the overall capacitance value, reduces the area of ​​the capacitor array, and reduces the requirements of the high-speed SAR ADC for the differential signal establishment time and reference voltage buffer.

Description

Technical Field

[0001] The present invention relates to the technical field of analog-to-digital conversion, and in particular to a capacitor array system applied to SAR ADC. Background Art

[0002] The successive approximation analog-to-digital converter (SAR ADC) is an ADC based on binary algorithm, which has the advantages of simple structure, small area and low power consumption. The SAR ADC includes four main modules: sample-and-hold circuit, comparator, SAR control logic circuit and CDAC capacitor network. The design of these module circuits is the most critical part of the entire SAR ADC and directly determines its performance. With the continuous advancement of CMOS manufacturing technology, the feature size of devices is getting smaller and smaller, and the communication length of transistors is also getting smaller and smaller. For operational amplifiers, there is a certain design difficulty under the short channel process, because the reduction of communication length will lead to a reduction in transistor output impedance, making it difficult for operational amplifiers to obtain high gain. The successive approximation structure has a high proportion of digital circuits and no operational amplifier. Compared with other structures, it is the most able to benefit from the continuous advancement of CMOS technology. Therefore, with the continuous reduction of transistor feature size, the successive approximation ADC is becoming more and more attractive.

[0003] However, due to its inherent binary algorithm characteristics, SAR ADC needs to consider more about the binary capacitor array area, reference voltage establishment and speed issues in high-precision applications, which greatly limits its use in high-precision applications. Summary of the invention

[0004] The present invention solves the technical problem of large area of ​​SAR ADC capacitor array in the prior art by providing a capacitor array system applied to SAR ADC.

[0005] The present invention provides the following technical solutions:

[0006] A capacitor array system for SAR ADC, comprising a first gate voltage bootstrap switch, a second gate voltage bootstrap switch, a first differential signal line, a second differential signal line, a comparator, a controller, a plurality of switching switches and a plurality of capacitors, wherein the sum of the capacitance values ​​of all the capacitors is 2 N-1 C, N is the number of bits of ADC, and C is the unit capacitance value;

[0007] One end of the first differential signal line is connected to the positive end of the analog input differential signal through the first gate voltage bootstrap switch, and the other end of the first differential signal line is connected to the first input end of the comparator. The sum of the capacitance values ​​is 2 N-2The top plate of the capacitor of part C is connected in parallel to the first differential signal line; one end of the second differential signal line is connected to the negative end of the analog input differential signal through the second gate voltage bootstrap switch, and the other end of the second differential signal line is connected to the second input end of the comparator. The sum of the capacitance values ​​is 2 N-2 The top plate of another part of the capacitor C is connected in parallel to the second differential signal line;

[0008] The first end of each switching switch is connected to the bottom plate of a capacitor, the second end of each switching switch is connected to a reference voltage, and the third end of each switching switch is grounded. The switching switch is used to connect the bottom plate of the corresponding capacitor to the reference voltage or the ground; the controller is connected to the control end of each switching switch, and is used to control the first end of each switching switch to connect to one of the second end and the third end;

[0009] The controller is also used to control each switch so that: when quantizing the nth bit, the sum of the capacitance values ​​of all capacitors on the bottom plate of the first differential signal line connected to the reference voltage is C1, and the sum of the capacitance values ​​of all capacitors on the bottom plate of the second differential signal line connected to the reference voltage is C2; when quantizing the n+1th bit, the sum of the capacitance values ​​of all capacitors on the bottom plate of the first differential signal line connected to the reference voltage is C3, and the sum of the capacitance values ​​of all capacitors on the bottom plate of the second differential signal line connected to the reference voltage is C4, |(C4-C3)-(C2-C1)|=2 N-n-2 C, n∈[1,2,...,N-1].

[0010] Preferably, the controller is also used to control each switch during the sampling phase of the ADC so that the sum of the capacitance values ​​of all capacitors on the first differential signal line whose bottom plate is connected to the reference voltage, the sum of the capacitance values ​​of all capacitors on the first differential signal line whose bottom plate is grounded, the sum of the capacitance values ​​of all capacitors on the second differential signal line whose bottom plate is connected to the reference voltage, and the sum of the capacitance values ​​of all capacitors on the second differential signal line whose bottom plate is grounded are all 2 N-3 C.

[0011] Preferably, all capacitors are divided into a first group of capacitors, a second group of capacitors, a third group of capacitors and a fourth group of capacitors, the number of capacitors in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors is the same, the capacitors in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors correspond to each other one by one, the capacitance values ​​of the corresponding capacitors are the same, the top plates of the first group of capacitors and the second group of capacitors are connected in parallel to the first differential signal line, and the top plates of the third group of capacitors and the fourth group of capacitors are connected in parallel to the second differential signal line;

[0012] The controller is also used to control each switch during the sampling phase of the ADC so that the bottom plates of the first and third capacitor groups are connected to the reference voltage and the bottom plates of the second and fourth capacitor groups are grounded.

[0013] Preferably, the controller is further used to control each switch so that when C1 is greater than C3, C2 is less than C4, and when C1 is less than C3, C2 is greater than C4.

[0014] Preferably, at least one capacitor in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors is formed by connecting two unit capacitors in parallel and then connecting a capacitor with a capacitance value of 2C in series.

[0015] Preferably, the capacitance value of at least one of the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors is C / 2, and the controller is further used to control only the bottom plate of one of the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors, whose capacitance value is C / 2, to change from being connected to the reference voltage to being grounded or from being grounded to being connected to the reference voltage when quantizing the Nth bit.

[0016] Preferably, the capacitors with a capacitance value of C / 2 in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors are composed of two unit capacitors connected in series.

[0017] Preferably, N is 4, and the first group of capacitors, the second group of capacitors, the third group of capacitors or the fourth group of capacitors includes 3 capacitors, and the capacitance values ​​are C, C / 2, and C / 2 respectively.

[0018] Preferably, the controller is further configured to: if the analog input differential signal is greater than Vref is the reference voltage. When the 4th bit is quantized, only the first end of the switch corresponding to a capacitor with a capacitance value of C / 2 in the first group of capacitors is controlled to change from being connected to the second end to being connected to the third end.

[0019] Preferably, N is 11, the first group of capacitors, the second group of capacitors, the third group of capacitors or the fourth group of capacitors includes 11 capacitors, and the capacitance values ​​are 120C, 64C, 32C, 18C, 10C, 5C, 3C, 2C, C, C / 2, and C / 2, respectively.

[0020] The technical solution provided by the present invention has at least the following technical effects or advantages:

[0021] For an N-bit SAR ADC, the capacitor array of the present invention only needs 2 N-2 The capacitor with unit capacitance value greatly reduces the overall capacitance value, reduces the area of ​​the capacitor array, and reduces the requirements of the high-speed SAR ADC for the differential signal establishment time and reference voltage buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 is a schematic diagram of a capacitor array system applied to a SAR ADC in an embodiment of the present invention;

[0024] Figure 2 Schematic diagram of a capacitor array with 4-bit resolution in a sampling phase according to an embodiment of the present invention;

[0025] Figure 3 Schematic diagram of a capacitor array with 4-bit resolution in a comparison quantization stage according to an embodiment of the present invention;

[0026] Figure 4 Schematic diagram of the change of the voltage on the first differential signal line and the voltage on the second differential signal line during the sampling and comparison quantization stages in an embodiment of the present invention;

[0027] Figure 5 This is another implementation of the capacitor array applied to the SAR ADC in the embodiment of the present invention. DETAILED DESCRIPTION

[0028] The embodiment of the present invention solves the technical problem of large area of ​​capacitor array of SAR ADC in the prior art by providing a capacitor array system applied to SAR ADC.

[0029] In order to better understand the technical solution of the present invention, the technical solution of the present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0030] First of all, the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0031] like Figure 1 As shown, the capacitor array system applied to the SAR ADC of this embodiment includes a first gate voltage bootstrap switch, a second gate voltage bootstrap switch, a first differential signal line, a second differential signal line, a comparator, a controller, a plurality of switching switches and a plurality of capacitors, and the sum of the capacitance values ​​of all the capacitors is 2 N-1 C, N is the number of bits of ADC, and C is the unit capacitance value;

[0032] One end of the first differential signal line is connected to the positive end of the analog input differential signal through the first gate voltage bootstrap switch, and the other end of the first differential signal line is connected to the first input end of the comparator. The sum of the capacitance values ​​is 2 N-2 The top plate of the capacitor of part C is connected in parallel to the first differential signal line; one end of the second differential signal line is connected to the negative end of the analog input differential signal through the second gate voltage bootstrap switch, and the other end of the second differential signal line is connected to the second input end of the comparator. The sum of the capacitance values ​​is 2 N-2 The top plate of another part of the capacitor C is connected in parallel to the second differential signal line;

[0033] The first end of each switching switch is connected to the bottom plate of a capacitor, the second end of each switching switch is connected to a reference voltage, and the third end of each switching switch is grounded. The switching switch is used to connect the bottom plate of the corresponding capacitor to the reference voltage or the ground; the controller is connected to the control end of each switching switch, and is used to control the first end of each switching switch to connect to one of the second end and the third end;

[0034] The controller is also used to control each switch so that: when quantizing the nth bit, the sum of the capacitance values ​​of all capacitors connected to the reference voltage on the bottom plate of the first differential signal line is C1, and the sum of the capacitance values ​​of all capacitors connected to the reference voltage on the bottom plate of the second differential signal line is C2; when quantizing the n+1th bit, the sum of the capacitance values ​​of all capacitors connected to the reference voltage on the bottom plate of the first differential signal line is C3, and the sum of the capacitance values ​​of all capacitors connected to the reference voltage on the bottom plate of the second differential signal line is C4, |(C4-C3)-(C2-C1)|=2 N-n-2 C, n∈[1,2,...,N-1].

[0035] In this embodiment, the number of capacitors and the capacitance value of each capacitor are various, and the bottom plate connection conditions of each capacitor are also various in the sampling stage and the comparison quantization stage of the ADC. Vref represents the reference voltage, Vip represents the positive terminal voltage of the analog input differential signal (the voltage on the first differential signal line when quantizing the first bit), Vin represents the negative terminal voltage of the analog input differential signal (the voltage on the second differential signal line when quantizing the first bit), Vip2 represents the voltage on the first differential signal line when quantizing the second bit, Vin2 represents the voltage on the second differential signal line when quantizing the second bit, Vip3 represents the voltage on the first differential signal line when quantizing the third bit, Vin3 represents the voltage on the second differential signal line when quantizing the third bit, Vip4 represents the voltage on the first differential signal line when quantizing the fourth bit, Vin4 represents the voltage on the second differential signal line when quantizing the fourth bit, and so on. It is easy to think that when quantizing the first bit, it is necessary to compare whether Vip-Vin is greater than 0. If the comparator outputs 1, the first bit is 1, and if the comparator outputs 0, the first bit is 0; if you want to quantize the second bit, you need to make Vip2-Vin2=Vip-Vin-(1 / 2)Vref. If the second bit is 1, when quantizing the third bit, you need to make Vip3-Vin3=Vip-Vin-(3 / 4)Vref. If the second bit is 0, when quantizing the third bit, you need to make Vip3-Vin3=Vip-Vin-(1 / 4)Vref. By analogy, when quantizing the nth bit, the difference between the differential voltage between the first differential signal line and the second differential signal line, and when quantizing the n+1th bit, the difference between the differential voltage between the first differential signal line and the second differential signal line needs to be

[0036] Assuming that in the sampling phase of the ADC, the sum of the capacitance values ​​of the capacitors connected to the reference voltage on the bottom plate of the first differential signal line is C1, and the sum of the capacitance values ​​of the capacitors connected to the reference voltage on the bottom plate of the second differential signal line is C2, then when the sampling is completed, the amount of charge stored in all capacitors on the first differential signal line is 2 N-2 Vip*C-Vref*C1, the charge stored in all capacitors on the second differential signal line is 2 N-2 Vin*C-Vref*C2. In the comparison and quantization stage of the ADC, the comparator compares whether Vip-Vin is greater than 0 to achieve the quantization of the first bit; when quantizing the second bit, the sum of the capacitance values ​​of the capacitors connected to the reference voltage on the bottom plate of the first differential signal line is changed to C3, and the sum of the capacitance values ​​of the capacitors connected to the reference voltage on the bottom plate of the second differential signal line is changed to C4. At this time, the amount of charge stored in all capacitors on the first differential signal line is 2 N-2 Vip2*C-Vref*C3, the charge stored in all capacitors on the second differential signal line is 2 N-2 Vin2*C-Vref*C4, according to the principle of conservation of capacitor charge, there are 2 N-2Vip*C-Vref*C1=2 N-2 Vip2*C-Vref*C3, we get There are 2 N-2 Vin*C-Vref*C2=2 N-2 Vin2*C-Vref*C4, we get Since |(C4-C3)-(C2-C1)|=2 N-n-2 C=2 N-3 C, assuming that (C4-C3)-(C2-C1) is greater than 0, then Vip2-Vin2 = Vip-Vin-(1 / 2)Vref, and the quantization of the second bit is achieved. Similarly, assuming that in the sampling stage of the ADC, the sum of the capacitance values ​​of the capacitors connected to the reference voltage on the bottom plate of the first differential signal line is C01, and the sum of the capacitance values ​​of the capacitors connected to the reference voltage on the bottom plate of the second differential signal line is C02, then when quantizing the nth bit, there is When quantizing the n+1th bit, we have but This can achieve quantification of each bit.

[0037] In this embodiment, the capacitor distribution method is preferably that the controller controls each switch during the sampling phase of the ADC so that the sum of the capacitance values ​​of all capacitors on the first differential signal line whose bottom plate is connected to the reference voltage, the sum of the capacitance values ​​of all capacitors on the first differential signal line whose bottom plate is grounded, the sum of the capacitance values ​​of all capacitors on the second differential signal line whose bottom plate is connected to the reference voltage, and the sum of the capacitance values ​​of all capacitors on the second differential signal line whose bottom plate is grounded are all 2. N-3 C; all capacitors are divided into the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors. The number of capacitors in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors is the same, and the capacitors in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors correspond to each other. The capacitance values ​​of the corresponding capacitors are the same. The top plates of the first group of capacitors and the second group of capacitors are connected in parallel to the first differential signal line, and the top plates of the third group of capacitors and the fourth group of capacitors are connected in parallel to the second differential signal line. The controller is also used to control each switching switch during the sampling stage of the ADC so that the bottom plates of the first group of capacitors and the third group of capacitors are connected to the reference voltage, and the bottom plates of the second group of capacitors and the fourth group of capacitors are grounded. In this way, the sum of the capacitance values ​​of all capacitors in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors is 2 N-3 C, in the sampling phase of the ADC, the sum of the capacitance values ​​connected to the reference voltage and the sum of the capacitance values ​​connected to the ground are both 2 N-3 C, when sampling is completed, the amount of charge stored in all capacitors on the first differential signal line is 2N-2 Vip*C-Vref*2 N-3 C, the charge stored in all capacitors on the second differential signal line is 2 N-2 Vin*C-Vref*2 N-3 C, get

[0038] For ease of understanding, Figure 2 As shown, taking N as 4 and the first group of capacitors, the second group of capacitors, the third group of capacitors or the fourth group of capacitors including 3 capacitors with capacitance values ​​of C, C / 2, and C / 2 respectively, when sampling is completed, the amount of charge stored in all capacitors on the first differential signal line is 4Vip*C-2Vref*C, and the amount of charge stored in all capacitors on the second differential signal line is 4Vin*C-2Vref*C.

[0039] Assume that the value of Vref-(Vip-Vin) is less than 1L SB, that is, Vip-Vin>Vref-(1 / 2 N )Vref=(15 / 16)Vref. Figure 3As shown, for the quantization of the first bit, first determine that Vip-Vin>0, and the comparator obtains the judgment result. For the quantization of the second bit, the bottom plate of the highest capacitor in the first group of capacitors at the positive end of the split capacitor array is changed from Vref to ground through digital logic control, and the connection method of other capacitors at the positive end remains unchanged. Then the amount of charge stored in all capacitors on the first differential signal line is 4Vip2*C-Vref*C. According to the principle of conservation of capacitor charge, 4Vip*C-2Vref*C=4Vip2*C-Vref*C, and Vip2=Vip-(1 / 4)Vref. At the same time, the bottom plate of the highest capacitor in the fourth group of capacitors at the negative end of the split capacitor array is controlled by digital logic from grounding to connecting to Vref. Then the amount of charge stored in all capacitors on the second differential signal line is 4Vin2*C-3Vref*C. According to the principle of conservation of capacitor charge, 4Vin*C-2Vref*C=4Vin2*C-3Vref*C, and we can solve for Vin2=Vin+(1 / 4)Vref. At this time, the differential voltage between the first differential signal line and the second differential signal line is expressed as Vip2-Vin2=Vip-Vin-(1 / 2)Vref, and the comparator determines that Vip2-Vin2>0, that is, Vip-Vin>(1 / 2)Vref, to achieve quantization of the second bit. Thereafter, the bottom plate of the second highest capacitor in the first group of capacitors at the positive end of the split capacitor array is controlled by digital logic to change from Vref to ground, and the connection method of other capacitors at the positive end remains unchanged. Then the amount of charge stored in all capacitors on the first differential signal line is 4Vip3*C-(1 / 2)Vref*C. According to the principle of conservation of capacitor charge, 4Vip*C-2Vref*C=4Vip3*C-(1 / 2)Vref*C, which can be solved to obtain Vip3=Vip-(3 / 8)Vref. At the same time, the digital logic controls the bottom plate of the second highest capacitor in the fourth group of capacitors at the negative end of the split capacitor array from grounding to connecting to Vref. Then the amount of charge stored in all capacitors on the second differential signal line is 4Vin3*C-(7 / 2)Vref*C. According to the principle of conservation of capacitor charge, 4Vin*C-2Vref*C=4Vin3*C-(7 / 2)Vref*C, which can be solved to obtain Vin3=Vin+(3 / 8)Vref. At this time, the differential voltage between the first differential signal line and the second differential signal line is expressed as Vip3-Vin3=Vip-Vin-(3 / 4)Vref, and the comparator determines that Vip3-Vin3>0, that is, Vip-Vin>(3 / 4)Vref, realizing the quantization of the third bit. After that, the bottom plate of the last capacitor in the first group of capacitors at the positive end of the split capacitor array is changed from Vref to ground through digital logic control, and the connection of other capacitors at the positive end remains unchanged. Then the charge stored in all capacitors on the first differential signal line is 4Vip4*C.According to the principle of conservation of capacitor charge, 4Vip*C-2Vref*C=4Vip4*C, and Vip4=Vip-(1 / 2)Vref. At the same time, all the bottom plate connections of the negative end of the split capacitor array controlled by digital logic remain unchanged. Then Vin4=Vin3=Vin+(3 / 8)Vref. At this time, the differential voltage between the first differential signal line and the second differential signal line is expressed as Vip4-Vin4=Vip-Vin-(7 / 8)Vref. By judging the positive and negative results of Vip4-Vin4, the quantization result of the 4th bit is finally achieved.

[0040] Here is a capacitance distribution method when N is 11, such as the first group of capacitors, the second group of capacitors, the third group of capacitors or the fourth group of capacitors includes 11 capacitors, and the capacitance values ​​are 120C, 64C, 32C, 18C, 10C, 5C, 3C, 2C, C, C / 2, and C / 2 respectively.

[0041] As can be seen from the above, for an N-bit SAR ADC, the capacitor array of this embodiment only needs 2 N-2 The capacitor with unit capacitance value greatly reduces the overall capacitance value, reduces the area of ​​the capacitor array, and reduces the requirements of the high-speed SAR ADC for the differential signal establishment time and reference voltage buffer.

[0042] In addition, from Figure 2 It can be seen from the quantization process that the controller is also used to control each switch so that when C1 is greater than C3, C2 is less than C4, and when C1 is less than C3, C2 is greater than C4. In this way, when quantizing any one of the 2nd to N-1th bits, when the voltage on the first differential signal line increases, the voltage on the second differential signal line decreases, and when the voltage on the first differential signal line decreases, the voltage on the second differential signal line increases. In this way, the phase change of the differential voltage is achieved, such as Figure 4 As shown, the common-mode voltage on the differential line is kept stable, and the dynamic offset of the comparator input terminal is reduced. In addition, the capacitance value of at least one of the first group of capacitors, the second group of capacitors, the third group of capacitors, and the fourth group of capacitors is C / 2. The controller is also used to control only the bottom plate of one of the first group of capacitors, the second group of capacitors, the third group of capacitors, and the fourth group of capacitors with a capacitance value of C / 2 to change from being connected to the reference voltage to being grounded or from being grounded to being connected to the reference voltage when quantizing the Nth bit. For example, when N is 4, if the analog input differential signal is greater than Vref is the reference voltage. When quantizing the fourth bit, the controller only controls the first end of the switch corresponding to a capacitor with a capacitance value of C / 2 in the first group of capacitors to change from connecting to the second end to connecting to the third end, even if the bottom plate of this capacitor changes from connecting to the reference voltage to grounding. In this way, only one end of the differential end changes the voltage, achieving further quantization and increasing one bit of resolution. In addition, in the allocation of capacitance values, a non-binary arrangement is used and a redundant bit is introduced, so that the establishment time of the differential signal has a certain redundancy, thereby accelerating the conversion of the ADC.

[0043] In this embodiment, the capacitor with a capacitance value of C / 2 is formed by two unit capacitors connected in series. Of course, the capacitor with a capacitance value of C / 2 may not be used, and at least one capacitor in the first group of capacitors, the second group of capacitors, the third group of capacitors, and the fourth group of capacitors may be formed by two unit capacitors connected in parallel and then connected in series with a capacitor with a capacitance value of 2C, such as Figure 5 When adjusting the bottom plate connection of two unit capacitors in parallel, it is equivalent to adjusting the bottom plate of the capacitor C / 2.

[0044] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0045] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A capacitor array system for SAR ADC, characterized in that: The invention comprises a first gate voltage bootstrap switch, a second gate voltage bootstrap switch, a first differential signal line, a second differential signal line, a comparator, a controller, a plurality of switching switches and a plurality of capacitors, wherein the sum of the capacitance values ​​of all the capacitors is 2 N-1 C, N is the number of bits of ADC, and C is the unit capacitance value; One end of the first differential signal line is connected to the positive end of the analog input differential signal through the first gate voltage bootstrap switch, and the other end of the first differential signal line is connected to the first input end of the comparator. The sum of the capacitance values ​​is 2 N-2 The top plate of the capacitor of part C is connected in parallel to the first differential signal line; one end of the second differential signal line is connected to the negative end of the analog input differential signal through the second gate voltage bootstrap switch, and the other end of the second differential signal line is connected to the second input end of the comparator. The sum of the capacitance values ​​is 2 N-2 The top plate of another part of the capacitor C is connected in parallel to the second differential signal line; The first end of each switching switch is connected to the bottom plate of a capacitor, the second end of each switching switch is connected to a reference voltage, and the third end of each switching switch is grounded. The switching switch is used to connect the bottom plate of the corresponding capacitor to the reference voltage or the ground; the controller is connected to the control end of each switching switch, and is used to control the first end of each switching switch to connect to one of the second end and the third end; The controller is also used to control each switch so that: when quantizing the nth bit, the sum of the capacitance values ​​of all capacitors on the bottom plate of the first differential signal line connected to the reference voltage is C1, and the sum of the capacitance values ​​of all capacitors on the bottom plate of the second differential signal line connected to the reference voltage is C2; when quantizing the n+1th bit, the sum of the capacitance values ​​of all capacitors on the bottom plate of the first differential signal line connected to the reference voltage is C3, and the sum of the capacitance values ​​of all capacitors on the bottom plate of the second differential signal line connected to the reference voltage is C4, |(C4-C3)-(C2-C1)|=2 N-n-2 C, n∈[1,2,...,N-1].

2. The capacitor array system for SAR ADC according to claim 1, wherein: The controller is also used to control each switch during the sampling phase of the ADC so that the sum of the capacitance values ​​of all capacitors on the first differential signal line whose bottom plate is connected to the reference voltage, the sum of the capacitance values ​​of all capacitors on the first differential signal line whose bottom plate is grounded, the sum of the capacitance values ​​of all capacitors on the second differential signal line whose bottom plate is connected to the reference voltage, and the sum of the capacitance values ​​of all capacitors on the second differential signal line whose bottom plate is grounded are all 2 N-3 C.

3. The capacitor array system for SAR ADC according to claim 2, characterized in that: All capacitors are divided into a first group of capacitors, a second group of capacitors, a third group of capacitors and a fourth group of capacitors. The number of capacitors in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors is the same. The capacitors in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors correspond to each other one by one. The capacitance values ​​of the corresponding capacitors are the same. The top plates of the first group of capacitors and the second group of capacitors are connected in parallel to the first differential signal line, and the top plates of the third group of capacitors and the fourth group of capacitors are connected in parallel to the second differential signal line. The controller is also used to control each switch during the sampling phase of the ADC so that the bottom plates of the first and third capacitor groups are connected to the reference voltage and the bottom plates of the second and fourth capacitor groups are grounded.

4. The capacitor array system for SAR ADC according to claim 3, characterized in that: The controller is further used to control each switch so that when C1 is greater than C3, C2 is less than C4, and when C1 is less than C3, C2 is greater than C4.

5. The capacitor array system for SAR ADC according to claim 3, characterized in that: At least one capacitor in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors is formed by connecting two unit capacitors in parallel and then connecting a capacitor with a capacitance value of 2C in series.

6. The capacitor array system for SAR ADC according to claim 3, characterized in that: The capacitance value of at least one of the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors is C / 2. The controller is further used to control only the bottom plate of one of the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors, whose capacitance value is C / 2, to change from being connected to the reference voltage to being grounded or from being grounded to being connected to the reference voltage when quantizing the Nth bit.

7. The capacitor array system for SAR ADC according to claim 6, characterized in that: The capacitors with a capacitance value of C / 2 in the first group of capacitors, the second group of capacitors, the third group of capacitors and the fourth group of capacitors are formed by two unit capacitors in series.

8. The capacitor array system for SAR ADC according to claim 6, wherein: N is 4, and the first group of capacitors, the second group of capacitors, the third group of capacitors, or the fourth group of capacitors includes three capacitors, and the capacitance values ​​are C, C / 2, and C / 2 respectively.

9. The capacitor array system for SAR ADC according to claim 8, characterized in that: The controller is also used to if the analog input differential signal is greater than Vref is the reference voltage. When the 4th bit is quantized, only the first end of the switch corresponding to a capacitor with a capacitance value of C / 2 in the first group of capacitors is controlled to change from being connected to the second end to being connected to the third end.

10. The capacitor array system for SAR ADC according to claim 3, characterized in that: N is 11, the first group of capacitors, the second group of capacitors, the third group of capacitors or the fourth group of capacitors includes 11 capacitors, and the capacitance values ​​are 120C, 64C, 32C, 18C, 10C, 5C, 3C, 2C, C, C / 2, and C / 2 respectively.

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