Camera element and camera device

Abstract

The imaging element comprises: a first substrate having a photoelectric conversion portion for generating electric charges by photoelectrically converting light, and a readout circuit for outputting a signal based on the electric charges generated by the photoelectric conversion portion; a second substrate stacked on the first substrate and having a processing portion for processing the signal output from the readout circuit; and a connecting portion having a bent portion that is bent at a portion other than the vicinity of the first and second substrates, for electrically connecting the readout circuit and the processing portion.

Description

Technical Field

[0001] The present invention relates to a photographing element and a photographing device. Background Art

[0002] Conventionally, a stacked imaging element is known (e.g., Patent Document 1) in which a first semiconductor chip with a pixel array and a second semiconductor chip with an A / D converter and logic circuits are stacked. In the imaging element of Patent Document 1, each pixel in the first semiconductor chip is connected to each A / D converter in the second semiconductor chip via conductive vias. However, the conductive vias limit the freedom of layout of other wiring.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-182038 Summary of the Invention

[0006] According to the first embodiment of the present invention, the imaging element comprises: a first substrate, which is provided with a photoelectric conversion portion that generates electric charges by photoelectrically converting light, and a readout circuit that outputs a signal based on the electric charges generated by the above-mentioned photoelectric conversion portion; a second substrate, which is stacked on the above-mentioned first substrate and is provided with a processing portion that processes the signal output from the above-mentioned readout circuit; and a connecting portion, which is provided with a bent portion that is bent at a portion other than the vicinity of the above-mentioned first substrate and the above-mentioned second substrate, and electrically connects the above-mentioned readout circuit and the above-mentioned processing portion.

[0007] According to the second embodiment of the present invention, the imaging element comprises: a first substrate, which is provided with a photoelectric conversion portion that generates electric charges by photoelectrically converting light, and a readout circuit that outputs a signal based on the electric charges generated by the above-mentioned photoelectric conversion portion; a second substrate, which is stacked on the above-mentioned first substrate and is provided with a control portion that controls the above-mentioned readout circuit; and a connecting portion, which has a bent portion that is bent at a portion other than the vicinity of the above-mentioned first substrate and the above-mentioned second substrate, and electrically connects the above-mentioned readout circuit and the above-mentioned control portion.

[0008] According to a third aspect of the present invention, an imaging device includes the imaging element according to the first aspect or the second aspect, and a generating unit that generates image data based on a signal output from the imaging element. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 It is a cross-sectional view schematically showing the structure of the imaging device according to the first embodiment.

[0010] Figure 2 This is a plan view of the imaging element according to the first embodiment as viewed from the imaging surface side.

[0011] Figure 3 This is a cross-sectional view of a portion of the imaging element according to the first embodiment.

[0012] Figure 4 It is a diagram showing the configuration of pixels and circuit units of the imaging element according to the first embodiment.

[0013] Figure 5 This is a cross-sectional view of a portion of the imaging element according to the second embodiment. DETAILED DESCRIPTION

[0014] (First embodiment)

[0015] Figure 1 This is a diagram showing a configuration example of a camera 1 as an example of an imaging device according to the first embodiment.

[0016] Figure 1 In the X direction, Y direction and Z direction indicated by the arrows, the direction indicated by the arrows is set as the + direction. The X direction, Y direction and Z direction are directions that are orthogonal to each other. In addition, the X direction, Y direction and Z direction shown in the following figures are also Figure 1 The X direction, Y direction, and Z direction shown are the same direction.

[0017] The camera 1 includes an imaging optical system (imaging optical system) 2, an image sensor 3, an imaging control unit 4, a memory 5, a display unit 6, and an operation unit 7. The imaging optical system 2 includes a plurality of lenses including a focus adjustment lens (focus lens) and an aperture stop, and forms an image of a subject on the image sensor 3. The imaging optical system 2 may be attachable to and detachable from the camera 1.

[0018] The imaging element 3 is an imaging element such as a CMOS image sensor or a CCD image sensor. It receives the light beam passing through the imaging optical system 2 and captures the subject image formed by the imaging optical system 2. In the imaging element 3, a plurality of pixels having a photoelectric conversion unit are arranged two-dimensionally (in rows and columns). The imaging element 3 performs photoelectric conversion on the received light to generate a signal, which is then output to the imaging control unit 4.

[0019] The memory 5 is a recording medium such as a memory card. Image data, control programs, and the like are stored in the memory 5. Writing and reading data into and from the memory 5 are controlled by the imaging control unit 4. The display unit 6 displays images based on the image data, information related to imaging such as shutter speed and aperture value, and menu screens. The operating unit 7 includes various setting switches, such as a release button, a power switch, and switches for switching between various modes, and outputs signals based on these operations to the imaging control unit 4.

[0020] The imaging control unit 4, comprised of a processor such as a CPU, FPGA, or ASIC, and memory such as ROM and RAM, controls various components of the camera 1 based on a control program. The imaging control unit 4 supplies signals to the imaging element 3 to control the operation of the imaging element 3. The imaging control unit 4 causes the imaging element 3 to capture an image of a subject and output a signal, whether capturing still images, capturing moving images, or displaying a live view image (preview image) of the subject on the display unit 6.

[0021] The imaging control unit 4 performs various image processing on the signal output from the imaging element 3 to generate image data. The imaging control unit 4 also serves as the image data generation unit 4, and generates still image data and moving image data based on the signal output from the imaging element 3. Image processing includes grayscale conversion processing, color interpolation processing, and other image processing.

[0022] (First embodiment of the imaging element)

[0023] Next, refer to Figures 2 to 4 , the structure of the imaging element 3 according to the first embodiment will be described.

[0024] Figure 2 This figure shows the image sensor 3 of the first embodiment as viewed from the light incident side (-Z side). The image sensor has a plurality of pixels 10 arranged in the X direction (horizontally) and the Y direction (vertically). The number of pixels 10 arranged in each of the X and Y directions can be 1,000 or more.

[0025] A horizontal control section HC is provided at the -X end of a region (pixel region) where a plurality of pixels 10 are arranged, and a vertical control section VC is provided at the +Y end. The horizontal control section HC and the vertical control section VC are collectively referred to as an element control section CU.

[0026] The plurality of pixels 10 are arranged in a so-called Bayer array, for example. Alternatively, some of the pixels 10 may be so-called image plane phase difference type pixels used for focus detection.

[0027] Figure 3 is a diagram showing a cross section (XZ plane) of the pixel area of ​​the imaging element 3. Figure 3 , only a portion of the pixel region of the imaging element 3 is shown in cross section. The imaging element 3 is a first substrate 20 and a second substrate 30 stacked in the Z direction. The first substrate 20 and the second substrate 30 are made of, for example, a semiconductor such as silicon. A plurality of pixels 10, indicated by dashed lines, are provided on the imaging element 3. Each pixel 10 includes a microlens 11, a color filter 12, a photoelectric converter 13, and a readout circuit 14. Alternatively, a single pixel 10 may include multiple photoelectric converters 13 or multiple readout circuits 14.

[0028] A photoelectric converter 13 and a readout circuit 14 are provided on the first substrate 20. The photoelectric converter 13 performs photoelectric conversion on light incident on the first substrate 20 to generate electric charge. The photoelectric converter 13 is composed of, for example, a photodiode. The readout circuit 14 outputs a pixel signal based on the electric charge generated by the photoelectric converter 13 to a vertical wiring (described later). The structure of the readout circuit 14 will be described later.

[0029] The microlens 11 is provided on the light incident side (−Z direction side) of the first substrate 20 . The microlens 11 collects the light incident on the first substrate 20 onto the photoelectric conversion section 13 .

[0030] The color filter 12 is provided between the microlens 11 and the photoelectric conversion section 13. The color filter 12 has a spectral characteristic such that light of a specific wavelength is incident on each photoelectric conversion section 13. The color filter 12 has a spectral characteristic defined as a Bayer array.

[0031] A plurality of circuit units 15 shown in dotted lines are provided on the second substrate 30. The circuit unit 15 includes a processing unit 16 for processing a signal output from the readout circuit 14 and a control unit 17 for controlling the readout circuit 14.

[0032] A first wiring layer 21 including a first insulating layer 22, pads 23, and wirings 24 to 29 is provided on the surface of the first substrate 20 facing the second substrate 30 (the +Z direction side). On the other hand, a second wiring layer 31 including a second insulating layer 32, pads 33, and wirings 34 to 39 is provided on the surface of the second substrate 30 facing the first substrate 20 (the -Z direction side).

[0033] Like the wiring that constitutes a typical semiconductor integrated circuit, wirings 24-29 and wirings 34-39 are formed on the first substrate 20 or the second substrate 30 using photolithography techniques using a conductor such as metal. Therefore, wirings 24-29 and wirings 34-39 include wirings 26-29 and 37-39 (hereinafter referred to as "horizontal wirings") that extend approximately parallel to the XY in-plane direction parallel to the surface of the first substrate 20 or the second substrate 30. Furthermore, wirings 24-29 and wirings 34-39 include wirings 24, 25, and 34 (hereinafter referred to as "vertical wirings") that extend approximately parallel to the Z direction perpendicular to the surface of the first substrate 20 or the second substrate 30.

[0034] Horizontal wirings 26-29 and 37-39 are formed in separate wiring layers. Horizontal wirings 26-29 and 37-39 are formed, for example, by patterning a layer of a conductor such as metal formed on the surface of the first substrate 20 or the second substrate 30 using photolithography. Alternatively, horizontal wirings 26-29 and 37-39 can be formed by forming grooves in an insulating layer formed on the surface of the first substrate 20 or the second substrate 30 using photolithography and then filling these grooves with a conductor such as metal.

[0035] Furthermore, vertical wirings 24, 25, and 34 are, for example, so-called VIA plugs formed in the vertical direction (Z direction) in an insulating layer formed on first substrate 20 or second substrate 30. Each vertical wiring 24, 25, and 34 may be a single VIA plug extending in the Z direction. Alternatively, vertical wirings 24, 25, and 34 may be a plurality of VIA plugs extending in the Z direction stacked at the same position in the XY plane.

[0036] Alternatively, the first insulating layer 22 and the second insulating layer 32 may be insulating layers formed by laminating a plurality of insulating layers.

[0037] also, Figure 3 The wirings 24 to 29 and wirings 34 to 39 shown are merely examples, and the total number is not limited to Figure 3 The total number of horizontal and vertical wiring can be more than Figure 3 Quantity shown.

[0038] In this embodiment, the wiring layers in which horizontal wirings 26 to 29 are formed and the first insulating layer 22 in which vertical wirings 24 and 25 are formed are collectively referred to as the first wiring layer 21. Similarly, the wiring layers in which horizontal wirings 37 to 39 are formed and the second insulating layer 32 in which vertical wiring 34 is formed are collectively referred to as the second wiring layer 31.

[0039] The first insulating layer 22 included in the first wiring layer 21 and the second insulating layer 32 included in the second wiring layer 31 are joined (stacked) at a joining surface (stacked surface) 50 .

[0040] The readout circuits 14 provided on the first substrate 20 are each electrically connected to at least one vertical wiring 24, either directly or via other wiring. The lower end (end on the +Z direction) of the vertical wiring 24 is connected to one end of a horizontal wiring 26 within the first wiring layer 21. Furthermore, the other end of the horizontal wiring 26 is connected to the upper end (end on the -Z direction) of the vertical wiring 25. The lower end (end on the +Z direction) of the vertical wiring 25 is connected to a pad 23, which serves as a connection electrode.

[0041] The pads 23 and 33 are connection electrodes and are bonded together at the bonding surface 50. The pads 33 are connected to the upper ends (ends on the -Z direction side) of the vertical wirings 34. The lower ends (ends on the +Z direction side) of the vertical wirings 34 are electrically connected, for example, directly to one of the processing units 16 provided on the second substrate 30 or via other wiring.

[0042] The pads 23 and the pads 33 constitute a junction that connects the wirings 24 to 29 formed in the first wiring layer 21 on the first substrate 20 and the wirings 34 to 39 formed in the second wiring layer 31 on the second substrate 30 .

[0043] In the present embodiment, the vertical wiring 24 , the horizontal wiring 26 , the vertical wiring 25 , the pad 23 , the pad 33 , and the vertical wiring 34 described above are collectively referred to as “first connection portion”.

[0044] The first connecting portion is a wiring that connects pixels provided on the first substrate 20 and the circuit unit 15 provided on the second substrate 30, which are separated in the Z direction (vertical direction). The wiring extends in the Z direction. The horizontal wiring 26 in the first connecting portion extends in the XY plane (horizontal direction) and is curved relative to the other first connecting portions. Therefore, the horizontal wiring 26 is also referred to as a "curved portion."

[0045] At the same Z position as the bent portion 26 (horizontal wiring 26), another horizontal wiring 26a other than the bent portion 26 may be formed. In other words, some of the plurality of horizontal wirings 26 and 26a in the same wiring layer may be used as the bent portion 26.

[0046] In the imaging element 3 of the first embodiment, the bent portion 26 is provided in the horizontal wiring 26, 26a located second from the bonding surface 50 in the -Z direction in the wiring layer 21. However, the bent portion 26 may also be provided in the horizontal wiring 29 located first from the bonding surface 50 in the -Z direction in the wiring layer 21. The bent portion 26 may also be provided in the horizontal wiring located third or higher from the bonding surface 50 in the -Z direction in the wiring layer 21, as long as the bent portion 26 is located closer to the bonding surface 50.

[0047] In the above description, it is assumed that one first connection portion electrically connects each readout circuit 14 provided on the first substrate 20 and the processing portion 16 provided on the second substrate 30 corresponding to each readout circuit 14 .

[0048] However, the first connection portion may be various control lines (such as the selection control line SEL) described later that electrically connect each readout circuit 14 provided on the first substrate 20 and the control portion 17 provided on the second substrate 30 corresponding to each readout circuit 14. As described later, when a plurality of control portions 17 are provided corresponding to each readout circuit 14, a plurality of first connection portions may be provided in accordance with the number of control portions 17.

[0049] also, Figure 3 The horizontal wiring 39 shown is, for example, a wiring for supplying a power supply voltage, a GND voltage, or a control signal to each control unit 17 provided on the second substrate 30. Figure 3 For example, the example in which the horizontal wiring 39 is connected to each control unit 17 is shown. However, Figure 3 In addition to the horizontal wiring 39 shown, there are also horizontal wirings for supplying power supply voltage, GND voltage, or control signals to the respective processing units 16 , or for outputting output signals from the processing units 16 .

[0050] Figure 4 This diagram shows the configuration of a photoelectric converter 13 and a readout circuit 14 included in a pixel 10 provided on a first substrate 20, and a processing unit 16 and a control unit 17 (17a to 17d) included in a circuit unit 15 provided on a second substrate 30. In the imaging element 3 of the first embodiment, the pixel 10 is also configured as a so-called four-transistor CMOS imaging pixel, for example.

[0051] The photoelectric conversion section 13 generates charges by photoelectrically converting light incident on the first substrate 20. The photoelectric conversion section 13 is composed of, for example, a photodiode.

[0052] The readout circuit 14 reads out a pixel signal based on the charge generated by the photoelectric converter 13. The readout circuit 14 includes a transfer unit TX, a drain unit TR, a floating diffusion (FD) FD, and an output unit OU including an amplifier TA and a selector TS.

[0053] The transfer unit TX transfers the charge photoelectrically converted by the photoelectric converter 13 to the floating diffusion FD. That is, the transfer unit TX is a transfer transistor TX forming a charge transfer path between the photoelectric converter 13 and the floating diffusion FD.

[0054] The floating diffusion FD receives the charge photoelectrically converted by the photoelectric converter 13 through the transfer section. The floating diffusion FD stores the charge photoelectrically converted by the photoelectric converter 13 through the transfer section TX. That is, the floating diffusion FD is a storage section that stores the charge.

[0055] The drain unit TR discharges the charge stored in the floating diffusion FD, thereby resetting the potential of the floating diffusion to a reference potential. The drain unit TR is a reset transistor TR that resets the potential of the floating diffusion to a reference potential.

[0056] The output unit OU outputs the pixel signal generated by the charge in the floating diffusion FD to the signal line SL. The signal line SL is one of the first connecting portions (23-26, 33-34). The signal line SL is a wiring for outputting the pixel signal to the processing unit 16. The output unit OU includes an amplifier TA and a selector TS. The amplifier TA is an amplifier transistor TA that generates the pixel signal using the charge in the floating diffusion FD. The selector TS is a selection transistor TS that controls the connection between the pixel 10 and the signal line SL. The selector TS outputs the pixel signal generated by the amplifier TA to the signal line SL.

[0057] The analog signal (pixel signal) output from the output unit OU of the readout circuit 14 provided on the first substrate 20 is transmitted via the signal line SL to the processing unit 16 of the circuit unit 15 provided on the second substrate 30. The processing unit 16 includes, for example, an analog-to-digital converter circuit ADC and a current source CS. The analog-to-digital converter circuit ADC converts the analog signal (pixel signal) output from the select transistor TS of the readout circuit 14 into a digital signal.

[0058] The vertical wirings 24 , 25 , and 34 described above include at least a portion of a signal line SL for transmitting a pixel signal from the pixel 10 to the readout unit ADC.

[0059] The circuit unit 15 includes a plurality of control units 17 (17a to 15d). In this embodiment, the selection control unit 17a, the voltage control unit 17b, the reset control unit 17c, and the transfer control unit 17d are collectively or individually referred to as "control units 17."

[0060] The selection control unit 17a is electrically connected to the gate of the selection transistor TS of the readout circuit 14 via the selection control line SEL, which is one of the first connection portions (23 to 26, 33 to 34). That is, the selection control unit 17a controls the selection transistor TS.

[0061] The voltage control unit 17 b controls the supply of the power supply voltage to the readout circuit 14 or the photoelectric conversion unit 13 via the power supply voltage line VDD, which is one of the first connection portions ( 23 to 26 , 33 to 34 ).

[0062] The reset control unit 17c is electrically connected to the gate of the reset transistor TR of the readout circuit 14 via the reset control line RST, which is one of the first connection portions (23 to 26, 33 to 34). That is, the reset control unit 17c controls the reset transistor TR.

[0063] The transmission control unit 17d acts as Figure 3 The transfer control line TRN, one of the first connection portions (23 to 26, 33 to 34) shown, is electrically connected to the gate of the transfer transistor TX of the readout circuit 14. That is, the transfer control portion 17d controls the transfer transistor TX.

[0064] Hereinafter, the selection control line SEL, reset control line RST, and transmission control line TRN are collectively referred to as "control lines." The control lines are wiring used to transmit control signals for controlling each transistor from the control unit 17 to the readout circuit 14. Furthermore, the control signals for controlling each transistor are transmitted from the control unit 17 to at least a portion of the horizontal wirings 27 and 28 via the first connecting portions ( 23 - 26 , 33 - 34 ).

[0065] The imaging element 3 of the first embodiment includes a plurality of processing units 16 corresponding to the number of pixels 10. Therefore, the imaging element 3 can read out pixel signals for each pixel 10. In other words, the imaging element 3 can read out and process the pixel signals generated by the plurality of pixels 10 at high speed. The imaging element 3 of the first embodiment includes a plurality of control units 17 corresponding to the number of pixels 10. Therefore, the imaging element 3 can control each pixel 10. In other words, the imaging element 3 can set different exposure times for each pixel and generate and output pixel signals.

[0066] Depending on the configuration of the image sensor 3, the arrangement period of the pixels 10, including the photoelectric converter 13 and the readout circuit 14, in the X or Y direction may differ from the arrangement period of the circuit unit 15, including the processing unit 16 and the control unit 17, in the X or Y direction. In other words, the distance between two adjacent pixels 10 in the X or Y direction (pixel pitch) may differ from the distance between two adjacent circuit units 15 in the X or Y direction (circuit pitch). This is because circuits other than the circuit unit 15 need to be arranged on the second substrate 30. On the other hand, it is necessary to arrange the pixels 10 at regular intervals on the first substrate 20. For example, the control circuit 15e of the control circuit unit 15 needs to be arranged on the second substrate 30 for every predetermined number of circuit units 15 arranged in the X or Y direction. The circuits arranged on the second substrate 30 are not limited to the control circuit 15e; other circuits such as shift registers and storage units may also be used.

[0067] Therefore, the width of the circuit unit 15 in the X direction or the Y direction (circuit pitch) needs to be smaller than the width of the pixel 10 in the X direction or the Y direction (pixel pitch). As a result, the arrangement period of the pixel 10 in the X direction or the Y direction may be different from the arrangement period of the circuit unit 15 in the X direction or the Y direction.

[0068] In this case, some of the multiple circuit units 15 cannot be arranged directly below the corresponding pixel 10 (in the +Z direction), but are arranged at positions offset in the X or Y direction from directly below the pixel 10. In particular, some of the multiple circuit units 15 cannot be arranged directly below the readout circuit 14 included in the corresponding pixel 10 (in the +Z direction), but are arranged at positions offset in the X or Y direction from directly below the readout circuit 14. The inability to arrange the corresponding circuit unit 15 directly below the pixel 10 is caused by the configuration of the imaging element 3 of the first embodiment in which the circuit unit 15 is arranged for each pixel 10.

[0069] The imaging element 3 of the first embodiment uses the curved portion 26 in the first connecting portion (23-26, 33-34) to adjust for positional deviations in the X or Y direction caused by the difference between the arrangement period of the pixels 10 and the arrangement period of the circuit unit 15. This solves the problem of the circuit unit 15 being unable to be positioned directly below the pixels 10 due to the difference between the arrangement period of the pixels 10 and the arrangement period of the circuit unit 15.

[0070] Specifically, if Figure 3 As shown, the imaging element 3 of the first embodiment has pads 33 connected to vertical wirings 34 extending from each circuit unit 15 in the upward direction (-Z direction). The pads 33 are arranged approximately directly above the circuit unit 15. Therefore, the arrangement period of the bonding portion (pads 23, 33) in the X direction or Y direction is set to coincide with the arrangement period of the circuit unit 15. In addition, the imaging element 3 of the first embodiment has the bent portion 26 for adjusting the position of the pixel 10 and the bonding portion 23 in the X direction or Y direction so that they coincide with each other, arranged on the first wiring layer 21. Thus, even if the arrangement period of the pixel 10 in the X direction or Y direction is different from the arrangement period of the circuit unit 15, the pixel 10 (readout circuit 14) and the circuit unit 15 can be electrically connected via the first connection portion (23 to 26, 33 to 34). In other words, even when the pixel pitch and the circuit pitch are different, the pixels 10 (readout circuit 14 ) and the circuit unit 15 can be electrically connected using the first connecting portions ( 23 to 26 , 33 to 34 ).

[0071] The direction of the bent portion 26 (the direction of the bend) may be, for example, the X direction or the Y direction which is the same as the arrangement direction of the pixels 10 .

[0072] Alternatively, the curved portion 26 may include a first portion extending in one direction in the XY plane and a first portion extending in a direction intersecting the one direction in the XY plane. In other words, the curved portion 26 may include a portion curved in the XY plane.

[0073] Also, near the first substrate 20, for example, there are multiple horizontal wirings 27-29 for controlling the readout circuit 14. Also, near the second substrate 30, for example, there are multiple horizontal wirings 37-39 for controlling the processing unit 16 or the control unit 17.

[0074] Therefore, if the bent portion 26 is formed near the first substrate 20, it will hinder the layout of the horizontal wirings 27 and 28 for controlling the readout circuit 14. Specifically, the degree of freedom in the wiring layout of the horizontal wirings 27 and 28 is limited by the bent portion 26. In addition, the integration density of the horizontal wirings 27 and 28 is reduced due to the bent portion 26.

[0075] Forming the curved portion 26 near the second substrate 30 hinders the layout of the horizontal wirings 38 and 39 used to control the processing unit 16 or the control unit 17. Specifically, the degree of freedom in the layout of the horizontal wirings 38 and 39 is limited. Furthermore, the curved portion 26 reduces the integration density of the horizontal wirings 38 and 39.

[0076] The horizontal wirings 26 to 29 included in the first wiring layer 21 include wiring for controlling the pixels 10, a GND line for supplying a GND voltage to the pixels 10, and a power supply line for supplying a power supply voltage to the pixels 10. The wiring for controlling the pixels 10 is, for example, wiring for controlling the transfer transistor TX, the reset transistor TR, and the select transistor TS included in the pixel 10. The wiring for controlling the transfer transistor TX or the reset transistor TR may be provided for each pixel 10 or for each pixel block including a predetermined number of pixels 10.

[0077] The wiring for these control transistors (hereinafter also referred to as "first control lines") is provided in the first wiring layer 21 near the first substrate 20 (on the first substrate side, in the -Z direction) to control the transfer transistor TX, the reset transistor TR, and the select transistor TS. Specifically, the horizontal wirings 27 and 28 arranged near the first substrate 20 include a plurality of first control lines.

[0078] The GND line and the power line are commonly provided in a plurality of pixels 10 or a plurality of pixel blocks. Therefore, the GND line and the power line are arranged in the first wiring layer 21 at a position farther from the first substrate 20 than the first control line (second substrate side, +Z direction side). In other words, the GND line and the power line are arranged at a position close to the bonding surface 50. In addition, as mentioned above, a plurality of first control lines are arranged near the pixel 10, that is, near the first substrate 20. Therefore, the GND line and the power line are arranged in the first wiring layer 21 at a position farther from the first substrate 20 than the first control line. That is, the horizontal wiring 29 arranged in the first wiring layer 21 at a position farther from the first substrate 20 includes a plurality of GND lines and power lines.

[0079] The horizontal wirings 37 to 39 included in the second wiring layer 31 include wiring for controlling the processing unit 16 or the control unit 17, a GND line for supplying a GND voltage to the processing unit 16 or the control unit 17, and a power supply line for supplying a power supply voltage to the processing unit 16 or the control unit 17. The wiring for controlling the processing unit 16 or the control unit 17 is, for example, wiring for controlling various switching elements such as transistors included in the processing unit 16 or the control unit 17.

[0080] The wiring for these control transistors (hereinafter also referred to as "second control lines") is provided in the second wiring layer 31 near the second substrate 30 (on the second substrate side, in the +Z direction) to control the various switching elements. Specifically, the horizontal wirings 38 and 39 arranged near the second substrate 30 include a plurality of second control lines.

[0081] The GND line and the power line are commonly provided in the plurality of processing units 16 or the plurality of control units 17. Therefore, the GND line and the power line are provided in the second wiring layer 31 at a position farther from the second substrate 30 than the second control line (on the first substrate side, on the -Z direction side). In other words, the GND line and the power line are provided at a position closer to the bonding surface 50. In addition, as described above, a plurality of second control lines are arranged near the processing unit 16 or the control unit 17, that is, near the second substrate 30. Therefore, the GND line and the power line are provided in the second wiring layer 31 at a position farther from the second substrate 30 than the second control line. That is, the horizontal wiring 37 of the second wiring layer 31 arranged at a position farther from the second substrate 30 includes a plurality of GND lines and power lines.

[0082] The control line transmits a high-frequency control signal to control each transistor and switch element. Therefore, the control line may become a noise source for the signal line SL including the bend 26. Conversely, the bend 26 of the signal line SL may become a noise source for the control line.

[0083] To avoid this, the imaging element 3 of the first embodiment has a bent portion 26 in a portion other than those near the first substrate 20 and the second substrate 30. In other words, the imaging element 3 of the first embodiment has the bent portion 26 near the bonding surface 50. With this structure, the imaging element 3 of the first embodiment does not restrict the freedom of layout of other wirings 27, 28, 37, and 38 by the first connecting portions (23 to 26, 33 to 34) including the bent portion 26, allowing the horizontal wirings 27, 28, 37, and 38 to be routed in an optimal layout. This prevents a reduction in the integration density of the wirings 27, 28, 37, and 38.

[0084] Furthermore, the imaging element 3 of the first embodiment includes a bent portion 26 at a location distant from the first control lines (horizontal wirings 27 and 28) arranged near the first substrate 20 and the second control lines (horizontal wirings 38 and 39) arranged near the second substrate 30. In other words, the imaging element 3 of the first embodiment includes the bent portion 26 near the junction. This configuration allows the imaging element 3 of the first embodiment to suppress the influence of noise from these control lines on the bent portion 26. Conversely, the influence of noise from these bent portions 26 on the control lines can also be suppressed.

[0085] Furthermore, the imaging element 3 of the first embodiment has a curved portion 26 located close to the GND and power lines. Since the GND and power lines are applied with essentially constant voltage, the noise impact on the signal line SL, including the curved portion 26, is minimal. Furthermore, the GND and power lines are less susceptible to noise from the curved portion 26 of the signal line SL. With this configuration, the imaging element 3 of the first embodiment can minimize the impact of noise on the curved portion 26. Furthermore, the impact of noise from the curved portion 26 can also be minimized.

[0086] Alternatively, the imaging element 3 may have the bent portion 26 provided at a position somewhat away from the first substrate 20 and the second substrate 30 , rather than being provided near the first substrate 20 and the second substrate 30 .

[0087] For example, the imaging element 3 may be provided with a bent portion 26 spaced at least one-quarter of the distance between the first substrate 20 and the second substrate 30. This arrangement does not restrict the degree of freedom in the layout of the horizontal wirings 27 and 28 for controlling the readout circuit 14 and the horizontal wirings 37 and 38 for controlling the processing unit 16 or the control unit 17. Consequently, the horizontal wirings 27, 28, 37, and 38 can be arranged in an optimal layout.

[0088] Furthermore, the imaging element 3 may include at least two wiring layers (horizontal wirings 27, 28 or horizontal wirings 37, 38) between the first substrate 20 and the curved portion 26, and between the second substrate 30 and the curved portion 26. This allows for unrestricted layout flexibility for the horizontal wirings 27, 28 for controlling the readout circuit 14, and the horizontal wirings 37, 38 for controlling the processing unit 16 or the control unit 17. Consequently, the horizontal wirings 27, 28, 37, and 38 can be arranged in an optimal layout.

[0089] Furthermore, the first connecting portion (23-26, 33-34) of the first embodiment includes first wiring portions (24-26) provided on the first wiring layer 21, a second wiring portion (34) provided on the second wiring layer 31, and pads 23 and 33 serving as a joining portion for joining the first and second wiring portions. Bend 26 is provided near pads 23 and 33 serving as the joining portion. In other words, bend 26 is provided closer to pads 23 and 33 serving as the joining portion than to first substrate 20 and second substrate 30.

[0090] (Second embodiment of imaging element)

[0091] Next, refer to Figure 5 , the structure of the imaging element 3a of the second embodiment will be described. Most of the structure of the imaging element 3a of the second embodiment is the same as that of the imaging element 3 of the first embodiment described above. Hereinafter, the same reference numerals are attached to the common structures, and the description thereof will be omitted as appropriate.

[0092] Figure 5 This is a diagram showing a cross section (XZ plane) of the pixel 10 portion of the imaging element 3a according to the second embodiment, which is similar to the above-mentioned Figure 3 The imaging element 3a of the second embodiment differs from the imaging element 3 of the first embodiment in that the electrical connection between the readout circuit 14 and the processing unit 16 or the control unit 17 is performed using the vertical wiring 24, the pad 23, the pad 33, the vertical wiring 35, the horizontal wiring 36, and the vertical wiring 34.

[0093] In this embodiment, the vertical wiring 24, pad 23, pad 33, vertical wiring 35, horizontal wiring 36, and vertical wiring 34 are collectively referred to as the "second connecting portion." Furthermore, the first connecting portion and the second connecting portion are collectively referred to as the "connecting portion" or individually.

[0094] In the imaging element 3a of the second embodiment, the second connecting portion (23 to 24, 33 to 36) has a first portion (24) provided on the first wiring layer 21, a second portion (34 to 36) provided on the second wiring layer 31, and pads 23 and 33 serving as a joining portion for joining the first portion and the second portion.

[0095] Furthermore, in the imaging element 3 a of the second embodiment, the horizontal wiring 36 as the bent portion is arranged at the second portion closer to the second substrate 30 than the pads 23 and 33 as the bonding portion.

[0096] Specifically, if Figure 5As shown, the imaging element 3a of the second embodiment has pads 23 connected to vertical wiring 24 extending directly below (in the +Z direction) from the readout circuit 14 of each pixel 10. The pads 23 are arranged approximately directly below the pixel 10 (readout circuit 14). Therefore, the arrangement period of the bonding portions (pads 23, 33) in the X or Y direction is set to coincide with the arrangement period of the readout circuit 14 of the pixel 10. Furthermore, the imaging element 3a of the second embodiment has a bent portion 26 in the second wiring layer 31 for aligning the positions of the bonding portions 33 and the circuit unit 15 in the X or Y direction. Thus, even if the arrangement period of the pixels 10 in the X or Y direction differs from the arrangement period of the circuit unit 15, the first connection portions (23-26, 33-34) can electrically connect the readout circuit 14 and the circuit unit 15.

[0097] Thus, even when the arrangement period of the pixels 10 differs from the arrangement period of the circuit unit 15 in the X direction or the Y direction, the pixels 10 (readout circuit 14) and the circuit unit 15 can be electrically connected using the first connecting portions (23 to 26, 33 to 34). In other words, even when the pixel pitch and the circuit pitch differ, the pixels 10 (readout circuit 14) and the circuit unit 15 can be electrically connected using the first connecting portions (23 to 26, 33 to 34).

[0098] The arrangement period of the pixels 10 in the X or Y direction is approximately uniform within the imaging surface (XY plane on the -Z side) of the imaging element 3a. Therefore, the imaging element 3a of the second embodiment can arrange the bonding portions (pads 23, 33) at approximately equal intervals in the X or Y direction. In other words, the bonding portions (pads 23, 33) are arranged approximately uniformly on the bonding surface 50. Therefore, the electrical impact of the bonding portions on the readout circuit 14 and the circuit unit 15 can be approximately uniform in the directions within the imaging surface (XY directions), and noise unevenness within the imaging surface can be suppressed.

[0099] Furthermore, in the second embodiment, the structure and purpose of horizontal wirings 27, 28, 37-39, etc. are the same as those in the first embodiment described above. In the second embodiment, the structure and purpose of the bent portion (horizontal wiring 36) are the same as those in the first embodiment described above. In the second embodiment, the positional relationship between the first substrate 20 and the second substrate 30 and the bent portion (horizontal wiring 36) in the Z direction is the same as that in the first embodiment described above. In the second embodiment, the positional relationship between the horizontal wirings 27, 28, 37-39 and the bent portion (horizontal wiring 36) in the Z direction is the same as that in the first embodiment described above. In the second embodiment, the positional relationship between the pads 23 and 33, which serve as bonding portions, and the bent portion in the Z direction is the same as that in the first embodiment described above. Furthermore, as in the first embodiment described above, horizontal wirings 36a other than the bent portion may be formed at the same Z position as the bent portion.

[0100] In the second embodiment as well, the upper end of the vertical wiring 24 is electrically connected to the readout circuit 14 provided on the first substrate 20, either directly or via another wiring. Furthermore, the lower end of the vertical wiring 34 is electrically connected to the processing unit 16 or the control unit 17 provided on the second substrate 30, either directly or via another wiring.

[0101] In the imaging element 3 of the first embodiment or the imaging element 3a of the second embodiment described above, the bent portions 26 and 36 are provided in the first and second portions near the bonding pads 23 and 33, respectively. This reduces the impact on the layout of wiring for controlling the readout circuit 14, the processing unit 16, the control unit 17, and the like.

[0102] Alternatively, the bent portions 26 and 36 may be provided at a distance from the bonding pads 23 and 33 that is within 1 / 4 of the distance between the first substrate 20 and the second substrate 30. This can reduce the impact on the layout of wiring for controlling the readout circuit 14, the processing unit 16, the control unit 17, and the like.

[0103] Furthermore, pads 23 and 33 are electrodes whose area in the XY plane is larger than that of vertical wirings 24, 25, and 34. However, if the first substrate 20 and the second substrate 30 can be stacked with high positional accuracy, it is not necessary to enlarge the area of ​​the joint. In this case, electrodes whose area in the XY plane is approximately the same as that of the vertical wirings 24, 25, and 34 can be used as the joint.

[0104] In the imaging elements 3 and 3a of the above embodiments, the photoelectric conversion unit 13 and the readout circuit 14 arranged on the first substrate 20 may each be provided with a connection unit (23 to 26, 33 to 36) connected to the processing unit 16 or the control unit 17 of the second substrate 30.

[0105] However, the number of the connecting portions (23 to 26, 33 to 36) may be smaller than the number of the readout circuits 14. For example, Figure 2 In the imaging plane of the imaging element 3 shown in FIG. 1 , a plurality of pixels 10 (in the image sensor 3) arranged in blocks BC each surrounded by a dotted line may be displayed. Figure 2 For example, one connection portion (23 to 26, 33 to 36) is configured for each pixel 10 (e.g., 4×4 pixels). In other words, one connection portion (23 to 26, 33 to 36) is shared by the multiple pixels 10 arranged in the block BC. Alternatively, one circuit unit 15 may be configured for each pixel 10 arranged in the block BC. In other words, one circuit unit 15 is shared by the multiple pixels 10 arranged in the block BC.

[0106] In this case, the signals (pixel signals) generated by the plurality of photoelectric converters 13 included in the plurality of pixels 10 within a single block BC are sequentially output to the processing unit 16 of the second substrate 30 via a single connection unit (23 to 26, 33 to 36). Furthermore, the control signals from the control units 17a to 17d of the second substrate 30 are also sequentially or simultaneously output to the plurality of readout circuits 14 included in a single block BC of the first substrate 20 via a single connection unit (23 to 26, 33 to 36).

[0107] Furthermore, even in imaging elements 3 and 3a configured with one connection portion and circuit unit 15 (processing unit 16, control unit 17) for each block BC having multiple pixels 10, there is a problem of not being able to arrange the corresponding circuit unit 15 directly below each block BC. However, as described above, this problem is resolved by providing the bent portion 26 in the wiring layer 21 of the imaging element 3 of the first embodiment and the bent portion 36 in the wiring layer 31 of the imaging element 3a of the second embodiment.

[0108] Furthermore, similar to the imaging element 3 of the first embodiment, the imaging element 3a of the second embodiment also has multiple control lines arranged near the substrates 20 and 30 for transmitting high-frequency control signals for controlling various transistors and switching elements. Therefore, in the imaging element 3a of the second embodiment, the bent portion 36 is provided in areas other than those near the first substrate 20 and the second substrate 30, thereby reducing the effects of noise from the control lines on the bent portion 36 and vice versa.

[0109] In the imaging element 3a of the second embodiment, the bend 36 is provided in the horizontal wirings 36 and 36a located second from the bonding surface 50 in the +Z direction in the wiring layer 31. However, the bend 36 may also be provided in the horizontal wirings 40 located first from the bonding surface 50 in the +Z direction in the wiring layer 31. The bend 36 may also be provided in the horizontal wirings located third or higher from the bonding surface 50 in the +Z direction in the wiring layer 31, as long as the bend 36 is located closer to the bonding surface 50.

[0110] The imaging element 3 of the first embodiment and the imaging element 3a of the second embodiment are both so-called stacked sensors, formed by stacking a first substrate 20 and a second substrate 30. Consequently, multiple control lines for controlling transistors and other components formed on each substrate are formed near the first substrate 20 and the second substrate 30. To suppress the effects of noise from these control lines and ensure flexibility in placement, the provision of curved sections 26 and 36 in areas other than those near the first and second substrates 20 and 30 is a unique feature of stacked sensors. In other words, the placement of curved sections 26 and 36 near the junction (pads 23 and 33) between the first and second substrates 20 and 30 is a unique feature of stacked sensors.

[0111] Furthermore, in the imaging elements 3 and 3a of the aforementioned embodiments, the lengths of the connections (23 to 26, 33 to 36) connected to the readout circuits 14 vary depending on the lengths of the included bent portions 26 and 36. Consequently, the impedance of the connections (23 to 26, 33 to 36) may vary depending on the lengths of the bent portions 26 and 36. If the impedance of the connections (23 to 26, 33 to 36) varies, there is a risk that streak noise associated with the impedance change will occur in images obtained from the imaging elements 3 and 3a.

[0112] To avoid this stripe noise, the thickness (line width) of the wiring of each connection portion (23-26, 33-36) can be varied based on the length of the bends 26 and 36, so that the impedance of each connection portion is substantially equal. Alternatively, a conductor with low resistance can be used in the wiring layer used as the bends 26 and 36 to minimize the variation in the impedance of each connection portion (23-26, 33-36).

[0113] Alternatively, a connection portion having a shorter bent portion 26 or 36 than other connection portions may include a component that generates resistance so that the impedance of each connection portion is approximately equal. Alternatively, to avoid this stripe noise, the characteristics of the current source CS connected to each connection portion (23 to 26, 33 to 36) may vary depending on the length of the bent portion 26 or 36 included in each connection portion. The characteristic of the current source CS that varies may be, for example, the amount of current supplied.

[0114] (1) From the first point of view, the imaging element 3, 3a of each of the above embodiments comprises: a first substrate 20, which is provided with a photoelectric conversion unit 13 that performs photoelectric conversion on light to generate electric charges, and a readout circuit 14 that outputs a signal based on the electric charges generated by the photoelectric conversion unit 13; a second substrate 30, which is stacked on the first substrate 20 and is provided with a processing unit 16 that processes the signal output from the readout circuit 14; and a connecting portion (23 to 26, 33 to 36), which is provided with a bent portion 26, 36 that is bent at a portion other than the vicinity of the first substrate 20 and the second substrate 30, and electrically connects the readout circuit 14 and the processing unit 16.

[0115] With this structure, even if the photoelectric converter 13 or the readout circuit 14 and the corresponding processing unit 16 have different arrangement periods in the X direction or the Y direction, they can be electrically connected by the connecting portions ( 23 to 26 , 33 to 36 ).

[0116] Furthermore, since the bent portions 26 and 36 are arranged to avoid the vicinity of the first substrate 20 and the second substrate 30 where various wirings are concentrated, the bent portions 26 and 36 can be arranged without adversely affecting the layout of other wirings. This prevents an increase in impedance in the various wirings.

[0117] (2) From the second point of view, the imaging element 3, 3a of each of the above embodiments comprises: a first substrate 20, which is provided with a photoelectric conversion unit 13 that generates charges by photoelectrically converting light, and a readout circuit 14 that outputs a signal based on the charges generated by the photoelectric conversion unit 13; a second substrate 30, which is stacked on the first substrate 20 and is provided with a control unit 17 that controls the readout circuit 14; and a connecting portion (23 to 26, 33 to 36), which has a bent portion 26, 36 that is bent at a portion other than the vicinity of the first substrate 20 and the second substrate 30, and electrically connects the readout circuit 14 and the control unit 17.

[0118] With this configuration, even if the photoelectric converter 13 or the readout circuit 14 and the corresponding control unit 17 have different arrangement periods in the X direction or the Y direction, they can be electrically connected by the connection portions ( 23 to 26 , 33 to 36 ).

[0119] Furthermore, since the bent portions 26 and 36 are arranged away from the vicinity of the first substrate 20 and the second substrate 30 where various wirings are concentrated, the bent portions 26 and 36 can be arranged without adversely affecting the layout of other wirings. This prevents an increase in impedance in the various wirings.

[0120] (3) Furthermore, the connection portions (23 to 26, 33 to 36) are configured such that no bent portions 26, 36 are provided near the first substrate 20 and near the second substrate 30, thereby further increasing the degree of freedom in the layout of various wirings and further suppressing the increase in impedance of the various wirings.

[0121] (4) Moreover, by configuring the bent portions 26 and 36 to be spaced apart from the first substrate 20 and the second substrate 30 by more than 1 / 4 of the distance between the first substrate 20 and the second substrate 30, the degree of freedom in the layout of various wirings can be further increased, and the increase in the impedance of various wirings can be further suppressed.

[0122] (5) Furthermore, by providing a plurality of wiring layers 26 to 28 and 36 to 38 provided between the first substrate 20 and the second substrate 30 and providing the bent portions 26 and 36 in the wiring layers, the manufacturing costs of the wiring layers and the bent portions can be reduced.

[0123] (6) Moreover, by setting a structure in which at least two wiring layers 27, 28, 37, 38 are respectively provided between the first substrate 20 and the bending parts 26, 36, and between the second substrate 30 and the bending parts 26, 36, the wiring layers 27, 28, 37, 38 can be used to wire the circuits formed on the first substrate 20 and the second substrate 30.

[0124] In the above, various embodiments and modifications have been described, but the present invention is not limited to these contents. In addition, each embodiment and modification can be applied separately or in combination. Other methods that are thought of within the scope of the technical concept of the present invention are also included in the scope of the present invention.

[0125] The disclosures of the following priority basic applications are incorporated herein by reference.

[0126] Japan Special Application No. 2019-180783 (application filed on September 30, 2019)

[0127] Description of Reference Numerals

[0128] 1: Imaging device, 2: Imaging lens, 3: Imaging element, 4: Imaging control unit (generation unit), 5: Lens moving unit, BC: Pixel block, HC: Horizontal control unit, VC: Vertical control unit, CU: Element control unit, 10: Pixel, 20: First substrate, 30: Second substrate, 11: Microlens, 12: Color filter, 13: Photoelectric conversion unit, 14: Readout circuit, 15: Circuit unit, 16: Processing unit, 17: Control unit, 17a: Selection control unit, 17b: Voltage control unit, 17c: Reset control unit, 17d: Transfer control unit, 21: Layer 1, 22: 1st insulating layer, 24-29: Wiring, 31: 2nd layer, 32: 2nd insulating layer, 34-40: Wiring, 23, 33: Pads, 50: Joint surface, TX: Transmission part (transmission transistor), TR: Drain part (reset transistor), TA: Amplification part (amplification transistor), TS: Selection part (selection transistor), FD: Floating diffusion part (FD), TRN: Transmission control line, RST: Reset control line, VDD: Power supply voltage line, SEL: Selection control line, SL: Output signal line, ADC: Readout part, CS: Current source.

Claims

1. A camera element comprising: a first substrate having a photoelectric conversion portion for generating electric charges by photoelectrically converting light, and a readout circuit for outputting a signal based on the electric charges generated by the photoelectric conversion portion; a second substrate stacked on the first substrate and provided with a processing unit for processing a signal output from the readout circuit; and a connecting portion having a bent portion bent at a portion other than the vicinity of the first substrate and the second substrate, and electrically connecting the readout circuit and the processing portion; The connecting portion includes a first portion provided on the first substrate side, a second portion provided on the second substrate side, and a joining portion joining the first portion and the second portion. The bent portion is provided on a side closer to the bonding portion than the first substrate and the second substrate.

2. The imaging element according to claim 1, wherein The connection portion is not provided with the bent portion near the first substrate and near the second substrate.

3. The imaging element according to claim 1, wherein The bent portion is provided away from the first substrate and the second substrate by at least 1 / 4 of the distance between the first substrate and the second substrate.

4. The imaging element according to claim 2, wherein: The bent portion is provided away from the first substrate and the second substrate by at least 1 / 4 of the distance between the first substrate and the second substrate.

5. The imaging element according to any one of claims 1 to 4, wherein: comprising a plurality of wiring layers provided between the first substrate and the second substrate, The bent portion is provided in the wiring layer.

6. The imaging element according to claim 5, wherein: At least two wiring layers are provided between the first substrate and the bent portion, and between the second substrate and the bent portion, respectively.

7. The imaging element according to claim 1, wherein The bent portion is provided at the first portion or the second portion in the vicinity of the joining portion.

8. The imaging element according to claim 1 or 7, wherein: The bent portion is provided at a distance from the bonding portion that is within ¼ of a distance between the first substrate and the second substrate.

9. The imaging element according to claim 1 or 7, wherein: The bonding portion is an electrode or a pad.

10. The imaging element according to any one of claims 1 to 4, wherein: The second substrate is provided with a plurality of the processing parts arranged in parallel along the first direction. The curved portion is curved in the first direction.

11. The imaging element according to any one of claims 1 to 4, wherein: The first substrate is provided with a plurality of the photoelectric conversion units, the number of which is different from that of the processing units.

12. The imaging element according to any one of claims 1 to 4, wherein: The second substrate is provided with the processing portion that is connected to the photoelectric conversion portion without using the connection portion.

13. The imaging element according to any one of claims 1 to 4, wherein: The connection section is a signal line that transmits a signal based on the charge generated by the photoelectric conversion section to the processing section.

14. The imaging element according to any one of claims 1 to 4, wherein: The processing unit is a conversion unit that converts an analog signal obtained based on the charge generated by the photoelectric conversion unit into a digital signal.

15. The imaging element according to any one of claims 1 to 4, wherein: The connecting portion is a wiring for supplying a predetermined voltage to the photoelectric conversion portion.

16. A camera element comprising: a first substrate having a photoelectric conversion portion for generating electric charges by photoelectrically converting light, and a readout circuit for outputting a signal based on the electric charges generated by the photoelectric conversion portion; a second substrate stacked on the first substrate and provided with a control unit for controlling the readout circuit; and a connecting portion having a bent portion bent at a portion other than the vicinity of the first substrate and the second substrate, and electrically connecting the readout circuit and the control portion; The connecting portion includes a first portion provided on the first substrate side, a second portion provided on the second substrate side, and a joining portion joining the first portion and the second portion. The bent portion is provided on a side closer to the bonding portion than the first substrate and the second substrate.

17. The imaging element according to claim 16, wherein: The bend is provided at the first portion or the second portion in the vicinity of the joining portion.

18. The imaging element according to claim 16 or 17, wherein: The connecting portion is a signal line that transmits a signal for controlling the readout circuit from the control portion to the readout circuit.

19. A photographing device comprising: The imaging element according to any one of claims 1 to 18; and A generating unit generates image data based on a signal output from the imaging element.

Images