Display panel, manufacturing method thereof, and display device

Abstract

A display panel and its manufacturing method and display device are disclosed. The display panel includes a substrate (11), a plurality of sub-pixels (12), a plurality of gate lines (13), and a gate driving circuit (21). The substrate (11) includes a display area (111) and a peripheral area (112). The gate driving circuit (21) is located in the display area (111) and includes cascaded multi-level gate driving units (211). Each level of gate driving unit (211) includes a first gate driving sub-circuit (211A1) and a second gate driving sub-circuit (211A2). The plurality of sub-pixels (12) includes a first group of sub-pixels (P1) and a second group of sub-pixels (P2). The first group of sub-pixels (P1) includes a first subgroup of sub-pixels (P11), a second subgroup of sub-pixels (P12), and a third subgroup of sub-pixels (P13). The pixel driving circuits (122) of the first, second, and third sub-group sub-pixels (P11, P12, P13) are electrically connected to the anodes (P11-1211, P12-1211, P13-1211) of the light-emitting elements of the first, second, and third sub-group sub-pixels (P11, P12, P13) via the first, second, and third sets of anode connection lines (GC1, GC2, GC3). At least one set of the first, second, and third sets of anode connection lines (GC1, GC2, GC3) includes multiple first anode connection lines (AC1), and the first anode connection line (AC1) closer to the first gate driving sub-circuit (211A1) among the multiple first anode connection lines (AC1) has a longer length.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel, a method for manufacturing the same, and a display device. Background Technology

[0002] In recent years, organic light-emitting diode (OLED) displays have been widely used due to their self-emissive, flexible, and simple manufacturing processes. Wearable and mobile displays are developing towards smaller bezels and larger screen-to-body ratios. Summary of the Invention

[0003] According to one aspect of the present disclosure, a display panel is provided, comprising: a substrate including a display area and a peripheral area surrounding the display area; a plurality of sub-pixels located in the display area, each sub-pixel including a light-emitting element and a pixel driving circuit configured to drive the light-emitting element; a plurality of gate lines located in the display area and electrically connected to the plurality of sub-pixels; and a gate driving circuit located in the display area, comprising cascaded multi-level gate driving units electrically connected to the plurality of gate lines, wherein one or more gate driving units in the multi-level gate driving circuit include a plurality of gate driving sub-circuits, the plurality of gate driving sub-circuits including a first gate driving sub-circuit and a second gate driving sub-circuit. The plurality of sub-pixels include a first group of sub-pixels and a second group of sub-pixels, wherein the pixel driving circuit of one group of sub-pixels in the first group of sub-pixels and the second group of sub-pixels is located between the first gate driving sub-circuit and the second gate driving sub-circuit, and the pixel driving circuit of the other group of sub-pixels in the first group of sub-pixels and the second group of sub-pixels is located on the side of the first gate driving sub-circuit away from the second gate driving sub-circuit. The first group of sub-pixels includes: a first sub-group of sub-pixels configured to emit light of a first color, wherein the pixel driving circuit of the first sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the first sub-group of sub-pixels via a first group of anode connection lines; a second sub-group of sub-pixels configured to emit light of a second color, wherein the pixel driving circuit of the second sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the second sub-group of sub-pixels via a second group of anode connection lines; and a third sub-group of sub-pixels configured to emit light of a third color, wherein the pixel driving circuit of the third sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the third sub-group of sub-pixels via a third group of anode connection lines. At least one group of the first group of anode connection lines, the second group of anode connection lines, and the third group of anode connection lines includes a plurality of first anode connection lines, wherein the plurality of first anode connection lines includes two first anode connection lines, and the first anode connection line closer to the first gate driving sub-circuit is longer.

[0004] In some embodiments, the length of the first anode connection line that is closer to the first gate drive sub-circuit is greater among the plurality of first anode connection lines.

[0005] In some embodiments, at least one of the first group of anode connection lines, the second group of anode connection lines, and the third group of anode connection lines is located on the same layer as the anode of the light-emitting element.

[0006] In some embodiments, the first set of anode connecting lines is integrally disposed with the anode of the light-emitting element of the first subgroup of sub-pixels; the second set of anode connecting lines is integrally disposed with the anode of the light-emitting element of the second subgroup of sub-pixels; and the third set of anode connecting lines is integrally disposed with the anode of the light-emitting element of the third subgroup of sub-pixels.

[0007] In some embodiments, the first set of anode connection lines are electrically connected to the pixel driving circuit of the first subgroup of sub-pixels via a first set of vias; the second set of anode connection lines are electrically connected to the pixel driving circuit of the second subgroup of sub-pixels via a second set of vias; and the third set of anode connection lines are electrically connected to the pixel driving circuit of the third subgroup of sub-pixels via a third set of vias.

[0008] In some embodiments, the second group of sub-pixels includes: a fourth group of sub-pixels configured to emit light of the first color, wherein the pixel driving circuit of the fourth group of sub-pixels is electrically connected to the anode of the light-emitting element of the fourth group of sub-pixels via a fourth group of anode connection lines; a fifth group of sub-pixels configured to emit light of the second color, wherein the pixel driving circuit of the fifth group of sub-pixels is electrically connected to the anode of the light-emitting element of the fifth group of sub-pixels via a fifth group of anode connection lines; and a sixth group of sub-pixels configured to emit light of the third color, wherein the pixel driving circuit of the sixth group of sub-pixels is electrically connected to the anode of the light-emitting element of the sixth group of sub-pixels via a sixth group of anode connection lines. At least one group of the fourth group of anode connection lines, the fifth group of anode connection lines, and the sixth group of anode connection lines includes a plurality of second anode connection lines, wherein the second anode connection lines closer to the first gate driving sub-circuit have a greater length.

[0009] In some embodiments, the plurality of sub-pixels further includes a third group of sub-pixels and a fourth group of sub-pixels. The pixel driving circuit of one group of the third group of sub-pixels and the fourth group of sub-pixels is located on the side of the second gate driving sub-circuit close to the first gate driving sub-circuit, the first group of sub-pixels, and the second group of sub-pixels. The pixel driving circuit of the other group of sub-pixels is located on the side of the second gate driving sub-circuit away from the first gate driving sub-circuit. The third group of sub-pixels includes: a seventh sub-group of sub-pixels configured to emit light of the first color, the pixel driving circuit of the seventh sub-group of sub-pixels being electrically connected to the anode of the light-emitting element of the seventh sub-group of sub-pixels via a seventh group of anode connection lines; an eighth sub-group of sub-pixels configured to emit light of the second color, the pixel driving circuit of the eighth sub-group of sub-pixels being electrically connected to the anode of the light-emitting element of the eighth sub-group of sub-pixels via an eighth group of anode connection lines; and a ninth sub-group of sub-pixels configured to emit light of the third color, the pixel driving circuit of the ninth sub-group of sub-pixels being electrically connected to the anode of the light-emitting element of the ninth sub-group of sub-pixels via a ninth group of anode connection lines. At least one of the seventh group of anode connection lines, the eighth group of anode connection lines, and the ninth group of anode connection lines includes multiple third anode connection lines, wherein the anode connection lines closer to the second gate drive sub-circuit have a longer length.

[0010] In some embodiments, the fourth group of sub-pixels includes: a tenth sub-pixel configured to emit light of the first color, wherein the pixel driving circuit of the tenth sub-pixel is electrically connected to the anode of the light-emitting element of the tenth sub-pixel via a tenth group of anode connection lines; an eleventh sub-pixel configured to emit light of the second color, wherein the pixel driving circuit of the eleventh sub-pixel is electrically connected to the anode of the light-emitting element of the eleventh sub-pixel via an eleventh group of anode connection lines; and a twelfth sub-pixel configured to emit light of the third color, wherein the pixel driving circuit of the twelfth sub-pixel is electrically connected to the anode of the light-emitting element of the twelfth sub-pixel via a twelfth group of anode connection lines. At least one group of the tenth group of anode connection lines, the eleventh group of anode connection lines, and the twelfth group of anode connection lines includes a plurality of fourth anode connection lines, wherein the length of the third anode connection line closer to the second gate driving sub-circuit is greater than that of the plurality of fourth anode connection lines.

[0011] In some embodiments, the plurality of sub-pixels further includes a fifth group of sub-pixels, wherein the pixel driving circuit of the fifth group of sub-pixels is located between the pixel driving circuit of the first group of sub-pixels and the pixel driving circuit of the fourth group of sub-pixels, the pixel driving circuit of the first group of sub-pixels is located between the first gate driving sub-circuit and the pixel driving circuit of the fifth group of sub-pixels, and the pixel driving circuit of the fourth group of sub-pixels is located between the pixel driving circuit of the fifth group of sub-pixels and the second gate driving sub-circuit. The fifth group of sub-pixels includes: a thirteenth sub-pixel group configured to emit light of the first color, wherein the pixel driving circuit of the thirteenth sub-pixel group is electrically connected to the anode of the light-emitting element of the thirteenth sub-pixel group via a thirteenth group of anode connection lines; a fourteenth sub-pixel group configured to emit light of the second color, wherein the pixel driving circuit of the fourteenth sub-pixel group is electrically connected to the anode of the light-emitting element of the fourteenth sub-pixel group via a fourteenth group of anode connection lines; and a fifteenth sub-pixel group configured to emit light of the third color, wherein the pixel driving circuit of the fifteenth sub-pixel group is electrically connected to the anode of the light-emitting element of the fifteenth sub-pixel group via a fifteenth group of anode connection lines. The thirteenth group of anode connection lines, the fourteenth group of anode connection lines, and the fifteenth group of anode connection lines are all of equal length.

[0012] In some embodiments, the first color, the second color, and the third color are different from each other.

[0013] In some embodiments, the first color is red, the second color is green, and the third color is blue.

[0014] In some embodiments, the display panel further includes: a first circuit connection line located in the display area, one end of the first circuit connection line being electrically connected to a first gate driving sub-circuit, and the other end of the first circuit connection line being electrically connected to a second gate driving sub-circuit. The first group of sub-pixels is located between the first gate driving sub-circuit and the second gate driving sub-circuit. The pixel driving circuit of at least one sub-pixel in the first group of sub-pixels includes: a first pixel driving sub-circuit located on one side of the first circuit connection line, including a driving transistor, the driving transistor including a first active layer located on one side of the substrate; a second pixel driving sub-circuit located on the side of the first circuit connection line away from the first pixel driving sub-circuit; and a connector, one end of the connector being electrically connected to the first pixel driving sub-circuit, and the other end of the connector being electrically connected to the second pixel driving circuit. The orthographic projection of the connector on the substrate overlaps with the orthographic projection of the first circuit connection line on the substrate, and the connector and the driving active layer are located on different layers.

[0015] In some embodiments, the driving transistor further includes: a first gate located on the side of the first active layer away from the substrate; a first insulating layer located on the side of the first gate away from the substrate; a second insulating layer located on the side of the first insulating layer away from the substrate; and a first electrode and a second electrode located on the side of the second insulating layer away from the substrate and electrically connected to the first active layer. The first pixel driving sub-circuit further includes a storage capacitor, comprising: a first electrode plate located on the same layer as the first gate; and a second electrode plate located between the first insulating layer and the second insulating layer. The first circuit connection line is located on the same layer as the first gate, and at least one of the second electrode plate, the first electrode, and the second electrode is located on the same layer as the connector.

[0016] In some embodiments, the first electrode, the second electrode, and the connector are located on the same layer.

[0017] In some embodiments, the one or more gate driving units include cascaded preceding gate driving units and subsequent gate driving units, wherein: the first gate driving sub-circuit of the preceding gate driving unit includes a first input terminal of the preceding gate driving unit, and the second gate driving sub-circuit of the preceding gate driving unit includes a first output terminal of the preceding gate driving unit; the first gate driving sub-circuit of the subsequent gate driving unit includes a first input terminal of the subsequent gate driving unit, and the second gate driving sub-circuit of the subsequent gate driving unit includes a first output terminal of the subsequent gate driving unit.

[0018] In some embodiments, the first output terminal of the preceding gate driving unit is electrically connected to the first gate line of the plurality of gate lines; the display panel further includes: a first cascade connection line located on the side of the pixel driving circuit of the first group of sub-pixels away from the second gate driving circuit, one end of the first cascade connection line being electrically connected to the first gate line, and the other end of the first cascade connection line being electrically connected to the first input terminal of the following gate driving unit.

[0019] In some embodiments, the display panel further includes: a plurality of reset lines located in the display area and electrically connected to the plurality of sub-pixels; the pixel driving circuit of the first group of sub-pixels between the first gate driving sub-circuit and the second gate driving sub-circuit of the subsequent gate driving unit is electrically connected to the first reset line among the plurality of reset lines, and the first reset line is electrically connected to the first gate line via the first cascade connection line.

[0020] In some embodiments, the first cascaded connection line is electrically connected to the first gate line via a first via, electrically connected to the first input terminal of the subsequent gate drive unit via a second via, and electrically connected to the first reset line via a third via.

[0021] In some embodiments, the display panel further includes: a second cascaded connection line located on the side of the first group of sub-pixels away from the first gate driving sub-circuit, one end of the second cascaded connection line being electrically connected to the first gate line, and the other end of the second cascaded connection line being electrically connected to the first reset line.

[0022] In some embodiments, the display panel further includes: a plurality of light-emitting control lines located in the display area and electrically connected to the plurality of sub-pixels; a light-emitting control driving circuit located in the display area, comprising cascaded multi-level light-emitting control driving units, the multi-level light-emitting control driving units being electrically connected to the plurality of light-emitting control lines, wherein one or more of the multi-level light-emitting control driving units include a plurality of light-emitting control driving sub-circuits, the plurality of light-emitting control driving sub-circuits including a first light-emitting control driving sub-circuit and a second light-emitting control driving sub-circuit, the first light-emitting control driving sub-circuit and the second light-emitting control driving sub-circuit being separated by the pixel driving circuit of the sixth group of sub-pixels in the plurality of sub-pixels.

[0023] According to another aspect of the present disclosure, a display device is provided, comprising: the display panel described in any of the above embodiments.

[0024] According to another aspect of the present disclosure, a method for manufacturing a display panel is provided, comprising: providing a substrate, the substrate including a display area and a peripheral area surrounding the display area; and forming a plurality of sub-pixels, a plurality of gate lines, and a gate driving circuit in the display area. Each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element, the plurality of gate lines being electrically connected to the plurality of sub-pixels. The gate driving circuit includes cascaded multi-level gate driving units, the multi-level gate driving units being electrically connected to the plurality of gate lines, one or more of the multi-level gate driving units in the multi-level gate driving circuit including a plurality of gate driving sub-circuits, the plurality of gate driving sub-circuits including a first gate driving sub-circuit and a second gate driving sub-circuit. The plurality of sub-pixels includes a first group of sub-pixels and a second group of sub-pixels, the pixel driving circuit of one group of sub-pixels in the first group of sub-pixels and the second group of sub-pixels being located between the first gate driving sub-circuit and the second gate driving sub-circuit, and the pixel driving circuit of the other group of sub-pixels in the first group of sub-pixels and the second group of sub-pixels being located on the side of the first gate driving sub-circuit away from the second gate driving sub-circuit. The first group of sub-pixels includes: a first sub-group of sub-pixels configured to emit light of a first color, wherein the pixel driving circuit of the first sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the first sub-group of sub-pixels via a first group of anode connection lines; a second sub-group of sub-pixels configured to emit light of a second color, wherein the pixel driving circuit of the second sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the second sub-group of sub-pixels via a second group of anode connection lines; and a third sub-group of sub-pixels configured to emit light of a third color, wherein the pixel driving circuit of the third sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the third sub-group of sub-pixels via a third group of anode connection lines. At least one group of the first group of anode connection lines, the second group of anode connection lines, and the third group of anode connection lines includes a plurality of first anode connection lines, wherein the plurality of first anode connection lines includes two first anode connection lines, and the first anode connection line closer to the first gate driving sub-circuit is longer. Attached Figure Description

[0025] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0026] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0027] Figure 1A This is a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure;

[0028] Figure 1BThis is a circuit diagram of a sub-pixel according to an embodiment of the present disclosure;

[0029] Figure 2 This is a schematic diagram illustrating the structure of a display panel according to another embodiment of the present disclosure;

[0030] Figure 3A This is a schematic diagram showing the distribution of a plurality of gate drive sub-circuits according to an embodiment of the present disclosure;

[0031] Figure 3B This is a schematic diagram showing the distribution of multiple light-emitting control driving sub-circuits according to an embodiment of the present disclosure;

[0032] Figures 4A-4F This is a schematic diagram showing the layout of different layers in a gate driving cell according to some implementations of the present disclosure;

[0033] Figure 5A yes Figure 4A An enlarged schematic diagram of 211A1 is shown below;

[0034] Figure 5B yes Figure 4A An enlarged schematic diagram of 211A2 is shown below;

[0035] Figure 6 This is a circuit diagram illustrating a gate driving unit according to an embodiment of the present disclosure;

[0036] Figures 7A-7F This is a schematic diagram showing the layout of different layers in a gate driving cell according to other implementations of this disclosure;

[0037] Figure 8A yes Figure 7A An enlarged schematic diagram of 211A1 is shown below;

[0038] Figure 8B yes Figure 7A An enlarged schematic diagram of 211A2 is shown below;

[0039] Figure 8C yes Figure 7A An enlarged schematic diagram of 211A3 is shown below;

[0040] Figure 9 This is a circuit diagram illustrating a gate driving unit according to another embodiment of the present disclosure;

[0041] Figures 10A-10F This is a schematic diagram showing the layout of different layers in a light-emitting control driving unit according to some implementations of this disclosure;

[0042] Figure 11A yes Figure 10A An enlarged schematic diagram of 221A2 is shown below;

[0043] Figure 11B yes Figure 10A An enlarged schematic diagram of 221A1 is shown below;

[0044] Figure 12 This is a circuit diagram illustrating a light-emitting control driving unit according to an embodiment of the present disclosure;

[0045] Figures 13A-13F This is a schematic diagram showing the layout of different layers in a light-emitting control driving unit according to some other implementations of this disclosure;

[0046] Figure 14A yes Figure 13A An enlarged schematic diagram of 221A2 is shown below;

[0047] Figure 14B yes Figure 13A An enlarged schematic diagram of 221A1 is shown below;

[0048] Figure 15 This is a circuit diagram illustrating a light-emitting control driving unit according to another embodiment of the present disclosure;

[0049] Figure 16A This is a schematic diagram showing the distribution of a plurality of gate drive sub-circuits according to another embodiment of the present disclosure;

[0050] Figure 16B This is a schematic diagram showing a partial cross-sectional view of a sub-pixel according to an embodiment of the present disclosure;

[0051] Figure 17A This is a schematic diagram showing the layout of overlapping gate drive sub-circuit connection lines and connectors according to an embodiment of the present disclosure;

[0052] Figure 17B It is along Figure 17A The diagram shows the cross-section cut by A-A'.

[0053] Figure 18 This is a schematic diagram showing the distribution of a plurality of light-emitting control driving sub-circuits according to another embodiment of the present disclosure;

[0054] Figure 19 This is a schematic diagram illustrating the layout of a portion of a layer in a sub-pixel according to an embodiment of the present disclosure;

[0055] Figure 20 This is a schematic diagram illustrating a cascaded two-stage gate drive unit according to an embodiment of the present disclosure;

[0056] Figure 21 This is a schematic diagram showing the distribution of a plurality of gate drive sub-circuits according to yet another embodiment of the present disclosure;

[0057] Figures 22A-22EThis is a schematic diagram showing different groups of anode connection lines according to some embodiments of the present disclosure;

[0058] Figure 23A This is a schematic diagram illustrating the structure of a display panel according to yet another embodiment of the present disclosure;

[0059] Figure 23B yes Figure 23A An enlarged schematic diagram of circle B shown;

[0060] Figure 24 It is shown Figure 23B A partial schematic diagram;

[0061] Figure 25 This is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure;

[0062] Figure 26 This is a schematic flowchart illustrating a method for manufacturing a display panel according to another embodiment of the present disclosure;

[0063] Figure 27 This is a schematic flowchart illustrating a method for manufacturing a display panel according to yet another embodiment of the present disclosure;

[0064] Figure 28 This is a schematic flowchart illustrating a method for manufacturing a display panel according to another embodiment of the present disclosure.

[0065] It should be understood that the dimensions of the various parts shown in the accompanying drawings are not necessarily drawn to actual scale. Furthermore, the same or similar reference numerals denote the same or similar components. Detailed Implementation

[0066] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless otherwise specifically stated, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0067] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "containing" mean that the element preceding the word encompasses the element listed after the word, and do not exclude the possibility of encompassing other elements as well. Terms such as "above" and "below" are used only to indicate relative positional relationships, and these relative positional relationships may also change accordingly when the absolute position of the described object changes.

[0068] In this disclosure, when a specific component is described as being located between a first component and a second component, an intermediary component may or may not be present between the specific component and the first or second component. When a specific component is described as connecting to other components, the specific component may be directly connected to the other components without having an intermediary component, or it may not be directly connected to the other components but may have an intermediary component.

[0069] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0070] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0071] In related technologies, driving circuits, such as gate driving circuits or light-emitting control driving circuits, are arranged in the peripheral area of ​​the display panel to drive the sub-pixels of the display panel to emit light. The inventors noted that for some small-sized wearable devices, such as round watches, a smaller bezel size is required.

[0072] In view of the above, the present disclosure provides the following technical solutions.

[0073] Figure 1A This is a schematic diagram of the structure of a display panel according to an embodiment of the present disclosure. Figure 1B This is a circuit diagram of a sub-pixel according to an embodiment of the present disclosure.

[0074] like Figure 1A As shown, the display panel includes a substrate 11 and a plurality of sub-pixels 12.

[0075] The substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area 111. Here, the display area 111 is schematically shown as generally circular, and the peripheral area 112 is schematically shown as generally annular. It should be understood that the embodiments disclosed herein are not limited thereto. For example, in other embodiments, the display area 111 may be generally rectangular, and the peripheral area 112 may be generally a rectangular ring. In some embodiments, the substrate 11 may include a flexible substrate, such as a polyimide (PI) substrate, etc.

[0076] Multiple subpixels 12 are located in the display area 111. For example, the multiple subpixels 12 may include red subpixels, green subpixels, or blue subpixels, etc.

[0077] like Figure 1B As shown, each sub-pixel 12 includes a light-emitting element 121 and a pixel driving circuit 122 configured to drive the light-emitting element 121. For example, the light-emitting element 121 may include an organic light-emitting diode (OLED), etc. See, for example, [link to documentation]. Figure 1B The pixel driving circuit 122 may include seven transistors and one capacitor (7T1C). For example, the seven transistors may be PMOS (P-channel metal oxide semiconductor) transistors. Alternatively, some of the seven transistors may be PMOS transistors, while the others may be NMOS (N-channel metal oxide semiconductor) transistors. In other embodiments, the pixel driving circuit 122 may include six transistors and one capacitor (6T1C).

[0078] It should be noted that for the display panels of the different embodiments described below, the substrate 11 and the plurality of sub-pixels 12 can all refer to the above description, and will not be described in detail again in the following description.

[0079] Figure 2 This is a schematic diagram illustrating the structure of a display panel according to another embodiment of the present disclosure. Figure 3A This is a schematic diagram showing the distribution of a plurality of gate drive sub-circuits according to an embodiment of the present disclosure. Figure 3B This is a schematic diagram showing the distribution of multiple light-emitting control driving sub-circuits according to an embodiment of the present disclosure.

[0080] like Figure 2 As shown, the display panel includes a substrate 11, multiple sub-pixels 12, multiple gate lines 13, multiple light-emitting control lines 14, a gate driving circuit 21, and a light-emitting control driving circuit 22.

[0081] The substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area 111. A plurality of sub-pixels 12 are located in the display area 111. A plurality of gate lines 13 are located in the display area 111 and electrically connected to the plurality of sub-pixels 12. The plurality of gate lines 13 are configured to provide gate drive signals to the plurality of sub-pixels 12. A plurality of light emission control lines 14 are located in the display area 111 and electrically connected to the plurality of sub-pixels 12. The plurality of light emission control lines 14 are configured to provide light emission control signals to the plurality of sub-pixels 12.

[0082] The gate driving circuit 21 is located in the display area 111 and includes cascaded multi-stage gate driving units 211. The multi-stage gate driving units 211 are electrically connected to multiple gate lines 13. For example, the multi-stage gate driving units 211 are electrically connected to multiple gate lines 13 in a one-to-one correspondence. For example, the gate driving unit 211 may be a shift register.

[0083] like Figure 3A As shown, the multi-level gate driving circuit 211 may include a plurality of gate driving sub-circuits 211A. The plurality of gate driving sub-circuits 211A may include a first gate driving sub-circuit 211A1 and a second gate driving sub-circuit 211A2. Here, the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 are separated by the pixel driving circuit 122 of the first group of sub-pixels P1 among the plurality of sub-pixels 12.

[0084] The light emission control driving circuit 22 is located in the display area 111 and includes cascaded multi-level light emission control driving units 221. The multi-level light emission control driving units 221 are electrically connected to multiple light emission control lines 14. For example, a single-level light emission control driving unit 221 is electrically connected to two light emission control lines 14. For example, the light emission control driving unit 221 may be a shift register.

[0085] like Figure 3B As shown, the multi-level light emission control driving unit 221 includes a plurality of light emission control driving sub-circuits 221A. The plurality of light emission control driving sub-circuits 221A includes a first light emission control driving sub-circuit 221A1 and a second light emission control driving sub-circuit 221A2. Here, the first light emission control driving sub-circuit 221A1 and the second light emission control driving sub-circuit 221A2 are separated by pixel driving circuits 122 of the second group of sub-pixels P2 (in some embodiments, the sixth group of sub-pixels P6) among the plurality of sub-pixels 12.

[0086] In the above embodiments, both the gate driving circuit 21 and the light emission control driving circuit 22 are located in the display area 111. The gate driving circuit 21 has at least one gate driving unit 211, which includes multiple gate driving sub-circuits 211A distributed in the pixel driving circuits 122 of the multiple sub-pixels 12. The light emission control driving circuit 22 has at least one light emission control driving unit 221, which includes multiple light emission control driving sub-circuits 221A distributed in the pixel driving circuits 122 of the multiple sub-pixels 12. This structure is advantageous for reducing the bezel size of the display panel.

[0087] The gate driving unit 211 of the gate driving circuit 21 can be split in different ways to obtain multiple corresponding gate driving sub-circuits 211A. These will be described below with reference to different embodiments.

[0088] Figures 4A-4F This is a schematic diagram showing the layout of different layers in a gate driving unit according to some implementations of this disclosure. Figure 5A yes Figure 4A An enlarged schematic diagram of 211A1 is shown.

[0089] Figure 5B yes Figure 4A The enlarged schematic diagram of 211A2 is shown below. (See below for reference.) Figure 2 , Figures 4A-4F ,as well as Figures 5A-5B Some ways of splitting the gate drive unit 211 of the gate drive circuit 21 are introduced.

[0090] In some embodiments, see Figure 2 The display panel also includes multiple initialization lines 17 and multiple reset lines 18. The multiple initialization lines 17 are located in the display area 111 and are electrically connected to multiple sub-pixels 12. The multiple initialization lines 17 are configured to provide initialization signals to the multiple sub-pixels 12. The multiple reset lines 18 are located in the display area 111 and are electrically connected to the multiple sub-pixels 12. The multiple reset lines 18 are configured to provide reset signals to the multiple sub-pixels 12.

[0091] See Figure 4A and Figure 4BThe first group of sub-pixels P1 is electrically connected to the first initialization line 171 among multiple initialization lines 17, the first reset line 181 among multiple reset lines 18, the first gate line 131 among multiple gate lines 13, and the first light emission control line 141 among multiple light emission control lines 14. Here, the first initialization line 171 and the first reset line 181 are located on one side of the multiple gate driving sub-circuits 211A, while the first gate line 131 and the first light emission control line 141 are located on the side of the multiple gate driving sub-circuits 211A away from the first initialization line 171 and the first reset line 181. This structure helps to reduce the space occupied by signal lines, thereby contributing to improving the resolution of the display panel.

[0092] In some embodiments, see Figure 4F The orthographic projection of at least one of the gate driving sub-circuits 211A on the substrate 11 overlaps with the orthographic projection of the anode 1211 of the light-emitting element 121 of the first portion of the sub-pixels 12 on the substrate 11, but does not overlap with the orthographic projection of the anode 1211 of the light-emitting element 121 of the remaining sub-pixels 12 on the substrate 11. In this manner, the bezel size of the display panel can be reduced while minimizing impact on display uniformity.

[0093] In some embodiments, the first group of sub-pixels P1 is electrically connected to the first gate line 131 of the plurality of gate lines 13. The first gate driving sub-circuit 211A1 of each stage of the gate driving unit 211 in the one or more stages of the gate driving unit 211 includes a first input terminal IN1 of each stage of the gate driving unit 211, configured to receive a first input signal. The second gate driving sub-circuit 211A2 of each stage of the gate driving unit 211 in the one or more stages of the gate driving unit 211 includes a first output terminal OUT1 of each stage of the gate driving unit 211, configured to output a gate driving signal to the first gate line 131. It should be understood that the first input terminal IN1 of the first stage gate driving unit 211 can receive a signal from outside the gate driving circuit 21 as the first input signal, and the first input terminal IN1 of other stages of the gate driving unit 211 can receive a gate driving signal from the previous stage gate driving unit 211 as the first input signal.

[0094] In some embodiments, see Figures 4A-4FEach level of the multi-level gate driving unit 211 includes multiple gate driving sub-circuits 211A. The first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 are separated by the pixel driving circuit 122 of the first group of sub-pixels P1 in a first direction. The first gate driving sub-circuit 211A1 in any level of the gate driving unit 211 is located between the first gate driving sub-circuit 211A1 in the preceding level of the gate driving unit 211 and the first gate driving sub-circuit 211A1 in the following level of the gate driving unit 211 in a second direction different from the first direction. The second gate driving sub-circuit 211A2 in any level of the gate driving unit 211 is located between the second gate driving sub-circuit 211A2 in the preceding level of the gate driving unit 211 and the second gate driving sub-circuit 211A2 in the following level of the gate driving unit 211 in the second direction. For example, the second direction is perpendicular to the first direction. For example, the first direction is the row direction of multiple sub-pixels 12, and the second direction is the column direction of multiple sub-pixels 12.

[0095] In some embodiments, the display panel further includes a first set of circuit connection lines. See also Figure 4A The first set of circuit connection lines includes a first circuit connection line N1 and a second circuit connection line N2. The second gate driving sub-circuit 211A2 is electrically connected to the first gate driving sub-circuit 211A1 via the first circuit connection line N1 and the second circuit connection line N2. The orthographic projection of one of the first circuit connection line N1 and the second circuit connection line N2 on the substrate 11 does not overlap with the orthographic projection of the pixel driving circuit 122 of the first group of sub-pixels P1 on the substrate 11, while the orthographic projection of the other on the substrate 11 overlaps with the orthographic projection of the pixel driving circuit 122 of at least one sub-pixel 12 in the first group of sub-pixels P1 on the substrate 11. For example, see... Figure 4A The orthographic projection of the first circuit connection line N1 on the substrate 11 does not overlap with the orthographic projection of the pixel driving circuit 122 of the first group of sub-pixels P1 on the substrate 11. The orthographic projection of the second circuit connection line N2 on the substrate 11 overlaps with the orthographic projection of the pixel driving circuit 122 of at least one sub-pixel in the first group of sub-pixels P1 on the substrate 11. It should be understood that the orthographic projection of the first circuit connection line N1 on the substrate 11 overlaps with the orthographic projection of the pixel driving circuit 122 of the first group of sub-pixels P1 located between the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 in the previous stage gate driving unit 211 on the substrate 11.

[0096] In some embodiments, see Figure 4A and Figure 4C The pixel driving circuit 122 of at least one sub-pixel 12 in the first group of sub-pixels P1 includes a first pixel driving sub-circuit 122A, a second pixel driving sub-circuit 122B, and a connector 122C. The first pixel driving sub-circuit 122A is located between the first circuit connection line N1 and the second circuit connection line N2, the second pixel driving sub-circuit 122B is located on the side of the second circuit connection line N2 away from the first pixel driving sub-circuit 122A, and the connector 122C is electrically connected to the first pixel driving sub-circuit 122A and the second pixel driving sub-circuit 122B. For example, one end of the connector 122C is electrically connected to the first pixel driving sub-circuit 122A via a via, and the other end of the connector 122C is electrically connected to the second pixel driving sub-circuit 122B via a via. Here, the orthographic projection of the connector 122C on the substrate 11 overlaps with the orthographic projection of the second circuit connection line N2 on the substrate 11.

[0097] In some embodiments, the first gate driving sub-circuit 211A1 includes a first group of transistors GT1 and a second capacitor C2, and the second gate driving sub-circuit 211A2 includes a second group of transistors GT2 and a first capacitor C1. The number of transistors GT2 in the second group is less than the number of transistors GT1 in the first group, and the aspect ratio of the channel of at least one transistor in the second group of transistors GT2 is greater than the aspect ratio of the channel of each transistor in the first group of transistors GT1. In this manner, the number and size of transistors in the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 are taken into account, so that the space occupied by the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 is relatively close.

[0098] In some embodiments, see Figure 4C The first gate driving sub-circuit 211A1 further includes a first clock signal line CK configured to receive a first clock signal, a second clock signal line CB configured to receive a second clock signal, a first power supply line VGL configured to receive a first power supply voltage, and a second power supply line VGH configured to receive a second power supply voltage. The second gate driving sub-circuit 211A2 further includes a third clock signal line CK' configured to receive the first clock signal, a fourth clock signal line CB' configured to receive the second clock signal, and a fourth power supply line VGH' configured to receive the second power supply voltage. For example, the first power supply voltage is lower than the second power supply voltage.

[0099] In some implementations, the first power line VGL is located on the side of the first group of transistors GT1 closer to the second gate drive sub-circuit 211A2; the second power line VGH is located on the side of the first group of transistors GT1 away from the second gate drive sub-circuit 211A2; the first clock signal line CK and the second clock signal line CB are located on the side of the second power line VGH away from the second gate drive sub-circuit 211A2; the fourth power line VGH' is located on the side of the second group of transistors GT2 and the second capacitor C2 away from the first gate drive sub-circuit 211A1; and the third clock signal line CK' and the fourth clock signal line CB' are located on the side of the second group of transistors GT2 and the second capacitor C2 closer to the first gate drive sub-circuit 211A1.

[0100] Figure 6 This is a circuit diagram illustrating a gate driving unit according to an embodiment of the present disclosure.

[0101] The following is combined Figure 6 This section introduces some specific implementation methods of the first group of transistors GT1 and the second group of transistors GT2.

[0102] See Figure 6 The first group of transistors GT1 is located to the left of line L, and the second group of transistors GT2 is located to the right of line L. For example, the first group of transistors GT1 includes a first transistor T1, a second transistor T2, a third transistor T3, a sixth transistor T6, and a seventh transistor T7. For example, the second group of transistors GT2 includes a fourth transistor T4 and a fifth transistor T5.

[0103] Each transistor in the first group of transistors GT1 and the second group of transistors GT2 includes a gate and an active layer. Here, the active layer includes a first electrode region, a second electrode region, and a channel located between the first and second electrode regions. It should be understood that the region of the active layer of each transistor covered by the gate is the channel, and the region not covered by the gate is the first and second electrode regions. As some implementations, the material of the active layer may include, for example, polysilicon, such as low-temperature polysilicon (LTPS). For example, the first transistor T1 includes a gate T10 and an active layer, the active layer including a first electrode region T11, a second electrode region T12, and a channel T13 located between the first electrode region T11 and the second electrode region T12, and so on. The active layers of transistors T2-T7 sequentially include channels T23, T33, T43, T53, T63, and T73.

[0104] See Figure 5A , Figures 4A-4CThe gate T10 of the first transistor T1 is electrically connected to the first clock signal line CK, and the first electrode region T11 of the first transistor T1 serves as the first input terminal IN1. For example, the first electrode region T11 of the first transistor T1 can be electrically connected to the input electrode 31 to receive the first input signal.

[0105] The gate T20 of the second transistor T2 is electrically connected to the second electrode region T12 of the first transistor T1, and the first electrode region T21 of the second transistor T2 is electrically connected to the gate of the first transistor T1. For example, the gate T20 of the second transistor T2 is electrically connected to the second electrode region T12 of the first transistor T1 via the first connection electrode 41. For example, the first electrode region T21 of the second transistor T2 is electrically connected to the gate T10 of the first transistor T1 via the second connection electrode 42. It should be noted that, in this document, the connection of one component or region to another component or region via a connection electrode can be understood as: one component or region is electrically connected to one end of the connection electrode via a via, and another component or region is electrically connected to the other end of the connection electrode via another via.

[0106] The gate of the third transistor T3 is electrically connected to the gate T10 of the first transistor T1, the first electrode region T31 of the third transistor T3 is electrically connected to the first power supply line VGL, and the second electrode region T32 of the third transistor T3 is electrically connected to the second electrode region T22 of the second transistor T2. For example, the gate T30 of the third transistor T3 is integrally formed with the gate T10 of the first transistor T1.

[0107] The gate T60 of the sixth transistor T6 is electrically connected to the second electrode region T32 of the third transistor T3, and the first electrode region T61 of the sixth transistor T6 is electrically connected to the second power supply line VGH. For example, the gate T60 of the sixth transistor T6 is electrically connected to the second electrode region T32 of the third transistor T3 via the third connection electrode 43.

[0108] The gate T70 of the seventh transistor T7 is electrically connected to the second clock signal line CB, the first electrode region T71 of the seventh transistor T7 is electrically connected to the second electrode region T62 of the sixth transistor T6, and the second electrode region T72 of the seventh transistor T7 is electrically connected to the second electrode region T12 of the first transistor T1.

[0109] See Figure 5B , Figures 4A-4C The gate T40 of the fourth transistor T4 is electrically connected to the gate T60 of the sixth transistor T6 via the second circuit connection line N2. The first electrode region T41 of the fourth transistor T4 is electrically connected to the third power supply line VGL'. The second electrode region T42 of the fourth transistor T4 serves as the first output terminal OUT1. For example, the second electrode region T42 of the fourth transistor T4 can be connected via the output electrode 32 (see...). Figure 4CThe gate T40 of the fourth transistor T4 is electrically connected to the second circuit connection line N2 via the fourth connection electrode 44. The first electrode region 41 of the fourth transistor T4 is electrically connected to the third power supply line VGL' via the fifth connection electrode 45.

[0110] The gate T50 of the fifth transistor T5 is electrically connected to the second electrode region T12 of the first transistor T1 via the first circuit connection line N1. The first electrode region T51 of the fifth transistor T5 is electrically connected to the output electrode 32, and the second electrode region T52 of the fifth transistor T5 is electrically connected to the third clock signal line CK'. For example, the gate T50 of the fifth transistor T5 is electrically connected to the first circuit connection line N1 via the sixth connection electrode 46. For example, the second electrode region of the fifth transistor T5 is electrically connected to the fourth clock signal line CB' via the seventh connection electrode 47.

[0111] The first electrode plate C11 of the first capacitor C1 is electrically connected to the gate T50 of the fifth transistor T5, and the second electrode plate C12 of the first capacitor C1 is electrically connected to the output electrode 32. For example, the first electrode plate C11 of the first capacitor C1 is integrally formed with the gate T50 of the fifth transistor T5. The first electrode plate C21 of the second capacitor C2 is electrically connected to the gate T60 of the sixth transistor T6, and the second electrode plate C22 of the second capacitor C2 is electrically connected to the second power supply line VGH. For example, the first electrode plate C21 of the second capacitor C2 is integrally formed with the gate T60 of the sixth transistor T6.

[0112] Figures 7A-7F This is a schematic diagram showing the layout of different layers in a gate drive unit according to other implementations of this disclosure. Figure 8A yes Figure 7A An enlarged schematic diagram of 211A1 is shown.

[0113] Figure 8B yes Figure 7A An enlarged schematic diagram of 211A2 is shown. Figure 8C yes Figure 7A An enlarged schematic diagram of 211A3 is shown.

[0114] The following is combined Figures 7A-7F ,as well as Figures 8A-8C Some other ways of splitting the gate drive unit 211 of the gate drive circuit 21 will be introduced.

[0115] In some embodiments, see Figure 7AThe first set of circuit connection lines includes a first circuit connection line N1, a second circuit connection line N2, and a third circuit connection line N3. The orthographic projections of the third circuit connection line N3 and the second circuit connection line N2 on the substrate 11 do not overlap with the orthographic projections of the pixel driving circuit 122 of the first group of sub-pixels P1 on the substrate 11. However, the orthographic projection of the first circuit connection line N1 on the substrate 11 overlaps with the orthographic projection of the pixel driving circuit 122 of the first group of sub-pixels P1 on the substrate 11. It should be understood that the orthographic projections of the third circuit connection line N3 and the second circuit connection line N2 on the substrate 11 overlap with the orthographic projection of the pixel driving circuit 122 of the first group of sub-pixels P1 located between the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 in the previous stage gate driving unit 211.

[0116] The plurality of gate driving sub-circuits 211A also includes a third gate driving sub-circuit 211A3. The third gate driving sub-circuit 211A3 is located on the side of the second gate driving sub-circuit 211A2 away from the first gate driving sub-circuit 211A1. The third gate driving sub-circuit 211A3 is electrically connected to the second gate driving sub-circuit 211A2 via a third circuit connection line N3, and is also electrically connected to the first gate driving sub-circuit 211A1 via a first circuit connection line N1. Here, the third gate driving sub-circuit 211A3 and the second gate driving sub-circuit 211A2 are separated by another first group of sub-pixels P1.

[0117] In some embodiments, the first gate driving sub-circuit 211A1 includes a third group of transistors GT3, a first clock signal line CK configured to receive a first clock signal, a second clock signal line CB configured to receive a second clock signal, and a first power supply line VGL configured to receive a first power supply voltage. The second gate driving sub-circuit 211A2 includes at least one capacitor, a fourth group of transistors GT4, and a second power supply line VGH configured to receive a second power supply voltage, wherein the aspect ratio of the channel of one transistor in the fourth group of transistors GT4 is greater than the aspect ratio of the channel of each transistor in the third group of transistors GT3. The third gate driving sub-circuit 211A3 includes a fifth group of transistors GT5, a third clock signal line CK' configured to receive a first clock signal, and a fourth clock signal line CB' configured to receive a second clock signal, wherein the aspect ratio of the channel of one transistor in the fifth group of transistors GT5 is greater than the aspect ratio of the channel of each transistor in the third group of transistors GT3.

[0118] In some implementations, the first power supply line VGL is located on the side of the third group transistor GT3 closest to the second gate drive sub-circuit 211A2. In some implementations, the first clock signal line CK and the second clock signal line CB are located on the side of the third group transistor GT3 furthest from the second gate drive sub-circuit 211A2. In some implementations, the third clock signal line CK' and the fourth clock signal line CB' are located on the side of the fifth group transistor GT5 furthest from the second gate drive sub-circuit 211A2.

[0119] Figure 9 This is a circuit diagram illustrating a gate driving unit according to another embodiment of the present disclosure.

[0120] The following is combined Figure 9 This paper introduces some specific implementations of at least one capacitor in the third group transistor GT3, the fourth group transistor GT4, the fifth group transistor GT5, and the second gate drive sub-circuit 211A2.

[0121] See Figure 9 The third group of transistors GT3 is located to the left of line L1, the fourth group of transistors GT4 is located to the right of line L1 and above line L2, and the fifth group of transistors GT5 is located to the right of line L1 and below line L2. For example, the third group of transistors GT3 includes the first transistor T1, the second transistor T2, and the third transistor T3. For example, the fourth group of transistors GT4 includes the fourth transistor T4 and the sixth transistor T6. For example, the fifth group of transistors GT5 includes the fifth transistor T5 and the seventh transistor T7. For example, at least one capacitor in the second gate drive sub-circuit 211A2 includes the first capacitor C1 and the second capacitor C2.

[0122] Each of the third group of transistors GT3, the fourth group of transistors GT4, and the fifth group of transistors GT5 includes a gate and an active layer. Here, the active layer includes a first electrode region, a second electrode region, and a channel located between the first and second electrode regions. As some implementations, the material of the active layer may include polysilicon, such as low-temperature polysilicon. For example, the first transistor T1 includes a gate T10 and an active layer, the active layer including a first electrode region T11, a second electrode region T12, and a channel T13 located between the first electrode region T11 and the second electrode region T12, and so on. The active layers of transistors T2-T7 sequentially include channels T23, T33, T43, T53, T63, and T73.

[0123] See Figure 8AThe gate T10 of the first transistor T1 is electrically connected to the first clock signal line CK, and the first electrode region T11 of the first transistor T1 serves as the first input terminal IN1. For example, the first electrode region T11 of the first transistor T1 can be electrically connected to the input electrode 31 to receive the first input signal.

[0124] The gate T20 of the second transistor T2 is electrically connected to the second electrode region T12 of the first transistor T1, and the first electrode region T21 of the second transistor T2 is electrically connected to the gate T10 of the first transistor T1. For example, the gate T20 of the second transistor T2 is connected via... Figure 7C The connecting electrode 51 shown is electrically connected to the second electrode region T12 of the first transistor T1, and the first electrode region T21 of the second transistor T2 is connected via... Figure 7C The connecting electrode 52 shown is electrically connected to the gate T10 of the first transistor T1.

[0125] The gate T30 of the third transistor T3 is electrically connected to the gate T10 of the first transistor T1. The first electrode region T31 of the third transistor T3 is electrically connected to the first power supply line VGL. The second electrode region T32 of the third transistor T3 is electrically connected to the second electrode region T22 of the second transistor T2. For example, the gate T30 of the third transistor T3 and the gate T10 of the first transistor T1 are integrally formed. For example, the second electrode region T32 of the third transistor T3 is connected via... Figure 7C The connecting electrode 53 shown is electrically connected to the second electrode region T22 of the second transistor T2.

[0126] See Figure 8B The gate of the fourth transistor T4 is electrically connected to the second electrode region T21 of the second transistor T2 via the second circuit connection line N2. The first electrode region T41 of the fourth transistor T4 is electrically connected to the second power supply line VGH. The second electrode region T42 of the fourth transistor T4 is electrically connected to the first gate line 131 via the first output electrode 32. For example, the gate of the fourth transistor T4 is connected via... Figure 7C The connecting electrode 54 shown is electrically connected to the second circuit connection line N2, which is connected via... Figure 7C The connecting electrode 55 shown and via Figure 7B The connecting electrode 56 shown is electrically connected to the second electrode region T21 of the second transistor T2.

[0127] The gate T60 of the sixth transistor T6 is electrically connected to the gate T40 of the fourth transistor T4, and the first electrode region T61 of the sixth transistor T6 is electrically connected to the second power supply line VGH. For example, the gate T60 of the sixth transistor T6 and the gate T40 of the fourth transistor T4 are integrally formed. For example, the first electrode region T61 of the sixth transistor T6 is electrically connected to the second power supply line VGH via a via.

[0128] The first electrode plate C11 of the first capacitor C1 is electrically connected to the gate T20 of the second transistor T2 via a first circuit connection line N1, and the second electrode plate C12 of the first capacitor C1 is electrically connected to the first output electrode 32. For example, the first electrode plate C11 of the first capacitor C1 is electrically connected to the gate T20 of the second transistor T2 via a first circuit connection line N1. Figure 7C The connecting electrode 57 shown is electrically connected to the first circuit connection line N1, which is connected via... Figure 7C The connection electrode 58 shown is electrically connected to the gate T20 of the second transistor T2. For example, the second electrode plate C12 of the first capacitor C1 is electrically connected to the first output electrode 32 via a via.

[0129] The first electrode plate C21 of the second capacitor C2 is electrically connected to the gate T40 of the fourth transistor T4, and the second electrode plate C22 of the second capacitor C2 is electrically connected to the second power supply line VGH. For example, the first electrode plate C21 of the second capacitor C2 and the gate T40 of the fourth transistor T4 are integrally formed. For example, the second electrode plate C22 of the second capacitor C2 is electrically connected to the second power supply line VGH via a via.

[0130] See Figure 8C The gate T50 of the fifth transistor T5 is electrically connected to the gate T20 of the second transistor T2 via the first circuit connection line N1. The first electrode region T51 of the fifth transistor T5 is electrically connected to the second output electrode 32', and the second electrode region T52 of the fifth transistor T5 is electrically connected to the fourth clock signal line CB'. For example, the gate T50 of the fifth transistor T5 is connected via... Figure 7C The connecting electrode 59 shown is electrically connected to the first circuit connection line N1. For example, the second electrode region T52 of the fifth transistor T5 is connected via... Figure 7C The connecting electrode 60 shown and Figure 7B The connecting electrode 61 shown is electrically connected to the fourth clock signal line CB'.

[0131] The gate T70 of the seventh transistor T7 is electrically connected to the fourth clock signal line CB'. The first electrode T71 region of the seventh transistor T7 is electrically connected to the second electrode region T62 of the sixth transistor T6 via the third circuit connection line N3. The second electrode region T72 of the seventh transistor T7 is electrically connected to the gate T50 of the fifth transistor T5. For example, the first electrode T71 region of the seventh transistor T7 is connected via... Figure 7C The connecting electrode 62 shown is electrically connected to the third circuit connection line N3, and the second electrode region T72 of the seventh transistor T7 is connected via... Figure 7C The connecting electrode 63 shown is electrically connected to the gate T50 of the fifth transistor T5.

[0132] Figure 8A One of the second electrode region T42 of the fourth transistor T4 and the first electrode region T51 of the fifth transistor T5 can be used as Figure 9 The first output terminal OUT1 is shown.

[0133] The light-emitting control driving unit 221 of the light-emitting control driving circuit 22 can also be split in different ways to obtain multiple corresponding light-emitting control driving sub-circuits 221A. These will be described below with reference to different embodiments.

[0134] Figures 10A-10F This is a schematic diagram showing the layout of different layers in a light-emitting control driving unit according to some implementations of this disclosure. Figure 11A yes Figure 10A An enlarged schematic diagram of 221A2 is shown. Figure 11B yes Figure 10A An enlarged schematic diagram of 221A1 is shown.

[0135] The following is combined Figures 10A-10F ,as well as Figures 11A-11B Some ways of splitting the light-emitting control driving unit 221 of the light-emitting control driving circuit 22 are introduced.

[0136] In some embodiments, see Figure 10A The second group of sub-pixels P2 includes multiple first sub-pixels P21 and multiple second sub-pixels P22. The multiple first sub-pixels P21 are electrically connected to the first light-emitting control line 141 of the multiple light-emitting control lines 14, and the multiple second sub-pixels P22 are electrically connected to the second light-emitting control line 142 of the multiple light-emitting control lines 14. The first light-emitting control driving sub-circuit 221A1 of each stage of the one-level or multi-level light-emitting control driving unit 221 includes a second input terminal IN2 of each stage of the light-emitting control driving unit 221. The second input terminal IN2 is configured to receive a second input signal. The second light-emitting control driving sub-circuit 221A2 of each stage of the one-level or multi-level light-emitting control driving unit 221 includes a second output terminal OUT2 of each stage of the light-emitting control driving unit 221. The second output terminal OUT2 is configured to output light-emitting control signals to the first light-emitting control line 141 and the second light-emitting control line 142.

[0137] In some embodiments, see Figure 10F The orthographic projection of at least one of the plurality of light-emitting control driving sub-circuits 221A on the substrate 11 overlaps with the orthographic projection of the anode 1211 of the light-emitting element 121 of the second portion of the plurality of sub-pixels 12 on the substrate 11, but does not overlap with the orthographic projection of the anode 1211 of the light-emitting element 121 of the remaining sub-pixels 12 on the substrate 11. In this manner, the bezel size of the display panel can be reduced while minimizing the impact on display uniformity.

[0138] In some embodiments, see Figures 10A-10F Each level of the multi-level light emission control driving unit 221 includes multiple light emission control driving sub-circuits 221A. The first light emission control driving sub-circuit 221A1 and the second light emission control driving sub-circuit 221A2 are separated by the pixel driving circuit 122 of the second group of sub-pixels P2 in a first direction. The first light emission control driving sub-circuit 221A1 in any level of the light emission control driving unit 221 is located between the first light emission control driving sub-circuit 221A1 in the preceding level of the light emission control driving unit 221 and the first light emission control driving sub-circuit 221A1 in the following level of the light emission control driving unit 221 in a second direction different from the first direction. The second light-emitting control driving sub-circuit 221A2 in any first-level light-emitting control driving unit 221 is located in a second direction between the second light-emitting control driving sub-circuit 221A2 in the preceding light-emitting control driving unit 221 and the second light-emitting control driving sub-circuit 221A2 in the following light-emitting control driving unit 221. For example, the second direction is perpendicular to the first direction.

[0139] In some embodiments, the display panel further includes a second set of circuit connection lines. See also Figure 10A The second set of circuit connection lines includes a fourth circuit connection line N4 and a fifth circuit connection line N5. The second light-emitting control driving sub-circuit 221A2 is electrically connected to the first light-emitting control driving sub-circuit 221A1 via the fourth circuit connection line N4 and the fifth circuit connection line N5. Here, the orthographic projection of the fourth circuit connection line N4 and the fifth circuit connection line N5 on the substrate 11 overlaps with the orthographic projection of the pixel driving circuit 122 of the second set of sub-pixels P2 on the substrate 11.

[0140] In some embodiments, the first light-emitting control driving sub-circuit 221A1 includes a first group of transistors GT1, a second capacitor C2, a first power supply line VGL configured to receive a first power supply voltage, and a second power supply line VGH configured to receive a second power supply voltage. The second light-emitting control driving sub-circuit 221A2 includes a second group of transistors GT2, a first capacitor C1, a third capacitor C3, a first clock signal line ECK configured to receive a first clock signal, and a second clock signal line ECB configured to receive a second clock signal. Here, the number of transistors in the first group GT1 is less than the number of transistors in the second group GT2, and the aspect ratio of the channel of at least one transistor in the first group GT1 is greater than the aspect ratio of the channel of each transistor in the second group GT2. In some embodiments, the aspect ratio of the channel of each transistor in the first group GT1 is greater than the aspect ratio of the channel of each transistor in the second group GT2.

[0141] In the above embodiments, the number and size of transistors in the first light-emitting control driving sub-circuit 221A1 and the second light-emitting control driving sub-circuit 221A2 are taken into account, so that the space occupied by the first light-emitting control driving sub-circuit 221A1 and the second light-emitting control driving sub-circuit 221A2 is relatively close.

[0142] In some embodiments, the second light-emitting control driving sub-circuit 221A2 may further include a power line configured to receive a first power supply voltage and a second power supply voltage. For example, see... Figure 10C The second light-emitting control driving sub-circuit 221A2 may further include a third power line VGL' configured to receive a first power supply voltage and a fourth power line VGH' configured to receive a second power supply voltage. In some embodiments, the second light-emitting control driving sub-circuit 221A2 may not include power lines configured to receive the first and second power supply voltages. In this case, the second light-emitting control driving sub-circuit 221A2 can be electrically connected to the first power line VGL and the second power line VGH in the first light-emitting control driving sub-circuit 221A1 via circuit connection lines.

[0143] In some embodiments, see Figure 10A The first light-emitting control driving sub-circuit 221A1 includes a first sub-circuit 221A11 and a second sub-circuit 221A12, and the second light-emitting control driving sub-circuit 221A2 includes a third sub-circuit 221A21 and a fourth sub-circuit 221A22.

[0144] The following describes some specific implementation methods of the first sub-circuit 221A11, the second sub-circuit 221A12, the third sub-circuit 221A21, and the fourth sub-circuit 221A22.

[0145] In some implementations, the first sub-circuit 221A11 is located on the side of the first light-emitting control line 141 away from the second light-emitting control line 142, and the second sub-circuit 221A12 is located between the first light-emitting control line 141 and the second light-emitting control line 142. The first sub-circuit 221A11 includes a first subgroup transistor GT11, which includes at least one transistor from the first group of transistors GT1. The second sub-circuit 221A12 includes a second subgroup transistor GT12 and a second capacitor C2, where the second subgroup transistor GT12 includes all transistors from the first group of transistors GT1 other than the first subgroup transistor GT11.

[0146] In some implementations, the third sub-circuit 221A21 is located on the side of the first light-emitting control line 141 away from the second light-emitting control line 142, and is electrically connected to the first sub-circuit 221A11 via a fourth circuit connection line N4. The fourth sub-circuit 221A22 is located between the first light-emitting control line 141 and the second light-emitting control line 142, and is electrically connected to the second sub-circuit 221A12 via a fifth circuit connection line N5. The third sub-circuit 221A21 includes a third sub-group transistor GT21, which includes at least one transistor from the second group transistor GT2. The fourth sub-circuit 221A22 includes a fourth sub-group transistor GT22 and a first capacitor C1, where the fourth sub-group transistor GT22 includes all transistors from the second group transistor GT2 except for the first sub-group transistor GT11.

[0147] According to different embodiments of this disclosure, one of the third sub-circuit 221A21 and the fourth sub-circuit 221A22 further includes a third capacitor C3. These will be described below in conjunction with different embodiments.

[0148] Figure 12 This is a circuit diagram illustrating a light-emitting control driving unit according to an embodiment of the present disclosure.

[0149] The following is combined Figure 12 , Figures 10A-10F ,as well as Figures 11A-11B This section introduces some specific implementations of the first group of transistors GT1 and the second group of transistors GT2. In these implementations, the third sub-circuit 221A21 also includes a third capacitor C3. Additionally, the second light-emitting control driving sub-circuit 221A2 includes a third power line VGL' configured to receive a first power supply voltage and a fourth power line VGH' configured to receive a second power supply voltage.

[0150] See Figure 12The second group of transistors GT2 is located to the left of line L1, and the first group of transistors GT1 is located to the right of line L1. The second group of transistors GT2 includes the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8. The first group of transistors GT1 includes the ninth transistor T9 and the tenth transistor T10.

[0151] The first subgroup of transistors, GT11, is located to the right of line L1 and below line L2. The second subgroup of transistors, GT12, is located to the right of line L1 and above line L2. The third subgroup of transistors, GT21, is located to the left of line L1 and to the left of line L2. The fourth subgroup of transistors, GT22, is located to the left of line L1 and to the right of line L2. The first subgroup of transistors, GT11, includes the tenth transistor, T10. The second subgroup of transistors, GT12, includes the ninth transistor, T9. The third subgroup of transistors, GT21, includes the first transistor, T1, T2, and T5. The fourth subgroup of transistors, GT22, includes the third transistor, T3, T4, T6, T7, and T8.

[0152] Each transistor in the first group of transistors GT1 and the second group of transistors GT2 includes a gate and an active layer. The active layer includes a first electrode region, a second electrode region, and a channel located between the first electrode region and the second electrode region. The material of the active layer may include, for example, polysilicon, such as low-temperature polysilicon. For example, the first transistor T1 includes a gate T10 and an active layer, the active layer including a first electrode region T11, a second electrode region T12, and a channel T13 located between the first electrode region T11 and the second electrode region T12, and so on. The active layers of transistors T2-T10 sequentially include channels T23, T33, T43, T53, T63, T73, T83, T93, and T103.

[0153] The gate T10 of the first transistor T1 is electrically connected to the first clock signal line CK, and the first electrode region T11 of the first transistor T1 serves as the second input terminal IN2. For example, the first electrode region T11 of the first transistor T1 can be electrically connected to the second input electrode 33 to receive the second input signal.

[0154] The gate T20 of the second transistor T2 is electrically connected to the second electrode region T12 of the first transistor T1, and the first electrode region T21 of the second transistor T2 is electrically connected to the gate T10 of the first transistor T1. The gate T20 of the second transistor T2 is connected via... Figure 10C The connection electrode 64 shown is electrically connected to the second electrode region T12 of the first transistor T1. For example, the first electrode region T21 of the second transistor T2 is connected via... Figure 10CThe connecting electrode 65 shown is electrically connected to the gate T10 of the first transistor T1.

[0155] The gate T30 of the third transistor T3 is electrically connected to the second electrode region T22 of the second transistor T2, and the first electrode region T31 of the third transistor T3 is electrically connected to the fourth power supply line VGH'. For example, the gate T30 of the third transistor T3 is connected via... Figure 10C The connecting electrode 66 shown is electrically connected to the second electrode region T22 of the second transistor T2.

[0156] The gate T40 of the fourth transistor T4 is electrically connected to the second clock signal line ECB, the first electrode region T41 of the fourth transistor T4 is electrically connected to the second electrode region T32 of the third transistor T3, and the second electrode region T42 of the fourth transistor T4 is electrically connected to the gate T20 of the second transistor T2. For example, the second electrode region T42 of the fourth transistor T4 is connected via... Figure 10C The connecting electrode 64 shown is electrically connected to the gate T20 of the second transistor T2.

[0157] The gate T50 of the fifth transistor T5 is electrically connected to the gate T10 of the first transistor T1. The first electrode region T51 of the fifth transistor T5 is electrically connected to the third power supply line VGL'. The second electrode region T52 of the fifth transistor T5 is electrically connected to the second electrode region T22 of the second transistor T2. For example, the gate T50 of the fifth transistor T5 and the gate T10 of the first transistor T1 are integrally formed. For example, the second electrode region T52 of the fifth transistor T5 is connected via... Figure 10C The connecting electrode 66 shown is electrically connected to the second electrode region T22 of the second transistor T2.

[0158] The gate T60 of the sixth transistor T6 is electrically connected to the gate T30 of the third transistor T3, and the first electrode region T61 of the sixth transistor T6 is electrically connected to the gate T40 of the fourth transistor T4. For example, the gate T60 of the sixth transistor T6 and the gate T30 of the third transistor T3 are integrally formed. For example, the first electrode region T61 of the sixth transistor T6 is connected via... Figure 10C The connecting electrode 67 shown is electrically connected to the gate T40 of the fourth transistor T4.

[0159] The gate T70 of the seventh transistor T7 is electrically connected to the gate T40 of the fourth transistor T4. For example, the gate T70 of the seventh transistor T7 and the gate T40 of the fourth transistor T4 are integrally formed.

[0160] The first electrode region T81 of the eighth transistor T8 is electrically connected to the fourth power supply line VGH', and the second electrode region T82 of the eighth transistor T8 is electrically connected to the second electrode region T72 of the seventh transistor T7. For example, the second electrode region T82 of the eighth transistor T8 is connected via... Figure 10CThe connecting electrode 68 shown is electrically connected to the second electrode region T72 of the seventh transistor T7.

[0161] The gate T90 of the ninth transistor T9 is electrically connected to the second electrode region T72 of the seventh transistor T7 via the fifth circuit connection line N5. The first electrode region T91 of the ninth transistor T9 is electrically connected to the second power supply line VGH. The second electrode region T92 of the ninth transistor T9 serves as the second output terminal OUT2. For example, the second electrode region T92 of the ninth transistor T9 is electrically connected to the first light-emitting control line 141 and the second light-emitting control line 142 via the second output electrode 34. For example, the gate T90 of the ninth transistor T9 is connected to the second output electrode 34 via the second output electrode 34. Figure 10C The connecting electrode 69 shown is electrically connected to the fifth circuit connection line N5, which is connected via... Figure 10C The connecting electrode 68 shown is electrically connected to the second electrode region T72 of the seventh transistor T7.

[0162] The first electrode region T101 of the tenth transistor T10 is electrically connected to the second output electrode 34, and the second electrode region T102 of the tenth transistor T10 is electrically connected to the first power supply line VGL.

[0163] The first electrode plate C11 of the first capacitor C1 is electrically connected to the gate T30 of the third transistor T3 and the gate T60 of the sixth transistor T6. The second electrode plate C12 of the first capacitor C1 is electrically connected to the second electrode region T62 of the sixth transistor T6 and the first electrode region T71 of the seventh transistor T7. The first electrode plate C11 of the first capacitor C1, the gate T30 of the third transistor T3, and the gate T60 of the sixth transistor T6 are integrally formed. For example, the second electrode plate C12 of the first capacitor C1 is connected via... Figure 10C The connection electrode 70 shown is electrically connected to the second electrode region T62 of the sixth transistor T6, and via... Figure 10C The connecting electrode 71 shown is electrically connected to the first electrode region T71 of the seventh transistor T7.

[0164] The first electrode plate C21 of the second capacitor C2 is electrically connected to the gate T90 of the ninth transistor T9, and the second electrode plate C22 of the second capacitor C2 is electrically connected to the second power supply line VGH. For example, the first electrode plate C21 of the second capacitor C2 and the gate T90 of the ninth transistor T9 are integrally formed.

[0165] The first electrode plate C31 of the third capacitor C3 is electrically connected to the gate T20 of the second transistor T2, the gate T80 of the eighth transistor T8, and the gate T100 of the tenth transistor T10. The second electrode plate C32 of the third capacitor C3 is electrically connected to the gate T40 of the fourth transistor T4. For example, the first electrode plate C31 of the third capacitor C3 and the gate T20 of the second transistor T2 are integrally formed. For example, the first electrode plate C31 of the third capacitor C3 is connected via... Figure 10C The connecting electrode 72 shown is electrically connected to the fourth circuit connection line N4 and the gate T80 of the eighth transistor T8. The fourth circuit connection line N4 is connected via... Figure 10C The connecting electrode 73 shown is electrically connected to the gate T100 of the tenth transistor T10. For example, the second electrode plate C32 of the third capacitor C3 is connected via... Figure 10C The connecting electrode 67 shown is electrically connected to the gate T40 of the fourth transistor T4.

[0166] Figures 13A-13F This is a schematic diagram showing the layout of different layers in a light-emitting control driving unit according to other implementations of this disclosure. Figure 14A yes Figure 13A An enlarged schematic diagram of 221A2 is shown. Figure 14B yes Figure 13A An enlarged schematic diagram of 221A1 is shown.

[0167] The following is combined Figures 13A-13F ,as well as Figures 14A-14B Some other ways of splitting the light-emitting control driving unit 221 of the light-emitting control driving circuit 22 will be introduced.

[0168] See Figure 13A The second set of circuit connection lines includes a fourth circuit connection line N4, a fifth circuit connection line N5, a sixth circuit connection line N6, and a seventh circuit connection line N7. The first light-emitting control driving sub-circuit 221A1 includes a first sub-circuit 221A11 and a second sub-circuit 221A12, and the second light-emitting control driving sub-circuit 221A2 includes a third sub-circuit 221A21 and a fourth sub-circuit 221A22. The third sub-circuit 221A21 is electrically connected to the first power line VGL via the sixth circuit connection line N6, and the third sub-circuit 221A21 is electrically connected to the second power line VGH via the seventh circuit connection line N7. In this case, the second light-emitting control driving sub-circuit 221A2 may not include the third power line VGL' and the fourth power line VGH', thereby reducing the space occupied by the second light-emitting control driving sub-circuit 221A2, and consequently reducing the space occupied by the light-emitting control driving unit 221.

[0169] Figure 15 This is a circuit diagram illustrating a light-emitting control driving unit according to another embodiment of the present disclosure.

[0170] The following is combined Figure 15 , Figures 13A-13F ,as well as Figures 14A-14B This section introduces some specific implementations of the first group of transistors GT1 and the second group of transistors GT2. In these implementations, the fourth sub-circuit 221A22 also includes a third capacitor C3.

[0171] See Figure 15 The second group of transistors GT2 is located to the left of line L1, and the first group of transistors GT1 is located to the right of line L1. The second group of transistors GT2 includes transistors T1, T2, T3, T4, T5, T6, and T7. The first group of transistors GT1 includes transistors T8, T9, and T10.

[0172] The first subgroup of transistors, GT11, is located to the right of line L1 and below line L2. The second subgroup of transistors, GT12, is located to the right of line L1 and above line L2. The third subgroup of transistors, GT21, is located to the left of line L1 and to the left of line L2. The fourth subgroup of transistors, GT22, is located to the left of line L1 and to the right of line L2. The first subgroup of transistors, GT11, includes the tenth transistor, T10. The second subgroup of transistors, GT12, includes the eighth transistor, T8, and the ninth transistor, T9. The third subgroup of transistors, GT21, includes the first transistor, T1, the second transistor, T2, the third transistor, T3, the fourth transistor, T4, and the fifth transistor, T5. The fourth subgroup of transistors, GT22, includes the sixth transistor, T6, and the seventh transistor, T7.

[0173] Similarly, each transistor in the first group of transistors GT1 and the second group of transistors GT2 includes a gate and an active layer. The active layer includes a first electrode region, a second electrode region, and a channel located between the first electrode region and the second electrode region. For example, the first transistor T1 includes a gate T10 and an active layer, which includes a first electrode region T11, a second electrode region T12, and a channel T13 located between the first electrode region T11 and the second electrode region T12, and so on. The active layers of transistors T2-T10 sequentially include channels T23, T33, T43, T53, T63, T73, T83, T93, and T103.

[0174] The gate T10 of the first transistor T1 is electrically connected to the first clock signal line ECK, and the first electrode region T11 of the first transistor T1 serves as the second input terminal IN2. For example, the second input terminal IN2 is electrically connected to the second input electrode 35 to receive the second input signal.

[0175] The gate T20 of the second transistor T2 is electrically connected to the second electrode region T12 of the first transistor T1, and the first electrode region T21 of the second transistor T2 is electrically connected to the gate T10 of the first transistor T1. For example, the gate T20 of the second transistor T2 is connected via... Figure 13C The connection electrode 74 shown is electrically connected to the second electrode region T12 of the first transistor T1. For example, the first electrode region T21 of the second transistor T2 is connected via... Figure 13C The connecting electrode 75 shown is electrically connected to the gate T10 of the first transistor T1.

[0176] The gate of the third transistor T3 is electrically connected to the second electrode region T22 of the second transistor T2, and the first electrode region T31 of the third transistor T3 is electrically connected to the second power supply line VGH via the seventh circuit connection line N7. For example, the gate of the third transistor T3 is connected via... Figure 13C The connecting electrode 76 shown is electrically connected to the second electrode region T22 of the second transistor T2. For example, the first electrode region T31 of the third transistor T3 is connected via... Figure 13C The connecting electrode 77 shown is electrically connected to the seventh circuit connection line N7, which is electrically connected to the second power supply line VGH via a via.

[0177] The gate T40 of the fourth transistor T4 is electrically connected to the second clock signal line ECB. The first electrode region T41 of the fourth transistor T4 is electrically connected to the second electrode region T32 of the third transistor T3. The second electrode region T42 of the fourth transistor T4 is electrically connected to the gate T20 of the second transistor T2. For example, the first electrode region T41 of the fourth transistor T4 and the second electrode region T32 of the third transistor T3 are integrally formed. For example, the second electrode region T42 of the fourth transistor T4 is connected via... Figure 13C The connecting electrode 78 shown is electrically connected to the gate T20 of the second transistor T2.

[0178] The gate T50 of the fifth transistor T5 is electrically connected to the gate T10 of the first transistor T1. The first electrode region T51 of the fifth transistor T5 is electrically connected to the first power supply line VGL via the sixth circuit connection line N6. The second electrode region T52 of the fifth transistor T5 is electrically connected to the second electrode region T22 of the second transistor T2. For example, the gate T50 of the fifth transistor T5 and the gate T10 of the first transistor T1 are integrally formed. For example, the first electrode region T51 of the fifth transistor T5 is connected via... Figure 13C The connecting electrode 79 shown is electrically connected to the sixth circuit connection line N6, which is electrically connected to the first power supply line VGL via a via. For example, the second electrode region T52 of the fifth transistor T5 is connected via... Figure 13C The connecting electrode 76 shown is electrically connected to the second electrode region T22 of the second transistor T2.

[0179] The gate T60 of the sixth transistor T6 is electrically connected to the gate T30 of the third transistor T3. For example, the gate T60 of the sixth transistor T6 is connected via... Figure 13C The connecting electrode 76 shown is electrically connected to the gate T30 of the third transistor T3.

[0180] The gate T70 of the seventh transistor T7 is electrically connected to the first electrode region T61 and the second clock signal line ECB of the sixth transistor T6, and the first electrode region T61 of the seventh transistor T7 is electrically connected to the second electrode region T61 of the sixth transistor T6. For example, the gate T70 of the seventh transistor T7 is connected via... Figure 13C The connecting electrode 84 shown is electrically connected to the first electrode region T61 of the sixth transistor T6. For example, the second electrode region T71 of the seventh transistor T7 is connected via... Figure 13C The connecting electrode 80 shown is electrically connected to the first electrode region T61 of the sixth transistor T6.

[0181] The gate T80 of the eighth transistor T8 is electrically connected to the gate T20 of the second transistor T2 via the fourth circuit connection line N4. The first electrode region T81 of the eighth transistor T8 is electrically connected to the second power supply line VGH. The second electrode region T82 of the eighth transistor T8 is electrically connected to the second electrode region T72 of the seventh transistor T7 via the fifth circuit connection line N5. For example, the gate T80 of the eighth transistor T8 and the fourth circuit connection line N4 are integrally formed. For example, the fourth circuit connection line N4 is connected via... Figure 13C The connection electrode 78 shown is electrically connected to the gate T20 of the second transistor T2. For example, the second electrode region T82 of the eighth transistor T8 is connected via... Figure 13C The connecting electrode 81 shown is electrically connected to the fifth circuit connection line N5, which is connected via... Figure 13C The connecting electrode 82 shown is electrically connected to the second electrode region T72 of the seventh transistor T7.

[0182] The gate T90 of the ninth transistor T9 is electrically connected to the second electrode region T72 of the seventh transistor T7 via the fifth circuit connection line N5. The first electrode region T91 of the ninth transistor T9 is electrically connected to the second power supply line VGH. The second electrode region T92 of the ninth transistor T9 is electrically connected to the first light-emitting control line 141 and the second light-emitting control line 142 via the second output electrode 36.

[0183] The gate T100 of the tenth transistor T10 is electrically connected to the gate T20 of the second transistor T2 via the fourth circuit connection line N4. The first electrode region T11 of the tenth transistor T10 is electrically connected to the second output electrode 36, and the second electrode region T12 of the tenth transistor T10 is electrically connected to the first power supply line VGL. For example, the gate T100 of the tenth transistor T10 is connected via... Figure 13C The connecting electrode 83 shown is electrically connected to the fourth circuit connection line N4.

[0184] The first electrode plate C11 of the first capacitor C1 is electrically connected to the gate T60 of the sixth transistor T6, and the second electrode plate C12 of the first capacitor C1 is electrically connected to the first electrode region T61 of the sixth transistor T6 and the first electrode region T71 of the seventh transistor T7. For example, the first electrode plate C11 of the first capacitor C1 and the gate T60 of the sixth transistor T6 are integrally formed. For example, the second electrode plate C12 of the first capacitor C1 is connected via... Figure 13C The connecting electrode 80 shown is electrically connected to the first electrode region T61 of the sixth transistor T6 and the first electrode region T71 of the seventh transistor T7.

[0185] The first electrode plate C21 of the second capacitor C2 is electrically connected to the gate T90 of the ninth transistor T9, and the second electrode plate C22 of the second capacitor C2 is electrically connected to the second power supply line VGH. For example, the first electrode plate C21 of the second capacitor C2 and the gate T90 of the ninth transistor T9 are integrally formed.

[0186] The first electrode plate C31 of the third capacitor C3 is electrically connected to the gate T70 of the seventh transistor T7, and the second electrode plate C32 of the third capacitor C3 is electrically connected to the fourth circuit connection line N4. For example, the first electrode plate C31 of the third capacitor C3 and the gate T70 of the seventh transistor T7 are integrally formed. For example, the second electrode plate C32 of the third capacitor C3 is connected via... Figure 13C The connecting electrode 78 shown is electrically connected to the fourth circuit connection line N4.

[0187] The above describes various ways of separating the gate driving unit 211 and the light emission control driving unit 221 according to different embodiments of the present disclosure. In the following description, the gate driving unit 211 and the light emission control driving unit 221 can be separated in the manner described above.

[0188] The inventors also noted that when the gate driving unit 211 and the light emission control driving unit 221 are separated into multiple sub-circuits, the circuit connection lines between different sub-circuits may adversely affect the sub-pixel 12. In related technologies, the circuit connection lines may overlap with the active layer in the pixel driving circuit 122 to form transistors, thereby affecting the normal display of the sub-pixel 12 and consequently affecting the display effect of the display panel.

[0189] In view of the above, the present disclosure also provides the following technical solutions.

[0190] Figure 16A This is a schematic diagram showing the distribution of a plurality of gate drive sub-circuits according to another embodiment of the present disclosure. Figure 16B This is a schematic diagram of a partial cross-section of a sub-pixel according to an embodiment of the present disclosure.

[0191] See Figure 1B , Figure 2 and Figure 16A and Figure 16B The display panel includes a substrate 11, multiple sub-pixels 12, multiple gate lines 13, multiple light-emitting control lines 14, a gate driving circuit 21, and gate driving sub-circuit connection lines 23.

[0192] The substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area 111. A plurality of sub-pixels 12 are located in the display area 111. Each sub-pixel 12 includes a light-emitting element 121 and a pixel driving circuit 122 configured to drive the light-emitting element 121. A plurality of gate lines 13 are located in the display area 111 and are electrically connected to the plurality of sub-pixels 12.

[0193] The gate driving circuit 21 is located in the display area 111 and includes cascaded multi-stage gate driving units 211. The multi-stage gate driving units 211 are electrically connected to multiple gate lines 13. For example, the multi-stage gate driving units 211 are electrically connected to multiple gate lines 13 in a one-to-one correspondence.

[0194] like Figure 16A As shown, the multi-level gate driving circuit 211 includes one or more gate driving units 211, which include multiple gate driving sub-circuits 211A. Each gate driving sub-circuit 211A includes a first gate driving sub-circuit 211A1 and a second gate driving sub-circuit 211A2, which are separated by pixel driving circuits 122 of the first group of sub-pixels P1 among the multiple sub-pixels 12.

[0195] The gate driver sub-circuit connection line 23 is located in the display area 111. One end of the gate driver sub-circuit connection line 23 is electrically connected to the first gate driver sub-circuit 211A1, and the other end of the gate driver sub-circuit connection line 23 is electrically connected to the second gate driver sub-circuit 211A2.

[0196] The pixel driving circuit 122 of at least one sub-pixel 12 in the first group of sub-pixels P1 includes a first pixel driving sub-circuit 122A and a second pixel driving sub-circuit 122B. The first pixel driving sub-circuit 122A is located on one side of the gate driving sub-circuit connection line 23, and the second pixel driving sub-circuit 122B is located on the side of the gate driving sub-circuit connection line 23 away from the first pixel driving sub-circuit 122A.

[0197] The first pixel driving sub-circuit 122A includes a driving transistor M3, for example... Figure 1B The driving transistor M3 is shown. See also... Figure 16BThe driving transistor M3 includes a first active layer M34 located on one side of the substrate 11. For example, the material of the first active layer M34 includes a semiconductor material such as polysilicon.

[0198] One end of connector 122C is electrically connected to the first pixel driving sub-circuit 122A, and the other end of connector 122C is electrically connected to the second pixel driving sub-circuit 122A2. The orthographic projection of connector 122C on the substrate 11 overlaps with the orthographic projection of the gate driving sub-circuit connection line 23 on the substrate 11, and connector 122C and the first active layer T14 are located on different layers.

[0199] It should be noted that, in this embodiment, multiple components located on different layers means that multiple components are formed by performing multiple patterning processes on different material layers, while multiple components located on the same layer means that multiple components are formed by performing a single patterning process on the same material layer. Therefore, the material of the connector 122C is different from the material of the first active layer M34.

[0200] In the above embodiment, the connector 122C and the first active layer M34 are located on different layers, and no transistor is formed between the gate drive sub-circuit connection line 23 and the connector 122C. Therefore, the problem of decreased display effect of the display panel caused by the formation of a transistor between the gate drive sub-circuit connection line 23 and the connector 122C is at least mitigated.

[0201] In some embodiments, see Figure 16B The driving transistor M3 further includes a first gate M30 located on the side of the first active layer M34 away from the substrate 11, a first insulating layer 123 located on the side of the first gate M30 away from the substrate 11, a second insulating layer 124 located on the side of the first insulating layer 123 away from the substrate 11, and a first electrode M3A (e.g., drain) and a second electrode M3B (e.g., source) located on the side of the second insulating layer 124 away from the substrate 11 and electrically connected to the first active layer M34. In some embodiments, the driving transistor M3 further includes a gate dielectric layer 122 located on the side of the first active layer M34 away from the substrate 11, and the first gate M30 is located on the side of the gate dielectric layer 122 away from the substrate 11. For example, the first electrode M3A and the second electrode M3B are electrically connected to the first active layer M34 through vias penetrating the second insulating layer 124, the first insulating layer 123, and the gate dielectric layer 122, respectively.

[0202] Figure 16BA light-emitting element 121 is also shown. For example, the light-emitting element 121 includes an anode 1211, a functional layer 1212 located on the side of the anode 1211 away from the substrate 11, and a cathode 1213 located on the side of the functional layer 1212 away from the substrate 11. For example, the anode 1211 of the light-emitting element 121 is electrically connected to the first electrode M3A of the driving transistor M3. Here, the functional layer 1212 includes at least a light-emitting layer, such as an organic light-emitting layer. In some embodiments, the functional layer 1212 may also include one or more of an electron transport layer, an electron injection layer, a hole transport layer, and a hole injection layer.

[0203] In some embodiments, see Figure 16B The sub-pixel 12 may further include a buffer layer 120 located between the substrate 11 and the first active layer M34, a planarization layer 125 covering the first electrode M3A and the second electrode M3B, a pixel defining layer 126 for defining a plurality of sub-pixels 12, a support layer 127, and an encapsulation layer 128. For example, the anode 1211 of the light-emitting element 121 can be electrically connected to the first electrode M3A of the driving transistor M3 through a via penetrating the planarization layer 125. For example, the pixel defining layer 126 has a plurality of openings corresponding to the plurality of sub-pixels 12, and the light-emitting elements 121 of the plurality of sub-pixels 12 are located in the plurality of openings. For example, the encapsulation layer 128 may include a thin film encapsulation layer. In some embodiments, the encapsulation layer 128 may include a first inorganic layer 1281, a second inorganic layer 1282, and an organic layer 1283 located between the first inorganic layer 1281 and the second inorganic layer 1282.

[0204] As some implementations, one or more of the second insulating layer 125, the first insulating layer 124, the gate dielectric layer 122, the buffer layer 120, the planarization layer 125, the pixel defining layer 126, and the support layer 127 may include organic insulating materials such as polyimide and resin materials, or inorganic insulating materials such as silicon oxides, silicon nitrides, and silicon oxynitrides.

[0205] See Figure 16B The first pixel driving sub-circuit 122A also includes a storage capacitor Cst. The storage capacitor Cst includes a first electrode plate Cst1 located on the same layer as the first gate M30, and a second electrode plate Cst2 located between the first insulating layer 123 and the second insulating layer 124. It should be understood that the storage capacitor Cst also includes a first insulating layer 123 located between the first electrode plate Cst1 and the second electrode plate Cst2.

[0206] For example, the gate drive sub-circuit connection line 23 is located on the same layer as the first gate M30, and at least one of the second electrode plate Cst2, the first electrode M3A, and the second electrode M3B is located on the same layer as the connector 122C. In other words, at least a first insulating layer 123 is provided between the gate drive sub-circuit connection line 23 and the connector 122C.

[0207] In some implementations, the gate driving sub-circuit connection line 23 and the first gate M30 are located on the same layer, and the second electrode plate Cst2 and the connector 122C are located on the same layer. In this case, a first insulating layer 123 is provided between the gate driving sub-circuit connection line 23 and the connector 122C, which reduces the adverse effects of the gate driving sub-circuit connection line 23 on the sub-pixel 12.

[0208] In other implementations, the gate drive sub-circuit connection line 23 is located on the same layer as the first gate M30, and the first electrode M3A, the second electrode M3B, and the connector 122C are located on the same layer. In this case, a first insulating layer 123 and a second insulating layer 124 are provided between the gate drive sub-circuit connection line 23 and the connector 122C, further reducing the adverse effects of the gate drive sub-circuit connection line 23 on the sub-pixel 12.

[0209] In the gate driving unit 211 through Figures 4A-4F When the circuit is divided into multiple gate drive sub-circuits 211A as shown, the gate drive sub-circuit connection line 23 can be... Figure 4A The second circuit connection N2 is shown. In other words, Figure 4A The second circuit connection N2 shown is... Figure 16B The first gate M30 shown is located on the same layer. Figure 4C The connector 122C shown, and Figure 16B The first electrode M3A and the second electrode M3B shown are located in the same layer. Additionally, in some embodiments, Figure 4A The first circuit connection line N1 shown is... Figure 16B The first gate M30 shown is located on the same layer as the first circuit connection line N1, and the connector 122C overlaps with it. Figure 16B The first electrode M3A and the second electrode M3B shown are located in the same layer.

[0210] In the gate driving unit 211 through Figures 7A-7F When the circuit is divided into multiple gate drive sub-circuits 211A as shown, the gate drive sub-circuit connection line 23 can be... Figure 7A The first circuit connection N1 is shown. In other words, Figure 7A The first circuit connection line N1 shown is... Figure 16B The first gate M30 shown is located on the same layer. Figure 7C The connector 122C shown, and Figure 16B The first electrode M3A and the second electrode M3B shown are located in the same layer. Additionally, in some embodiments, Figure 7A The second circuit connection line N2 and the third circuit connection line N3 shown are... Figure 16B The first gate M30 shown is located on the same layer as the second circuit connection line N2, and the connector 122C overlapping with the third circuit connection line N3 is... Figure 16B The first electrode M3A and the second electrode M3B shown are located in the same layer.

[0211] Figure 17A This is a schematic diagram showing the layout of overlapping gate drive sub-circuit connection lines and connectors according to an embodiment of the present disclosure. Figure 17B It is along Figure 17A The diagram shows a cross-section cut from A-A'.

[0212] like Figure 17A As shown, the first pixel driving sub-circuit 122A, the second pixel driving sub-circuit 122B, and the connector 122C constitute a sub-pixel 12 in the first group of sub-pixels P1. One end of the connector 122C is electrically connected to the first pixel driving sub-circuit 122A via via VC1, and the other end of the connector 122C is electrically connected to the second pixel driving sub-circuit 122B via via VC2.

[0213] like Figure 17B As shown, the gate drive sub-circuit connection line 23 and Figure 16B The first gate T10 shown is located on the same layer, and the connector 122C is with Figure 16B The first electrode T1A and the second electrode T1B shown are located in the same layer.

[0214] In some embodiments, see Figure 17A and Figure 17B At least one sub-pixel 12 also includes a shielding layer 129. For example, as Figure 17A As shown, the shielding layer 129 can be electrically connected to the power line 16 via the via V161. For example, as Figure 17B As shown, the shielding layer 129 can be with Figure 16B The second electrode plate Cst2 shown is located on the same layer. Furthermore, the orthographic projections of the connector 122C and the gate drive sub-circuit connection line 23 on the substrate 11 at least partially overlap with the orthographic projection of the shielding layer 129 on the substrate 11. In this manner, the shielding layer 129 can reduce the mutual interference between the gate drive sub-circuit connection line 23 and the connector 122C.

[0215] In some embodiments, the portion where the orthographic projection of the connector 122C on the substrate 11 overlaps with the orthographic projection of the gate drive sub-circuit connection line 23 on the substrate 11 lies within the orthographic projection of the shielding layer 129 on the substrate 11. In this manner, the shielding layer 129 can more effectively reduce the mutual interference between the gate drive sub-circuit connection line 23 and the connector 122C.

[0216] Figure 18 This is a schematic diagram showing the distribution of multiple light-emitting control driving sub-circuits according to another embodiment of the present disclosure.

[0217] In some embodiments, see Figure 2 and Figure 18 The display panel also includes a light-emitting control driving circuit 22 and a light-emitting control driving sub-circuit connection line 24 located in the display area 111.

[0218] The light-emitting control driving circuit 22 includes cascaded multi-stage light-emitting control driving units 221 electrically connected to multiple light-emitting control lines 14. For example... Figure 18 As shown, the multi-level light emission control driving unit 221 includes a plurality of light emission control driving sub-circuits 221A. The plurality of light emission control driving sub-circuits 221A includes a first light emission control driving sub-circuit 221A1 and a second light emission control driving sub-circuit 221A2, which are separated by pixel driving circuits 122 of the second group of sub-pixels P2 among the plurality of sub-pixels 12. One end of the light emission control driving sub-circuit connecting line 24 is electrically connected to the first light emission control driving sub-circuit 221A1, and the other end of the light emission control driving sub-circuit connecting line 24 is electrically connected to the second light emission control driving sub-circuit 221A2.

[0219] The pixel driving circuit 122 of at least one sub-pixel 12 in the second group of sub-pixels P2 includes a first pixel driving sub-circuit 122A and a second pixel driving sub-circuit 122B. The first pixel driving sub-circuit 122A is located on one side of the light emission control driving sub-circuit connection line 24, and the second pixel driving sub-circuit 122B is located on the side of the light emission control driving sub-circuit connection line 24 away from the first pixel driving sub-circuit 122A. One end of the connector 122C is electrically connected to the first pixel driving sub-circuit 122A, and the other end of the connector 122C is electrically connected to the second pixel driving sub-circuit 122B.

[0220] The orthographic projection of connector 122C on substrate 11 overlaps with the orthographic projection of light-emitting control driving sub-circuit connection line 24 on substrate 11, and connector 122C and the first active layer M34 are located on different layers. For example, light-emitting control driving sub-circuit connection line 24 and... Figure 16BThe first gate M30 shown is located on the same layer, and the connector 122C is with Figure 16B The first electrode M3A and the second electrode M3B shown are located in the same layer.

[0221] The above embodiments can reduce the adverse effects of the light emission control driving sub-circuit connection line 24 on the sub-pixel 12 and improve the display effect of the display panel.

[0222] Similarly, the aforementioned shielding layer 129 can be provided between the light-emitting control driver sub-circuit connection line 24 and the connector 122C to reduce the mutual influence between the light-emitting control driver sub-circuit connection line 24 and the connector 122C.

[0223] Figure 19 This is a schematic diagram illustrating the layout of a portion of a layer in a sub-pixel according to an embodiment of the present disclosure.

[0224] The following is combined Figure 1B , Figure 2 and Figure 19 This paper introduces some specific implementation methods of the first pixel driving sub-circuit 122A and the second pixel driving sub-circuit 122B.

[0225] See Figure 2 The display panel also includes multiple light-emitting control lines 14, multiple power lines 16, multiple initialization lines 17, and multiple reset lines 18. The multiple light-emitting control lines 14, multiple power lines 16, multiple initialization lines 17, and multiple reset lines 18 are all located in the display area 111 and are electrically connected to multiple sub-pixels 12.

[0226] See Figure 1B The first pixel driving sub-circuit 122A is located on the right side of line L, and the second pixel driving sub-circuit 122B is located on the left side of line L.

[0227] The first pixel driving sub-circuit 122A includes a driving transistor M3, multiple transistors MT, and a storage capacitor Cst. The multiple transistors MT include a first light-emitting control transistor M6. The driving transistor M3 includes a first gate M30 and a first active layer M34. The storage capacitor Cst includes a first electrode plate Cst1 and a second electrode plate Cst2. The first electrode plate Cst1 is electrically connected to one of the multiple power lines 16.

[0228] The second pixel driving sub-circuit 122B includes a first reset transistor M7. Each of the first reset transistor M7 and a plurality of transistors MT includes a second gate and a second active layer. Each of the second active layer and the first active layer M34 includes a first electrode region, a second electrode region, and a channel located between the first electrode region and the second electrode region. For example, the first active layer M34 of the driving transistor M3 includes a first electrode region M31, a second electrode region M32, and a channel M33 located between the first electrode region M31 and the second electrode region M32. For example, the second active layer M64 of the first light-emitting control transistor M6 includes a first electrode region M61, a second electrode region M62, and a channel M63 located between the first electrode region M61 and the second electrode region M62. For example, the second active layer M74 of the first reset transistor M7 includes a first electrode region M71, a second electrode region M72, and a channel M73 located between the first electrode region M71 and the second electrode region M72.

[0229] The first gate M30 of the driving transistor M3 is electrically connected to the second electrode plate Cst2 of the storage capacitor Cst, and the first electrode region M31 of the driving transistor M3 is electrically connected to one of the multiple power lines 16. The second gate M60 of the first light-emitting control transistor M6 is electrically connected to one of the multiple light-emitting control lines 14, and the first electrode region M61 of the first light-emitting control transistor M6 is electrically connected to the second electrode region M32 of the driving transistor M3. The second electrode region M62 of the first light-emitting control transistor M6 is electrically connected to one end of the connector 122C. The second gate M70 of the first reset transistor M7 is electrically connected to one of the multiple reset lines 18, the first electrode region M71 of the first reset transistor M7 is electrically connected to one of the multiple initialization lines 17, and the second electrode region M72 of the first reset transistor M7 is electrically connected to the other end of the connector 122C.

[0230] In addition, the anode 1211 of the light-emitting element 121 of at least one sub-pixel 12 is electrically connected to one end of the connector 122C.

[0231] The following is combined Figure 1B , Figure 2 and Figure 19 This section introduces some specific implementation methods for multiple transistor MTs.

[0232] In some embodiments, see Figure 2 The display panel also includes multiple data lines 15. These data lines 15 are located in the display area 111 and are electrically connected to multiple sub-pixels 12. See also... Figure 1B The multiple transistors MT also include a data writing transistor M4, a second reset transistor M1, a second light-emitting control transistor M5, and a threshold compensation transistor M2.

[0233] See Figure 19The second gate M40 of the data writing transistor M4 is electrically connected to one of the multiple gate lines 13, the first electrode region M41 of the data writing transistor M4 is electrically connected to one of the multiple data lines 15, and the second electrode region M42 of the data writing transistor M4 is electrically connected to the first electrode region M31 of the driving transistor M3.

[0234] The second gate M10 of the second reset transistor M1 is electrically connected to another of the multiple reset lines 18, the first electrode region M10 of the second reset transistor M1 is electrically connected to the second electrode plate Cst2 of the storage capacitor Cst, and the second electrode region M20 of the second reset transistor M1 is electrically connected to another of the multiple initialization lines 17. In other words, the second gate M10 of the second reset transistor M1 and the second gate M70 of the first reset transistor M7 are electrically connected to different reset lines 18. The second electrode region M20 of the second reset transistor M1 and the first electrode region M71 of the first reset transistor M7 are electrically connected to different initialization lines 17.

[0235] The second gate M50 of the second light-emitting control transistor M5 is electrically connected to one of the multiple light-emitting control lines 14, the first electrode region M51 of the second light-emitting control transistor M5 is electrically connected to one of the multiple power supply lines 16, and the second electrode region M52 of the second light-emitting control transistor M5 is electrically connected to the first electrode region M31 of the driving transistor M3. For example, the second gate M50 of the second light-emitting control transistor M5 and the second gate M60 of the first light-emitting control transistor M6 are electrically connected to the same light-emitting control line 14.

[0236] The second gate M20 of the threshold compensation transistor M2 is electrically connected to one of the multiple gate lines 13, the first electrode region M21 of the threshold compensation transistor M2 is electrically connected to the first electrode region M11 of the second reset transistor M1, and the second electrode region M22 of the threshold compensation transistor M2 is electrically connected to the second electrode region M32 of the drive transistor M3. For example, the second gate M20 of the threshold compensation transistor M2 and the second gate M40 of the data write transistor M4 are electrically connected to the same gate line 13.

[0237] Figure 20 This is a schematic diagram illustrating a cascaded two-stage gate drive unit according to an embodiment of the present disclosure.

[0238] like Figure 20As shown, the single-stage or multi-stage gate driving unit 211 includes a cascaded preceding gate driving unit 211-1 and a subsequent gate driving unit 211-2. The first gate driving sub-circuit 211A1 of the preceding gate driving unit 211-1 includes a first input terminal IN1, and the second gate driving sub-circuit 211A2 of the preceding gate driving unit 211-1 includes a first output terminal OUT1. The first gate driving sub-circuit 211A1 of the subsequent gate driving unit 211-2 includes a first input terminal IN1, and the second gate driving sub-circuit 211A2 of the subsequent gate driving unit 211-2 includes a first output terminal OUT1.

[0239] The following is combined Figures 4A-4F The connection method of the cascaded gate drive unit 211-1 and the gate drive unit 211-2 is described.

[0240] like Figure 4A As shown, the gate driving unit at the upper end is the previous stage gate driving unit 211-1, and the gate driving unit at the lower end is the next stage gate driving unit 211-2. The first output terminal OUT1 of the previous stage gate driving unit 211-1 is electrically connected to the first gate line 131 of the plurality of gate lines 13. For example, the first output terminal OUT1 of the previous stage gate driving unit 211-1 is electrically connected to the first gate line 131 via the output electrode 32.

[0241] like Figure 4C As shown, the display panel also includes a first cascade connection line CC1, located on the side of the pixel driving circuit 122 of the first group of sub-pixels P1 away from the second gate driving sub-circuit 211A2. One end of the first cascade connection line CC1 is electrically connected to the first gate line 131, and the other end of the first cascade connection line CC1 is electrically connected to the first input terminal IN1 of the next stage gate driving unit 211-2. For example, one end of the first cascade connection line CC1 is electrically connected to the first gate line 131 via the first via VC1, and the other end of the first cascade connection line CC1 is electrically connected to the first input terminal IN1 of the next stage gate driving unit 211-2 via the second via VC2.

[0242] In the above embodiment, the first gate line 131 passes laterally through the pixel driving circuit 122 of the first group of sub-pixels P1, and the first cascade connection line CC1 is electrically connected to the first gate line 131 and the first input terminal IN1 of the subsequent gate driving unit 211-2. In this way, it is not necessary to electrically connect the first output terminal OUT1 of the previous gate driving unit 211-1 and the first input terminal IN1 of the subsequent gate driving unit 211-2 through an additional lateral connection line, which reduces the space occupied by the gate driving circuit and helps to improve the resolution of the display panel.

[0243] In some embodiments, see Figure 2 The display panel also includes multiple reset lines 18. These reset lines 18 are located in the display area 111 and are electrically connected to multiple sub-pixels 12. See also... Figure 4B The pixel driving circuit 122 of the first group of sub-pixels P1 between the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 of the subsequent gate driving unit 121-2 is electrically connected to the first reset line 181 among multiple reset lines 18. The first reset line 181 is electrically connected to the first gate line 131 via the first cascade connection line CC1. For example, the first reset line 181 is electrically connected to the first cascade connection line CC1 via the third via VC3.

[0244] In some embodiments, see Figure 4C The display panel also includes a second cascaded connection line CC2, located on the side of the first group of sub-pixels P1 away from the first gate drive sub-circuit 211A1. One end of the second cascaded connection line CC2 is electrically connected to the first gate line 131, and the other end is electrically connected to the first reset line 181. For example, one end of the second cascaded connection line CC2 is electrically connected to the first gate line 131 via via VC4, and the other end is electrically connected to the first reset line 181 via via VC5. In some embodiments, the second cascaded connection line CC2 and the first output electrode 32 are integrally disposed. In this manner, it can be ensured that the gate drive signal on the first gate line 131 is input as the first input signal to the first input terminal IN1 of the subsequent gate drive unit 211-2.

[0245] In some embodiments, at least one of the first electrode M3A and the second electrode M3B of the driving transistor M3 is located on the same layer as the first cascade connection line CC1. In some embodiments, at least one of the first electrode M3A and the second electrode M3B of the driving transistor M3 is located on the same layer as the second cascade connection line CC2.

[0246] The inventors also noted that when multiple gate driving sub-circuits 211A are distributed among multiple sub-pixels 12, the space occupied by some sub-pixels 12 on both sides of the gate driving sub-circuit 211A needs to be compressed. In this case, some sub-pixels that emit the same color in the compressed space (e.g., multiple red sub-pixels, multiple green sub-pixels, or multiple blue sub-pixels) have a problem of uneven display, which affects the display effect of the display panel.

[0247] In view of the above, the present disclosure also provides the following technical solutions.

[0248] Figure 21 This is a schematic diagram showing the distribution of a plurality of gate drive sub-circuits according to yet another embodiment of the present disclosure. Figures 22A-22E This is a schematic diagram showing different groups of anode connection lines according to some embodiments of the present disclosure.

[0249] The following is combined Figure 2 , Figure 21 , Figures 22A-22E A display panel according to some embodiments of the present disclosure will be described.

[0250] See Figure 2 The display panel includes a substrate 11, multiple sub-pixels 12, multiple gate lines 13, and a gate driving circuit 21.

[0251] The substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area 111. A plurality of sub-pixels 12 are located in the display area 111. A plurality of gate lines 13 are located in the display area 111 and electrically connected to the plurality of sub-pixels 12. A gate driving circuit 21 is located in the display area 111 and includes cascaded multi-stage gate driving units 211. The multi-stage gate driving units 211 are electrically connected to the plurality of gate lines 13.

[0252] like Figure 21 As shown, the multi-level gate driving circuit 211 includes a first-level or multi-level gate driving unit 211, which includes multiple gate driving sub-circuits 211A. The multiple gate driving sub-circuits 211A include a first gate driving sub-circuit 211A1 and a second gate driving sub-circuit 211A2.

[0253] The plurality of sub-pixels 12 includes a first group of sub-pixels P1 and a second group of sub-pixels P2. The pixel driving circuit 122 of one group of sub-pixels in the first group of sub-pixels P1 and the second group of sub-pixels P2 is located between the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2, while the pixel driving circuit 122 of the other group of sub-pixels in the first group of sub-pixels P1 and the second group of sub-pixels P2 is located on the side of the first gate driving sub-circuit 211A1 away from the second gate driving sub-circuit 211A2. It should be noted that... Figure 21The diagram schematically illustrates a situation where the first group of sub-pixels P1 is located between the first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2, and the pixel driving circuit 122 in the second group of sub-pixels P2 is located on the side of the first gate driving sub-circuit 211A1 away from the second gate driving sub-circuit 211A2.

[0254] See Figure 22A The first group of sub-pixels P1 includes a first sub-pixel group P11 configured to emit light of a first color, a second sub-pixel group P12 configured to emit light of a second color, and a third sub-pixel group P13 configured to emit light of a third color. In some embodiments, the first color, the second color, and the third color are different from each other. For example, the first color is red, the second color is green, and the third color is blue.

[0255] The pixel driving circuit 122 of the first sub-group sub-pixel P11 is electrically connected to the anode P11-1211 of the light-emitting element 121 of the first sub-group sub-pixel P11 via the first group of anode connection lines GC1. The pixel driving circuit 122 of the second sub-group sub-pixel P12 is electrically connected to the anode P12-1211 of the light-emitting element 121 of the second sub-group sub-pixel P12 via the second group of anode connection lines GC2. The pixel driving circuit 122 of the third sub-group sub-pixel P13 is electrically connected to the anode P13-1211 of the light-emitting element 121 of the third sub-group sub-pixel P13 via the third group of anode connection lines GC3.

[0256] At least one of the first group of anode connection lines GC1, the second group of anode connection lines GC2, and the third group of anode connection lines GC3 includes multiple first anode connection lines AC1. For example, each of the first group of anode connection lines GC1, the second group of anode connection lines GC2, and the third group of anode connection lines GC3 includes multiple first anode connection lines AC1. The multiple first anode connection lines AC1 include two first anode connection lines AC1, and the first anode connection line AC1 closer to the first gate drive sub-circuit 211A1 has a larger length.

[0257] For example, in the first group of anode connection lines GC1, the length of the two first anode connection lines AC1 that are closer to the first gate drive sub-circuit 211A1 is greater. As another example, in the second group of anode connection lines GC2, the length of the two first anode connection lines AC1 that are closer to the first gate drive sub-circuit 211A1 is greater. And as yet another example, in the third group of anode connection lines GC1, the length of the two first anode connection lines AC1 that are closer to the first gate drive sub-circuit 211A1 is greater.

[0258] In the above embodiments, the length of the first anode connection line AC1 closer to the first gate driving sub-circuit 211A1 is greater in at least one of the first group of anode connection lines GC1, GC2, and GC3. This structure helps to improve the display uniformity of the first group of sub-pixels 12, thereby improving the display effect of the display panel.

[0259] In some embodiments, among at least one group of multiple first anode connection lines AC1 of the first group of anode connection lines GC1, the second group of anode connection lines GC2, and the third group of anode connection lines GC3, the first anode connection line AC1 closest to the first gate driving sub-circuit 211A1 has a longer length. In other words, among all the first anode connection lines AC1 of at least one group of the first group of anode connection lines GC1, the second group of anode connection lines GC2, and the third group of anode connection lines GC3, the first anode connection line AC1 closest to the first gate driving sub-circuit 211A1 has a longer length. This structure helps to further improve the display uniformity of the first group of sub-pixels P1, thereby improving the display effect of the display panel.

[0260] In some embodiments, at least one of the first group of anode connection lines GC1, the second group of anode connection lines GC2, and the third group of anode connection lines GC3 is located on the same layer as the anode 1211 of the light-emitting element 121. This structure facilitates process implementation and reduces process complexity. In some implementations, the first group of anode connection lines GC1 is integrally disposed with the anodes P11-1211 of the light-emitting element 121 of the first sub-group sub-pixel P11. In some implementations, the second group of anode connection lines GC2 is integrally disposed with the anodes P12-1211 of the light-emitting element 121 of the second sub-group sub-pixel P12. In some implementations, the third group of anode connection lines GC3 is integrally disposed with the anodes P13-1211 of the light-emitting element 121 of the third sub-group sub-pixel P13.

[0261] In some implementations, the first set of anode connection lines GC1 is electrically connected to the pixel driving circuit 122 of the first sub-group sub-pixel P11 via the first set of vias VP1; the second set of anode connection lines GC2 is electrically connected to the pixel driving circuit 122 of the second sub-group sub-pixel P12 via the second set of vias VP2; and the third set of anode connection lines GC3 is electrically connected to the pixel driving circuit 122 of the third sub-group sub-pixel P13 via the third set of vias VP3.

[0262] Next, combine Figure 22B This section introduces some implementation methods for the second group of sub-pixels P2.

[0263] See Figure 22BThe second group of sub-pixels P2 includes a fourth group of sub-pixels P21 configured to emit light of the first color, a fifth group of sub-pixels P22 configured to emit light of the second color, and a sixth group of sub-pixels P23 configured to emit light of the third color.

[0264] The pixel driving circuit 122 of the fourth sub-group sub-pixel P21 is electrically connected to the anode P21-1211 of the light-emitting element 121 of the fourth sub-group sub-pixel P21 via the fourth anode connection line GC4. The pixel driving circuit 122 of the fifth sub-group sub-pixel P22 is electrically connected to the anode P22-1211 of the light-emitting element 121 of the fifth sub-group sub-pixel P22 via the fifth anode connection line GC5. The pixel driving circuit 122 of the sixth sub-group sub-pixel P23 is electrically connected to the anode P23-1211 of the light-emitting element 121 of the sixth sub-group sub-pixel P23 via the sixth anode connection line GC6.

[0265] At least one of the fourth group of anode connection lines GC4, the fifth group of anode connection lines GC5, and the sixth group of anode connection lines GC6 includes multiple second anode connection lines AC2, with the second anode connection line AC2 closest to the first gate driving sub-circuit 211A1 having a longer length. For example, each of the fourth group of anode connection lines GC4, the fifth group of anode connection lines GC5, and the sixth group of anode connection lines GC6 includes multiple second anode connection lines AC2, with the second anode connection line AC2 closest to the first gate driving sub-circuit 211A1 having a longer length. This structure helps improve the display uniformity of the second group of sub-pixels P2, thereby further improving the display effect of the display panel.

[0266] In some embodiments, see Figure 21 The multiple sub-pixels 12 also include a third group of sub-pixels P3 and a fourth group of sub-pixels P4. The pixel driving circuit 122 of one group of sub-pixels in the third group of sub-pixels P3 and the fourth group of sub-pixels P4 is located on the side of the second gate driving sub-circuit 211A2 closest to the first gate driving sub-circuit 211A1, the first group of sub-pixels P1, and the second group of sub-pixels P2. The pixel driving circuit 122 of the other group of sub-pixels is located on the side of the second gate driving sub-circuit 211A2 furthest from the first gate driving sub-circuit 211A1. Here, Figure 21 The pixel driving circuit 122 of the fourth group of sub-pixels P4 is schematically shown to be located on the side of the second gate driving sub-circuit 211A2 close to the first gate driving sub-circuit 211A1, the first group of sub-pixels P1 and the second group of sub-pixels P2, and the pixel driving circuit 122 of the third group of sub-pixels P3 is located on the side of the second gate driving sub-circuit 211A2 away from the first gate driving sub-circuit 211A1.

[0267] The following is combined Figure 22CThis section introduces some implementation methods for the third group of sub-pixels P3.

[0268] See Figure 22C The third group of sub-pixels P3 includes a seventh group of sub-pixels P31 configured to emit light of the first color, an eighth group of sub-pixels P32 configured to emit light of the second color, and a ninth group of sub-pixels P33 configured to emit light of the third color.

[0269] The pixel driving circuit 122 of the seventh sub-group sub-pixel P31 is electrically connected to the anode P31-1211 of the light-emitting element 121 of the seventh sub-group sub-pixel P31 via the seventh anode connection line GC7. The pixel driving circuit 122 of the eighth sub-group sub-pixel P32 is electrically connected to the anode P32-1211 of the light-emitting element 121 of the eighth sub-group sub-pixel P32 via the eighth anode connection line GC8. The pixel driving circuit 122 of the ninth sub-group sub-pixel P33 is electrically connected to the anode P33-1211 of the light-emitting element 121 of the ninth sub-group sub-pixel P33 via the ninth anode connection line GC9.

[0270] At least one of the seventh group of anode connection lines GC7, the eighth group of anode connection lines GC8, and the ninth group of anode connection lines GC9 includes multiple third anode connection lines AC3, with the anode connection lines closer to the second gate drive sub-circuit 211A2 having a longer length. For example, each of the seventh group of anode connection lines GC7, the eighth group of anode connection lines GC8, and the ninth group of anode connection lines GC9 includes multiple third anode connection lines AC3, with the anode connection lines closer to the second gate drive sub-circuit 211A2 having a longer length. This structure helps improve the display uniformity of the third group of sub-pixels P3, thereby further improving the display effect of the display panel.

[0271] The following is combined Figure 22D This section introduces some implementation methods for the fourth group of sub-pixels, P4.

[0272] See Figure 22D The fourth group of subpixels P4 includes a tenth subpixel P41 configured to emit light of the first color, an eleventh subpixel P42 configured to emit light of the second color, and a twelfth subpixel P43 configured to emit light of the third color.

[0273] The pixel driving circuit 122 of the tenth sub-group sub-pixel P41 is electrically connected to the anode P41-1211 of the light-emitting element 121 of the tenth sub-group sub-pixel P41 via the tenth group anode connection line GC10. The pixel driving circuit 122 of the eleventh sub-group sub-pixel P42 is electrically connected to the anode P42-1211 of the light-emitting element 121 of the eleventh sub-group sub-pixel P42 via the eleventh group anode connection line GC11. The pixel driving circuit 122 of the twelfth sub-group sub-pixel P43 is electrically connected to the anode P43-1211 of the light-emitting element 121 of the twelfth sub-group sub-pixel P43 via the twelfth group anode connection line GC12.

[0274] At least one of the tenth group of anode connection lines GC10, the eleventh group of anode connection lines GC11, and the twelfth group of anode connection lines GC12 includes multiple fourth anode connection lines AC4, with the anode connection lines closer to the second gate drive sub-circuit 211A2 having a longer length. For example, each of the tenth group of anode connection lines GC10, the eleventh group of anode connection lines GC11, and the twelfth group of anode connection lines GC12 includes multiple fourth anode connection lines AC4, with the anode connection lines closer to the second gate drive sub-circuit 211A2 having a longer length. This structure helps improve the display uniformity of the fourth group of sub-pixels P4, thereby further improving the display effect of the display panel.

[0275] In some embodiments, see Figure 21 The display panel also includes a fifth group of sub-pixels 12. The pixel driving circuit 122 of the fifth group of sub-pixels P5 is located between the pixel driving circuit 122 of the first group of sub-pixels P1 and the pixel driving circuit 122 of the fourth group of sub-pixels P4. The pixel driving circuit 122 of the first group of sub-pixels P1 is located between the first gate driving sub-circuit 211A1 and the pixel driving circuit 122 of the fifth group of sub-pixels P5. The pixel driving circuit 122 of the fourth group of sub-pixels P4 is located between the pixel driving circuit 122 of the fifth group of sub-pixels P5 and the second gate driving sub-circuit 211A2.

[0276] The following is combined Figure 22D This section introduces some implementation methods for the fifth sub-pixel P5.

[0277] See Figure 22D The fifth group of subpixels P5 includes a thirteenth subpixel P51 configured to emit light of the first color, a fourteenth subpixel P52 configured to emit light of the second color, and a fifteenth subpixel P53 configured to emit light of the third color.

[0278] The pixel driving circuit 122 of the thirteenth sub-group sub-pixel P51 is electrically connected to the anode P51-1211 of the light-emitting element 121 of the thirteenth sub-group sub-pixel P51 via the thirteenth anode connection line GC13. The pixel driving circuit 122 of the fourteenth sub-group sub-pixel P52 is electrically connected to the anode P52-1211 of the light-emitting element 121 of the fourteenth sub-group sub-pixel P52 via the fourteenth anode connection line GC14. The pixel driving circuit 122 of the fifteenth sub-group sub-pixel P53 is electrically connected to the anode P53-1211 of the light-emitting element 121 of the fifteenth sub-group sub-pixel P53 via the fifteenth anode connection line GC15.

[0279] Here, the lengths of the thirteenth group of anode connection lines GC13, the fourteenth group of anode connection lines GC14, and the fifteenth group of anode connection lines GC15 are all the same.

[0280] When the display panel includes the aforementioned first group of sub-pixels P1, second group of sub-pixels P2, third group of sub-pixels P3, fourth group of sub-pixels P4, and fifth group of sub-pixels P5, the dimensions of the pixel driving circuits for the first group of sub-pixels P1, second group of sub-pixels P2, third group of sub-pixels P3, and fourth group of sub-pixels P4 are compressed in the first direction. In other words, the dimensions of the sub-pixels on both sides of the first gate driving sub-circuit 211A1 and the dimensions of the sub-pixels on both sides of the second gate driving sub-circuit 211A2 are compressed in the first direction. This structure helps to improve the display uniformity of the display panel, thereby improving the display effect of the display panel.

[0281] The inventors also noted that when a display panel utilizes a multiplexing circuit, it suffers from poor display uniformity. Through research, they discovered that in related technologies, the control signal lines providing control signals to the multiplexing circuit have a similar shape to the edge of the display area. For example, if the display area has a stepped edge, the control signal lines also have a similar stepped shape. Such control signal lines are relatively long, resulting in higher resistance and a larger voltage drop. This, in turn, prevents sub-pixels from turning on or off properly, affecting the display panel's performance.

[0282] In view of the above, the present disclosure also provides the following technical solutions.

[0283] Figure 23A This is a schematic diagram illustrating the structure of a display panel according to yet another embodiment of the present disclosure. Figure 23B yes Figure 23A An enlarged schematic diagram of circle B shown.

[0284] The following is combined Figure 23A , Figure 23B , Figure 3AA display panel according to some embodiments of the present disclosure is described.

[0285] See Figure 23A The display panel includes a substrate 11, multiple sub-pixels 12, multiple gate lines 13, a gate driving circuit 21, multiple control signal lines 19, multiple data signal input lines 20, and a multiplexing circuit MX.

[0286] The substrate 11 includes a display area 111 and a peripheral area 112 surrounding the display area 111. The peripheral area 112 includes a first peripheral area 112A, the edge of the first peripheral area 112A away from the display area 11 having a first curvature greater than 0. For example, the edge of the first peripheral area 112A away from the display area 11 has an arc, such as a circular arc. Here, when the entire edge of the peripheral area 112 away from the display area 11 has a curvature greater than 0 (e.g., a ring), the first peripheral area 112A can be any part of the peripheral area 112; when the edge portion of the peripheral area 112 away from the display area 11 has a curvature greater than 0 (e.g., a corner portion), the first peripheral area 112A can be a corner portion of the peripheral area 112, such as one of the four corner areas.

[0287] Multiple sub-pixels 12 are located in the display area 111. Multiple gate lines 13 are located in the display area 111 and are electrically connected to the multiple sub-pixels 12. A gate driving circuit 21 is located in the display area 111 and includes cascaded multi-stage gate driving units 211. The multi-stage gate driving units 211 are electrically connected to the multiple gate lines 13.

[0288] See Figure 3A The multi-level gate driving circuit 211 includes one or more gate driving units 211, which include multiple gate driving sub-circuits 211A. Each gate driving sub-circuit 211A includes a first gate driving sub-circuit 211A1 and a second gate driving sub-circuit 211A2. The first gate driving sub-circuit 211A1 and the second gate driving sub-circuit 211A2 are separated by pixel driving circuits 122 of the first group of sub-pixels P1 among the multiple sub-pixels 12.

[0289] See Figure 23B Multiple control signal lines 19, multiple data signal input lines 20, and a multiplexing circuit MX are located at least in the first peripheral region 112A. At least a portion of at least one of the multiple control signal lines 19 has a second curvature greater than 0. For example, each of the multiple control signal lines 19 has a second curvature greater than 0. In some embodiments, the second curvature is the same as the first curvature. As some implementations, each control signal line 19 is arc-shaped.

[0290] The multiplexing circuit MX is located between the multiple control signal lines 19 and the display area 111. The multiplexing circuit MX includes multiple multiplexing units MX1, each of which is electrically connected to the multiple control signal lines 19, one of the multiple data signal input lines 20, and at least two of the multiple data lines 15.

[0291] In the above embodiments, at least a portion of at least one of the plurality of control signal lines 19 has a second curvature greater than 0. Such a structure helps to reduce the length of the control signal lines 19 and lower their resistance, thereby improving the display uniformity of the display panel.

[0292] In some embodiments, see Figure 23B The display panel also includes a power bus VDD, configured to supply power voltage to the power lines 16 of the display area 111. For example, the power bus VDD is located on the side of the multiple control signal lines 19 away from the display area 111.

[0293] In some embodiments, see Figure 23B The plurality of sub-pixels 12 include a first row of sub-pixels C1 and a second row of sub-pixels C2 arranged and adjacent to each other in a first direction, wherein the number of first row sub-pixels C1 is greater than the number of second row sub-pixels C2. At least one of the plurality of multiplexing units MX is at least partially located in a first region 112A1 of the first peripheral region 112A. Here, the first region 112A1 is located on the side of the second row of sub-pixels C2 away from the display area 111 in the first direction, and the first region 112A1 is located on the side of the first row of sub-pixels C1 away from the display area 11 in a second direction perpendicular to the first direction. For example, the first region 112A1 is located to the left of the second row of sub-pixels C2 in the first direction, and the first region 112A1 is located below the first row of sub-pixels C1 in the second direction.

[0294] For example, the closed space enclosed by the first straight line containing the left edge of the first row of sub-pixels C1, the second straight line containing the lower edge of the first row of sub-pixels C1, the third straight line containing the left edge of the second row of sub-pixels C2, and the fourth straight line containing the lower edge of the second row of sub-pixels C2 can be regarded as the first region 112A1. It should be understood that the first peripheral region 112A may include multiple first regions 112A1.

[0295] In some embodiments, see Figure 23B The display panel also includes multiple control signal connection lines 19A, which are electrically connected to multiple multiplexing units MX. For example, the multiple control signal lines 19 are electrically connected to the multiple control signal connection lines 19A in a one-to-one correspondence, and the multiple control signal connection lines 19A are electrically connected to the multiple multiplexing units MX in a one-to-one correspondence.

[0296] In some embodiments, the extension direction of the multiple control signal connection lines 19A and the multiple data lines 15 (see...) Figure 23A The extension direction is the same, that is, it extends along the second direction. This helps to reduce the length of the control signal connection line 19A and reduce the resistance of the control signal connection line 19A, thereby helping to improve the display uniformity of the display panel.

[0297] Figure 24 It is shown Figure 23B A partial schematic diagram. The following is combined with... Figure 24 This section presents a schematic diagram of the multiplexing unit MX.

[0298] See Figure 24 Each of the plurality of multiplexing units MX includes a plurality of switching transistors SW corresponding one-to-one with a plurality of control signal lines 19 and at least two data lines 15. As an example, each of the plurality of multiplexing units MX includes six switching transistors, six control signal lines 19, and six data lines 15. For example, three of the six switching transistors are located in one first region 112A1, and the other three are located in another first region 112A1.

[0299] Each of the plurality of switching transistors SW has its gate SW0 electrically connected to one of the plurality of control signal lines 19. Each of the plurality of switching transistors SW has its first electrode SW1 electrically connected to one of the plurality of data signal input lines 20. Each of the plurality of switching transistors SW has its second electrode SW2 electrically connected to one of at least two data lines 15. For example, the gate SW0 of each switching transistor SW is electrically connected to a corresponding control signal line 19 via a corresponding control signal connection line 19.

[0300] It should be noted that the technical solutions of the display panels provided in different embodiments of this disclosure can be combined with each other to obtain display panels with multiple embodiments.

[0301] This disclosure also provides various methods for manufacturing display panels.

[0302] Figure 25 This is a schematic flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present disclosure.

[0303] In step 252, a substrate is provided, the substrate including a display area and a peripheral area surrounding the display area.

[0304] In step 254, multiple sub-pixels, multiple gate lines, multiple light-emitting control lines, a gate driving circuit, and a light-emitting control driving circuit are formed in the display area.

[0305] Each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element. Multiple gate lines are electrically connected to multiple sub-pixels, and multiple light-emitting control lines are electrically connected to multiple sub-pixels. The gate driving circuit includes cascaded multi-stage gate driving units electrically connected to multiple gate lines. One or more gate driving units in the multi-stage gate driving circuit include multiple gate driving sub-circuits, including a first gate driving sub-circuit and a second gate driving sub-circuit, which are spaced apart by pixel driving circuits of a first group of sub-pixels in the multiple sub-pixels. The light-emitting control driving circuit includes cascaded multi-stage light-emitting control driving units electrically connected to multiple light-emitting control lines. One or more light-emitting control driving units in the multi-stage light-emitting control driving unit include multiple light-emitting control driving sub-circuits, including a first light-emitting control driving sub-circuit and a second light-emitting control driving sub-circuit, which are spaced apart by pixel driving circuits of a second group of sub-pixels in the multiple sub-pixels.

[0306] In the above embodiments, both the gate driving circuit and the light emission control driving circuit are located in the display area. At least one stage of the gate driving circuit includes multiple gate driving sub-circuits distributed within the pixel driving circuits of multiple sub-pixels, and at least one stage of the light emission control driving circuit includes multiple light emission control driving sub-circuits distributed within the pixel driving circuits of multiple sub-pixels. This structure is advantageous for reducing the bezel size of the display panel.

[0307] Figure 26 This is a schematic flowchart illustrating a method for manufacturing a display panel according to another embodiment of the present disclosure.

[0308] In step 262, a substrate is provided, the substrate including a display area and a peripheral area surrounding the display area.

[0309] In step 264, multiple sub-pixels, multiple gate lines, gate driving circuits, and gate driving sub-circuit connection lines are formed in the display area.

[0310] Each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element. Multiple gate lines are electrically connected to multiple sub-pixels. The gate driving circuit includes cascaded multi-level gate driving units. The multi-level gate driving units are electrically connected to multiple gate lines. One or more gate driving units in the multi-level gate driving circuit include multiple gate driving sub-circuits. The multiple gate driving sub-circuits include a first gate driving sub-circuit and a second gate driving sub-circuit. The first gate driving sub-circuit and the second gate driving sub-circuit are separated by the pixel driving circuits of a first group of sub-pixels in the multiple sub-pixels.

[0311] One end of the gate driver sub-circuit connection line is electrically connected to the first gate driver sub-circuit, and the other end of the gate driver sub-circuit connection line is electrically connected to the second gate driver sub-circuit.

[0312] The pixel driving circuit for at least one sub-pixel in the first group of sub-pixels includes a first pixel driving sub-circuit, a second pixel driving sub-circuit, and a connector. The first pixel driving sub-circuit is located on one side of the gate driving sub-circuit connection line and includes a driving transistor, the driving transistor including a first active layer located on one side of the substrate. The second pixel driving sub-circuit is located on the side of the gate driving sub-circuit connection line away from the first pixel driving sub-circuit. One end of the connector is electrically connected to the first pixel driving sub-circuit, and the other end of the connector is electrically connected to the second pixel driving sub-circuit. The orthographic projection of the connector on the substrate overlaps with the orthographic projection of the gate driving sub-circuit connection line on the substrate. The connector and the first active layer are located on different layers.

[0313] In the above embodiments, the connector and the first active layer are located on different layers, and no transistor is formed between the gate drive sub-circuit connection line and the connector. Therefore, the problem of decreased display effect of the display panel caused by the formation of transistors between the gate drive sub-circuit connection line and the connector is at least mitigated.

[0314] Figure 27 This is a schematic flowchart illustrating a method for manufacturing a display panel according to yet another embodiment of the present disclosure.

[0315] In step 272, a substrate is provided, the substrate including a display area and a peripheral area surrounding the display area.

[0316] In step 274, multiple sub-pixels, multiple gate lines, and gate driving circuits are formed in the display area.

[0317] Each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element, with multiple gate lines electrically connected to the multiple sub-pixels. The gate driving circuit includes cascaded multi-stage gate driving units electrically connected to multiple gate lines. One or more gate driving units in the multi-stage gate driving circuit include multiple gate driving sub-circuits, including a first gate driving sub-circuit and a second gate driving sub-circuit.

[0318] The multiple sub-pixels include a first group of sub-pixels and a second group of sub-pixels. The pixel driving circuit of one group of sub-pixels in the first group of sub-pixels and the second group of sub-pixels is located between the first gate driving sub-circuit and the second gate driving sub-circuit. The pixel driving circuit of the other group of sub-pixels in the first group of sub-pixels and the second group of sub-pixels is located on the side of the first gate driving sub-circuit away from the second gate driving sub-circuit.

[0319] The first group of sub-pixels includes: a first sub-group of sub-pixels configured to emit light of a first color, wherein the pixel driving circuit of the first sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the first sub-group of sub-pixels via a first set of anode connection lines; a second sub-group of sub-pixels configured to emit light of a second color, wherein the pixel driving circuit of the second sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the second sub-group of sub-pixels via a second set of anode connection lines; and a third sub-group of sub-pixels configured to emit light of a third color, wherein the pixel driving circuit of the third sub-group of sub-pixels is electrically connected to the anode of the light-emitting element of the third sub-group of sub-pixels via a third set of anode connection lines.

[0320] At least one of the first group of anode connection lines, the second group of anode connection lines, and the third group of anode connection lines includes multiple first anode connection lines, and the multiple first anode connection lines include two first anode connection lines. The first anode connection line closer to the first gate drive sub-circuit has a longer length.

[0321] In the above embodiments, the length of the first anode connection line closer to the first gate driving sub-circuit is greater in at least one of the first group of anode connection lines, the second group of anode connection lines, and the third group of anode connection lines. This structure helps to improve the display uniformity of the first group of sub-pixels, thereby improving the display effect of the display panel.

[0322] Figure 28 This is a schematic flowchart illustrating a method for manufacturing a display panel according to another embodiment of the present disclosure.

[0323] In step 282, a substrate is provided, the substrate including a display area and a peripheral area surrounding the display area, the peripheral area including a first peripheral area, the edge of the first peripheral area away from the display area having a first curvature greater than 0.

[0324] In step 284, multiple sub-pixels, multiple data lines, multiple gate lines, a gate driving circuit, multiple control signal lines, multiple data signal input lines, and a multiplexing circuit are formed.

[0325] Each sub-pixel includes a light-emitting element and a pixel driving circuit configured to drive the light-emitting element. Multiple data lines are located in the display area and electrically connected to the multiple sub-pixels. Multiple gate lines are located in the display area and electrically connected to the multiple sub-pixels. A gate driving circuit is located in the display area and includes cascaded multi-stage gate driving units. The multi-stage gate driving units are electrically connected to the multiple gate lines. One or more gate driving units in the multi-stage gate driving circuit include multiple gate driving sub-circuits, including a first gate driving sub-circuit and a second gate driving sub-circuit, which are spaced apart by the pixel driving circuits of a first group of sub-pixels in the multiple sub-pixels.

[0326] Multiple control signal lines are located at least in a first peripheral area, and at least a portion of at least one of the multiple control signal lines has a second curvature greater than 0. Multiple data signal input lines are located at least in the first peripheral area. A multiplexing circuit is located at least in the first peripheral area and between the multiple control signal lines and the display area. The multiplexing circuit includes multiple multiplexing units, each of which is electrically connected to the multiple control signal lines, one of the multiple data signal input lines, and at least two of the multiple data lines.

[0327] In the above embodiments, at least a portion of at least one of the multiple control signal lines has a second curvature greater than 0. This structure helps to reduce the length of the control signal lines and lower their resistance, thereby improving the display uniformity of the display panel.

[0328] This disclosure also provides a display device, which may include the display panel of any of the above embodiments. In some embodiments, the display device may be, for example, any product or component with display function, such as a wearable device (e.g., a watch), a mobile terminal, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or electronic paper.

[0329] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0330] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A display panel, comprising: a substrate, including a display area and a peripheral area surrounding the display area; a plurality of sub-pixels located in the display area, each sub-pixel including a light emitting element and a pixel driving circuit configured to drive the light emitting element; a plurality of gate lines located in the display area and electrically connected to the plurality of sub-pixels; and a gate driving circuit located in the display area, including a plurality of cascaded gate driving units, the plurality of cascaded gate driving units being electrically connected to the plurality of gate lines, one or more gate driving units of the plurality of cascaded gate driving units including a plurality of gate driving sub-circuits, the plurality of gate driving sub-circuits including a first gate driving sub-circuit and a second gate driving sub-circuit, wherein: the plurality of sub-pixels include a first group of sub-pixels, a second group of sub-pixels, and a fifth group of sub-pixels, the pixel driving circuit of the first group of sub-pixels being located between the first gate driving sub-circuit and the second gate driving sub-circuit, the pixel driving circuit of the second group of sub-pixels being located on a side of the first gate driving sub-circuit away from the second gate driving sub-circuit, the pixel driving circuit of the fifth group of sub-pixels being located between the pixel driving circuit of the first group of sub-pixels and the second gate driving sub-circuit, the first group of sub-pixels including: a first sub-group of sub-pixels configured to emit a first color of light, the pixel driving circuit of the first sub-group of sub-pixels being electrically connected to anodes of the light emitting elements of the first sub-group of sub-pixels via a first group of anode connection lines, a second sub-group of sub-pixels configured to emit a second color of light, the pixel driving circuit of the second sub-group of sub-pixels being electrically connected to anodes of the light emitting elements of the second sub-group of sub-pixels via a second group of anode connection lines, and a third sub-group of sub-pixels configured to emit a third color of light, the pixel driving circuit of the third sub-group of sub-pixels being electrically connected to anodes of the light emitting elements of the third sub-group of sub-pixels via a third group of anode connection lines, wherein at least one of the first group of anode connection lines, the second group of anode connection lines, and the third group of anode connection lines includes a plurality of first anode connection lines, the plurality of first anode connection lines including two first anode connection lines, a first anode connection line of the two first anode connection lines being closer to the first gate driving sub-circuit having a greater length than a second anode connection line of the two first anode connection lines; the fifth group of sub-pixels including: a thirteenth sub-group of sub-pixels configured to emit the first color of light, the pixel driving circuit of the thirteenth sub-group of sub-pixels being electrically connected to anodes of the light emitting elements of the thirteenth sub-group of sub-pixels via a thirteenth group of anode connection lines; a fourteenth sub-group of sub-pixels configured to emit the second color of light, the pixel driving circuit of the fourteenth sub-group of sub-pixels being electrically connected to anodes of the light emitting elements of the fourteenth sub-group of sub-pixels via a fourteenth group of anode connection lines; and a fifteenth sub-group of sub-pixels configured to emit the third color of light, the pixel driving circuit of the fifteenth sub-group of sub-pixels being electrically connected to anodes of the light emitting elements of the fifteenth sub-group of sub-pixels via a fifteenth group of anode connection lines. ​ The thirteenth group of anode connection lines have the same length, the fourteenth group of anode connection lines have the same length, and the fifteenth group of anode connection lines have the same length.

2. The display panel of claim 1, wherein, The first anode connection lines closer to the first gate drive sub-circuit have a greater length.

3. The display panel of claim 1, wherein, At least one of the first group of anode connection lines, the second group of anode connection lines, and the third group of anode connection lines is integrated with the anodes of the light emitting elements.

4. The display panel of claim 3, wherein: The first group of anode connection lines is integrated with the anodes of the light emitting elements of the first sub-group of sub-pixels; The second group of anode connection lines is integrated with the anodes of the light emitting elements of the second sub-group of sub-pixels; The third group of anode connection lines is integrated with the anodes of the light emitting elements of the third sub-group of sub-pixels.

5. The display panel of claim 4, wherein: The first group of anode connection lines is electrically connected to the pixel drive circuits of the first sub-group of sub-pixels via a first group of vias; The second group of anode connection lines is electrically connected to the pixel drive circuits of the second sub-group of sub-pixels via a second group of vias; The third group of anode connection lines is electrically connected to the pixel drive circuits of the third sub-group of sub-pixels via a third group of vias.

6. The display panel of claim 1, wherein, The second group of sub-pixels includes: a fourth sub-group of sub-pixels configured to emit light of the first color, the pixel drive circuits of the fourth sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the fourth sub-group of sub-pixels via a fourth group of anode connection lines; a fifth sub-group of sub-pixels configured to emit light of the second color, the pixel drive circuits of the fifth sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the fifth sub-group of sub-pixels via a fifth group of anode connection lines; and a sixth sub-group of sub-pixels configured to emit light of the third color, the pixel drive circuits of the sixth sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the sixth sub-group of sub-pixels via a sixth group of anode connection lines, wherein at least one of the fourth group of anode connection lines, the fifth group of anode connection lines, and the sixth group of anode connection lines includes a plurality of second anode connection lines, the second anode connection lines closer to the first gate drive sub-circuit having a greater length.

7. The display panel according to any one of claims 1-6, wherein, The plurality of sub-pixels further includes a third group of sub-pixels and a fourth group of sub-pixels, the pixel drive circuits of one of the third group of sub-pixels and the fourth group of sub-pixels being located on a side of the second gate drive sub-circuit closer to the first gate drive sub-circuit, the first group of sub-pixels, and the second group of sub-pixels, and the pixel drive circuits of the other group of sub-pixels being located on a side of the second gate drive sub-circuit farther from the first gate drive sub-circuit, the third group of sub-pixels including: a seventh sub-group of sub-pixels configured to emit light of the first color, the pixel drive circuits of the seventh sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the seventh sub-group of sub-pixels via a seventh group of anode connection lines; an eighth sub-group of sub-pixels configured to emit light of the second color, the pixel driving circuit of the eighth sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the eighth sub-group of sub-pixels via an eighth group of anode connection lines; and a ninth sub-group of sub-pixels configured to emit light of the third color, the pixel driving circuit of the ninth sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the ninth sub-group of sub-pixels via a ninth group of anode connection lines, wherein at least one of the seventh group of anode connection lines, the eighth group of anode connection lines and the ninth group of anode connection lines comprises a plurality of third anode connection lines, the length of the third anode connection lines being greater closer to the anode connection lines of the second gate driving sub-circuit.

8. The display panel of claim 7, wherein, the fourth group of sub-pixels comprises: a tenth sub-group of sub-pixels configured to emit light of the first color, the pixel driving circuit of the tenth sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the tenth sub-group of sub-pixels via a tenth group of anode connection lines; an eleventh sub-group of sub-pixels configured to emit light of the second color, the pixel driving circuit of the eleventh sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the eleventh sub-group of sub-pixels via an eleventh group of anode connection lines; and a twelfth sub-group of sub-pixels configured to emit light of the third color, the pixel driving circuit of the twelfth sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the twelfth sub-group of sub-pixels via a twelfth group of anode connection lines, wherein at least one of the tenth group of anode connection lines, the eleventh group of anode connection lines and the twelfth group of anode connection lines comprises a plurality of fourth anode connection lines, the length of the fourth anode connection lines being greater closer to the fourth anode connection lines of the second gate driving sub-circuit.

9. The display panel of claim 8, wherein, the pixel driving circuit of the fifth group of sub-pixels is located between the pixel driving circuit of the first group of sub-pixels and the pixel driving circuit of the fourth group of sub-pixels, the pixel driving circuit of the first group of sub-pixels is located between the first gate driving sub-circuit and the pixel driving circuit of the fifth group of sub-pixels, and the pixel driving circuit of the fourth group of sub-pixels is located between the pixel driving circuit of the fifth group of sub-pixels and the second gate driving sub-circuit.

10. The display panel of claim 1, wherein, the first color, the second color and the third color are different from each other.

11. The display panel of claim 10, wherein, the first color is red, the second color is green, and the third color is blue.

12. The display panel of claim 1, further comprising: a first circuit connection line located in the display area, one end of the first circuit connection line being electrically connected to the first gate driving sub-circuit, and the other end of the first circuit connection line being electrically connected to the second gate driving sub-circuit; the first group of sub-pixels is located between the first gate driving sub-circuit and the second gate driving sub-circuit, and the pixel driving circuit of at least one sub-pixel in the first group of sub-pixels comprises: The first pixel driving sub-circuit is located at one side of the first circuit connection line and includes a driving transistor, the driving transistor includes a first active layer located at one side of the substrate, The second pixel driving sub-circuit is located at one side of the first circuit connection line away from the first pixel driving sub-circuit, and The connecting piece has one end electrically connected to the first pixel driving sub-circuit and the other end electrically connected to the second pixel driving sub-circuit, the connecting piece has a projection on the substrate that overlaps the projection of the first circuit connection line on the substrate, and the connecting piece and the first active layer are located in different layers.

13. The display panel of claim 12, wherein: The driving transistor further includes: a first gate located at one side of the first active layer away from the substrate, a first insulating layer located at one side of the first gate away from the substrate, a second insulating layer located at one side of the first insulating layer away from the substrate, and a first electrode and a second electrode located at one side of the second insulating layer away from the substrate and electrically connected to the first active layer; The first pixel driving sub-circuit further includes a storage capacitor, including: a first electrode plate located in the same layer as the first gate, and a second electrode plate located between the first insulating layer and the second insulating layer; The first circuit connection line is located in the same layer as the first gate, and at least one of the second electrode plate, the first electrode and the second electrode is located in the same layer as the connecting piece.

14. The display panel of claim 13, wherein, The first electrode, the second electrode and the connecting piece are located in the same layer.

15. The display panel of claim 12, wherein, The first-stage or multi-stage gate driving unit includes a front-stage gate driving unit and a rear-stage gate driving unit in cascade, wherein: The first gate driving sub-circuit of the front-stage gate driving unit includes a first input end of the front-stage gate driving unit, and the second gate driving sub-circuit of the front-stage gate driving unit includes a first output end of the front-stage gate driving unit; The first gate driving sub-circuit of the rear-stage gate driving unit includes a first input end of the rear-stage gate driving unit, and the second gate driving sub-circuit of the rear-stage gate driving unit includes a first output end of the rear-stage gate driving unit.

16. The display panel of claim 15, wherein: The first output end of the front-stage gate driving unit is electrically connected to a first gate line of the plurality of gate lines; The display panel further includes: a first cascade connection line located at one side of the pixel driving circuit of the first group of sub-pixels away from the second gate driving sub-circuit, one end of the first cascade connection line is electrically connected to the first gate line, and the other end of the first cascade connection line is electrically connected to the first input end of the rear-stage gate driving unit.

17. The display panel of claim 16, further comprising: a plurality of reset lines located in the display area and electrically connected to the plurality of sub-pixels. The pixel driving circuit of the first group of sub-pixels between the first gate driving sub-circuit and the second gate driving sub-circuit of the last-stage gate driving unit is electrically connected to a first reset line of the plurality of reset lines, and the first reset line is electrically connected to the first gate line via the first cascade connection line.

18. The display panel of claim 17, wherein, The first cascade connection line is electrically connected to the first gate line via a first via, electrically connected to a first input end of the last-stage gate driving unit via a second via, and electrically connected to the first reset line via a third via.

19. The display panel of claim 17, further comprising: a second cascade connection line located on a side of the first group of sub-pixels away from the first gate driving sub-circuit, one end of the second cascade connection line being electrically connected to the first gate line, and the other end of the second cascade connection line being electrically connected to the first reset line.

20. The display panel of claim 1, further comprising: a plurality of light-emitting control lines located in the display area and electrically connected to the plurality of sub-pixels; and a light-emitting control driving circuit located in the display area and comprising a plurality of cascade light-emitting control driving units, the plurality of cascade light-emitting control driving units being electrically connected to the plurality of light-emitting control lines, one or more light-emitting control driving units of the plurality of cascade light-emitting control driving units comprising a plurality of light-emitting control driving sub-circuits, the plurality of light-emitting control driving sub-circuits comprising a first light-emitting control driving sub-circuit and a second light-emitting control driving sub-circuit, the first light-emitting control driving sub-circuit and the second light-emitting control driving sub-circuit being spaced apart by the pixel driving circuit of a sixth group of sub-pixels of the plurality of sub-pixels. The display panel of any one of claims 1-20.

21. A display device comprising:

22. A method of manufacturing a display panel, comprising: providing a substrate, the substrate comprising a display area and a peripheral area surrounding the display area; and forming a plurality of sub-pixels, a plurality of gate lines, and a gate driving circuit in the display area, wherein: each sub-pixel comprises a light-emitting element and a pixel driving circuit configured to drive the light-emitting element; the plurality of gate lines are electrically connected to the plurality of sub-pixels, the gate driving circuit comprises a plurality of cascade gate driving units, the plurality of cascade gate driving units being electrically connected to the plurality of gate lines, one or more gate driving units of the plurality of cascade gate driving units comprising a plurality of gate driving sub-circuits, the plurality of gate driving sub-circuits comprising a first gate driving sub-circuit and a second gate driving sub-circuit, the plurality of sub-pixels comprise a first group of sub-pixels, a second group of sub-pixels, and a fifth group of sub-pixels, the pixel driving circuit of the first group of sub-pixels being located between the first gate driving sub-circuit and the second gate driving sub-circuit, the pixel driving circuit of the second group of sub-pixels being located on a side of the first gate driving sub-circuit away from the second gate driving sub-circuit, and the pixel driving circuit of the fifth group of sub-pixels being located between the pixel driving circuit of the first group of sub-pixels and the second gate driving sub-circuit, the first group of sub-pixels comprising: ​ a first sub-group of sub-pixels configured to emit light of a first color, the pixel driving circuit of the first sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the first sub-group of sub-pixels via a first group of anode connection lines, a second sub-group of sub-pixels configured to emit light of a second color, the pixel driving circuit of the second sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the second sub-group of sub-pixels via a second group of anode connection lines, and a third sub-group of sub-pixels configured to emit light of a third color, the pixel driving circuit of the third sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the third sub-group of sub-pixels via a third group of anode connection lines, wherein at least one of the first, second and third groups of anode connection lines comprises a plurality of first anode connection lines, the plurality of first anode connection lines comprising two first anode connection lines, the length of the first anode connection line closer to the first gate driving sub-circuit being greater than the length of the other first anode connection line; the fifth group of sub-pixels comprises: a thirteenth sub-group of sub-pixels configured to emit light of the first color, the pixel driving circuit of the thirteenth sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the thirteenth sub-group of sub-pixels via a thirteenth group of anode connection lines; a fourteenth sub-group of sub-pixels configured to emit light of the second color, the pixel driving circuit of the fourteenth sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the fourteenth sub-group of sub-pixels via a fourteenth group of anode connection lines; and a fifteenth sub-group of sub-pixels configured to emit light of the third color, the pixel driving circuit of the fifteenth sub-group of sub-pixels being electrically connected to the anodes of the light emitting elements of the fifteenth sub-group of sub-pixels via a fifteenth group of anode connection lines, wherein the length of the thirteenth group of anode connection lines is the same, the length of the fourteenth group of anode connection lines is the same, and the length of the fifteenth group of anode connection lines is the same.

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