Three-dimensional memory and its manufacturing method

Abstract

This invention provides a three-dimensional memory and a method for manufacturing the same. The method includes: forming a first region on a substrate, the first region including a first stacked structure and a first channel structure disposed on the substrate, the first channel structure penetrating the first stacked structure; forming an array common source electrode on the first region, the first channel structure being connected to the array common source electrode; and forming a second region on the array common source electrode, the second region including a second stacked structure and a second channel structure, the second channel structure penetrating the second stacked structure and being connected to the array common source electrode. In this embodiment, the first region and the second region are perpendicularly arranged and share an array common source electrode, which overcomes the technological difficulty of forming vias, enables high-layer stacking, reduces the length of the channel layers of the first and second channel structures, lowers the channel resistance, increases the channel current, and improves the stability of the three-dimensional memory.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a three-dimensional memory and its manufacturing method. Background Technology

[0002] In a three-dimensional memory, individual memory cells are connected in series to form a memory string. Each memory string is connected to a source select line (SSL) and a drain select line (DSL) at its two ends, and then to a bit line (BL) and an array common source (ACS) terminal, respectively. During operation, different voltages are applied to the source select line, drain select line, bit line, ACS terminal, and gate to perform read, write, and erase operations on the cells.

[0003] In some 3D memory technologies, to increase the storage capacity per unit area, designers can choose one or more methods, such as increasing the storage capacity per memory cell, increasing the number of stacked layers, or increasing the number of cells by reducing the size of each memory cell. These methods may be accompanied by numerous manufacturing difficulties. For example, when the number of stacked layers in a 3D memory increases, on the one hand, the etching depth of the channel vias increases, making the manufacturing process more complex and difficult; on the other hand, the resistance of the channel filler (e.g., polysilicon) increases, resulting in a corresponding decrease in channel current and increasing the operational difficulty of the memory cells. Therefore, it is difficult to achieve further layer stacking in existing 3D memory product architectures.

[0004] How to increase the number of stacking layers of 3D memory and further increase its storage capacity has become an urgent technical problem to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a three-dimensional memory and a method for manufacturing the same, which can increase the number of stacked layers of the three-dimensional memory and further increase the storage capacity of the three-dimensional memory.

[0006] The present invention provides a method for manufacturing a three-dimensional memory, comprising: forming a first region on a substrate, the first region including a first stacked structure and a first channel structure disposed on the substrate, the first channel structure penetrating the first stacked structure; forming an array common source electrode on the first region, the first channel structure being connected to the array common source electrode; and forming a second region on the array common source electrode, the second region including a second stacked structure and a second channel structure, the second channel structure penetrating the second stacked structure and being connected to the array common source electrode.

[0007] In some embodiments, the method further includes the following steps: providing a peripheral device structure, the peripheral device structure including a peripheral device layer and a first interconnect layer, the peripheral device layer being connected to the first interconnect layer; forming a second interconnect layer on the second region, the second interconnect layer being electrically connected to the second channel structure; and electrically connecting the first interconnect layer and the second interconnect layer.

[0008] In some embodiments, the method of forming a second interconnect layer on the second region includes the following steps: forming a first interconnect sublayer on the second region, the first interconnect sublayer being electrically connected to the second channel structure; forming a second interconnect sublayer, the second interconnect sublayer being connected to the first interconnect sublayer, the first interconnect sublayer and the second interconnect sublayer together serving as the second interconnect layer.

[0009] In some embodiments, the method further includes the steps of: forming a third interconnect layer on the side of the first region away from the second region, the third interconnect layer being connected to the first channel structure; and forming lead-out pads on the third interconnect layer, the lead-out pads being connected to the third interconnect layer.

[0010] In some embodiments, the step of forming a third interconnect layer on the side of the first region away from the second region further includes: thinning the substrate to expose the first channel structure; forming a third interconnect sublayer on the side of the first region away from the second region, the third interconnect sublayer being connected to the first channel structure; forming a fourth interconnect sublayer on the third interconnect sublayer, the fourth interconnect sublayer being connected to the third interconnect sublayer, the third interconnect sublayer and the fourth interconnect sublayer together serving as the third interconnect layer.

[0011] In some embodiments, the method further includes the following steps: before forming the second region, forming a first sub-conductive contact portion extending through the first region to a first step of the first stacked structure in the first region; after forming the second region, forming a second sub-conductive contact portion extending through the second region, wherein the second sub-conductive contact portion is electrically connected to the first sub-conductive contact portion and together serves as a first conductive contact portion, and the first conductive contact portion is electrically connected to the second interconnect layer.

[0012] In some embodiments, the method further includes the following steps: forming an array common source conductive contact portion that extends through the second region in the second region, wherein the array common source conductive contact portion is connected to the array common source and the second interconnect layer.

[0013] In some embodiments, the method further includes the following steps: forming a second conductive contact portion in the second region that extends through the second region to the second step of the second stacked structure, wherein the second conductive contact portion is connected to the second interconnect layer.

[0014] In some embodiments, the method further includes the following steps: before forming the second region, forming a first sub-peripheral conductive contact portion in the first region, the first sub-peripheral contact portion penetrating the first region; after forming the second region, forming a second sub-peripheral conductive contact portion in the second region, the second sub-peripheral conductive contact portion penetrating the second region, the second sub-peripheral conductive contact portion being connected to the first sub-peripheral conductive contact portion, together serving as a peripheral conductive contact portion.

[0015] In some embodiments, the method further includes the following steps: forming a first conductive contact portion penetrating the second region, the first region to the first step of the first stacked structure; forming a second conductive contact portion penetrating the second region to the second step of the second stacked structure; forming an array common source conductive contact portion penetrating the second region to the array common source electrode; and forming a peripheral conductive contact portion penetrating the second region and the second region.

[0016] Another embodiment of the present invention provides a three-dimensional memory, comprising: a first region including a first stacking structure and a first channel structure, the first channel structure penetrating the first stacking structure; an array common source electrode disposed on the first region, and the first channel structure being connected to the array common source electrode; and a second region disposed on the array common source electrode, the second region including a second stacking structure and a second channel structure, the second channel structure penetrating the second stacking structure and being connected to the array common source electrode.

[0017] In some embodiments, the system further includes: a second interconnect layer disposed on the second region and connected to the second channel structure; and a peripheral device structure disposed on the second interconnect layer, the peripheral device structure including a peripheral device layer and a first interconnect layer, the peripheral device layer being connected to the first interconnect layer and the first interconnect layer being connected to the second interconnect layer.

[0018] In some embodiments, the second interconnect layer includes: a first interconnect sublayer disposed on the second region and connected to the second channel structure; and a second interconnect sublayer disposed on the first interconnect sublayer and connected to the first interconnect sublayer, wherein the second interconnect sublayer is connected to the first interconnect layer.

[0019] In some embodiments, the system further includes: a first conductive contact portion extending through the second region and the first region to the first step of the first stacked structure, and the first conductive contact portion being connected to the second interconnect layer; and a second conductive contact portion extending through the second region to the second step of the second stacked structure, and the second conductive contact portion being connected to the second interconnect layer.

[0020] In some embodiments, the system further includes: a third interconnect layer disposed on the side of the first region away from the second region, the third interconnect layer being connected to the first channel structure; and lead-out pads disposed on the third interconnect layer and connected to the third interconnect layer.

[0021] In some embodiments, the third interconnect layer includes: a third interconnect sublayer disposed on the side of the first region away from the second region and connected to the first channel structure; and a fourth interconnect sublayer disposed on the third interconnect sublayer and connected to the third interconnect sublayer.

[0022] In some embodiments, a peripheral conductive contact portion is also included, penetrating the second region and the first region.

[0023] In some embodiments, the system further includes an array common source conductive contact portion, which extends through the second region to the array common source.

[0024] In some embodiments, the first stacked structure includes a plurality of alternately stacked conductive layers and insulating layers, wherein a portion of the conductive layer on the side of the first stacked structure facing away from the second region serves as a drain select gate of the first stacked structure, and a portion of the conductive layer on the side of the first stacked structure facing the second region serves as a source select gate of the first stacked structure.

[0025] In some embodiments, the second stacked structure includes a plurality of alternately stacked conductive layers and insulating layers, wherein a portion of the conductive layer on the side of the second stacked structure away from the first region serves as a drain select gate of the second stacked structure, and a portion of the conductive layer on the side of the second stacked structure facing the first region serves as a source select gate of the second stacked structure.

[0026] In the fabrication method of the three-dimensional memory provided in the embodiments of the present invention, the first region and the second region are arranged vertically and share the array common source electrode, which can overcome the process difficulty of forming channel holes, realize the stacking of high layers, reduce the length of the channel layer of the first channel structure and the second channel structure, reduce the channel resistance, increase the channel current, and improve the stability of the three-dimensional memory. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the steps of a three-dimensional memory manufacturing method provided in a specific embodiment of the present invention;

[0028] Figures 2A to 2H A schematic diagram of the main process cross-sections during the formation of a three-dimensional memory according to a specific embodiment of the present invention;

[0029] Figures 3A to 3D A schematic diagram of the main process cross-sections during the formation of a three-dimensional memory, according to another specific embodiment of the present invention. Detailed Implementation

[0030] The specific embodiments of the three-dimensional memory and its manufacturing method provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a schematic diagram illustrating the steps of a method for manufacturing a three-dimensional memory according to a specific embodiment of the present invention. Please refer to [link / reference]. Figure 1 The manufacturing method includes the following steps: Step S10, forming a first region on a substrate, the first region including a first stacked structure and a first channel structure disposed on the substrate, the first channel structure penetrating the first stacked structure; Step S11, forming an array common source electrode on the first region, the first channel structure being connected to the array common source electrode; Step S12, forming a second region on the array common source electrode, the second region including a second stacked structure and a second channel structure, the second channel structure penetrating the second stacked structure and being connected to the array common source electrode; Step S13, providing a peripheral device structure, the peripheral device structure including a peripheral device layer and a first interconnect layer, the peripheral device layer being connected to the first interconnect layer; Step S14, forming a second interconnect layer on the second region, the second interconnect layer being electrically connected to the second channel structure, and the first interconnect layer being electrically connected to the second interconnect layer; Step S15, forming a third interconnect layer on the side of the first region away from the second region, the third interconnect layer being connected to the first channel structure; Step S16, forming a lead-out pad on the third interconnect layer, the lead-out pad being connected to the third interconnect layer.

[0032] Figures 2A to 2H This is a schematic diagram of the main process cross-sections during the formation of a three-dimensional memory, provided by a specific embodiment of the present invention.

[0033] Please refer to step S10 and Figure 2A A first region 21 is formed on the substrate 20. The first region 21 includes a first stacked structure 210 and a first channel structure 211 disposed on the substrate 20. The first channel structure 211 penetrates the first stacked structure 210.

[0034] The substrate 20 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds. In this specific embodiment, the substrate 20 is made of single-crystal silicon (Si).

[0035] The first stacked structure 210 includes a plurality of alternately stacked conductive layers 212 and insulating layers 213. The insulating layer 213 serves as an isolation layer between adjacent conductive layers 212. In this specific embodiment, an insulating layer 213 is disposed on the substrate 20 as a bottom layer, conductive layers 212 and insulating layers 213 are sequentially and cyclically disposed on the insulating layer 213, and the insulating layer 213 is disposed on the top of the first stacked structure 210 as a top layer.

[0036] In some specific embodiments, the first stacked structure 210 is opposite to the second region 23 (see...). Figure 2C The conductive layer 212 on one side of the ) (e.g., Figure 2A The conductive layer 212 at the bottom of the first stacked structure serves as the drain selection gate of the first stacked structure 210, which faces the second region 23 (see [reference]). Figure 2C The conductive layer 212 on one side of the ) (e.g., Figure 2A The conductive layer 212 at the top of the first stacked structure serves as the source select gate of the first stacked structure 210, and the conductive layer 212 between the drain select gate and the source select gate serves as the control gate of the first stacked structure. For example, in this specific embodiment, the two conductive layers 212 at the bottom of the first stacked structure 210 serve as the drain select gate of the first stacked structure 210, and the two conductive layers 212 at the top of the first stacked structure 210 serve as the source select gate of the first stacked structure 210. It is understood that in other specific embodiments of the present invention, the number of conductive layers serving as the drain select gate and the source select gate may also be other values, such as one layer or three layers. The number of conductive layers serving as the drain select gate and the number of conductive layers serving as the source select gate may be the same or different, and may be set according to the specific design of the semiconductor structure.

[0037] The first channel structure 211 extends through the first stacked structure 210 to the substrate 20. In some embodiments, the first channel structure 211 further extends into the interior of the substrate 20. The first channel structure 211 includes a functional layer (not shown in the figures), a channel layer (not shown in the figures), and a channel filling layer (not shown in the figures). The functional layer includes a charge blocking layer, a charge trapping layer, and a tunneling layer stacked together.

[0038] Furthermore, the first area 21 includes a first core area B1, a first step area A1, and a first connecting area C1.

[0039] The first core region B1 is used to provide a storage array, and the first channel structure 211 is disposed in the first core region B1.

[0040] The first step region A1 includes a plurality of first steps 210A, each first step 210A being connected to a corresponding conductive layer 212, and a cover layer 216 covering the first steps 210A. A first sub-conductive contact portion 240A penetrates the cover layer 216 to the first step 210A of the corresponding conductive layer 212, thereby achieving an electrical connection with the corresponding conductive layer 212.

[0041] In the first connection region C1, a cover layer 216 covers the substrate 20. A first sub-peripheral conductive contact 260A extends through the cover layer 216 to the substrate 20. The first sub-peripheral conductive contact 260A is used to connect the second interconnect layer 270 (see...) Figure 2E ) and the third interconnect layer 280 (see Figure 2G )connect.

[0042] Furthermore, in some specific embodiments, the overlay layer 216 also covers the first core region B1 to provide support for the subsequent formation of the array common source 220.

[0043] As an example, this specific embodiment also provides a method for forming the first region 21. The method includes the following steps: forming a stacked layer of sacrificial layer and insulating layer 213 alternately stacked on a substrate 20, the stacked layer being distributed in a first core region B1 and a first step region A1, and the first connection region C1 exposing the substrate 20; forming a channel hole penetrating the stacked layer in the first core region B1, and forming a first channel structure 211 in the channel hole; forming a plurality of first steps 210A in the first step region A1; forming a capping layer 216 in the first step region A1 and the first connection region C1; removing the sacrificial layer to form a trench; filling the trench with a dielectric layer and a conductive material, the conductive material forming the conductive layer 212; forming a first sub-conductive contact portion 240A penetrating the capping layer 216 to the corresponding first step 210A in the first step region A1, and forming a first sub-peripheral conductive contact portion 260A penetrating the capping layer 216 in the first connection region C1.

[0044] The above is merely an example of forming the first stacked structure 210. Other methods may also be used to form the first stacked structure 210, and the present invention does not limit this method.

[0045] Please refer to step S11 and Figure 2B An array common source 220 is formed on the first stacked structure 210, and the first channel structure 211 is connected to the array common source 220.

[0046] In this step, the array common source 220 is formed in the first core region B1 of the first stacked structure 210. For example, one or more thin-film deposition processes (e.g., ALD, CVD, PVD, any other suitable process or any combination thereof) can be used to deposit a semiconductor layer (e.g., polysilicon) on the surface of the first region 21, and the semiconductor layer is patterned to form the array common source 220 located in the first core region B1. Connection portions 241 connected to the first sub-conductive contact 240A and connection portions 261 connected to the first sub-peripheral conductive contact 260A are formed in the first step region A1 and the first connection region C1. Further, the semiconductor layer can be doped before or after patterning using processes such as ion implantation to form a doped semiconductor layer, which serves as the array common source 220. The array common source 220 is electrically connected to one end of the first channel structure 211 to provide electrical connection between the sources of the memory array.

[0047] As an example, some specific embodiments of the present invention also provide a method for forming the array common source 220. Specifically, in the first region 21, the cover layer 216 is etched to form a connection hole, the connection hole exposing the first channel structure 211; a material layer is formed in the first region 21, the material layer covering the surface of the cover layer 216 and filling the connection hole; the material layer is patterned to form the array common source 220 electrically connected to the first channel structure 211 in the first core region B1, and a connection portion 241 connected to the first sub-conductive contact portion 240A and a connection portion 261 connected to the first sub-peripheral conductive contact portion 260A are formed in the first step region A1 and the first connection region C1; a dielectric layer 217 is formed to fill the area between the array common source 220, the connection portion 241, and the connection portion 261, and to cover the surface of the cover layer 216. After the material layer fills the connection hole, a connection portion 221 is formed in the connection hole. The array common source electrode 220 is electrically connected to the first channel structure 211 through the connection portion 221, which increases the contact area with the first channel structure 211 and greatly improves the electrical connection performance between the array common source electrode 220 and the first channel structure 211.

[0048] The above is merely an example of forming the array common source 220. Other methods can also be used to form the array common source 220, and the present invention does not limit this.

[0049] In some embodiments, the array common source 220 is formed after the steps of forming the first sub-conductive contact portion 240A and the first sub-peripheral conductive contact portion 260A. In other embodiments, the second region 23 may be formed after the array common source 220 is formed (see [link to previous embodiments]). Figure 2C Before that, the first sub-conductive contact portion 240A and the first sub-peripheral conductive contact portion 260A are formed.

[0050] Please refer to step S12 and Figure 2C A second region 23 is formed on the array common source 220. The second region 23 includes a second stack structure 230 and a second channel structure 231. The second channel structure 231 penetrates the second stack structure 230 and is connected to the array common source 220.

[0051] The second stacked structure 230 includes a plurality of alternately stacked conductive layers 232 and insulating layers 233. The insulating layer 233 serves as an isolation layer between adjacent conductive layers 232. In this specific embodiment, an insulating layer 233 is disposed on the array common source electrode 220 as a bottom layer, conductive layers 232 and insulating layers 233 are sequentially and cyclically disposed on the insulating layer 233, and the insulating layer 233 is disposed on the top of the second stacked structure 230 as a top layer.

[0052] In this specific embodiment, a portion of the conductive layer 232 of the second stacked structure 230 facing the first region 21 (e.g., Figure 2C The conductive layer 232 at the bottom of the second stacked structure serves as the source selection gate of the second stacked structure 230. A portion of the conductive layer 232 on the side of the second stacked structure 230 facing away from the first region 21 (e.g., Figure 2C The conductive layer 232 at the top of the second stacked structure serves as the drain select gate of the second stacked structure 230, and the conductive layer 232 between the drain select gate and the source select gate serves as the control gate of the second stacked structure 230. For example, in this specific embodiment, the two conductive layers 232 at the bottom of the second stacked structure 230 serve as the source select gate of the second stacked structure 230, and the two conductive layers 232 at the top of the second stacked structure 230 serve as the drain select gate of the second stacked structure 230. It is understood that in other specific embodiments of the present invention, the number of conductive layers serving as the drain select gate and the source select gate may also be other values, such as one layer or three layers. The number of conductive layers serving as the drain select gate and the number of conductive layers serving as the source select gate may be the same or different, and may be set according to the specific design of the semiconductor structure.

[0053] The second channel structure 231 extends through the second stacked structure 230 to the array common source 220. In some specific embodiments, the second channel structure 231 further extends into the interior of the array common source 220. The second channel structure 231 includes a functional layer (not shown in the figures), a channel layer (not shown in the figures), and a channel filling layer (not shown in the figures). The functional layer includes a charge blocking layer, a charge trapping layer, and a tunneling layer stacked together.

[0054] Furthermore, the second zone 23 includes a second step zone A2, a second core zone B2, and a second connecting zone C2.

[0055] The second core region B2 is used to provide a storage array, and the second channel structure 231 is disposed in the second core region B2.

[0056] The second step region A2 includes multiple second steps 230A, each of which is connected to a corresponding conductive layer 232. A cover layer 236 covers the second steps 230A. A second conductive contact 250 penetrates the cover layer 236 to the second step 230A of the corresponding conductive layer 232, thereby achieving electrical connection with the corresponding conductive layer 232. The material of the second conductive contact 250 can be a conductive material such as polycrystalline silicon or metal.

[0057] The second connection region C2 is disposed corresponding to the exposed surface of the array common source electrode 220, the first step region A1, and the first connection region C1. Specifically, in some embodiments, the second connection region C2 is located above the exposed surface of the array common source electrode 220, the first step region A1, and the first connection region C1. The second sub-conductive contact 240B penetrates the cover layer 236 and is connected to the first sub-conductive contact 240A, and together they serve as the first conductive contact 240. The first conductive contact 240 is used to connect the conductive layer 212 of the first region 21 to the second interconnect layer 270 (see...). Figure 2E Electrical connection.

[0058] Specifically, in this embodiment, the second sub-conductive contact 240B is connected to the connecting part 241, and the connecting part 241 is then connected to the first sub-conductive contact 240A. The first sub-conductive contact 240A, the connecting part 241, and the second sub-conductive contact 240B together serve as the first conductive contact 240.

[0059] The materials of the first sub-conductive contact portion 240A and the second sub-conductive contact portion 240B can be conductive materials such as polycrystalline silicon or metal.

[0060] Furthermore, the second sub-peripheral conductive contact 260B penetrates the cover layer 236 and connects with the first sub-peripheral conductive contact 260A, together serving as a peripheral conductive contact 260. The peripheral conductive contact 260 is used to connect the second interconnect layer 270 (see...) Figure 2E ) and the third interconnect layer 280 (see Figure 2G Electrical connection.

[0061] Specifically, in this embodiment, the second sub-peripheral conductive contact 260B is connected to the connecting part 261, and the connecting part 261 is then connected to the first sub-peripheral conductive contact 260A. The first sub-peripheral conductive contact 260A, the connecting part 261, and the second sub-peripheral conductive contact 260B together serve as the peripheral conductive contact 260.

[0062] The materials of the first sub-peripheral conductive contact 260A and the second sub-peripheral conductive contact 260B can be conductive materials such as polycrystalline silicon or metal.

[0063] Furthermore, an array common-source conductive contact 222 is formed in the second connection region C2, the array common-source conductive contact 222 penetrating the cover layer 236 to the array common-source 230. One end of the array common-source conductive contact 222 is electrically connected to the array common-source 220, and the other end is used to connect to the second interconnect layer 270 (see...). Figure 2E Electrical connection.

[0064] As an example, this specific embodiment also provides a method for forming the second region 23. The method includes the following steps: forming a stacked layer of sacrificial layer and insulating layer 233 alternately stacked on the array common source 220 and the first region 21, the stacked layer being distributed in the second core region B2 and the second step region A2, the second connection region C2 exposing the first region 21; forming a channel hole penetrating the stacked layer in the second core region B2, and forming a second channel structure 231 in the channel hole; forming a plurality of second steps 230A in the second step region A2; forming a cover layer 236 in the second step region A2 and the second connection region C2; removing the sacrificial layer to form a trench; filling the trench with a dielectric layer and a conductive material, the conductive material forming the conductive layer 232; forming a second conductive contact portion 250 penetrating the cover layer 236 to the corresponding second step 230A in the second step region A2, and forming a second sub-conductive contact portion 240B and a second sub-peripheral conductive contact portion 260B penetrating the cover layer 236 in the second connection region C2.

[0065] The above is merely an example of forming the second region 23. Other methods may also be used to form the second region 23, and the present invention does not limit this method.

[0066] The first region 21 and the second region 23 are arranged vertically and share the array common source 220. This can reduce the depth of the channel hole in each region, overcome the process difficulty, realize the stacking of multiple layers, and reduce the length of the channel layer of the first channel structure 211 and the second channel structure 231, reduce the channel resistance, increase the channel current, and improve the stability of the three-dimensional memory.

[0067] Please refer to step S13 and Figure 2D A peripheral device structure 290 is provided. The peripheral device structure 290 includes a peripheral device layer 291 and a first interconnect layer 292, wherein the peripheral device layer 291 is connected to the first interconnect layer 292.

[0068] The peripheral device layer 291 can be used to lay out peripheral circuits for providing control circuitry for the three-dimensional memory. The first interconnect layer 292 is used to electrically bring out the peripheral device layer 291.

[0069] Please refer to step S14 and Figure 2E A second interconnect layer 270 is formed on the second region 23. The second interconnect layer 270 is electrically connected to the second channel structure 231, and the first interconnect layer 292 is electrically connected to the second interconnect layer 270.

[0070] The method for electrically connecting the first interconnect layer 292 and the second interconnect layer 270 can be hybrid bonding. That is, using the planes where the first interconnect layer 292 and the second interconnect layer 270 are located as bonding surfaces, the peripheral device structure 290 is connected to the second interconnect layer 270 by bonding.

[0071] In some specific embodiments, the method of forming the second interconnect layer 270 includes:

[0072] A first interconnect sublayer 271 is formed on the second region 23. The first interconnect sublayer 271 is electrically connected to the second channel structure 231, the second conductive contact 250, the first conductive contact 240, and the peripheral conductive contact 260. In some specific embodiments, the first interconnect sublayer 272 includes a bit line structure and an interconnect structure. The bit line structure is electrically connected to the second channel structure 231 and can serve as a bit line for the second region 23. The two ends of the second channel structure 231 are respectively connected to the array common source 220 and the bit line structure, so that the second channel structure 231 can form a circuit loop. The interconnect structure is electrically connected to the second conductive contact 250, the first conductive contact 240, the array common source conductive contact 222, and the peripheral conductive contact 260, and is used to electrically lead out the first conductive contact 240, the second conductive contact 250, the array common source conductive contact 222, and the peripheral conductive contact 260.

[0073] A second interconnect sublayer 272 is formed, which is connected to the first interconnect sublayer 271. The first interconnect sublayer 271 and the second interconnect sublayer 272 together constitute the second interconnect layer 270. One side of the second sub-interconnect layer 272 is connected to the first sub-interconnect layer 271, and the other side is connected to the first interconnect layer 292, for electrically connecting the first sub-interconnect layer 271 and the first interconnect layer 292.

[0074] As an example, this specific embodiment also provides a method for forming the second interconnect layer 270. The method includes the following steps: forming a dielectric layer on the surface of the second region 23 using one or more deposition processes; etching the dielectric layer to form a patterned layer; filling the patterned layer with a conductive material and polishing it to form a first sub-interconnect layer 271. Forming a dielectric layer on the surface of the second interconnect layer 270 using one or more deposition processes; etching the dielectric layer to form a patterned layer; filling the patterned layer with a conductive material and polishing it to form the second sub-interconnect layer 272. The deposition processes include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof.

[0075] Please refer to step S15 and Figure 2G A third interconnect layer 280 is formed on the side of the first region 21 away from the second region 23, and the third interconnect layer 280 is connected to the first channel structure 211.

[0076] In this specific embodiment, the method for forming the third interconnect layer includes: Please refer to... Figure 2F The substrate 20 is thinned to expose the first channel structure 211. In this step, the three-dimensional memory can be flipped so that the substrate 20 faces upward, and the substrate 20 is thinned. For example, wet etching, dry etching, chemical mechanical polishing, or other processes can be used to thin the substrate 20. After the substrate 20 is thinned, the first channel structure 211 is exposed; specifically, the channel layer of the first channel structure 211 is exposed for subsequent electrical connections. Furthermore, in this step, after the substrate 20 is thinned, the first sub-peripheral conductive contact 260A is also exposed for electrical connection with the third interconnect layer 280.

[0077] Please see Figure 2GA third interconnect layer 280 is formed on the side of the first region 21 away from the second region 23. The third interconnect layer 280 includes a third sub-interconnect layer 281 and a fourth sub-interconnect layer 282. The third sub-interconnect layer 281 is electrically connected to the first channel structure 211, serving as a bit line of the first stacked structure 210. Both ends of the first channel structure 211 are connected to the array common source 220 and the third sub-interconnect layer 281, respectively, enabling the first channel structure 211 to form a circuit loop. The fourth sub-interconnect layer 282 is electrically connected to the third sub-interconnect layer 281, used to bring out the third sub-interconnect layer 281.

[0078] As an example, this specific embodiment provides a method for forming the third interconnect layer 280 after thinning the substrate 20. The method includes the following steps: forming a dielectric layer on the side of the region 21 away from the second region 23 using one or more deposition processes; etching the dielectric layer to form a patterned layer; filling the patterned layer with a conductive material and polishing it to form the third interconnect layer 281; forming a dielectric layer on the surface of the third interconnect layer 281 and the first region 21 using one or more deposition processes; etching the dielectric layer to form a patterned layer; filling the patterned layer with a conductive material and polishing it to form the fourth sub-interconnect layer 282. The deposition processes include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof.

[0079] Furthermore, the third sub-interconnect layer 281 is also connected to the peripheral conductive contact 260. For example, in this specific embodiment, the third sub-interconnect layer 281 is connected to the first sub-peripheral conductive contact 260A. The third sub-interconnect layer 281 is also connected to the array common source 220, the second channel structure 231, and the peripheral device structure 290. For example, the third sub-interconnect layer 281 is connected to the array common source 220, the second channel structure 231, and the peripheral device structure 290 through the peripheral conductive contact 260.

[0080] Please refer to step S16 and Figure 2H A lead-out pad 2821 is formed on the third interconnect layer 280, and the lead-out pad 2821 is connected to the third interconnect layer 280. The lead-out pad 2821 is used to provide an interface for external electrical connection.

[0081] As an example, this specific embodiment also provides a method for forming the lead-out pad 2821: the method includes the following steps: forming a dielectric layer on the third interconnect layer 280; etching the dielectric layer to form a pattern layer; filling the pattern layer with a conductive material to form the lead-out pad 2821.

[0082] The three-dimensional memory manufacturing method provided by the specific embodiments of the present invention can form a first region and a second region that are vertically stacked and share an array common source, thereby achieving high-level stacking. It can also reduce the length of the channel layers of the first channel structure 211 and the second channel structure 231, reduce the channel resistance, increase the channel current, and improve the stability of the three-dimensional memory.

[0083] In the above specific embodiments, the first conductive contact portion 240 is formed in two parts, for example, a first sub-conductive contact portion 240A and a second sub-conductive contact portion 240B, and the two parts are formed in different steps; the peripheral conductive contact portion 260 is also divided into two parts, for example, a first sub-peripheral conductive contact portion 260A and a second sub-peripheral conductive contact portion 260B, and the two parts are formed in different steps. However, in other specific embodiments of the present invention, the two parts of the first conductive contact portion 240 can be formed in the same step, and the two parts of the peripheral conductive contact portion 260 can also be formed in the same step.

[0084] As an example, another specific embodiment of the present invention provides a method for forming the first conductive contact portion 240 and the peripheral conductive contact portion 260.

[0085] Please see Figure 3A In some specific embodiments of the present invention, after the first stacked structure 210 is formed, only the cover layer 216 is formed in the first step region A1 and the first connection region C1.

[0086] Please see Figure 3B An array common source electrode 220 is formed on the first region 21, and a first channel structure 211 is connected to the array common source electrode 220. The array common source electrode 220 is formed in the first core region B1.

[0087] Please see Figure 3C A second region 23 is formed on the array common source electrode 220 and the first region 21. The second region 23 includes a second stacking structure 230 and a second channel structure 231. The second channel structure 231 penetrates the second stacking structure 230 and is connected to the array common source electrode 220. In this step, only a cover layer 236 is formed in the second step region A2 and the second connection region C2.

[0088] Please see Figure 3DThe system forms a first conductive contact 240, a second conductive contact 250, a peripheral conductive contact 260, and an array common source conductive contact 222. The first conductive contact 240 penetrates the cover layer 236 and the cover layer 216 to the first step; the second conductive contact 250 penetrates the cover layer 236 to the second step; the peripheral conductive contact 260 penetrates the cover layer 236 and the cover layer 216 to the substrate 20; and the array common source conductive contact 222 penetrates the cover layer 236 to the array common source 220.

[0089] A further embodiment of the present invention provides a three-dimensional memory formed using the above-described preparation method. Please refer to [link / reference]. Figure 2H The three-dimensional memory includes a first region 21, an array common source 220, and a second region 23.

[0090] The first region 21 includes a first stacking structure 210 and a first channel structure 211, wherein the first channel structure 211 penetrates the first stacking structure 210.

[0091] The first stacked structure 210 includes a plurality of alternately stacked conductive layers 212 and insulating layers 213. The insulating layer 213 serves as an isolation layer between adjacent conductive layers 212. The portion of the conductive layer 212 in the first stacked structure 210 facing away from the second region 23 serves as the drain select gate of the first stacked structure 210, the portion of the conductive layer 212 in the first stacked structure 210 facing the second region 23 serves as the source select gate of the first stacked structure 210, and the conductive layer 212 between the drain select gate and the source select gate serves as the control gate of the first stacked structure.

[0092] It should be noted that in the accompanying drawings of the specific embodiments of the present invention, the number of conductive layer 212 and insulating layer 213 is only schematically shown in order to illustrate the technical solution of the specific embodiments of the present invention, and does not represent the actual number of conductive layer 212 and insulating layer 213.

[0093] The first channel structure 211 extends through the first stacked structure 210 to the substrate 20 (see...) Figure 2A The first channel structure 211 includes a functional layer (not shown in the figures), a channel layer (not shown in the figures), and a channel filling layer (not shown in the figures). The functional layer includes a charge blocking layer, a charge trapping layer, and a tunneling layer stacked together.

[0094] Furthermore, the first area 21 includes a first step area A1, a first core area B1, and a first connection area C1.

[0095] The first core region B1 is used to provide a storage array, and the first channel structure 211 is disposed in the first core region B1.

[0096] The first step area A1 includes a plurality of first steps 210A (see...) Figure 2A The first step 210A is connected to the corresponding conductive layer 212, and the cover layer 216 covers the first step 210A. In some specific embodiments of the present invention, the first sub-conductive contact 240A (see...) Figure 2A It penetrates through the cover layer 216 to the first step 210A of the corresponding conductive layer 212, thereby achieving an electrical connection with the corresponding conductive layer 212.

[0097] In the first connection area C1, the overlay layer 216 (see...) Figure 2A The cover layer 216 covers the substrate 20. A first sub-peripheral conductive contact 260A extends through the cover layer 216 to the substrate 20. The first sub-peripheral conductive contact 260A is used to connect the second interconnect layer 270 and the third interconnect layer 280.

[0098] The array common source 220 is placed on the first region 21, and the first channel structure 210 is connected to the array common source 220. In this specific embodiment, the array common source 220 is disposed corresponding to the first core region B1. The array common source 220 is electrically connected to one end of the first channel structure 211 to provide electrical connection between the sources of the memory array.

[0099] The second region 23 is placed on the array common source 220. The second region 23 includes a second stacking structure 230 and a second channel structure 231. The second channel structure 231 penetrates the second stacking structure 230 and is connected to the array common source 220.

[0100] The second stacked structure 230 includes a plurality of alternately stacked conductive layers 232 and insulating layers 233. The insulating layer 233 serves as an isolation layer between adjacent conductive layers 232. In this specific embodiment, the portion of the conductive layer 232 facing the first region 21 of the second stacked structure 230 serves as the source select gate of the second stacked structure 230, the portion of the conductive layer 232 facing away from the first region 21 serves as the drain select gate of the second stacked structure 230, and the conductive layer 232 between the drain select gate and the source select gate serves as the control gate of the second stacked structure 230.

[0101] It should be noted that in the accompanying drawings of the specific embodiments of the present invention, the number of conductive layer 232 and insulating layer 233 is only schematically shown in order to illustrate the technical solution of the specific embodiments of the present invention, and does not represent the actual number of conductive layer 232 and insulating layer 233.

[0102] The second channel structure 231 extends through the second stacked structure 230 to the array common source 220. In some specific embodiments, the second channel structure 231 further extends into the interior of the array common source 220. The second channel structure 231 includes a functional layer (not shown in the figures), a channel layer (not shown in the figures), and a channel filling layer (not shown in the figures). The functional layer includes a charge blocking layer, a charge trapping layer, and a tunneling layer stacked together.

[0103] Furthermore, the second zone 23 includes the second step zone A2 and the second core zone B2 (see...). Figure 2C ) and the second outer perimeter area C2.

[0104] The second core region B2 is used to provide a storage array, and the second channel structure 231 (see...) Figure 2C The second core area B2 is located above the first core area B1.

[0105] The second step area A2 includes multiple second steps 230A (see...) Figure 2C The second step 230A is connected to the corresponding conductive layer 232. Cover layer 236 (see...) Figure 2C The second conductive contact 250 covers the second step 230A. The second conductive contact 250 penetrates the cover layer 236 to the step of the corresponding conductive layer 232, thereby achieving an electrical connection with the corresponding conductive layer 232.

[0106] The second connection region C2 is disposed corresponding to the exposed surface of the array common source electrode 220, the first step region A1, and the first connection region C1. Specifically, in some embodiments, the second connection region C2 is located above the exposed surface of the array common source electrode 220, the first step region A1, and the first connection region C1. The second sub-conductive contact 240B penetrates the cover layer 236 and is connected to the first sub-conductive contact 240A, and together they serve as the first conductive contact 240, which is used to electrically connect the conductive layer 212 of the first region to the second interconnect layer 270.

[0107] Furthermore, in some specific embodiments, the second sub-conductive contact portion 240B and the first sub-conductive contact portion 240A are connected by a connecting portion 241.

[0108] In some specific embodiments, due to limitations in the manufacturing process, the first conductive contact portion 240 is divided into a first sub-conductive contact portion 240A and a second sub-conductive contact portion 240B. These two portions are formed in different steps. For other specific embodiments of the present invention, please refer to [link to relevant documentation]. Figure 3D The first conductive contact portion 240 can also be formed directly in the same step.

[0109] Furthermore, a second sub-peripheral conductive contact 260B is also provided in the second connection area C2. The second sub-peripheral conductive contact 260B is connected to the first sub-peripheral conductive contact 260A and together serve as a peripheral conductive contact 260. The peripheral conductive contact 260 is used to electrically connect the second interconnect layer 270 to the second circuit structure 280.

[0110] Furthermore, in some specific embodiments, the second sub-peripheral conductive contact portion 260B is connected to the first sub-peripheral conductive contact portion 260A via a connecting portion 261.

[0111] In some specific embodiments, due to limitations in the manufacturing process, the peripheral conductive contact portion 260 is divided into a first sub-peripheral conductive contact portion 260A and a second sub-peripheral conductive contact portion 260B. These two portions are formed in different steps. For other specific embodiments of the present invention, please refer to [link to relevant documentation]. Figure 3D The peripheral conductive contact portion 260 can also be formed directly in the same step.

[0112] Furthermore, an array of common-source conductive contacts 222 is also formed in the second connection region C2 (see...). Figure 2C The array common source conductive contact 222 extends through the second region 23 to the array common source 230. One end of the array common source conductive contact 222 is electrically connected to the array common source 220, and the other end can be electrically connected to the second interconnect layer 270.

[0113] Furthermore, the three-dimensional memory also includes a second interconnect layer 270 and a peripheral device structure 290.

[0114] The second interconnect layer 270 is disposed on the second region 23 and is electrically connected to the second channel structure 231, the second conductive contact 250, the first conductive contact 240, and the peripheral conductive contact 260. The peripheral device structure 290 is disposed on the second interconnect layer and is used to provide the control circuitry for the three-dimensional memory.

[0115] The second interconnect layer 270 includes a first interconnect sublayer 271 and a second interconnect sublayer 272.

[0116] The first interconnect sublayer 271 is electrically connected to the second channel structure 231, the second conductive contact 250, the first conductive contact 240, and the peripheral conductive contact 260. In some specific embodiments, the first interconnect sublayer 272 includes a bit line structure and an interconnect structure. The bit line structure is electrically connected to the second channel structure 231 and can serve as the bit line of the second region 23. The two ends of the second channel structure 231 are respectively connected to the array common source 220 and the bit line structure, so that the second channel structure 231 can form a circuit loop. The interconnect structure is electrically connected to the second conductive contact 250, the first conductive contact 240, the array common source conductive contact 222, and the peripheral conductive contact 260, and is used to electrically lead out the first conductive contact 240, the second conductive contact 250, the array common source conductive contact 222, and the peripheral conductive contact 260.

[0117] The second interconnect sub-layer 272 is connected to the first interconnect sub-layer 271, and the first interconnect sub-layer 271 and the second interconnect sub-layer 272 together constitute the second interconnect layer 270. One side of the second sub-interconnect layer 272 is connected to the first sub-interconnect layer 271, and the other side is connected to the peripheral circuit structure 290, for electrically connecting the first sub-interconnect layer 271 and the peripheral circuit structure 290.

[0118] The peripheral device structure 290 includes a peripheral device layer 291 and a first interconnect layer 292, with the peripheral device layer 291 connected to the first interconnect layer 292. The peripheral device layer 291 can be used to lay out peripheral circuitry, providing control circuitry for the three-dimensional memory. The first interconnect layer 292 is used to electrically lead out the peripheral device layer 291. The first interconnect layer 292 is connected to a second sub-interconnect layer 272.

[0119] Furthermore, the three-dimensional memory also includes a third interconnect layer 280. The third interconnect layer 280 is located on the side of the first region 21 away from the second region 23. In some specific embodiments, the third interconnect layer 280 is connected to the first channel structure 211 and the peripheral conductive contact portion 260.

[0120] The third interconnect layer 280 includes a third sub-interconnect layer 281 and a fourth sub-interconnect layer 282. The third sub-interconnect layer 281 is electrically connected to the first channel structure 211, serving as a bit line of the first stacked structure 210. The two ends of the first channel structure 211 are respectively connected to the array common source 220 and the third sub-interconnect layer 281, enabling the first channel structure 211 to form a circuit loop. The third sub-interconnect layer 281 can also be connected to the peripheral conductive contact 260 to bring out the peripheral conductive contact 260. The fourth sub-interconnect layer 282 is electrically connected to the third sub-interconnect layer 281 and is used to bring out the third sub-interconnect layer 281.

[0121] The three-dimensional memory also includes lead-out pads 2821, which are connected to the third interconnect layer 280 to provide an interface for external electrical connections.

[0122] The first and second regions of the three-dimensional memory provided in the specific embodiments of the present invention are arranged vertically and share the same array source. This can overcome the process difficulty caused by excessively deep channel holes, realize the stacking of multiple layers, reduce the length of the channel layers of the first and second channel structures, reduce the channel resistance, increase the channel current, and improve the stability of the three-dimensional memory.

[0123] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that, include: A first region is formed on a substrate, the first region including a first stacked structure and a first channel structure disposed on the substrate, the first channel structure penetrating the first stacked structure; An array of common source electrodes is formed on the first region, and the first channel structure is connected to the array of common source electrodes; as well as A second region is formed on the array common source electrode. The second region includes a second stack structure and a second channel structure. The second channel structure penetrates the second stack structure and is connected to the array common source electrode.

2. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Further steps include the following: A peripheral device structure is provided, the peripheral device structure including a peripheral device layer and a first interconnect layer, the peripheral device layer being connected to the first interconnect layer; A second interconnect layer is formed on the second region, and the second interconnect layer is electrically connected to the second channel structure; The first interconnect layer is electrically connected to the second interconnect layer.

3. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, The method for forming a second interconnect layer on the second region includes the following steps: A first interconnect sublayer is formed on the second region, and the first interconnect sublayer is electrically connected to the second channel structure; A second interconnect sublayer is formed, which is connected to the first interconnect sublayer. The first interconnect sublayer and the second interconnect sublayer together serve as the second interconnect layer.

4. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Further steps include the following: A third interconnect layer is formed on the side of the first region away from the second region, and the third interconnect layer is connected to the first channel structure; Lead-out pads are formed on the third interconnect layer and are connected to the third interconnect layer.

5. The method for manufacturing a three-dimensional memory according to claim 4, characterized in that, The step of forming a third interconnect layer on the side of the first region away from the second region further includes: Thinning the substrate exposes the first channel structure; A third interconnect sublayer is formed on the side of the first region away from the second region, and the third interconnect sublayer is connected to the first channel structure; A fourth interconnect sublayer is formed on the third interconnect sublayer, and the fourth interconnect sublayer is connected to the third interconnect sublayer. The third interconnect sublayer and the fourth interconnect sublayer together serve as the third interconnect layer.

6. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, Further steps include the following: Before the second region is formed, a first sub-conductive contact portion is formed in the first region, extending through the first region to the first step of the first stacked structure; After the second region is formed, a second sub-conductive contact portion is formed that penetrates the second region. The second sub-conductive contact portion is electrically connected to the first sub-conductive contact portion and together they serve as the first conductive contact portion. The first conductive contact portion is electrically connected to the second interconnect layer.

7. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, The method further includes the following steps: forming an array common source conductive contact portion that extends through the second region in the second region, wherein the array common source conductive contact portion is connected to the array common source and the second interconnect layer.

8. The method for manufacturing a three-dimensional memory according to claim 2, characterized in that, The method further includes the following steps: forming a second conductive contact portion in the second region that extends through the second region to the second step of the second stacked structure, wherein the second conductive contact portion is connected to the second interconnect layer.

9. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Further steps include the following: Before the second region is formed, a first sub-peripheral conductive contact portion is formed in the first region, and the first sub-peripheral contact portion penetrates the first region; After the second region is formed, a second sub-peripheral conductive contact is formed in the second region. The second sub-peripheral conductive contact penetrates the second region and is connected to the first sub-peripheral conductive contact, together serving as a peripheral conductive contact.

10. The method for manufacturing a three-dimensional memory according to claim 1, characterized in that, Further steps include the following: A first conductive contact portion is formed, extending through the second region, the first region, and to the first step of the first stacked structure; A second conductive contact portion is formed, penetrating the second region to the second step of the second stacked structure; Forming an array common source conductive contact portion extending through the second region to the array common source electrode; and A conductive contact portion is formed that extends through the second region and the outer periphery of the second region.

11. A three-dimensional memory, characterized in that, include: The first region includes a first stacked structure and a first channel structure, wherein the first channel structure penetrates the first stacked structure; An array common source electrode is placed on the first region, and the first channel structure is connected to the array common source electrode. The second region is placed on the common source of the array. The second region includes a second stack structure and a second channel structure. The second channel structure penetrates the second stack structure and is connected to the common source of the array.

12. The three-dimensional memory according to claim 11, characterized in that, Also includes: A second interconnect layer is placed on the second region and connected to the second channel structure; A peripheral device structure is placed on the second interconnect layer. The peripheral device structure includes a peripheral device layer and a first interconnect layer. The peripheral device layer is connected to the first interconnect layer, and the first interconnect layer is connected to the second interconnect layer.

13. The three-dimensional memory according to claim 12, characterized in that, The second interconnect layer includes: The first interconnect sublayer is placed on the second region and connected to the second channel structure; The second interconnect sublayer is placed on the first interconnect sublayer and connected to the first interconnect sublayer. The second interconnect sublayer is connected to the first interconnect layer.

14. The three-dimensional memory according to claim 12, characterized in that, Also includes: A first conductive contact extends through the second region and the first region to the first step of the first stacked structure, and the first conductive contact is connected to the second interconnect layer; The second conductive contact extends through the second region to the second step of the second stacked structure, and the second conductive contact is connected to the second interconnect layer.

15. The three-dimensional memory according to claim 11, characterized in that, Also includes: A third interconnect layer is placed on the side of the first region away from the second region, and the third interconnect layer is connected to the first channel structure; The solder pads are brought out, placed on the third interconnect layer, and connected to the third interconnect layer.

16. The three-dimensional memory according to claim 15, characterized in that, The third interconnection layer includes: The third interconnect sublayer is located on the side of the first region away from the second region and is connected to the first channel structure; The fourth interconnect sublayer is placed on the third interconnect sublayer and connected to the third interconnect sublayer.

17. The three-dimensional memory according to claim 11, characterized in that, It also includes peripheral conductive contacts that penetrate the second region and the first region.

18. The three-dimensional memory according to claim 11, characterized in that, It also includes an array common source conductive contact portion, which extends through the second region to the array common source electrode.

19. The three-dimensional memory according to claim 11, characterized in that, The first stacked structure includes multiple alternating conductive layers and insulating layers. A portion of the conductive layer on the side of the first stacked structure facing away from the second region serves as the drain select gate of the first stacked structure, and a portion of the conductive layer on the side of the first stacked structure facing the second region serves as the source select gate of the first stacked structure.

20. The three-dimensional memory according to claim 11, characterized in that, The second stacked structure includes multiple alternating conductive layers and insulating layers. A portion of the conductive layer on the side of the second stacked structure away from the first region serves as the drain select gate of the second stacked structure, and a portion of the conductive layer on the side of the second stacked structure facing the first region serves as the source select gate of the second stacked structure.

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