Thin Film Transistor Circuit and Method for Manufacturing the Same

Abstract

The present invention relates to a thin film transistor circuit and a method for manufacturing the thin film transistor circuit. The polysilicon layer includes a polysilicon portion of a polysilicon thin film transistor. The first conductor layer includes a first gate electrode portion of the polysilicon thin film transistor. The first insulator layer includes a first insulator portion located between the first gate electrode portion and the polysilicon portion. The oxide semiconductor layer includes an oxide semiconductor portion of an oxide semiconductor thin film transistor. The second conductor layer includes a second gate electrode portion of the oxide semiconductor thin film transistor. The second insulator layer includes a second insulator portion located between the second gate electrode portion and the oxide semiconductor portion. The second insulator layer has a relative dielectric constant of not less than 8. The entire region of the second insulator layer is covered by the second conductor layer.

Description

Technical Field

[0001] The present invention relates to a thin film transistor circuit and a method of manufacturing the thin film transistor circuit. Background Art

[0002] Techniques for incorporating low-temperature polycrystalline silicon thin film transistors (LTPS TFTs) and oxide semiconductor TFTs into one circuit have become available in practical applications. For example, pixel circuits including low-temperature polycrystalline silicon TFTs and oxide semiconductor TFTs have been proposed. By incorporating low-temperature polycrystalline silicon TFTs with high mobility and oxide semiconductor TFTs with small leakage current into one circuit, improvement of circuit characteristics and reduction of power consumption have been achieved.

[0003] Since the mobility of oxide semiconductor TFTs is low, in order to increase the on-current of oxide semiconductor TFTs or reduce the drive voltage of oxide semiconductor TFTs, use of a high-k insulator for the gate insulator of oxide semiconductor TFTs has been proposed. Summary of the Invention

[0004] The relative dielectric constant of a high-k insulator film is higher than that of a general silicon-based gate insulating film. Therefore, a high-k insulator film can increase the on-current of a TFT, but may cause a large parasitic capacitance. Accordingly, a technique for improving the current characteristics of oxide semiconductor TFTs while preventing generation of an undesired parasitic capacitance is needed.

[0005] One aspect of the present invention is a thin film transistor circuit including: a polycrystalline silicon layer; a first conductor layer located above the polycrystalline silicon layer; a first insulator layer located between the first conductor layer and the polycrystalline silicon layer; an oxide semiconductor layer; a second conductor layer located above the oxide semiconductor layer; and a second insulator layer located between the second conductor layer and the oxide semiconductor layer. The polycrystalline silicon layer includes a polycrystalline silicon portion of a polycrystalline silicon thin film transistor. The first conductor layer includes a first gate electrode portion of the polycrystalline silicon thin film transistor. The first insulator layer includes a first insulator portion located between the first gate electrode portion and the polycrystalline silicon portion. The oxide semiconductor layer includes an oxide semiconductor portion of an oxide semiconductor thin film transistor. The second conductor layer includes a second gate electrode portion of the oxide semiconductor thin film transistor. The second insulator layer includes a second insulator portion located between the second gate electrode portion and the oxide semiconductor portion. The second insulator layer has a relative dielectric constant of not less than 8. The entire region of the second insulator layer is covered by the second conductor layer.

[0006] One aspect of the present invention is a method of manufacturing a thin film transistor circuit. The method includes: forming a polysilicon layer including a polysilicon portion of a polysilicon thin film transistor; forming a first insulator layer including an insulator portion of a polysilicon thin film transistor on an upper layer of the polysilicon layer; forming a first conductor layer including a gate electrode portion of a polysilicon thin film transistor on an upper layer of the first insulator layer; forming an oxide semiconductor layer including an oxide semiconductor portion of an oxide semiconductor thin film transistor; forming a second insulator layer including an insulator portion of an oxide semiconductor thin film transistor on an upper layer of the oxide semiconductor layer; and forming a second conductor layer including a gate electrode portion of an oxide semiconductor thin film transistor on an upper layer of the second insulator layer. The second insulator layer has a relative dielectric constant of not less than 8. The second conductor layer and the second insulator layer are etched together or the second insulator layer is etched using the second conductor layer as a mask.

[0007] One aspect of the present invention improves the characteristics of a circuit including a polysilicon thin film transistor and an oxide semiconductor thin film transistor.

[0008] It should be understood that the foregoing general description and the following detailed description are both exemplary and explanatory, and not restrictive of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 Schematically shows a configuration example of an OLED display device;

[0010] Figure 2 Shows a configuration example of a pixel circuit;

[0011] Figure 3 Schematically shows a cross-sectional structure of a part of a TFT substrate;

[0012] Figure 4 Schematically shows a cross-sectional structure of another part of a TFT substrate;

[0013] Figure 5 Is a top view of a part of a TFT substrate;

[0014] Figure 6 Shows an example of a CMOS (complementary metal oxide semiconductor) circuit;

[0015] Figure 7 Schematically shows Figure 6 An example of a cross-sectional structure of the CMOS circuit shown;

[0016] Figure 8A Shows Figure 3 An example of steps of a manufacturing method of the structure shown;

[0017] Figure 8B Shows Figure 3Steps of an example of a manufacturing method of the structure shown;

[0018] Figure 8C Shows Figure 3 Steps of an example of a manufacturing method of the structure shown;

[0019] Figure 8D Shows Figure 3 Steps of an example of a manufacturing method of the structure shown;

[0020] Figure 8E Shows Figure 3 Steps of an example of a manufacturing method of the structure shown;

[0021] Figure 8F Shows Figure 3 Steps of an example of a manufacturing method of the structure shown;

[0022] Figure 9 Schematically shows a cross-sectional structure of a part of the pixel circuit in Embodiment 2;

[0023] Figure 10 Schematically shows a cross-sectional structure of the CMOS circuit in Embodiment 2;

[0024] Figure 11 Is a cross-sectional view of an example of the configuration of the oxide semiconductor TFT in Embodiment 3;

[0025] Figure 12 Is a cross-sectional view of another example of the configuration of the oxide semiconductor TFT in Embodiment 3;

[0026] Figure 13A Shows Figure 11 Steps of an example of the manufacturing method of the oxide semiconductor TFT shown in;

[0027] Figure 13B Shows Figure 11 Steps of an example of the manufacturing method of the oxide semiconductor TFT shown in;

[0028] Figure 13C Shows Figure 11 Steps of an example of the manufacturing method of the oxide semiconductor TFT shown in;

[0029] Figure 13D Shows Figure 11 Steps of an example of the manufacturing method of the oxide semiconductor TFT shown in;

[0030] Figure 13E Shows Figure 11 Steps of an example of the manufacturing method of the oxide semiconductor TFT shown in;

[0031] Figure 13F shows Figure 11 steps of an example of a method for manufacturing an oxide semiconductor TFT shown in

[0032] Figure 14 shows an Figure 11 oxide semiconductor TFT having the structure shown in applied to Figure 4 an example of a pixel circuit shown in; and

[0033] Figure 15 shows an Figure 11 oxide semiconductor TFT having the structure shown in applied to Figure 7 an example of a CMOS circuit shown in DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present invention will be described with reference to the drawings. It should be noted that the above embodiments are merely examples for implementing the present invention and do not limit the technical scope of the present invention. Common elements in the drawings are denoted by the same reference numerals, and some elements in the drawings are enlarged in size or shape for a clear understanding of the description.

[0035] Overview

[0036] The following description uses an organic light-emitting diode (OLED) display device as an example of a device including a thin-film transistor circuit. The OLED display device in the present invention includes low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs) and oxide semiconductor TFTs in pixel circuits and / or peripheral circuits. An example of the oxide semiconductor is indium gallium zinc oxide (IGZO).

[0037] The oxide semiconductor TFT generates a small leakage current. Therefore, for example, it can be used as a switching transistor connected to a storage capacitor (capacitive element) for maintaining the gate potential of a driving transistor in a pixel circuit. For example, a low-temperature polycrystalline silicon TFT having a high mobility can be used as a driving transistor. The configuration of the present invention can be applied to devices other than display devices.

[0038] In one embodiment, the oxide semiconductor TFT has a top-gate structure, and its gate insulator portion is made of a high-k insulator having a high relative dielectric constant. The relative dielectric constant of the high-k insulator in the following description is not less than 8. Using an insulator having a high relative dielectric constant for the gate insulator portion improves the on-current characteristics of the oxide semiconductor TFT, so that the device can have a smaller size or a lower driving voltage. The relative dielectric constant of one example of the high-k insulator is not greater than 100, and the relative dielectric constant of another example is not greater than 50.

[0039] In a thin film transistor circuit having a stacked structure, a gate electrode portion of an oxide semiconductor TFT is included in a conductor layer, and a gate insulator portion of the oxide semiconductor TFT is included in a high-k insulator layer. An oxide semiconductor portion of the oxide semiconductor TFT is included in an oxide semiconductor layer.

[0040] The gate electrode portion, the gate insulator portion, and the oxide semiconductor portion are part of the oxide semiconductor TFT, and each of them is all or part of a film of a specific material. A layer is made of the same material by the same process and may be composed of an unseparated film or multiple separated films. A film may have a single-layer structure or a multi-layer structure.

[0041] In one embodiment, the entire region of the above-mentioned high-k insulator layer in the thin film transistor circuit is covered by the region of the conductor layer including the gate electrode portion when observed in the stacking direction (in a top view). This configuration suppresses the generation of parasitic capacitance caused by the high-k insulator. In a pixel circuit of one embodiment, the high-k insulator layer includes a gate insulator portion of the oxide semiconductor TFT. In a pixel circuit of another embodiment, the high-k insulator layer further includes an insulator portion of a storage capacitor for maintaining the gate potential of the driving TFT. This configuration reduces the area of the storage capacitor.

[0042] In the previous pixel circuit of the above one embodiment, the conductor or semiconductor located below the insulator layer including the gate insulator portion and overlapping with the insulator layer is only the oxide semiconductor portion of the oxide semiconductor TFT. In the latter pixel circuit of the above another embodiment, the conductor or semiconductor located below the insulator layer including the gate insulator portion and overlapping with the insulator layer in the stacking direction is only the oxide semiconductor portion of the oxide semiconductor TFT and the lower electrode portion of the storage capacitor.

[0043] Embodiment 1

[0044] Configuration of the display device

[0045] Figure 1 Fig. schematically shows a configuration example of an OLED display device 1. The OLED display device 1 includes a thin film transistor (TFT) substrate 10 on which an organic light-emitting element (OLED element) and a pixel circuit are fabricated, a packaging substrate 20 for encapsulating the organic light-emitting element, and a bonding portion (glass powder sealant) 30 for bonding the TFT substrate 10 to the packaging substrate 20. The space between the TFT substrate 10 and the packaging substrate 20 is filled with dry nitrogen gas and sealed with the bonding portion 30. The packaging substrate 20 and the bonding portion 30 constitute a structural packaging unit. The structural packaging unit may be a thin film encapsulation (TFE) unit.

[0046] Around the periphery of the cathode electrode region 14 outside the display region 25 of the TFT substrate 10, a scan driver 31, an emission driver 32, a protection circuit 33, a driver IC 34, and a demultiplexer 36 are provided. The driver IC 34 is connected to an external device through a flexible printed circuit (FPC) 35. The scan driver 31, the emission driver 32, and the protection circuit 33 are peripheral circuits fabricated on the TFT substrate 10.

[0047] The scan driver 31 drives the scan lines on the TFT substrate 10. The emission driver 32 drives the emission control lines to control the light emission period of the pixels. The driver IC 34 is, for example, mounted with an anisotropic conductive film (ACF).

[0048] The protection circuit 33 protects the elements in the pixel circuit from the influence of electrostatic discharge. The driver IC 34 supplies power and timing signals (control signals) to the scan driver 31 and the emission driver 32, and also supplies power and data signals to the demultiplexer 36.

[0049] The demultiplexer 36 sequentially outputs the output of one pin of the driver IC 34 to d data lines (d is an integer greater than 1). The demultiplexer 36 switches the data line to which the data signal is output from the driver IC 34 d times during each scan period to drive d times the number of data lines as the number of output pins of the driver IC 34.

[0050] Configuration of the pixel circuit

[0051] A plurality of pixel circuits are fabricated on the TFT substrate 10 to control the current supplied to the anode electrode portion of the sub-pixels (also simply referred to as pixels). Figure 2 An example of the configuration of the pixel circuit is shown. Each pixel circuit includes a driving transistor T1, a selection transistor T2, an emission transistor T3, and a storage capacitor C1. The pixel circuit controls the light emission of the OLED element E1. The transistors are TFTs. All transistors except the driving transistor T1 are switching transistors.

[0052] The selection transistor T2 is a switch for selecting the sub-pixel. The selection transistor T2 is an n-channel oxide semiconductor TFT, and its gate terminal is connected to the scan line 16. The source terminal is connected to the data line 15. The drain terminal is connected to the gate terminal of the driving transistor T1.

[0053] The driving transistor T1 is a transistor (driving TFT) for driving the OLED element E1. The driving transistor T1 is a p-channel type low-temperature polycrystalline silicon TFT, and its gate terminal is connected to the drain terminal of the selection transistor T2. The source terminal of the driving transistor T1 is connected to the drain terminal of the emission transistor T3, and the drain terminal of the driving transistor T1 is connected to the OLED element E1. A storage capacitor C1 is provided between the gate terminal of the driving transistor T1 and the power supply line 18.

[0054] The emission transistor T3 is a switch for controlling the supply / stop of the driving current to the OLED element E1. The emission transistor T3 is a p-channel type low-temperature polycrystalline silicon TFT, and its gate is connected to the emission control line 17. The source terminal of the emission transistor T3 is connected to the power supply line 18, and the drain terminal of the emission transistor T3 is connected to the source terminal of the driving transistor T1.

[0055] Next, the operation of the pixel circuit is described. The scan driver 31 outputs a selection pulse to the scan line 16 to turn on the selection transistor T2. The data voltage supplied from the driver IC 34 through the data line 15 is stored in the storage capacitor C1. The storage capacitor C1 holds the stored voltage during one frame period. The conductance of the driving transistor T1 changes in an analog manner according to the stored voltage, so that the driving transistor T1 supplies a forward bias current corresponding to the light emission level to the OLED element E1.

[0056] The emission transistor T3 is located on the supply path of the driving current. The emission driver 32 outputs a control signal to the emission control line 17 to control the on / off of the emission transistor T3. When the emission transistor T3 is on, the driving current is supplied to the OLED element E1. When the emission transistor T3 is off, the supply is stopped. The lighting period (duty ratio) in one frame period can be controlled by controlling the on / off of the transistor T3. Figure 2 The circuit configuration in is just an example; the pixel circuit can have different configurations.

[0057] Configuration of the TFT Substrate

[0058] Hereinafter, an example of the configuration of a TFT substrate including low-temperature polycrystalline silicon TFTs and oxide semiconductor TFTs is described. The oxide semiconductor can be IGZO. The configuration described in this specification can be applied to circuits including TFTs with other types of oxide semiconductors.

[0059] Figure 3 The cross-sectional structure of a part of the TFT substrate is schematically shown. The low-temperature polycrystalline silicon TFT 141, the oxide semiconductor TFT 142, the storage capacitor 143, and the OLED element 144 are formed on the insulating substrate 101. These elements correspond to Figure 2The driving transistor T1, the selection transistor T2, the storage capacitor C1, and the OLED element E1 therein.

[0060] The insulating substrate 101 is a flexible or non-flexible substrate made of resin or glass. The low-temperature polycrystalline silicon TFT 141 includes a low-temperature polycrystalline silicon portion 102. The low-temperature polycrystalline silicon portion 102 may be an island-shaped low-temperature polycrystalline silicon active film and includes source / drain regions 104 and 105 and a channel region 103 sandwiched between the source / drain regions 104 and 105 in the in-plane direction.

[0061] The source / drain regions 104 and 105 are made of low-temperature polycrystalline silicon with reduced resistance caused by doping with high-concentration impurities; they are connected to the source / drain electrode portions 109 and 110. The channel region 103 is made of low-temperature polycrystalline silicon with unreduced resistance (high-resistance low-temperature polycrystalline silicon).

[0062] The low-temperature polycrystalline silicon portion 102 is included in a low-temperature polycrystalline silicon layer. The low-temperature polycrystalline silicon layer includes the low-temperature polycrystalline silicon portions of the low-temperature polycrystalline silicon TFTs in a plurality of pixel circuits. The low-temperature polycrystalline silicon layer is formed directly on the insulating substrate 101. Although Figure 3 in the example, the low-temperature polycrystalline silicon portion 102 is in contact with the insulating substrate 101, another insulator layer such as a silicon nitride layer may be provided therebetween.

[0063] The low-temperature polycrystalline silicon TFT 141 has a top-gate structure. In addition to the top gate, the low-temperature polycrystalline silicon TFT 141 may also have a bottom gate. This also applies to other embodiments. The low-temperature polycrystalline silicon TFT 141 further includes a gate electrode portion 107 and a gate insulator portion 106 located between the gate electrode portion 107 and the channel region 103 in the stacking direction. The gate insulator portion (first insulator portion) 106 is included in an insulator layer (first insulator layer) including the gate insulator portions of other low-temperature polycrystalline silicon TFTs. The channel region 103, the gate insulator portion 106, and the gate electrode portion 107 are arranged in this order from the bottom (the side closer to the insulating substrate 101); the gate insulator portion 106 is in contact with the channel region 103 and the gate electrode portion 107.

[0064] The gate electrode portion (first gate electrode portion) 107 is made of a conductor and is included in a conductor layer (first conductor layer). The gate electrode portion 107 may be made of metal. For example, the metal material may desirably be selected from Mo, W, Nb, and Al. In Figure 3 the configuration example, the metal film including the gate electrode portion 107 and the insulating film including the gate insulator portion 106 have an island shape; the entire region of the insulating film is covered by the metal film. In this example, the gate insulator portion 106 is made of silicon oxide and is included in a silicon oxide layer. This configuration provides high operating stability for the low-temperature polycrystalline silicon TFT 141.

[0065] The interlayer insulating film 108 is provided to cover the low-temperature polycrystalline silicon portion 102, the gate insulating portion 106, and the gate electrode portion 107. The interlayer insulating film 108 can be a silicon oxide film or a silicon nitride film. The source / drain electrode portions 109 and 110 are provided above the interlayer insulating film 108 and are connected to the source / drain regions 104 and 105 through contact holes in the interlayer insulating film 108. The materials of the source / drain electrode portions 109 and 110 can be, for example, Al or Ti.

[0066] The storage capacitor 143 includes a lower electrode portion 111, an upper electrode portion 120 opposite to the lower electrode portion 111, and an insulator portion 118 sandwiched between the lower electrode portion 111 and the upper electrode portion 120. The lower electrode portion 111 is located above the interlayer insulating film 108 and is continuous with the source / drain electrode portion 110. The lower electrode portion 111 is included in the same conductor layer as the source / drain electrode portions 109 and 110.

[0067] Another interlayer insulating film 112 is disposed above the interlayer insulating film 108. The interlayer insulating film 112 can be a silicon oxide film. The interlayer insulating film 112 is provided to cover the lower electrode portion 111, the source / drain electrode portions 109 and 110, and the interlayer insulating film 108. The interlayer insulating film 112 has an opening in a portion between the lower electrode portion 111 and the upper electrode portion 120. The insulator portion 118 is provided inside the opening and on the outer periphery of the opening.

[0068] The insulator portion 118 is made of a high-k insulator; it contacts the lower electrode portion 111 inside the opening, and the top surface of the insulator portion 118 contacts the upper electrode portion 120. The entire insulating portion of the storage capacitor 143 is composed of the high-k insulator portion 118 and a part of the interlayer insulating film 112. The high-k insulator can be an insulating metal compound, such as a metal oxide or a metal nitride. Specifically, TaOx, AlOx, HfOx, ZrOx, YOx, or NbOx can be adopted. The configuration in which at least a part of the insulator portion 118 is located in the opening increases the average relative dielectric constant of the storage capacitor 143, thereby obtaining a higher electrostatic capacitance.

[0069] The oxide semiconductor TFT 142 includes an oxide semiconductor portion 113. The oxide semiconductor portion 113 can be an island-shaped oxide semiconductor active film and includes source / drain regions 115 and 116 and a channel region 114 sandwiched between the source / drain regions 115 and 116 in the in-plane direction.

[0070] The source / drain regions 115 and 116 are made of resistance-reduced IGZO; they are connected to the source / drain electrode portions 122 and 123. The channel region 114 is made of non-resistance-reduced IGZO (high-resistance IGZO).

[0071] The oxide semiconductor part 113 is included in the oxide semiconductor layer. The oxide semiconductor layer includes the oxide semiconductor parts of a plurality of oxide semiconductor TFTs. The oxide semiconductor layer is provided above the interlayer insulating film 112.

[0072] The oxide semiconductor TFT 142 has a top-gate structure. In addition to the top gate, the oxide semiconductor TFT 142 may also have a bottom gate. This also applies to other embodiments. The oxide semiconductor TFT 142 further includes a gate electrode part 119 and a gate insulator part 117 located between the gate electrode part 119 and the channel region 114 in the stacking direction. The channel region 114, the gate insulator part 117, and the gate electrode part 119 are arranged in this order from the bottom (the side closer to the insulator substrate 101); the gate insulator part 117 is in contact with the channel region 114 and the gate electrode part 119.

[0073] The gate electrode part (second gate electrode part) 119 is made of a conductor and is included in the conductor layer (second conductor layer). The gate electrode part 119 may be made of a metal. For example, the metal material may desirably be selected from Mo, W, Nb, and Al.

[0074] The gate insulator part (second insulator part) 117 is included in the high-k insulator layer (second insulator layer) made of a high-k insulator. The high-k insulator layer includes the insulator part 118 of the storage capacitor 143. The high-k insulator layer includes the insulator parts of the oxide semiconductor TFTs of a plurality of pixel circuits and the storage capacitors. In Figure 3 the configuration example shown, the metal film including the gate electrode part 119 and the insulating film including the gate insulator part 117 have an island shape; the entire region of the insulating film is covered by the metal film. Although Figure 3 one low-temperature polysilicon TFT and one oxide semiconductor TFT are shown, the other low-temperature polysilicon TFTs and oxide semiconductor TFTs in the pixel circuit have the same structure specifically.

[0075] The interlayer insulating film 121 is provided to cover the oxide semiconductor part 113, the gate insulator part 117, and the gate electrode part 119 of the oxide semiconductor TFT 142, and the insulator part 118 and the upper electrode part 120 of the storage capacitor 143. The interlayer insulating film 121 covers a part of the interlayer insulating film 112. The interlayer insulating film 121 may be a silicon oxide film.

[0076] The source / drain electrode parts 122 and 123 of the oxide semiconductor TFT 142 are provided above the interlayer insulating film 121. The source / drain electrode parts 122 and 123 are connected to the source / drain regions 115 and 116 of the oxide semiconductor TFT 142 through contact holes in the interlayer insulating film 121.

[0077] The connecting portion 129 continuous with the source / drain electrode portion 123 is connected to the upper electrode portion 120 of the storage capacitor 143 through a contact hole penetrating an opening in the interlayer insulating film 121 and is further connected to the gate electrode portion 107 of the low-temperature polysilicon TFT 141 through a contact hole penetrating openings in the interlayer insulating films 121, 112, and 108. The connecting portion 129 interconnects the source / drain electrode portion 123, the upper electrode portion 120, and the gate electrode portion 107. The source / drain electrode portions 122 and 123 and the connecting portion 129 are included in the conductor layer. The material of the conductor layer is selected according to requirements; for example, Al or Ti can be used.

[0078] The insulating planarization film 124 is disposed to cover the exposed portion of the above-mentioned conductor layer and the interlayer insulating film 121. The planarization film 124 can be made of an organic material. The anode electrode portion 125 is provided above the planarization film 124. The anode electrode portion 125 is connected to the source / drain electrode portion 109 of the low-temperature polysilicon TFT 141 through a contact hole penetrating openings in the planarization film 124 and the interlayer insulating films 121 and 112.

[0079] The anode electrode portion 125 can include three layers, namely, a transparent film of ITO or IZO, a reflective film of a metal such as Ag, Mg, Al, or Pt or an alloy containing such a metal, and another transparent film as described above, for example. This three-layer structure of the anode electrode portion 125 is only an example; the anode electrode portion 125 can have a two-layer structure.

[0080] Above the anode electrode portion 125, an insulating pixel defining layer 126 is provided to isolate the OLED element 144. The pixel defining layer 126 can be made of an organic material. The organic light-emitting film 127 is provided above the anode electrode portion 125. The organic light-emitting film 127 is composed of, for example, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer in this order from the bottom. The stacked structure of the organic light-emitting film 127 is determined according to the design.

[0081] Furthermore, a cathode electrode portion 128 is provided above the organic light-emitting film 127. The cathode electrode portion 128 of one OLED element 144 is part of an unseparated conductor film. The cathode electrode portion 128 transmits a part of the visible light from the organic light-emitting film 127. The stack of the anode electrode portion 125, the organic light-emitting film 127, and the cathode electrode portion 128 disposed in the opening of the pixel defining layer 126 corresponds to the OLED element 144.

[0082] Figure 4 The cross-sectional structure of another part of the TFT substrate is schematically shown. Figure 4 Not included Figure 3The OLED element 144 included therein, but includes a scan line 130 for transmitting a selection signal for selecting a sub-pixel to which a data signal is to be supplied. The scan line 130 is disposed above the planarization film 124 and is connected to the gate electrode portion 119 of the oxide semiconductor TFT 142 through a contact hole passing through the planarization film 124 and the opening of the interlayer insulating film 121.

[0083] Figure 4 Reference numerals of layers including conductive elements are provided. In the following examples, the conductor layer is a metal layer. Specifically, the gate electrode portion 107 of the low-temperature polycrystalline silicon TFT 141 is included in the metal layer M1. The lower electrode portion 111 of the storage capacitor 143 and the source / drain electrode portions 109 and 110 of the low-temperature polycrystalline silicon TFT 141 are included in the metal layer M2.

[0084] The gate electrode portion 119 of the oxide semiconductor TFT 142 and the upper electrode portion 120 of the storage capacitor 143 are included in the metal layer M3. The source / drain electrode portions 122 and 123 of the oxide semiconductor TFT 142 and the connection portion 129 are included in the metal layer M4. The scan line 130 is included in the metal layer M5. As described above, the gate insulator portion of the oxide semiconductor TFT 142 and the insulator portion of the storage capacitor 143 are included in the same high-k insulator layer.

[0085] Figure 5 It is a top view of a part of the TFT substrate. The metal film 151 included in the lowermost metal layer M1 includes the gate electrode portion 107 of the low-temperature polycrystalline silicon TFT 141. The gate electrode portion 107 may be an overlapping portion of the metal film 151 and the low-temperature polycrystalline silicon portion 102 when viewed in plan (in the stacking direction).

[0086] The metal layer M2 above the metal layer M1 includes metal films 152 and 153. The metal film 152 includes the source / drain electrode portion 109 of the low-temperature polycrystalline silicon TFT 141. The metal film 153 includes the source / drain electrode portion 110 of the low-temperature polycrystalline silicon TFT 141 and the lower electrode portion 111 of the storage capacitor 143. The lower electrode portion 111 may be an overlapping portion of the metal film 153 and the upper electrode portion 120 of the storage capacitor 143 when viewed in plan.

[0087] The metal layer M3 above the metal layer M2 includes a metal film 154 and a metal film corresponding to the upper electrode portion 120 of the storage capacitor 143. The metal film 154 includes the gate electrode portion 119 of the oxide semiconductor TFT 142 and a connecting portion connecting the scan line 130 and the gate electrode portion 119. The gate electrode portion 119 may be an overlapping portion of the metal film 154 and the oxide semiconductor portion 113 when viewed in plan (in the stacking direction). The upper electrode portion 120 is composed of one metal film. The upper electrode portion 120 is smaller than the metal film 153, and the outer periphery of the upper electrode portion 120 is located inside the outer periphery of the metal film 153; the entire upper electrode portion 120 is located within the area of the metal film 153.

[0088] A high-k insulator film including a gate insulator portion 117 is provided directly below the metal film 154. The entire area of this insulator film is covered by the metal film 154. In one example, the outer periphery of this insulator film coincides with the outer periphery of the metal film 154. In addition, an insulator portion 118 of the storage capacitor 143 of the high-k insulator film is provided directly below the upper electrode portion 120 of the storage capacitor 143. The entire area of this insulator portion (insulator film) 118 is covered by the upper electrode portion 120. In one example, the outer periphery of this insulator portion 118 coincides with the outer periphery of the upper electrode portion 120.

[0089] As described above, the gate insulator portion 117 and the insulator portion 118 are included in the same high-k insulator layer. Insulator films including gate insulator portions of other oxide semiconductor TFTs in the pixel circuit are all covered by the metal film including the gate electrode portion in the same manner. Gate insulator portions of all oxide semiconductor TFTs in the pixel circuit are included in the same high-k insulator layer. The entire area of the high-k insulator layer including these insulator portions is covered by the metal layer M3 in the pixel circuit. This configuration suppresses an increase in parasitic capacitance caused by the high-k insulator.

[0090] The metal layer M4 above the metal layer M3 includes a metal film 155. The metal film 155 includes a source / drain electrode portion 123 of the oxide semiconductor TFT 142 and a connecting portion 129 connecting the source / drain electrode portion 123, the upper electrode portion 120, and the gate electrode portion 107 of the low-temperature polycrystalline silicon TFT 141 to each other.

[0091] The metal layer M5 above the metal layer M4 includes the scan line 130. Since the scan line 130 connected to the gate electrode portion 119 of the oxide semiconductor TFT 142 is provided on a metal layer different from the layer of the gate electrode portion 119, a high-k insulator is not provided below the scan line 130, thereby suppressing parasitic capacitance.

[0092] In an example of the pixel circuit, the conductor located below the high-k insulator layer and overlapping the high-k insulator layer in a plan view is only the lower electrode portion 111 of the storage capacitor 143. Further, the semiconductor overlapping the high-k insulator layer is only the oxide semiconductor portion of all the oxide semiconductor TFTs in the pixel circuit. This configuration effectively suppresses the generation of parasitic capacitance caused by the high-k insulator. The entire insulator portion of the storage capacitor 143 may be made of an insulator different from the high-k insulator (e.g., silicon oxide or silicon nitride).

[0093] Next, the configuration of the CMOS circuit included in the drive circuit 31 or 32 on the TFT substrate will be described. Figure 6 An example of the CMOS circuit is shown. The CMOS circuit includes a p-channel low-temperature polycrystalline silicon TFT 201 and an n-channel oxide semiconductor TFT 202. The source / drain of the low-temperature polycrystalline silicon TFT 201 is connected to the source / drain of the n-channel oxide semiconductor TFT 202. The gate of the low-temperature polycrystalline silicon TFT 201 and the gate of the oxide semiconductor TFT 202 are connected and the same signal is provided to them.

[0094] Figure 7 is schematically shown Figure 6 an example of the cross-sectional structure of the Figure 3 shown CMOS circuit. The differences from Figure 7 the example of the cross-sectional structure shown will be mainly described. In Figure 3 the configuration example, the storage capacitor 143 in

[0095] Figure 7 the configuration example of Figure 3 is removed. Further, the source / source electrode portion 210 of the low-temperature polycrystalline silicon TFT 201 and the source / drain electrode portion 223 of the oxide semiconductor TFT 202 are connected, and further, the gate electrode portion 207 and the gate electrode portion 219 are connected.

[0096] The low-temperature polycrystalline silicon portion 208, the gate insulator portion 206, the gate electrode portion 207, and the source / drain electrode portions 209, 210 respectively correspond to Figure 3The low-temperature polysilicon portion 102, gate insulator portion 106, gate electrode portion 107, and source / drain electrode portions 109, 110 therein. Each element is included in the same layer as the corresponding element.

[0097] Figure 7 The oxide semiconductor TFT 202 therein may have the same configuration as Figure 3 the oxide semiconductor TFT 142 therein. Their sizes may be different. The oxide semiconductor TFT 202 includes an oxide semiconductor portion 213, a gate insulator portion 217, and a gate electrode portion 219. The oxide semiconductor portion 213 includes a channel region 214 and source / drain regions 215, 216. The oxide semiconductor portion 213, gate insulator portion 217, and gate electrode portion 219 respectively correspond to Figure 3 the oxide semiconductor portion 113, gate insulator portion 117, and gate electrode portion 119 therein. Each element is included in the same layer as the corresponding element.

[0098] The connection portion 229 is continuous from the source / drain electrode portion 223 of the oxide semiconductor TFT 202 and is connected to the source / drain electrode portion 210 of the low-temperature polysilicon TFT 201 through a contact hole that opens through the interlayer insulating films 112 and 121. The connection portion 230 is connected to the gate electrode portion 219 of the oxide semiconductor TFT 202 through a contact hole that opens through the interlayer insulating film 121 and the planarization film 124. The connection portion 230 is also connected to the gate electrode portion 207 of the low-temperature polysilicon TFT 201 through a contact hole that opens through the interlayer insulating films 108, 112, and 121 and the planarization film 124. The connection portion 230 is included in the metal layer M5.

[0099] Similar to the configuration described in the reference Figure 3 the gate insulator portion 217 of the oxide semiconductor TFT 202 is included in a high-k insulator layer. In the drive circuits 31 and 32, the entire region of the insulator film including the gate insulator portion of each oxide semiconductor TFT is covered by the metal film including the gate electrode portion of the oxide semiconductor TFT.

[0100] The gate insulator portions of all the oxide semiconductor TFTs in the drive circuits 31 and 32 are included in the same high-k insulator layer. In the drive circuit, the entire region of the high-k insulator layer including these insulator portions is covered by the metal layer including the gate electrode portion 219 of the oxide semiconductor TFT 202. This configuration of the insulator layer suppresses the increase in parasitic capacitance caused by the high-k insulator. In one example, the outer periphery of each high-k insulator film coincides with the outer periphery of the metal film covering it.

[0101] In driving circuits 31 and 32, when viewed in plan, the conductor and semiconductor located below the high-k insulator layer and overlapping with the high-k insulator layer are only the oxide semiconductor part of one or more oxide semiconductor TFTs in the driving circuit, or the oxide semiconductor part of one or more oxide semiconductor TFTs and the lower electrode part of one or more capacitors in the driving circuit. This configuration effectively suppresses the generation of parasitic capacitance caused by the high-k insulator.

[0102] Manufacturing method

[0103] Refer to Figures 8A to 8F Description Figure 3 The manufacturing method of the structure shown in. As Figure 8A Shown, this manufacturing fabricates a low-temperature polycrystalline silicon TFT 141. This manufacturing first forms a low-temperature polycrystalline silicon part 102 on an insulating substrate 101. Specifically, this manufacturing deposits amorphous silicon by CVD (chemical vapor deposition) and crystallizes the amorphous silicon by excimer laser annealing to form a low-temperature polycrystalline silicon film. This manufacturing patterns the low-temperature polycrystalline silicon film by photolithography to form an island-shaped polycrystalline silicon part 102.

[0104] Next, this manufacturing forms an insulator layer (such as a SiOx film) including a gate insulator part 106 by CVD, for example. In addition, this manufacturing forms a metal layer M1 by sputtering (see Figure 4 ) and patterns (etches) the metal layer M1 and the insulator layer together (by the same process using the same mask) to form a gate electrode part 107 and a gate insulator part 106. As a result of this process, the insulator remains only below the metal layer M1. Another example of the manufacturing first etches the metal layer including the gate electrode part 107, and then etches the insulator layer below it using the metal layer M1 as a mask.

[0105] Further, this manufacturing injects impurities into the low-temperature polycrystalline silicon part 102 using the gate electrode part 107 as a mask to generate low-resistance regions 104 and 105. The high-resistance region covered by the gate electrode part 107 corresponds to the channel region 103.

[0106] Next, this manufacturing forms an interlayer insulating film 108 by CVD, and further opens contact holes in the stacked insulating film by anisotropic etching. Further, this manufacturing forms a metal layer M2 by sputtering (see Figure 4 ) and patterns the metal layer M2 by photolithography to form source / drain electrode parts 109 and 110 and the lower electrode part 111 of a storage capacitor 143 (see Figure 4 ).

[0107] Next, refer to Figure 8B, the fabrication forms an interlayer insulating film 112 on the interlayer insulating film 108 and the source / drain electrode portions 109 and 110 by CVD. Next, the fabrication forms an oxide semiconductor layer by sputtering and patterns the oxide semiconductor layer by photolithography. As a result, an island-shaped oxide semiconductor portion 113 of the oxide semiconductor TFT 142 is formed (see Figure 4 ).

[0108] Next, referring to Figure 8C , the fabrication removes a part of the interlayer insulating film 112 by etching to expose a part of the lower electrode portion 111 of the storage capacitor 143 from the opening of the interlayer insulating film 112 (see Figure 4 ).

[0109] Next, referring to Figure 8D , the fabrication forms a high-k insulator film by sputtering. The fabrication further forms a metal layer M3 by sputtering (see Figure 4 ). The fabrication patterns (etches) the metal layer M3 and the high-k insulator film together (by the same process using the same mask) to form a gate electrode portion 119 of the oxide semiconductor TFT 142, an upper electrode portion 120 of the storage capacitor 143, a gate insulator portion 117 of the oxide semiconductor TFT 142, and an insulator portion 118 of the storage capacitor 143.

[0110] As a result of this process, the high-k insulator remains only under the metal layer M3 and the entire remaining region of the high-k insulator layer is covered by the metal layer M3. Another example of the fabrication patterns the metal layer M3 to form the gate electrode portion 119 and the upper electrode portion 120, and then patterns the high-k insulator layer using the metal layer (metal pattern) M3 as a mask. The insulator portion 118 of the storage capacitor 143 is also provided in the opening in the interlayer insulating film 112. This configuration increases the average relative dielectric constant of the storage capacitor 143, thereby providing a higher electrostatic capacitance for the storage capacitor 143.

[0111] Next, referring to Figure 8E , the fabrication uses the gate electrode portion 119 as a mask to reduce the resistance of the end regions 115 and 116 of the oxide semiconductor portion 113. By exposing the oxide semiconductor portion 113 in the region not covered by the gate electrode portion 119 to He plasma, the resistance can be reduced. The region 114 covered by the gate electrode portion 119 corresponds to a high-resistance channel region. The resistance reduction can be performed in the next step of forming the interlayer insulating film 121.

[0112] Next, referring to Figure 8F, the manufacturing forms the interlayer insulating film 121 by CVD, and performs anisotropic etching on the interlayer insulating film 121 by photolithography to open contact holes. Further, the manufacturing forms the metal layer M4 (see Figure 4 ) by sputtering and patterns the metal layer M4 by photolithography. As a result, the source / drain electrode portions 122 and 123 and the connection portion 129 of the oxide semiconductor TFT 142 are formed.

[0113] Although not shown in the figure, the manufacturing further forms the planarization film 124 and the metal layer M5, and then forms the anode electrode portion 125. In addition, the manufacturing forms the pixel defining layer 126, and then forms the organic light-emitting film on the anode electrode portion 125. The organic light-emitting film is formed by vapor deposition of an organic light-emitting material at positions corresponding to the pixels through a metal mask. The manufacturing further deposits a metal material for the cathode electrode portion 128.

[0114] Embodiment 2

[0115] An example of a circuit including an oxide semiconductor TFT having a structure different from that in Embodiment 1 is described below. Figure 9 The cross-sectional structure of a part of the pixel circuit is schematically shown. The differences from the Figure 3 configuration shown are mainly described below.

[0116] The gate insulator portion of the oxide semiconductor TFT 142 is composed of a plurality of stacked insulator portions. Specifically, it is composed of a high-k insulator portion 136 and an interface insulator portion 135. The interface insulator portion 135 has an interface with the high-k insulator portion 136 and the oxide semiconductor portion 113.

[0117] In one example, the interface insulator portion 135 is included in a silicon-based insulator layer including the interface insulator portions of other oxide semiconductor TFTs. Examples of the silicon-based insulator layer are made of silicon oxide (SiOx). Another example is made of silicon nitride. Interposing the silicon-based insulator between the high-k insulator and the oxide semiconductor stabilizes the characteristics of the oxide semiconductor TFT 142.

[0118] The relative dielectric constant of silicon oxide is lower than that of the high-k insulator. The interface insulator portion 135 can be thinner than the high-k insulator portion 136. This configuration prevents the overall relative dielectric constant of the gate insulator portion from becoming low.

[0119] In another example, the interface insulator portion 135 is made of a high-k insulator containing a carbon element (carbon-containing high-k insulator), and the high-k insulator portion 136 is made of a high-k insulator substantially free of a carbon element (carbon-free high-k insulator). The interface insulator portion 135 is included in the carbon-containing high-k insulator layer of the interface insulator portion including other oxide semiconductor TFTs. The high-k insulator portion 136 is included in the carbon-free high-k insulator layer of the high-k insulator portion including other oxide semiconductor TFTs. Interposing the carbon-containing high-k insulator between the carbon-free high-k insulator and the oxide semiconductor stabilizes the characteristics of the oxide semiconductor TFT 142.

[0120] The interface insulator portion 135 made of the carbon-containing high-k insulator can be thinner than the high-k insulator portion 136 made of the carbon-free high-k insulator. The carbon-free high-k insulator can be formed by general sputtering. On the other hand, the carbon-containing high-k insulator is formed by atomic layer deposition (ALD), which is a CVD using a metal organic as a precursor. The film formation time of the carbon-containing high-k insulator is longer than that of the carbon-free high-k insulator. Therefore, the above film thickness relationship enables a shorter process time.

[0121] At the same time, when the carbon concentration in the carbon-containing high-k insulator is not less than 1×10 18 cm -3 and the carbon concentration in the carbon-free high-k insulator is less than 1×10 18 cm -3 the characteristics of the oxide semiconductor TFT 142 are more stable.

[0122] In the Figure 9 configuration example, the insulator portion of the storage capacitor 143 is generally composed of the interface insulator portion 137, the high-k insulator portion 138, and a part of the interlayer insulating film 112. The interface insulator portion 137 is included in the same layer as the interface insulator portion 135. The high-k insulator portion 138 is included in the same layer as the high-k insulator portion 136.

[0123] The metal layer M3, the insulator layer including the interface insulator portions 135 and 137, and the insulator layer including the high-k insulator portions 136 and 138 have the same planar shape. The laminated structure thereof can be formed by etching the two insulator layers together with the metal layer M3 (by the same process using the same mask) or by etching the two insulator layers using the metal layer M3 as a mask. The interface insulator portion 137 is optional.

[0124] Figure 10 The cross-sectional structure of the CMOS circuit is schematically shown. The main description is related to Figure 7Differences from the configuration example shown. The gate insulator portion of the oxide semiconductor TFT 202 is composed of a high-k insulator portion 236 and an interface insulator portion 235. The high-k insulator portion 236 may be included in the same layer as the high-k insulator portions 136 and 138. The interface insulator portion 235 may be included in the same layer as the interface insulator portions 135 and 137.

[0125] The interface insulator portion 235 has interfaces with the high-k insulator portion 236 and the oxide semiconductor portion 213. In one example, the interface insulator portion 235 may be made of silicon oxide (SiOx). Interposing silicon oxide between the high-k insulator and the oxide semiconductor stabilizes the characteristics of the oxide semiconductor TFT 202.

[0126] The interface insulator portion 235 may be thinner than the high-k insulator portion 236. This configuration prevents the overall relative dielectric constant of the gate insulator portion from becoming low.

[0127] In another example, the interface insulator portion 235 is made of a carbon-containing high-k insulator, and the high-k insulator portion 236 is made of a carbon-free high-k insulator. This configuration stabilizes the characteristics of the oxide semiconductor TFT 202. The interface insulator portion 235 made of a carbon-containing high-k insulator may be thinner than the high-k insulator portion 236 made of a carbon-free high-k insulator. This film thickness relationship enables a shorter process time.

[0128] Embodiment 3

[0129] Another configuration example of an oxide semiconductor TFT is described below. The oxide semiconductor TFT described below includes a compound layer of a high-k insulator and an oxide semiconductor as an interface layer between the source / drain regions of the oxide semiconductor portion and the source / drain electrode portion. The interface layer has interfaces with each source / drain region and each source / drain electrode portion. The interface layer provides good contact characteristics between the source / drain regions and the source / drain electrode portion. What is described below is an oxide semiconductor TFT having a top-gate structure, but the interface layer can be applied to an oxide semiconductor TFT having a bottom-gate structure.

[0130] Figure 11 is a cross-sectional view of this configuration example of the oxide semiconductor TFT. The oxide semiconductor TFT is formed on an insulating substrate 301. An example of the oxide semiconductor is IGZO. The oxide semiconductor TFT includes an oxide semiconductor portion 311. The oxide semiconductor portion 311 may be an island-shaped oxide semiconductor active film and includes source / drain regions 315 and 316 and a channel region 314 between the source / drain regions 315 and 316 in the in-plane direction.

[0131] The source / drain regions 315 and 316 are made of a reduced-resistance oxide semiconductor. The channel region 314 is made of an oxide semiconductor with unchanged resistance. A mixture interface portion 317 made of a mixture of an oxide semiconductor and a high-k insulator is provided above the channel region 314. The high-k insulator can be the high dielectric material mentioned in Embodiment 1 or a ferroelectric material (such as PZT) having a remanent polarization intensity. The mixture interface portion 317 has an interface with the gate insulator portion 321 made of a high-k insulator and the channel region 314.

[0132] Above the source / drain regions 315 and 316, compound interface portions 318 and 319 made of a compound of an oxide semiconductor and a high-k insulator are provided. The source / drain regions 315 and 316 are connected to the source / drain electrode portions 322 and 323 through the compound interface portions 318 and 319. The compound interface portion 318 has an interface with the source / drain electrode portion 323 and the source / drain region 315, and the compound interface portion 319 has an interface with the source / drain electrode portion 322 and the source / drain region 316.

[0133] In the example of using InGaZnO x as the oxide semiconductor and using AlO y as an example of the high-k insulator, the mixture interface portion 317 can be expressed as (IGZO x +AlO y ). The compound interface portions 318 and 319 can be expressed as (IGZO x-1 AlO y+1 ). As noted from this example, in the compound interface portions 318 and 319, the oxygen deficiency in the oxide semiconductor increases. As a result, the resistance of the compound interface portions 318 and 319 becomes lower than the resistance of the source / drain regions 315 and 316, thereby obtaining better contact characteristics and on-current characteristics.

[0134] The compound interface portions 318 and 319 can be composed not only of the above-mentioned elemental oxide semiconductor and high-k insulator (for example, In-Ga-Zn-Al-O), but also of elements contained in the process gas in the manufacturing step. For example, as described below, when the film is exposed to fluorine-containing plasma, the compound interface portions 318 and 319 can be composed of In-Ga-Zn-Al-F-O. As described above, the high-k insulator can include Ta or Hf elements in addition to Al.

[0135] The gate electrode portion 320 is disposed above the gate insulator portion 321. The gate electrode portion 320 is made of a conductor; for example, a metal such as Mo, W, Nb, or Al can be used. Similar to the configuration in the foregoing other embodiments, the entire region of the insulator layer including the gate insulator portion 321 is covered by the metal layer of the gate electrode portion 320 in the oxide semiconductor TFT.

[0136] The interlayer insulating film 324 is provided to cover the above-described elements of the oxide semiconductor portion. The interlayer insulating film 324 can be a silicon oxide film. The source / drain electrode portions 322 and 323 of the oxide semiconductor TFT are provided above the interlayer insulating film 324. The source / drain electrode portions 322 and 323 are connected to the source / drain regions 315 and 316 through contact holes in the interlayer insulating film 324 and the compound interface portions 318 and 319.

[0137] Figure 12 is a cross-sectional view of another configuration example of the oxide semiconductor TFT. The differences from the configuration example in Figure 11 are mainly described. In the oxide semiconductor TFT in Figure 12 , the high-k insulator portion located between the gate electrode portion 320 and the oxide semiconductor portion 311 is included in the high-k insulator film 325 that extends outside the gate electrode portion 320. The high-k insulator film 325 covers the oxide semiconductor portion 311. Different from the configurations in Embodiments 1 and 2, the compound interface portions 318 and 319 can be applied to the circuit where the high-k insulator extends from the region under the gate electrode portion to the outside of the gate electrode portion.

[0138] These compound interface portions are generated when the surface of the oxide semiconductor portion 311 is exposed to a fluorine-containing plasma before depositing the high-k insulator film 325. In the film formation of the high-k insulator film 325, the resistance of the compound interface portion is further reduced by the kinetic energy and thermal energy of particles (plasma particles and radical particles). In Figure 11 and Figure 12 In the shown configuration, the gate insulator portion 321 can have a stacked structure of a lower high-k insulator and an upper low-k insulator having a relative dielectric constant lower than 8.

[0139] Next, with reference to Figures 13A to 13F an example of the manufacturing method of the oxide semiconductor TFT shown in Figure 11 will be described. With reference to Figure 13A , an oxide semiconductor layer is formed on the insulating substrate 301 by sputtering and the oxide semiconductor layer is patterned by photolithography. As a result, an island-shaped oxide semiconductor film 351 is formed.

[0140] Next, with reference to Figure 13B, the fabrication forms the high-k insulator film 352 by sputtering. As a result, a mixture portion 354 of the high-k insulator and the oxide semiconductor is generated in the oxide semiconductor film 351. The layer below the mixture portion 354 is the oxide semiconductor portion 311 composed only of the oxide semiconductor. Further, the fabrication forms the metal film 353 by sputtering.

[0141] Next, referring to Figure 13C , the fabrication etches the metal film 353 and the high-k insulator film 352 together (by the same process using the same mask) by photolithography to form the gate electrode portion 320 and the gate insulator portion 321. In another example, the fabrication etches the metal film 353 and then uses the gate electrode portion 320 as a mask to etch the high-k insulator film 352 to form the gate insulator film 321.

[0142] Next, referring to Figure 13D , the fabrication exposes the mixture portion 354 and the oxide semiconductor portion 311 to a fluorine plasma in a region not covered by the gate electrode portion 320 that is not used as a mask. As a result of this process, compound interface portions 318 and 319 and source / drain regions 315 and 316 are generated. The compound interface portions 318 and 319 may contain a fluorine element in addition to the elements constituting the oxide semiconductor and the high-k insulator. The region between the compound interface portions 318 and 319 corresponds to the mixture interface portion 317, and the region between the source / drain regions 315 and 316 corresponds to the high-resistance channel region 314. This process using the fluorine plasma can be achieved by exposing the mixture portion 354 and the oxide semiconductor portion 311 to the plasma of a gas such as CF4 after performing etching as shown in Figure 13C .

[0143] Next, referring to Figure 13E , the fabrication forms the interlayer insulating film 324 by CVD. Next, referring to Figure 13F , the fabrication anisotropically etches the interlayer insulating film 324 by photolithography to form contact holes in the interlayer insulating film 324. Further, the fabrication forms a metal film by sputtering and patterns the metal film by photolithography. As a result, the source / drain electrode portions 322 and 323 of the oxide semiconductor TFT are formed.

[0144] Figure 14 and Figure 15 show examples of applying the oxide semiconductor TFT having the structure described with reference to Figure 11 to the pixel circuit shown in Figure 4 and the CMOS circuit shown in Figure 7 . In the pixel circuit of Figure 14 , the oxide semiconductor TFT 142 includes compound interface portions 401 and 402. In Figure 15In the CMOS circuit, the oxide semiconductor TFT 202 includes compound interface portions 405 and 406. These circuits exhibit the effects described in Embodiment 1 and Embodiment 3. As noted from these examples, the oxide semiconductor TFT in the present embodiment can be applied to various circuits.

[0145] The compound interface portion described in Embodiment 3 and the interface insulator portion described in Embodiment 2 can be applied to one oxide semiconductor TFT. This configuration provides the oxide semiconductor TFT with higher operation stability and better on-current characteristics.

[0146] As described above, embodiments of the present invention have been described; however, the present invention is not limited to the above embodiments. Those skilled in the art can easily modify, add, or convert each element in the above embodiments within the scope of the present invention. A part of the configuration of one embodiment can be replaced with the configuration of another embodiment, or the configuration of one embodiment can be incorporated into the configuration of another embodiment.

Claims

1. A thin film transistor circuit, comprising: A polysilicon layer; A first conductor layer located above the polysilicon layer; A first insulator layer located between the first conductor layer and the polysilicon layer; An oxide semiconductor layer; A second conductor layer located above the oxide semiconductor layer; And A second insulator layer located between the second conductor layer and the oxide semiconductor layer, Wherein, the polysilicon layer includes a polysilicon portion of a polysilicon thin film transistor, Wherein, the first conductor layer includes a first gate electrode portion of the polysilicon thin film transistor, Wherein, the first insulator layer includes a first insulator portion located between the first gate electrode portion and the polysilicon portion, Wherein, the oxide semiconductor layer includes an oxide semiconductor portion of an oxide semiconductor thin film transistor, Wherein, the second conductor layer includes a second gate electrode portion of the oxide semiconductor thin film transistor, Wherein, the second insulator layer includes a second insulator portion located between the second gate electrode portion and the oxide semiconductor portion, Wherein, the second insulator layer has a relative dielectric constant of not less than 8, Wherein, the entire region of the second insulator layer is covered by the second conductor layer, Wherein, the relative dielectric constant of the first insulator layer is lower than that of the second insulator layer, Wherein, the second conductor layer includes an upper electrode portion of a capacitive element, Wherein, the upper electrode portion of the capacitive element is connected to the first gate electrode portion, and Wherein, the second insulator layer includes an insulator portion of the capacitive element.

2. The thin film transistor circuit according to claim 1, Among them, The oxide semiconductor portion includes a channel region and source / drain regions sandwiching the channel region, and Wherein, one of the source / drain regions is connected to the first gate electrode portion.

3. The thin film transistor circuit according to claim 1, Among them, The oxide semiconductor portion includes a channel region and source / drain regions sandwiching the channel region, Wherein, the polysilicon portion includes a channel region and source / drain regions sandwiching the channel region, and Wherein, one of the source / drain regions of the oxide semiconductor portion is connected to one of the source / drain regions of the polysilicon portion.

4. The thin film transistor circuit according to claim 1, further comprising a silicon-based insulator portion having an interface with the oxide semiconductor portion and another interface with the second insulator portion.

5. A thin film transistor circuit, comprising: A polysilicon layer; A first conductor layer located above the polysilicon layer; A first insulator layer located between the first conductor layer and the polysilicon layer; An oxide semiconductor layer; A second conductor layer located above the oxide semiconductor layer; And A second insulator layer located between the second conductor layer and the oxide semiconductor layer, Wherein, the polysilicon layer includes a polysilicon portion of a polysilicon thin film transistor, Wherein, the first conductor layer includes a first gate electrode portion of the polysilicon thin film transistor, Wherein, the first insulator layer includes a first insulator portion located between the first gate electrode portion and the polysilicon portion, Among them, the oxide semiconductor layer includes the oxide semiconductor portion of an oxide semiconductor thin film transistor. Among them, the second conductor layer includes the second gate electrode portion of the oxide semiconductor thin film transistor. Among them, the second insulator layer includes a second insulator portion located between the second gate electrode portion and the oxide semiconductor portion. Among them, the second insulator layer has a relative dielectric constant of not less than 8. Among them, the entire region of the second insulator layer is covered by the second conductor layer. Among them, the thin film transistor circuit further includes an interface insulator portion having an interface with the oxide semiconductor portion and another interface with the second insulator portion. Among them, the relative dielectric constant of the interface insulator portion is not less than 8, and Among them, the carbon concentration in the interface insulator part is not less than 1×10 18 cm -3 , and the carbon concentration in the second insulator part is less than 1×10 18 cm -3 .

6. A thin film transistor circuit, comprising: A polysilicon layer; A first conductor layer located above the polysilicon layer; A first insulator layer located between the first conductor layer and the polysilicon layer; An oxide semiconductor layer; A second conductor layer located above the oxide semiconductor layer; And A second insulator layer located between the second conductor layer and the oxide semiconductor layer, Among them, the polysilicon layer includes the polysilicon portion of a polysilicon thin film transistor. Among them, the first conductor layer includes the first gate electrode portion of the polysilicon thin film transistor. Among them, the first insulator layer includes a first insulator portion located between the first gate electrode portion and the polysilicon portion. Among them, the oxide semiconductor layer includes the oxide semiconductor portion of an oxide semiconductor thin film transistor. Among them, the second conductor layer includes the second gate electrode portion of the oxide semiconductor thin film transistor. Among them, the second insulator layer includes a second insulator portion located between the second gate electrode portion and the oxide semiconductor portion. Among them, the second insulator layer has a relative dielectric constant of not less than 8. Among them, the entire region of the second insulator layer is covered by the second conductor layer. Among them, the oxide semiconductor portion includes a channel region and source / drain regions sandwiching the channel region, and Among them, the oxide semiconductor thin film transistor includes a compound interface portion located above the source / drain regions, the compound interface portion including constituent elements of the oxide semiconductor portion and constituent elements of the second insulator layer, and having a resistance lower than that of the channel region.

7. A method for manufacturing a thin film transistor circuit, the method comprising: Forming a polysilicon layer including the polysilicon portion of a polysilicon thin film transistor; Forming a first insulator layer including the insulator portion of the polysilicon thin film transistor on the upper layer of the polysilicon layer; Forming a first conductor layer including the first gate electrode portion of the polysilicon thin film transistor on the upper layer of the first insulator layer; Forming an oxide semiconductor layer including the oxide semiconductor portion of an oxide semiconductor thin film transistor; Forming a second insulator layer including the insulator portion of the oxide semiconductor thin film transistor on the upper layer of the oxide semiconductor layer; And Form a second conductor layer including a second gate electrode portion of the oxide semiconductor thin film transistor on the upper layer of the second insulator layer, wherein the second insulator layer has a relative dielectric constant of not less than 8, wherein the second conductor layer and the second insulator layer are etched together or the second insulator layer is etched using the second conductor layer as a mask, wherein the relative dielectric constant of the first insulator layer is lower than that of the second insulator layer, wherein the second conductor layer includes an upper electrode portion of a capacitor element, wherein the upper electrode portion of the capacitor element is connected to the first gate electrode portion, and wherein the second insulator layer includes an insulator portion of the capacitor element.

8. A method of manufacturing a thin film transistor circuit, the method comprising: Form a polysilicon layer including a polysilicon portion of a polysilicon thin film transistor; Form a first insulator layer including a first insulator portion of the polysilicon thin film transistor on the upper layer of the polysilicon layer; Form a first conductor layer including a first gate electrode portion of the polysilicon thin film transistor on the upper layer of the first insulator layer; Form an oxide semiconductor layer including an oxide semiconductor portion of an oxide semiconductor thin film transistor; Form a second insulator layer including a second insulator portion of the oxide semiconductor thin film transistor on the upper layer of the oxide semiconductor layer; and Form a second conductor layer including a second gate electrode portion of the oxide semiconductor thin film transistor on the upper layer of the second insulator layer, wherein the second insulator layer has a relative dielectric constant of not less than 8, wherein the second conductor layer and the second insulator layer are etched together or the second insulator layer is etched using the second conductor layer as a mask, wherein the thin film transistor circuit further includes an interface insulator portion having an interface with the oxide semiconductor portion and another interface with the second insulator portion, wherein the relative dielectric constant of the interface insulator portion is not less than 8, and Among them, the carbon concentration in the interface insulator part is not less than 1×10 18 cm -3 , and the carbon concentration in the second insulator part is less than 1×10 18 cm -3 .

9. A method of manufacturing a thin film transistor circuit, the method comprising: Form a polysilicon layer including a polysilicon portion of a polysilicon thin film transistor; Form a first insulator layer including an insulator portion of the polysilicon thin film transistor on the upper layer of the polysilicon layer; Form a first conductor layer including a first gate electrode portion of the polysilicon thin film transistor on the upper layer of the first insulator layer; Form an oxide semiconductor layer including an oxide semiconductor portion of an oxide semiconductor thin film transistor; Form a second insulator layer including an insulator portion of the oxide semiconductor thin film transistor on the upper layer of the oxide semiconductor layer; and Form a second conductor layer including a second gate electrode portion of the oxide semiconductor thin film transistor on the upper layer of the second insulator layer, wherein the second insulator layer has a relative dielectric constant of not less than 8, wherein the second conductor layer and the second insulator layer are etched together or the second insulator layer is etched using the second conductor layer as a mask, Among them, the oxide semiconductor portion includes a channel region and source / drain regions sandwiching the channel region, and Among them, the oxide semiconductor thin film transistor includes a compound interface portion respectively located above the source / drain regions. The compound interface portion includes constituent elements of the oxide semiconductor portion and constituent elements of the second insulator layer, and has a resistance lower than that of the channel region.

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