Semiconductor Chip and Its Presintering Test Method

Abstract

The present disclosure provides a semiconductor chip and a pre-burning test method therefor. Further, the present disclosure performs a pre-test that checks the electrical connection between each electrical contact of a socket and a corresponding pin of the semiconductor chip during a pre-test phase before the pre-burning test. The electrical connection between each electrical contact and each pin is checked through a plurality of signal channels. Even when one of the signal channels fails, as long as another one of the signal channels passes the pre-test, the pre-test and the pre-burning test can still be performed. Additionally, the pre-test phase through the plurality of signal channels also provides information for determining whether the failure of the semiconductor chip is caused by the electrical connection between the sockets of the pre-burning board or by the semiconductor chip itself.

Description

Technical Field

[0001] The present disclosure relates to a memory device, and more particularly, to a semiconductor chip and a burn-in test method thereof. Background Art

[0002] In order to identify defective chips, a burn-in procedure is performed on the chips.

[0003] In the burn-in test, each chip is inserted into a socket or slot of a test fixture (or burn-in board) to receive commands, data, power, etc. from a test controller or computer. These burn-in tests are usually designed to burn in multiple chips connected to the same electrical bus (i.e., in parallel) to save time and cost. In some cases, one or more sockets of the test fixture may be contaminated. For example, the socket may be contaminated by particles, dirt, dust, etc. Alternatively, due to the wear of the test fixture, the contact part of the socket may have a poor connection. In any case, the contaminated connection between the memory chip and the burn-in test fixture will provide inaccurate test results. The contaminated connection in one socket may affect the remaining sockets connected to the same electrical bus, which are connected to the same signal channel of the test fixture. In addition, it is time-consuming to troubleshoot contaminated or damaged sockets. Using the current configuration of the burn-in test, the results of the test may be unreliable, and time is wasted on troubleshooting the test fixture. Summary of the invention

[0004] In the present disclosure, a semiconductor chip is configured to perform a pre-test or a burn-in test through a plurality of signal channels. The pre-test is configured to check electrical connection between each pin of the semiconductor chip with respect to a socket of a burn-in board or a controller of a burn-in system performing the burn-in test.

[0005] The semiconductor chip of the present invention includes a control circuit and a plurality of pins coupled to the control circuit. The plurality of pins are configured to receive a first signal from a first signal channel through a first set of pins and to receive a second signal from a second signal channel through a second set of pins. The control circuit receives and decodes the first signal and the second signal, and performs a pre-test before a burn-in test based on the first signal and the second signal to obtain a state of electrical connection between each of the first set of pins and the first signal channel and between each of the second set of pins and the second signal channel.

[0006] The semiconductor chip pre-burning system of the present invention includes a pre-burning device, a plurality of semiconductor chips and a controller. The pre-burning device includes a pre-burning board. The pre-burning board includes a plurality of sockets, each of which includes a plurality of electrical contacts. Each of the plurality of semiconductor chips includes a control circuit and a plurality of pins coupled to the control circuit, each of which is coupled to one of the electrical contacts of the socket. In addition, the controller is coupled to the plurality of semiconductor chips through the socket of the pre-burning board, and is configured to transmit a first signal and a second signal to start a pre-test before the pre-burning test. In the pre-test, the control circuit reconfigures the pins into a first set of pins as a first signal channel to receive the first signal, and reconfigures the pins into a second set of pins as a second signal channel to receive the second signal, and obtains the state of electrical connection between each of the first set of pins and the corresponding electrical contact of the socket and between each of the second set of pins and the corresponding electrical contact of the socket.

[0007] The present invention provides a method for testing a plurality of semiconductor chips. The method comprises the steps of reconfiguring a plurality of pins into a first set of pins as a first signal channel to receive a first signal from a controller, and reconfiguring a plurality of pins into a second set of pins as a second signal channel to receive a second signal from the controller. The method further comprises the steps of performing a pre-test to determine the state of electrical connection of each of the first set of pins and the second set of pins relative to the controller before a burn-in test based on the first signal and the second signal received through the first channel and the second channel, respectively. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.

[0009] Figure 1 is a block diagram showing a semiconductor chip burn-in system in an embodiment according to the present disclosure;

[0010] Figure 2 is a block diagram showing a burn-in board of a burn-in device according to an embodiment of the present disclosure;

[0011] Figure 3 shows the connection between the chip and the socket on the burn-in board according to the embodiment of the present disclosure;

[0012] Figure 4 is a block diagram showing a memory chip in an embodiment according to the present disclosure;

[0013] Figure 5 is a flow chart showing a semiconductor chip burn-in test procedure in an embodiment according to the present disclosure;

[0014] Figure 6 is a timing diagram showing a test signal of a pre-test according to an embodiment of the present disclosure;

[0015] Figure 7 is a schematic diagram showing the transmission of an input signal from a controller to a memory chip according to an embodiment of the present disclosure;

[0016] Figure 8 is a schematic diagram showing a register file read / write control unit according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0017] Figure 1 is a block diagram showing a semiconductor chip burn-in system 1 according to an embodiment of the present disclosure. Figure 1 In the present invention, a semiconductor chip burn-in system 1 includes a controller 20 and a burn-in device 10. The controller 20 and the burn-in device 10 may be communicatively coupled to each other via a cable or wirelessly. The burn-in device 10 includes a plurality of burn-in boards 100. Each of the burn-in boards 100 may include a plurality of sockets 110 configured to respectively accommodate and provide electrical connections to a plurality of semiconductor chips 120 (which may be referred to as chips or integrated chips (ICs)). Although Figure 1 The controller 20 and the burn-in device 10 are shown as two different components, but in other embodiments, the controller 20 may be included in the burn-in device 10 .

[0018] Controller 20 may include one or more processors configured to instruct burn-in device 10 to perform a burn-in test on chip 120 connected to socket 110 of burn-in board 101. Controller 20 may also include analog and digital circuits that provide signals and power to chip 120 for performing the burn-in test.

[0019] Figure 21 is a block diagram showing a burn-in board 100 of a burn-in device 10 according to an embodiment of the present disclosure. The burn-in board 100 may be a printed circuit board (PCB), the printed circuit board comprising: one or more electrical connectors 101; a plurality of electrical buses 103(1)_CH1 to 103(n)_CH1, 103(1)_CH2 to 103(n)_CH2; and a plurality of sockets 110(1,1) to 110(n,m), coupled to the electrical connector 101 via the electrical buses 103(1)_CH1 to 103(n)_CH1, 103(1)_CH2 to 103(n)_CH2, wherein n and m may be any number greater than zero. For the purpose of brevity, unless otherwise specified, the socket 110 and the electrical bus 103 may be referred to as a plurality of sockets 110 (1, 1) to sockets 110 (n, m) and a plurality of electrical buses 103 (1) to electrical buses 103 (n). The electrical connector 101 is configured to be disposed in the burn-in device 10 and to communicate bidirectionally with the controller 20. In detail, the controller 20 may access the chip 120 connected to the socket 110 through the electrical connector 101 and the electrical bus 103. The electrical connector 101 may be a goldfinger connector or any suitable connector, such as a D-sub connector, an RS connector, etc. In an embodiment, the electrical connector 101 is disposed in the burn-in device 10. For example, the burn-in device 10 may include a plurality of slots or connectors (not shown) configured to be coupled to the electrical connector 101, so that the controller 20 may access the chip 110 disposed on the burn-in board 100 through the electrical connector 101. Each of the electrical buses 103 ( 1 )_CH1 to 103 ( n )_CH1 and the electrical buses 103 ( 1 )_CH2 to 103 ( n )_CH2 may be a bus having a plurality of traces, and each trace is connected to an electrical contact of the socket 110 .

[0020] Figure 3The connection between the chip 120 and the socket 110 on the burn-in board 100 in an embodiment according to the present disclosure is shown. The socket 110 includes a plurality of electrical contacts 111, and the semiconductor chip 120 includes a plurality of pins 121 (or pins, pads, etc.). Each of the electrical contacts 111 of the socket 110 is configured to be coupled to one of the pins 121 of the semiconductor chip 120 to form an electrical connection. The number of electrical contacts 111 and the number of pins 121 may include any number and may be the same or different. For example, in some embodiments, the number of electrical contacts 111 may be greater than the number of pins 121. As described above, the electrical contacts 111 of the socket 110 may be contaminated (e.g., by particles), thereby causing the electrical connection between the socket 110 and the semiconductor chip 120 to fail. Conventionally, the socket 110 may be cleaned by an air gun or any other means, and the burn-in test will have to be performed again. In contrast, in the embodiments of the present disclosure, multiple signal channels between the socket 110 and the semiconductor chip 120 can reduce failures of the burn-in test caused by contaminated electrical contacts 111 of the socket 110 because the test signal can be transmitted to the semiconductor chip 120 through other signal channels.

[0021] Figure 4 4 is a block diagram showing a memory chip 420 in an embodiment according to the present disclosure. Although a memory chip is used as an example to represent the semiconductor chip 120 as described above, it is not intended to limit the present disclosure. Figure 1 , Figure 2 as well as Figure 4 , the memory chip 420 may be placed in the socket 110 of the burn-in board 100, and the burn-in board 100 is placed in the burn-in device 10. The memory chip 420 is coupled to the controller 20 and receives a signal through the socket 110. In an embodiment, the signal received from the controller 20 may be a control signal, a data signal, and other signals (such as a power signal). In other embodiments, the power signal may be provided by a power supply in the burn-in device 10, and the present disclosure is not intended to limit the source of the power signal.

[0022] In an embodiment, the memory chip 420 includes a plurality of pins 421(1) to 421(K), a first channel interface 422, a second channel interface 423, a control circuit 424, a memory array 426, a row decoder 427, and a column decoder 428. The plurality of pins 421(1) to 421(K) are configured to receive and transmit signals, where k is greater than zero. The pins 421(1) to 421(K) may be directly or indirectly coupled to the control circuit 424. In an embodiment, the pins 421(1) to 421(x) are coupled to the control circuit 424 via the first interface 422, and the pins 421(x+1) to 421(y) are coupled to the control circuit 424 via the second interface 423, where y is a positive real number greater than x and less than k. Although the embodiment shows that the pins 421(y+1) to 421(k) are directly coupled to the control circuit 424, the present disclosure is not limited thereto. In other embodiments, pins 421 (y+1) to 421 ( k ) are coupled to control circuit 424 through an interface (not shown).

[0023] The control circuit 424 is coupled to the input / output logic 425, the row decoder 427, and the column decoder 428 to store data in the memory array 426 and extract data from the memory array 426. The memory array 426 includes a plurality of memory cells arranged in a matrix. The control circuit 424 is configured to decode the signal received from the pin 421 (1) to the pin 421 (k), and the signal may include a command, data, etc. For example, the control circuit 424 decodes the address to be accessed based on the signal received from the pin 421 (1) to the pin 421 (k). The control circuit 424 transmits the data of the received signal to the input / output logic 425, and transmits the row address and the column address to the row decoder 427 and the column decoder 428 for accessing the memory array 426. In an embodiment, the control circuit 424 is configured to recognize a command signal from the controller 20 instructing the memory chip 420 to enter a pre-test mode. The command signal may include an entry code (ie, signal switching) of each of pins 421 ( 1 ) to 421 ( y ) for sequentially switching signal channels, which will be described in detail later.

[0024] In an embodiment, pins 421(1) to 421(y) are configured to receive test signals from the controller 20 as a plurality of signal channels. In detail, a plurality of signal channels are formed by configuring a portion of pins 421(1) to 421(x) of the memory chip 420 (i.e., a first portion of the plurality of pins) as a first signal channel receiving a first test signal S1, and configuring another portion of pins 421(x+1) to 421(y) of the memory chip 420 (i.e., a second portion of the plurality of pins) as a second signal channel receiving a second test signal S2. The number of pins forming the first signal channel (e.g., pins 421(1) to 421(x)) may be the same as the number of pins forming the second signal channel (e.g., pins 421(x+1) to 421(y)), and the first test signal S1 and the second test signal S2 may be the same or different. Pins 421(y+1) to 421(k) are configured to receive or transmit other signals between the memory chip 420 and the controller 20 (or other devices outside the memory chip 420). The other signals may include a power signal, an output signal of the memory chip 420, and any other control signal. The power signal may be provided by the controller 20 or the burn-in device 10. In response to the test signal S1 and the test signal S2, the output signal may be a feedback signal from the control circuit 424. Although the embodiment shows only the first channel and the second channel, it should be noted that more signal channels can be formed by reconfiguring the functions of pins 421(1) to 421(k).

[0025] The multiple signal channels are configured to avoid the problem of contaminated electrical contacts 111 on the socket 110 of the burn-in board 100. For example, the electrical connection between the electrical contacts 111 of the socket 110 and one of the pins 421(1) to 421(x) configured as the first signal channel is contaminated. The first signal channel will not be able to receive the entire first test signal. For a memory chip having only one signal channel (i.e., a conventional configuration), this condition will cause the burn-in test to fail. However, in an embodiment, pins 421(x+1) to 421(y) will still receive the second test signal S2 to complete the pre-test and the burn-in test. The function of the memory chip 420 (e.g., accessing the memory array 426) can be subjected to burn-in or stress testing through the second signal channel. In other words, the stress test of the memory chip 420 during the burn-in test can be performed by the burn-in test signal received by the first signal channel or the second signal channel. The burn-in test signals received by the first signal channel and the second signal channel can be the same or different. Thus, the user may clean the contaminated electrical contacts 111 of the socket 110 during the pre-test phase, or allow the memory chips placed on the burn-in board 110 to continue the burn-in test phase.

[0026] Figure 5is a flowchart illustrating a semiconductor chip burn-in test procedure in an embodiment according to the present disclosure. Figure 5 An x-axis representing time and a y-axis representing temperature are included to illustrate various stages of a semiconductor chip burn-in test. The burn-in test procedure includes a chip loading stage 1100, a pre-test stage 1200, a burn-in test stage 1300, and a chip unloading stage 1400. In an embodiment, the chip loading stage 1100, a portion of the pre-test stage 1200, and the chip unloading stage 1400 are performed at a first temperature T1, which may be room temperature. Another portion of the pre-test stage 1200 and the burn-in test stage are performed at a second temperature T2, which may be a temperature controlled by the burn-in device 10. For example, the burn-in device 10 may be controlled to heat the internal compartment containing the burn-in board to a designed burn-in temperature, for example, 40 degrees Celsius to 150 degrees Celsius. In the chip loading stage 1100, a plurality of semiconductor chips 120 are loaded onto a plurality of sockets 110 of the burn-in board 100. A plurality of burn-in boards 100 each having a plurality of semiconductor chips 120 may be inserted or plugged into the burn-in apparatus 10 to perform a burn-in test on a batch of semiconductor chips. A batch of semiconductor chips refers to semiconductor chips mounted on a plurality of burn-in boards 100 and to be tested during the same period of time.

[0027] In the pre-test phase 1200, the electrical connection between the socket 110 and the semiconductor chip 120 is checked before the burn-in test phase 1300. The pre-test phase 1200 includes a first pre-test 1210, a second pre-test 1220, and a chip reloading step 1230. In an embodiment, the first pre-test 1210 and the chip reloading step 1230 are performed at a first temperature, and the second pre-test 1220 is performed at a second temperature. After the chip loading phase 1100, the controller 20 instructs the burn-in test device 10 to perform the first pre-test in step 1211, and determines whether the electrical connection between the semiconductor chip 120 and the socket 110 of the burn-in board 110 passes the first pre-test in step 1212. If the first pre-test 1210 is passed, the program will go to the second pre-test 1220 at the second temperature (i.e., the "yes" path out of step 1212). If the first pre-test 1210 fails (ie, does not pass), the program will go to the chip reload step 1230 (ie, the "no" path out of step 1212).

[0028] In the chip reloading step 1230, the semiconductor chip 120 is reloaded onto the socket 110. For example, the semiconductor chip may be pulled out of the socket 110 for cleaning the electrical contacts 111 of the socket 110 and / or the pins 121 of the semiconductor chip 120. Then, the semiconductor chip 120 may be reloaded onto the socket 110. The program will then return to the first pre-test stage 1210 to retest the electrical connection at the first temperature T1. The first pre-test stage 1210 may generate a test result indicating which burn-in board 100 and / or which socket 110 failed the first pre-test 1210, so that the cleaning of the socket and the reloading of the semiconductor chip can be limited to the problematic portion.

[0029] When a batch of semiconductor chips passes the first pre-test stage 1210, the program proceeds to the second pre-test stage 1220. Similar to the first pre-test stage 1210, the second pre-test stage 1220 includes a step 1221 of performing a second pre-test at a second temperature T2 and a step 1222 of determining whether the batch of semiconductor chips passes the second pre-test at the second temperature T2. If the batch of semiconductor chips fails the second pre-test (i.e., the "No" path from step 1222), the program proceeds to a chip reloading step 1230. If the batch of semiconductor chips passes the second pre-test (i.e., the "Yes" path from step 1222), the program proceeds to a burn-in test stage 1300 to perform a burn-in test on the batch of semiconductor chips.

[0030] After the burn-in test phase 1300, the process will proceed to the chip unloading phase 1400, where the semiconductor chips 120 will be unloaded from the burn-in board 100. The results of the burn-in test performed during the burn-in test phase 1300 will be provided to screen defective chips that appear after some use.

[0031] Hereinafter, the pretests performed during the first pretest 1210 and the second pretest 1220 in the pretest stage 1200 will be described in detail. One of the purposes of the pretest is to identify any communication failure between the socket 110 of the burn-in board 100 and the semiconductor chip 120. As described above, due to the defective electrical connection between the socket 110 and the semiconductor chip 120, particles on the socket 110 may cause communication failure. After the burn-in test, the defective electrical connection may be misunderstood as a failure of the semiconductor chip 120. In this case, the burn-in test may be performed again for the semiconductor chip that did not pass the burn-in test. In an embodiment, the pretest stage 1200 may identify defective electrical connections before the burn-in test so that the burn-in test does not have to be performed again. The pretest stage may take 2 hours to 10 hours to complete, and the burn-in time of the burn-in test may be several times the amount of time that the pretest will take. Therefore, it is desirable to capture defective electrical connections in the pretest stage 1200 before the burn-in test stage 1300.

[0032] Figure 6 is a timing diagram showing a test signal of a pre-test according to an embodiment of the present disclosure. The test signal includes an entry code that switches the pins of the memory chip in a sequential order to instruct the memory chip 421 to enter a test mode. After the entry code, commands and data of the test signal may be transmitted to the memory chip for accessing the memory chip. Figure 6 , signal S1(1) to signal S1(x) represent signals of the first signal channel (CH1), and signal S2(x+1) to signal S2(y) represent signals of the second signal channel (CH2). Signals S1(1) to signal S1(x), signal S2(x+1) to signal S2(y) are transmitted from the controller 20 to each of the pins 421(1) to pin 421(y) of the memory chip relative to the clock CLK. The entry code includes a first part, which switches each of the pins 421(1) to pin 421(y) twice simultaneously with one or more clock cycles apart. The entry code also includes a second part, which switches each of the pins 421(1) to pin 421(y) of the memory chip 421 in sequential order in each clock cycle, which can also be referred to as signal switching of individual pins. Signal switching of individual pins or switching of any pin refers to a signal transmitted between low and high within one clock cycle. According to Figure 6 , the signal switching of the individual pins is performed on the first signal channel (CH1) and the second signal channel (CH2), respectively. For example, the first signal S1(1) of the first signal channel (CH1) is switched during the same clock cycle as the first signal S2(x+1) of the second signal channel (CH2). In other embodiments, the signal switching of the individual pins may include other modes instead of the above. Figure 6. For example, the first pin connected to the first signal path (or the second signal path) may be switched first, and then the signal switching of the last pin connected to the first signal path (or the second signal path) may be switched. The remaining pins connected to the first signal path (or the second signal path) may be switched in any order. In yet other embodiments, the pins connected to the first signal path and the second signal path may be switched in a random order, respectively.

[0033] although Figure 6 The test signal of the pre-test stage includes an entry code, a command, and data, but the present disclosure is not intended to be limited thereto. In other embodiments, the entry code is sufficient to show the electrical connection between the electrical contact 111 of the socket 110 and the pin 421 of the memory chip 420 involved in the signal switching. Therefore, the test signal of the pre-test may only contain an entry code, which is used to determine whether the electrical connection between the socket and the memory chip is established for subsequent tests such as a burn-in test.

[0034] A test signal for instructing each memory chip to enter a test mode is transmitted from the controller 20 to each memory chip 420 disposed in the socket 110 through the electrical buses 103 ( 1 ) to 103 ( n ) of the burn-in board 100 . Figure 7 is a diagram showing the transmission of input signals from the controller 20 to the memory chip 420 according to an embodiment of the present disclosure. In an embodiment, the number of pins for transmitting test signals is reduced to create multiple signal paths, thereby avoiding inaccurate burn-in tests caused by contaminated electrical connections between the sockets of the burn-in board and the pins of the memory chip. For example, if the memory chip initially has 20 pins for receiving input signals to test the memory chip, then the embodiment will reduce the number of pins to create multiple signal paths. In the case where the memory chip has 20 pins (i.e., the number of pins), if Figure 2 and Figure 4The embodiment shown in will divide 20 pins into 2 signal channels, wherein each signal channel will utilize 10 pins for transmitting input signals. Because the data amount of the input signal before and after the multiple signal channel configuration will be the same, the input signal will be transmitted and / or received in a time division manner. For example, conventionally, the address of the input signal may require all 20 pins to be transmitted. When multiple signal channel configurations are used, only 10 pins are assigned to one signal channel. In an embodiment, the address of the input signal is divided into a first address (Addr#1) and a second address (Addr#2), wherein the first address is transmitted at the rising edge of the clock cycle, and the second address is transmitted at the falling edge of the same clock cycle. Similar techniques are used to transmit commands (CMD#1, CMD#2) and data (DQ#1, DQ#2) of the first signal channel and the second signal channel (CH1, CH2). The present disclosure is not limited to the above-mentioned reduced pin count (RPC) technology, and other RPC technologies may be suitable for embodiments of the present disclosure.

[0035] It should be noted that the memory chip 420 is used to illustrate the concept of the present disclosure in some of the above embodiments, however, all descriptions related to the memory chip 420 can also be applied to the following embodiments: Figures 1 to 3 The semiconductor chip 120 is shown in FIG.

[0036] Figure 8 1 is a flow chart showing a method of testing a plurality of semiconductor chips according to an embodiment of the present disclosure. In step S810, a test signal including an entry code is received from a controller. After receiving the test signal, in step S820, a control circuit of the semiconductor chip enters a test mode, and a plurality of pins are reconfigured into a first set of pins as a first signal channel to receive a first signal from the controller, and reconfigured into a second set of pins as a second signal channel to receive a second signal from the controller. In step S830, a pre-test before a burn-in test is performed to determine a state of electrical connection of each of the first set and the second set of pins relative to the controller.

[0037] In an embodiment, the pre-test of step S830 includes a first pre-test and a second pre-test. In step S831, when the semiconductor chip is placed in an environment having a first temperature (e.g., ambient temperature), the first pre-test is performed by switching each of the pins through a first signal path and a second signal path. The first pre-test determines whether at least one of the first signal path or the second signal path passes the test (see also FIG. Figure 5 If not passed, the semiconductor chip can be reloaded onto the socket of the burn-in board and the first pre-test can be performed again (see also 1210 in FIG. 1 ). Figure 51230 shown in ). If passed, the program goes to the second pre-test in step S833, where the environment is changed to a second temperature that may be higher or lower than the first temperature. The second pre-test determines whether at least one of the first signal channel or the second signal channel passes the test. If not passed, the temperature of the environment of the semiconductor chip can be changed back to the ambient temperature, and the semiconductor chip can be reloaded onto the socket of the burn-in board. Then, the pre-test will be performed again from the first pre-test in step S831. However, the present disclosure is not intended to be limited to this. In other embodiments, after reloading the semiconductor chip, the program may return to the beginning of the second pre-test in step S833. It should also be noted that semiconductor chip reloading may refer to reloading a semiconductor chip with an electrical connection problem as identified by the first pre-test and the second pre-test. If the semiconductor chip passes the second pre-test in step S833, the program goes to step S840 to perform the burn-in test.

[0038] Based on the above, the present disclosure can quickly test the electrical connection between multiple electrical contacts of the socket and multiple pins of the semiconductor chip during the pre-test phase before the time-consuming pre-burn-in test phase. In detail, the electrical connection between each of the electrical contacts and each of the pins can be checked through multiple signal channels. Even when one of the signal channels fails, as long as another of the signal channels passes the pre-test, the pre-test and the burn-in test can still be performed. In addition, the pre-test phase through multiple signal channels also provides information for determining whether the failure of the semiconductor chip is caused by the electrical connection between the sockets of the burn-in board or by the semiconductor chip itself.

Claims

1. A semiconductor chip, comprising: a plurality of pins disposed in the same single semiconductor chip, receiving a first signal from a first signal channel through a first set of the pins and receiving a second signal from a second signal channel through a second set of the pins; and a control circuit that receives and decodes the first signal and the second signal, and performs a pre-test before a burn-in test based on the first signal and the second signal to obtain an electrical connection state between each of the first set of the pins and the first signal channel and an electrical connection state between each of the second set of the pins and the second signal channel.

2. The semiconductor chip according to claim 1, wherein the control circuit is further configured to receive a burn-in test signal for performing the burn-in test when one of the first set or the second set of the pins passes the pre-test.

3. The semiconductor chip according to claim 1, wherein each of the first signal and the second signal includes an entry code for instructing the control circuit to enter the pre-test, and the entry code includes signal switching of individual pins in the first set and the second set of the pins.

4. The semiconductor chip according to claim 3, wherein the signal switching of the individual pins switches each of the first set and the second set of the pins in a sequential order.

5. The semiconductor chip according to claim 3, wherein the signal switching of the individual pins switches each of the first set and the second set of the pins in a random order.

6. A semiconductor chip burn-in system, comprising: a burn-in device having a burn-in board, wherein the burn-in board includes a plurality of sockets, and each socket includes a plurality of electrical contacts; a plurality of semiconductor chips, each including a control circuit and a plurality of pins coupled to the control circuit, wherein each of the pins is coupled to one of the electrical contacts of the socket; and a controller coupled to the plurality of semiconductor chips through the sockets of the burn-in board, transmitting a first signal and a second signal to start a pre-test before a burn-in test, wherein, in the pre-test, the control circuit reconfigures the pins into a first set of the pins as a first signal channel to receive the first signal and a second set of the pins as a second signal channel to receive the second signal, and obtains an electrical connection state between each of the first set of the pins and the electrical contact corresponding to the socket and an electrical connection state between each of the second set of the pins and the electrical contact corresponding to the socket.

7. The semiconductor chip burn-in system according to claim 6, wherein the control circuit is further configured to receive a burn-in test signal for performing the burn-in test when one of the first set or the second set of the pins passes the pre-test.

8. The semiconductor chip burn-in system according to claim 6, wherein the first signal and the second signal are the same.

9. The semiconductor chip pre-burning system according to claim 6, wherein the pre-test includes a first pre-test at a first temperature and a second pre-test performed at a second temperature, and the second temperature is greater than the first temperature.

10. A method for testing a plurality of semiconductor chips, wherein the semiconductor chips include a control circuit and a plurality of pins coupled between the control circuit and a controller external to the semiconductor chip, and the plurality of pins are disposed in the same single semiconductor chip, the method comprises: reconfiguring the plurality of pins into a first set of pins serving as a first signal channel to receive a first signal from the controller, and a second set of pins serving as a second signal channel to receive a second signal from the controller; and performing a pre-test before the pre-burning test to determine the electrical connection status of each of the first set and the second set of the pins with respect to the controller based on the first signal and the second signal received through the first signal channel and the second signal channel, respectively.

11. The method for testing a plurality of semiconductor chips according to claim 10, further comprising receiving a pre-burning test signal for performing the pre-burning test when one of the first set or the second set of the pins passes the pre-test.

12. The method for testing a plurality of semiconductor chips according to claim 10, wherein each of the first signal and the second signal includes an entry code for instructing the control circuit to enter the pre-test, and the entry code includes signal switching of individual pins in the first set and the second set of the pins, and the first signal and the second signal are the same.

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