Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure, comprising: forming a first gate across a first fin and a second gate across a second fin; etching the first fins on both sides of the first gate to form a first groove, etching the second fins on both sides of the second gate to form a second groove, wherein the width of the first groove is smaller than the width of the second groove; forming a sacrificial layer covering the sidewalls of the first gate, the sidewalls of the first groove, the sidewalls of the second gate, and the sidewalls of the second groove, wherein the sacrificial layer also covers a pad oxide layer on a substrate in a first region, wherein the sacrificial layer exposes the pad oxide layer on the sidewalls of the second fin located at the bottom of the second groove; etching the pad oxide layer exposed by the sacrificial layer to expose the sidewalls of the second fin located at the bottom of the second groove; removing the sacrificial layer; and in the same process step, using an epitaxial growth process to form a first source-drain doping layer in the first groove and a second source-drain doping layer in the second groove. The formation method is helpful to increase the growth volume of the second source-drain doping layer and simplify the process flow.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of MOSFETs is also shortened accordingly. However, as the device channel length shortens, the distance between the source and drain of the device also shortens, resulting in a poorer control of the gate over the channel and a greater likelihood of short-channel effects (SCE).

[0003] Fin field effect transistor (FinFET) has outstanding performance in suppressing short channel effect. The gate of FinFET can control the fin from at least two sides. Therefore, compared with planar MOSFET, the gate of FinFET has stronger control over the channel and can effectively suppress the short channel effect.

[0004] However, the performance of semiconductor structures in the prior art still needs to be improved. Summary of the invention

[0005] The problem solved by the present invention is to provide a method for forming a semiconductor structure, which is helpful to increase the growth volume of the second source-drain doping layer and simplify the process flow.

[0006] To solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a first region and a second region, the substrate in the first region having a discrete first fin, and the substrate in the second region having a discrete second fin; forming a liner oxide layer on the top and sidewalls of the first fin, the top and sidewalls of the second fin, and the substrate; after forming the liner oxide layer, forming a plurality of first gates that are discretely arranged and span the first fin, forming a plurality of second gates that are discretely arranged and span the second fin, wherein the spacing between adjacent first gates is smaller than the spacing between adjacent second gates; etching the first fins on both sides of the first gate to form a first groove, etching the second fins on both sides of the second gate to form a second groove, wherein the first groove extends along the first fin. The width of the second groove in the extension direction is smaller than the width of the second groove along the extension direction of the second fin; a sacrificial layer is formed covering the sidewall of the first gate, the sidewalls of the first groove on both sides of the first gate, the sidewalls of the second gate and the sidewalls of the second groove on both sides of the second gate, the sacrificial layer also covers the top of the pad oxide layer on the substrate of the first region, the sacrificial layer exposes the pad oxide layer on the sidewall of the second fin located at the bottom of the second groove and perpendicular to the extension direction of the second gate; the pad oxide layer exposed by the sacrificial layer is etched to expose the sidewall of the second fin located at the bottom of the second groove; the sacrificial layer is removed; in the same process step, a first source-drain doping layer is formed in the first groove by an epitaxial growth process, and a second source-drain doping layer is formed in the second groove by an epitaxial growth process.

[0007] Optionally, the step of forming the sacrificial layer includes: forming a sacrificial film covering the top and sidewalls of the first gate, the sidewalls and bottom of the first groove on both sides of the first gate, the top and sidewalls of the second gate, and the sidewalls and bottom of the second groove on both sides of the second gate, the sacrificial film also covering the top of the pad oxide layer on the substrate located in the first region and the second region; etching the sacrificial film to remove the sacrificial film at the bottom of the second groove, the top of the first gate, and the top of the second gate, and removing the sacrificial film on both sides of the second fin at the bottom of the second groove along the extension direction of the second gate, exposing the pad oxide layer on the sidewalls of the second fin at the bottom of the second groove perpendicular to the extension direction of the second gate, to form the sacrificial layer.

[0008] Optionally, in the step of forming the sacrificial film, the sacrificial film completely fills the first groove and the gap between adjacent first gate sidewalls.

[0009] Optionally, the sacrificial film is etched using a dry etching process.

[0010] Optionally, in the step of etching the sacrificial layer to expose the pad oxide layer, the etching thickness of the pad oxide layer is 3 nm to 20 nm.

[0011] Optionally, the step of forming the first gate and the second gate further includes: forming a first hard mask layer on the top of the first gate, and forming a second hard mask layer on the top of the second gate.

[0012] Optionally, after forming the first gate and the second gate and before forming the first groove and the second groove, it also includes: forming a first side wall covering the side wall of the first gate and the side wall of the first hard mask layer, and forming a second side wall covering the side wall of the second gate and the side wall of the second hard mask layer.

[0013] Optionally, in the step of forming the first groove and the second groove, one first groove is formed between adjacent first gates, and one second groove is formed between adjacent second gates.

[0014] Optionally, the material of the pad oxide layer is silicon oxide.

[0015] Optionally, the material of the sacrificial layer is silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride or boron carbonitride.

[0016] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0017] In the technical solution of the method for forming a semiconductor structure provided by the present invention, the width of the first groove along the extension direction of the first fin is smaller than the width of the second groove along the extension direction of the second fin, and the distance between the center of the bottom of the first groove and the side walls on both sides is smaller than the distance between the center of the bottom of the second groove and the side walls on both sides. The sacrificial layer covers the side walls of the first gate, the side walls of the first groove on both sides of the first gate, the side walls of the second gate, the side walls of the second groove on both sides of the second gate, and the top of the pad oxide layer on the substrate of the first region to prevent these positions from being etched. The sacrificial layer exposes the pad oxide layer on the side wall of the second fin at the bottom of the second groove that is perpendicular to the extension direction of the second gate, and the pad oxide layer exposed by the sacrificial layer is etched to expose the side wall of the second fin at the bottom of the second groove, so as to increase the exposed area of ​​the side wall of the second fin in the central region of the bottom of the second groove, and subsequently grow the second source and drain doping layer in the second groove, which helps to increase the growth rate of the second source and drain doping layer at the central region of the bottom of the second groove, so as to increase the growth volume of the second source and drain doping layer. The above formation method can modulate the growth rates of the first source-drain doped layer and the second source-drain doped layer, so that within the same or similar process time, the first source-drain doped layer fills the first groove and the second source-drain doped layer fills the second groove, which helps to simplify the process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 and Figure 2 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0019] Figures 3 to 12 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0020] As can be seen from the background technology, the performance of existing semiconductor structures still needs to be improved.

[0021] Now, a method for forming a semiconductor structure is analyzed. The process steps for forming the semiconductor structure mainly include:

[0022] refer to Figure 1, providing a substrate 10, the substrate 10 comprising a first region i and a second region ii, the substrate 10 in the first region i having a discrete first fin 21, the substrate 10 in the second region ii having a discrete second fin 22; forming a pad oxide layer 11 on the top and sidewall of the first fin 21, the top and sidewall of the second fin 22, and the substrate 10; forming a plurality of first gates 31 that are discretely arranged and span the first fin 21, forming a plurality of second gates 32 that are discretely arranged and span the second fin 22, adjacent to the first The spacing between the gates 31 is smaller than the spacing between the adjacent second gates 32; the first gate 31 has a first hard mask layer 34 on the top, and the second gate 32 has a second hard mask layer 35 on the top; a first sidewall 36 is formed on the sidewalls of the first gate 31 and the first hard mask layer 34, and a second sidewall 37 is formed on the sidewalls of the second gate 32 and the second hard mask layer 35; the first fin 21 on both sides of the first gate 31 is etched to form a first groove 41, and the second fin 22 on both sides of the second gate 32 is etched to form a second groove 42.

[0023] refer to Figure 2 In the same process step, an epitaxial growth process is used to form a layer that fills the first groove 41 (reference Figure 1 ) is formed by an epitaxial growth process to fill the second groove 42 (reference Figure 1 )'s second source / drain doped layer 52.

[0024] Since the spacing between adjacent first gates 31 is smaller than the spacing between adjacent second gates 32, in the step of forming the first groove 41 and the second groove 42, the width of the first groove 41 along the extension direction of the first fin 21 is smaller than the width of the second groove 42 along the extension direction of the second fin 22. The first source-drain doped layer 51 and the second source-drain doped layer 52 are formed in the same process step, and the growth rate of the first source-drain doped layer 51 near the sidewall of the first groove 41 is faster than that in the middle area of ​​the first groove 41. The growth rate of the second source-drain doped layer 52 near the sidewall of the second groove 42 is faster than that in the middle area of ​​the second groove 42. Compared with the middle area of ​​the first groove 41 and the middle area of ​​the second groove 42, since the middle area of ​​the second groove 42 is farther away from the side walls on both sides, the growth rate of the second source-drain doped layer 52 in the middle area of ​​the second groove 42 is slower, resulting in the overall growth rate of the second source-drain doped layer 52 being lower than the overall growth rate of the first source-drain doped layer 51, causing the growth volume of the second source-drain doped layer 52 to be small. When the first source-drain doped layer 51 fills the first groove 41, the second source-drain doped layer 52 only covers the side walls and bottom of the second groove 42, affecting the process progress.

[0025] The inventors have studied the method for forming the above-mentioned semiconductor structure. Through creative work, the inventors noticed that by etching the pad oxide layer on the side wall of the second fin located at the bottom of the second groove and perpendicular to the extension direction of the second gate, the side wall of the second fin located at the bottom of the second groove is exposed, which helps to increase the growth rate of the second source-drain doped layer in the middle area of ​​the second groove, thereby increasing the growth volume of the second source-drain doped layer.

[0026] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0027] Figures 3 to 12 A schematic structural diagram of a semiconductor structure forming process provided by an embodiment of the present invention.

[0028] refer to Figure 3 and Figure 4, providing a substrate 100, wherein the substrate 100 includes a first region I and a second region II, wherein the substrate 100 in the first region I has a discrete first fin 210, and the substrate 100 in the second region II has a discrete second fin 220; forming a pad oxide layer 110 on the top and sidewall of the first fin 210, the top and sidewall of the second fin 220, and the substrate 100; after forming the pad oxide layer 110, forming a plurality of discretely arranged first gates 310 and spanning the first fin 210, forming a plurality of discretely arranged second gates 320 and spanning the second fin 220, and the spacing between adjacent first gates 310 is smaller than the spacing between adjacent second gates 320.

[0029] Figure 3 The cross-sectional direction is parallel to the extension direction of the first fin 210 and perpendicular to the surface of the substrate 100 in the first region I, and is parallel to the extension direction of the second fin 220 and perpendicular to the surface of the substrate 100 in the second region II. Figure 4 The cross-sectional direction is perpendicular to the extending direction of the first fin 210 in the first region I, and is perpendicular to the extending direction of the second fin 220 in the second region II.

[0030] The first region I is used as a short channel region, and the second region II is used as a long channel region.

[0031] The material of the substrate 100 is silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. In this embodiment, the material of the substrate 100 is silicon.

[0032] In this embodiment, the first fin 210 and the second fin 220 are formed in the same process step.

[0033] The process steps for forming the first fin 210 and the second fin 220 include: providing an initial substrate, the initial substrate including a first region and a second region; forming a patterned mask layer on top of the initial substrate; using the mask layer as a mask, etching the initial substrate to form the first fin in the first region and the second fin in the second region.

[0034] Since the first fin 210 and the second fin 220 are formed in the same step with the same process time and process chamber environment, the first fin 210 and the second fin 220 have the same height.

[0035] In this embodiment, the material of the pad oxide layer 110 is silicon oxide.

[0036] In this embodiment, since the pad oxide layer 110 is formed on the substrate 100 in the first region I and the second region II in the same process step, the process time and the process chamber environment are the same, the thickness of the pad oxide layer 110 formed on the substrate 100 in the first region I and the second region II is the same.

[0037] In this embodiment, a deposition process is used to form the pad oxide layer 110. In other embodiments, an oxidation process is used to form the pad oxide layer.

[0038] In this embodiment, the step of forming the first gate 310 and the second gate 320 further includes: forming a first hard mask layer 331 on the top of the first gate 310 , and forming a second hard mask layer 332 on the top of the second gate 320 .

[0039] In this embodiment, the semiconductor structure is formed by a gate-last process, and both the first gate 310 and the second gate 320 are dummy gate structures. The materials of the first gate 310 and the second gate 320 are both polysilicon.

[0040] In other embodiments, both the first gate 310 and the second gate 320 are metal gate structures, and the materials of the first gate 310 and the second gate 320 are both metal.

[0041] In this embodiment, after forming the first gate 310 and the second gate 320, it also includes: forming a first side wall 341 covering the side wall of the first gate 310 and the side wall of the first hard mask layer 331, and forming a second side wall 342 covering the side wall of the second gate 320 and the side wall of the second hard mask layer 332.

[0042] In this embodiment, the materials of the first sidewall 341 and the second sidewall 342 are both silicon nitride. In other embodiments, the materials of the first sidewall 341 and the second sidewall 342 are silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride or boron carbonitride.

[0043] refer to Figure 5 and Figure 6 The first fin 210 on both sides of the first gate 310 is etched to form a first groove 401, and the second fin 220 on both sides of the second gate 320 is etched to form a second groove 402, and the width W1 of the first groove 401 along the extension direction of the first fin 210 is smaller than the width W2 of the second groove 402 along the extension direction of the second fin 220.

[0044] Figure 5The cross-sectional direction is parallel to the extension direction of the first fin 210 and perpendicular to the surface of the substrate 100 in the first region I, and is parallel to the extension direction of the second fin 220 and perpendicular to the surface of the substrate 100 in the second region II. Figure 6 The cross-sectional direction is perpendicular to the extending direction of the first fin 210 in the first region I, and is perpendicular to the extending direction of the second fin 220 in the second region II.

[0045] In this embodiment, the first groove 401 and the second groove 402 are formed in the same process step.

[0046] In this embodiment, a first groove 401 is formed between adjacent first gates 310 , and a second groove 402 is formed between adjacent second gates 320 .

[0047] In this embodiment, the width W1 of the first groove 401 along the extension direction of the first fin 210 is the same as the distance between the first sidewall 341 on the adjacent sidewall of the first gate 310. The width W2 of the second groove 402 along the extension direction of the second fin 220 is the same as the distance between the second sidewall 342 on the adjacent sidewall of the second gate 320.

[0048] Since the first groove 401 and the second groove 402 are formed in the same process step, the process time and the process chamber environment are the same, and the depths of the first groove 401 and the second groove 402 are the same.

[0049] refer to Figure 7 and Figure 8 , forming the first groove 401 covering the sidewall of the first gate 310 and both sides of the first gate 310 (refer to Figure 5 ) sidewall, the sidewall of the second gate 320 and the sacrificial layer 410 on the sidewalls of the second groove 402 on both sides of the second gate 320, such as Figure 8 As shown, the sacrificial layer 410 also covers the top of the pad oxide layer 110 on the substrate 100 in the first region I, and the sacrificial layer 410 exposes the pad oxide layer 110 on the sidewall of the second fin 220 at the bottom of the second groove 402 that is perpendicular to the extension direction of the second gate 320 .

[0050] Figure 7 The cross-sectional direction is parallel to the extension direction of the first fin 210 and perpendicular to the surface of the substrate 100 in the first region I, and is parallel to the extension direction of the second fin 220 and perpendicular to the surface of the substrate 100 in the second region II. Figure 8 The cross-sectional direction is perpendicular to the extending direction of the first fin 210 in the first region I, and is perpendicular to the extending direction of the second fin 220 in the second region II.

[0051] The pad oxide layer 110 is subsequently etched, and the sacrificial layer 410 can protect the covered positions to prevent these positions from being etched.

[0052] In this embodiment, the step of forming the sacrificial layer 410 includes: forming the first groove 401 (refer to Figure 5 ) a sacrificial film (not shown in the figure) covering the sidewalls and bottom of the second groove 402, the top and sidewalls of the second gate 320, and the sidewalls and bottom of the second groove 402 on both sides of the second gate 320, wherein the sacrificial film also covers the top of the pad oxide layer 110 on the substrate 100 located in the first region I and the second region II; the sacrificial film is etched by a dry etching process to remove the sacrificial film at the bottom of the second groove 402, the top of the first gate 310, and the top of the second gate 320, and the sacrificial film on both sides of the second fin 220 located at the bottom of the second groove 402 along the extension direction of the second gate 320 is removed to expose the pad oxide layer 110 on the sidewalls of the second fin 220 located at the bottom of the second groove 402 that are perpendicular to the extension direction of the second gate 320, thereby forming the sacrificial layer 410.

[0053] In this embodiment, since the width W1 of the first groove 401 along the extending direction of the first fin 210 (refer to Figure 5 ) is smaller than the width W2 of the second groove 402 along the extending direction of the second fin 220 (refer to Figure 5 ), in the step of forming the sacrificial film, the sacrificial film fills the first groove 401 and the gap between the adjacent side walls of the first gate 310, so that the formed sacrificial layer 410 can also cover the bottom of the first groove 401, so as to protect the bottom of the first groove 401 in the subsequent process of etching the liner oxide layer 110. On the other hand, the sacrificial film formed in the second groove 402 is U-shaped, and the sacrificial film covering the bottom of the second groove 402 is removed in the dry etching process, so that the formed sacrificial layer 410 exposes the middle area of ​​the bottom of the second groove 402.

[0054] In this embodiment, the material of the sacrificial layer 410 is silicon oxycarbonitride. In other embodiments, the material of the sacrificial layer 410 is silicon nitride, silicon carbide, silicon carbonitride, silicon oxynitride, boron nitride or boron carbonitride.

[0055] refer to Fig. 9 , the sacrificial layer 410 is etched to expose the liner oxide layer 110 , thereby exposing the sidewall of the second fin 220 located at the bottom of the second groove 402 .

[0056] Fig. 9 The cross-sectional direction is perpendicular to the extending direction of the first fin 210 in the first region I, and is perpendicular to the extending direction of the second fin 220 in the second region II.

[0057] In this embodiment, the etched thickness of the pad oxide layer 110 is 3 nm to 20 nm. Accordingly, the sidewall of the second fin 220 at the bottom of the second groove 402 perpendicular to the extending direction of the second gate 320 is exposed by 3 nm to 20 nm.

[0058] In this embodiment, the etched liner oxide layer 110 still covers a portion of the sidewall of the second fin 220 at the bottom of the second groove 402 .

[0059] In the present embodiment, since the sacrificial layer 410 covers the pad oxide layer 110 on the side wall of the first fin 210 at the bottom of the first groove 401, only a portion of the pad oxide layer 110 on the side wall of the second fin 220 at the bottom of the second groove 402 is etched away, so that compared with the first fin 210 in the central area of ​​the bottom of the first groove 401, the exposed area of ​​the side wall of the second fin 220 in the central area of ​​the bottom of the second groove 402 is larger. The subsequent growth of the second source-drain doped layer in the second groove 402 helps to increase the growth rate of the second source-drain doped layer in the central area of ​​the bottom of the second groove 402.

[0060] refer to Fig.10 After etching the sacrificial layer 410 to expose the liner oxide layer 110, the sacrificial layer 410 is removed (refer to Fig. 9 ).

[0061] refer to Fig.11 and Fig.12 In the same process step, an epitaxial growth process is used to form a first source-drain doped layer 510 in the first groove 401 , and an epitaxial growth process is used to form a second source-drain doped layer 520 in the second groove 402 .

[0062] Fig.10 The cross-sectional direction is parallel to the extension direction of the first fin 210 and perpendicular to the surface of the substrate 100 in the first region I, and is parallel to the extension direction of the second fin 220 and perpendicular to the surface of the substrate 100 in the second region II. Fig.11 The cross-sectional direction is perpendicular to the extending direction of the first fin 210 in the first region I, and is perpendicular to the extending direction of the second fin 220 in the second region II.

[0063] In this embodiment, by increasing the exposed area of ​​the sidewalls of the second fin 220 in the bottom center area of ​​the second groove 402 as mentioned above, the growth rate of the second source-drain doped layer 520 in the bottom center area of ​​the second groove 402 can be increased, so that the growth rate of the second source-drain doped layer 520 in the bottom center area of ​​the second groove 402 exceeds the growth rate of the second source-drain doped layer 520 at the sidewalls of the second groove 402, so as to increase the growth volume of the second source-drain doped layer 520, and the growth rate of the second source-drain doped layer 520 in the bottom center area of ​​the second groove 402 even exceeds the growth rate of the first source-drain doped layer 510 in the first groove 401.

[0064] The above-mentioned formation method can modulate the growth rates of the first source-drain doped layer 510 and the second source-drain doped layer 520, so that within the same or similar process time, the first source-drain doped layer 510 fills the first groove 401 and the second source-drain doped layer 520 fills the second groove 402, which helps to simplify the process flow.

[0065] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a first region and a second region, the substrate in the first region having discrete first fins thereon, and the substrate in the second region having discrete second fins thereon; forming a pad oxide layer on the top and sidewalls of the first fin, the top and sidewalls of the second fin, and the substrate; After forming the pad oxide layer, forming a plurality of first gates that are arranged discretely and span the first fin, forming a plurality of second gates that are arranged discretely and span the second fin, and a spacing between adjacent first gates is smaller than a spacing between adjacent second gates; Etching the first fins on both sides of the first gate to form a first groove, and etching the second fins on both sides of the second gate to form a second groove, wherein a width of the first groove along an extension direction of the first fin is smaller than a width of the second groove along an extension direction of the second fin; forming a sacrificial layer covering the first gate sidewall, the first groove sidewalls on both sides of the first gate, the second gate sidewall and the second groove sidewalls on both sides of the second gate, the sacrificial layer also covering the top of the liner oxide layer on the substrate of the first region, and the sacrificial layer exposing the liner oxide layer on the sidewall of the second fin located at the bottom of the second groove and perpendicular to the extension direction of the second gate; Etching the pad oxide layer exposed by the sacrificial layer to expose the sidewall of the second fin located at the bottom of the second groove; removing the sacrificial layer; In the same process step, an epitaxial growth process is used to form a first source-drain doped layer in the first groove, and an epitaxial growth process is used to form a second source-drain doped layer in the second groove.

2. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the sacrificial layer comprises: forming a sacrificial film covering the top and sidewalls of the first gate, the sidewalls and bottom of the first groove on both sides of the first gate, the top and sidewalls of the second gate, and the sidewalls and bottom of the second groove on both sides of the second gate, wherein the sacrificial film also covers the top of the pad oxide layer on the substrate located in the first region and the second region; The sacrificial film is etched to remove the sacrificial film at the bottom of the second groove, the top of the first gate and the top of the second gate, and the sacrificial film on both sides of the second fin at the bottom of the second groove along the extension direction of the second gate is removed to expose the pad oxide layer on the side wall of the second fin at the bottom of the second groove that is perpendicular to the extension direction of the second gate, thereby forming the sacrificial layer.

3. The method for forming a semiconductor structure according to claim 2, wherein: In the step of forming the sacrificial film, the sacrificial film completely fills the first groove and the gap between adjacent first gate sidewalls.

4. The method for forming a semiconductor structure according to claim 2, wherein: The sacrificial film is etched by a dry etching process.

5. The method for forming a semiconductor structure according to claim 1, wherein: In the step of etching the sacrificial layer to expose the pad oxide layer, the etching thickness of the pad oxide layer is 3 nm to 20 nm.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of forming the first gate and the second gate further includes: forming a first hard mask layer on the top of the first gate, and forming a second hard mask layer on the top of the second gate.

7. The method for forming a semiconductor structure according to claim 6, wherein: After forming the first gate and the second gate and before forming the first groove and the second groove, it also includes: forming a first sidewall covering the first gate sidewall and the first hard mask layer sidewall, and forming a second sidewall covering the second gate sidewall and the second hard mask layer sidewall.

8. The method for forming a semiconductor structure according to claim 1, wherein: In the step of forming the first groove and the second groove, one first groove is formed between adjacent first gates, and one second groove is formed between adjacent second gates.

9. The method for forming a semiconductor structure according to claim 1, wherein: The material of the pad oxide layer is silicon oxide.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the sacrificial layer is silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride oxide, silicon nitride oxide, boron nitride or boron carbonitride.

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