Packaging structure and manufacturing method thereof

Abstract

The present invention provides a packaging structure and a manufacturing method thereof, wherein the packaging structure comprises a first chip, a second chip, a dielectric, a conductive terminal, a circuit layer and a patterned insulating layer. The second chip is arranged on the first chip. The second active surface of the second chip faces the first active surface of the first chip. The dielectric covers the first chip. The conductive terminal is located on the dielectric and opposite to the second chip. The circuit layer comprises a first circuit portion and a second circuit portion. The first circuit portion passes through the dielectric. The first chip is electrically connected to the conductive terminal via the first circuit portion. The second circuit portion is embedded in the dielectric. The second chip is electrically connected to the first chip via the second circuit portion. The patterned insulating layer covers the circuit layer and is embedded in the dielectric.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a packaging structure with multiple chips and a manufacturing method thereof. Background Art

[0002] In order to make electronic products thin and light, semiconductor packaging technology has been developing day by day to develop products that meet the requirements of small size, light weight, high density and high competitiveness in the market.

[0003] In a chip package structure with multiple chips, how to improve the quality or efficiency of signal transmission between chips has become an urgent issue to be solved. Summary of the invention

[0004] The present invention is directed to a chip packaging structure and a manufacturing method of the chip packaging structure, which has better signal transmission quality or efficiency.

[0005] According to an embodiment of the present invention, a packaging structure includes a first chip, a second chip, a dielectric, a conductive terminal, a first circuit layer and a first patterned insulating layer. The first chip has a first active surface. The second chip has a second active surface. The second chip is arranged on the first chip in such a way that its second active surface faces the first active surface. The dielectric covers the first chip. The conductive terminal is located on the dielectric and opposite to the second chip. The first circuit layer includes a first circuit portion and a second circuit portion. The first circuit portion passes through the dielectric. The first chip is electrically connected to the conductive terminal via the first circuit portion. The second circuit portion is embedded in the dielectric. The second chip is electrically connected to the first chip via the second circuit portion. The first patterned insulating layer covers the circuit layer and is embedded in the dielectric.

[0006] According to an embodiment of the present invention, a method for manufacturing a packaging structure includes the following steps: providing a carrier; arranging a first chip on the carrier; forming a dielectric on the carrier to cover the first chip; forming a first circuit layer on the carrier, and the first circuit layer includes a first circuit portion and a second circuit portion, wherein the first circuit portion passes through the dielectric, and the second circuit portion is embedded in the dielectric; forming a first patterned insulating layer on the carrier to cover the circuit layer and embed the dielectric; arranging a second chip on the first chip, the second active surface of the second chip faces the first active surface of the first chip, and the second chip is electrically connected to the first chip via the second circuit portion; and removing the carrier to form a conductive terminal on the dielectric relative to the second chip, and the first chip is electrically connected to the conductive terminal via the first circuit portion.

[0007] Based on the above, the chip packaging structure and the manufacturing method of the chip packaging structure of the present invention can have better signal transmission quality or efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1E is a partial cross-sectional schematic diagram of a partial manufacturing method of a packaging structure according to a first embodiment of the present invention;

[0009] Figure 1F is a cross-sectional schematic diagram of a packaging structure according to a first embodiment of the present invention;

[0010] Figure 1G is a partial cross-sectional schematic diagram of a packaging structure according to a first embodiment of the present invention;

[0011] Figure 2 is a cross-sectional schematic diagram of a packaging structure according to a second embodiment of the present invention;

[0012] Figure 3 is a schematic cross-sectional view of a packaging structure according to a third embodiment of the present invention.

[0013] Description of Reference Numerals

[0014] 100, 200, 300: packaging structure;

[0015] 110: first chip;

[0016] 110a: first active surface;

[0017] 110b: first back side;

[0018] 110c: first side surface;

[0019] 120: second chip;

[0020] 120a: second active surface;

[0021] 120b: second back side;

[0022] 120c: second side surface;

[0023] 111, 121: base material;

[0024] 112, 122: chip connection pads;

[0025] 113, 123: chip insulation layer;

[0026] 124: chip protection layer;

[0027] 125: chip terminal;

[0028] 125s: seed layer;

[0029] 125p: plating layer;

[0030] 125r: conductive connection layer;

[0031] 130: Re-wiring layer;

[0032] 131, 133: conductive layer;

[0033] 132, 134: insulation layer;

[0034] 134d: opening;

[0035] 140: Dielectric;

[0036] 140d, 140e: dielectric openings;

[0037] 140a: dielectric top surface;

[0038] 140b: dielectric bottom surface;

[0039] 150: first circuit layer;

[0040] 150a: conductive top surface;

[0041] 150b: conductive bottom surface;

[0042] 150c: conductive side;

[0043] 151: first line section;

[0044] 152: Second line section;

[0045] 151s, 152s, 153s: seed layer;

[0046] 151p, 152p, 153p: plating layer;

[0047] 160: a first patterned insulating layer;

[0048] 160d: Insulation opening;

[0049] 178: conductive connector;

[0050] 179: conductive terminal;

[0051] F1, F2: interface;

[0052] 184: adhesive layer;

[0053] 181: filling layer;

[0054] 282, 382: molded body;

[0055] 383: Thermal interface materials;

[0056] 384: heat sink;

[0057] 92: release layer;

[0058] 91: Carrier board. DETAILED DESCRIPTION

[0059] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0060] Directional terms used herein (e.g., up, down, right, left, front, back, top, bottom) are used only for reference to the drawings and are not intended to imply an absolute orientation. In addition, for clarity of representation, some layers or components may be omitted in the drawings.

[0061] Unless otherwise limited, the terms "disposed," "connected," "contacted," and other similar terms herein are used in a broad sense and encompass direct and indirect dispositions, connections, contacts, and other similar terms. Similarly, the terms "facing," "faces," and the like herein are used in a broad sense and encompass direct and indirect facing. Accordingly, the drawings and descriptions should be regarded as illustrative in nature and not restrictive.

[0062] Unless expressly stated otherwise, it is in no way intended that any method described herein be construed as requiring that its steps be performed in a specific order.

[0063] The present invention is more fully described with reference to the accompanying drawings of the present embodiment. However, the present invention may be embodied in various forms and should not be limited to the embodiments described herein. The thickness, size or size of the layers or regions in the drawings may be exaggerated for clarity. The same or similar reference numbers represent the same or similar components, and the following paragraphs will not be repeated one by one.

[0064] Figures 1A to 1E It is a partial cross-sectional schematic diagram of a partial manufacturing method of a packaging structure according to the first embodiment of the present invention.

[0065] Please refer to Figure 1A , providing a carrier 91. The present invention has no particular limitation on the carrier 91, as long as the carrier 91 is suitable for carrying the film layer formed thereon or the components disposed thereon.

[0066] In this embodiment, the carrier 91 may have a release layer 92, but the present invention is not limited thereto. The release layer 92 is, for example, a light to heat conversion (LTHC) adhesive layer or other similar film layers.

[0067] Please continue to refer to Figure 1AIn the present embodiment, a redistribution wiring layer 130 may be formed on the carrier 91. The redistribution wiring layer 130 may include conductive layers 131, 133 and insulating layers 132, 134. The top insulating layer 134 (i.e., the insulating layer farthest from the carrier 91 in the redistribution wiring layer 130; may be referred to as: the second patterned insulating layer) may have a plurality of openings 134d, and the openings 134d may expose the top conductive layer 133 (i.e., the conductive layer farthest from the carrier 91 in the redistribution wiring layer 130; may be referred to as: the second wiring layer). The redistribution wiring layer 130 may be formed by commonly used semiconductor processes (such as: deposition processes, lithography processes and / or etching processes), and therefore will not be described in detail here.

[0068] Please continue to refer to Figure 1A , a first chip 110 is disposed on the carrier 91. In this embodiment, the first chip 110 may be disposed on the redistribution wiring layer 130, but the present invention is not limited thereto.

[0069] In the present embodiment, the first chip 110 may include a substrate 111, a plurality of chip connection pads 112 (which may be referred to as: first chip connection pads) and a chip insulation layer 113 (which may be referred to as: first chip insulation layer). One side of the substrate 111 has a component area (not shown), and the surface where the component area is located may be referred to as a first active surface 110a. The surface relative to the first active surface 110a may be referred to as a first back surface 110b. The surface connected between the first active surface 110a and the first back surface 110b may be referred to as a first side surface 110c. The chip connection pad 112 may be located on the first active surface 110a. The chip insulation layer 113 may cover the chip connection pad 112, and the chip insulation layer 113 exposes a portion of the chip connection pad 112. In general chip design, components in a component area (eg, components in the component area of ​​the first chip 110 ) can be electrically connected to corresponding die pads (eg, some die pads 112 of the first chip 110 ) via corresponding back end of line interconnects (BEOL interconnects).

[0070] In this embodiment, the chip connection pad 112 is, for example, an aluminum pad, a copper pad or other suitable chip connection pads, but the invention is not limited thereto.

[0071] In one embodiment, the first back side 110 b of the first chip 110 may have an adhesive layer 184 , but the present invention is not limited thereto. The adhesive layer 184 may include a die attach film (DAF), but the present invention is not limited thereto.

[0072] Please refer to Figure 1A to Figure 1B, a dielectric body 140 is formed on the carrier 91. The dielectric body 140 may cover the first chip 110. For example, the dielectric body 140 may cover the first active surface 110a and the first side surface 110c of the first chip 110. The dielectric body 140 may have a second dielectric opening 140e exposing the chip connection pad 112. In one embodiment, the dielectric body 140 may be formed by coating or other suitable processes, but the present invention is not limited thereto.

[0073] In the present embodiment, the dielectric 140 may be formed on the redistribution wiring layer 130, but the present invention is not limited thereto. The dielectric 140 may have a first dielectric opening 140d exposing the topmost conductive layer 134. For example, a photosensitive dielectric material (photoimageable dielectric material; PID material) may be coated on the redistribution wiring layer 130. Then, part of the photosensitive dielectric material may be cured by photopolymerization and / or baking. Furthermore, after curing part of the photosensitive dielectric material, the remaining uncured photosensitive dielectric material may be removed by wet cleaning or other suitable methods. In this way, a dielectric 140 having a first dielectric opening 140d and a second dielectric opening 140e may be formed by the above method.

[0074] In one embodiment, the formation method of the dielectric 140 can be adjusted according to its properties, which is not limited in the present invention.

[0075] Please refer to Figure 1B to Figure 1C , a first circuit layer 150 is formed on the carrier 91. The first circuit layer 150 can cover the dielectric 140, and the first circuit layer 150 can fill the first dielectric opening 140d (indicated at Figure 1B ) and the second dielectric opening 140e (indicated at Figure 1B ).

[0076] In the present embodiment, the first circuit layer 150 can be formed by a sputtering process, a lithography process, an electroplating process and / or an etching process, but the present invention is not limited thereto. For example, a seed layer can be formed on the surface of the dielectric 140 by a sputtering process. Then, a patterned photoresist layer can be formed on the seed layer by a lithography process. Then, a plating layer can be formed on the portion of the seed layer exposed by the patterned photoresist layer by an electroplating process. Then, the patterned photoresist layer and another portion of the seed layer not covered by the plating layer can be removed by an etching process. The patterned seed layers 151s, 152s, 153s (indicated in Figure 1G ) and the patterned plating layers 151p, 152p, 153p (indicated at Figure 1G ) can constitute a patterned first circuit layer 150.

[0077] In this embodiment, the first wiring layer 150 may include a first wiring portion 151. The first wiring portion 151 may be located in the first dielectric opening 140d (indicated at Figure 1B The portion of the first line portion 151 located in the first dielectric opening 140d may conformally cover the bottom and sidewalls of the first dielectric opening 140d.

[0078] In this embodiment, the first line portion 151 can completely fill the opening 134d (indicated by Figure 1B ). The first wiring portion 151 can directly contact the topmost conductive layer 133 in the redistribution wiring layer 130. For example, the patterned seed layer (indicated in FIG. 1 ) belonging to the first wiring portion 151 Figure 1G ) can directly contact part of the conductive layer 133.

[0079] In this embodiment, the first circuit portion 151 and the conductive layer 133 are formed through different steps. Thus, the first circuit portion 151 and the conductive layer 133 in contact may have an interface F1 (indicated by Figure 1G For example, the portion of the patterned seed layer 151s (indicated by Figure 1G ) may have an interface F1 between the conductive layer 133.

[0080] In this embodiment, the first wiring layer 150 may include a second wiring portion 152. The second wiring portion 152 may be located in the second dielectric opening 140e (indicated at Figure 1B ), and the second line portion 152 can completely fill the second dielectric opening 140e. The second line portion 152 can directly contact the chip connection pad 112 of the first chip 110. For example, the patterned seed layer 152s belonging to the second line portion 152 can directly contact the chip connection pad 112 of the first chip 110.

[0081] Please refer to Figure 1C to Figure 1D , a first patterned insulating layer 160 is formed on the carrier 91. The material of the first patterned insulating layer 160 may include an inorganic material, an organic material, other suitable insulating materials or a stack of the above, which is not limited by the present invention. In one embodiment, the formation method of the first patterned insulating layer 160 can be adjusted according to its properties, which is not limited by the present invention.

[0082] In this embodiment, the first patterned insulating layer 160 may cover the first wiring layer 150. The first patterned insulating layer 160 may have a plurality of insulating openings 160d to expose a portion of the first wiring layer 150. For example, the insulating openings 160d may expose a portion of the second wiring portion 152.

[0083] In this embodiment, the first patterned insulating layer 160 may contact the dielectric body 140. For example, the first patterned insulating layer 160 may directly contact a portion of the dielectric top surface 140a of the dielectric body 140 (ie, the surface of the first patterned insulating layer 160 farthest from the carrier 91 or the redistribution wiring layer 130).

[0084] In this embodiment, the first patterned insulating layer 160 and the dielectric body 140 are formed by different steps. Thus, the first patterned insulating layer 160 and the dielectric body 140 in contact may have an interface F2 (indicated by Figure 1G ).

[0085] In this embodiment, a portion of the first patterned insulating layer 160 may be filled into the second dielectric opening 140e (indicated by Figure 1B ). In this way, the possibility of peeling of the first circuit portion 151 located in the second dielectric opening 140e can be reduced. In addition, when forming the first circuit layer 150, the thickness of the plating can be reduced, thereby improving the manufacturing efficiency of the packaging structure.

[0086] Please refer to Figure 1D to Figure 1E After forming the first patterned insulating layer 160 , the second chip 120 may be placed on the first chip 110 . The second chip 120 may be electrically connected to the first chip 110 via the conductive connection member 178 .

[0087] In the present embodiment, the second chip 120 may include a substrate 121, a plurality of chip connection pads 122 (which may be referred to as: second chip connection pads), a chip insulation layer 123 (which may be referred to as: second chip insulation layer), a chip protection layer 124, and a plurality of chip terminals 125. One side of the substrate 121 has a component area (not shown), and the surface where the component area is located may be referred to as a second active surface 120a. The surface relative to the second active surface 120a may be referred to as a second back surface 120b. The surface connected between the second active surface 120a and the second back surface 120b may be referred to as a second side surface 120c. The chip connection pad 122 may be located on the second active surface 120a. The chip insulation layer 123 may cover the chip connection pad 122, the chip protection layer 124 may cover the chip insulation layer 123, and the chip insulation layer 123 and the chip protection layer 124 may expose a portion of the chip connection pad 122. In a general chip design, components in the component area (e.g., components in the component area of ​​the second chip 120) can be electrically connected to corresponding connection pads (e.g., part of the chip connection pads 122 of the second chip 120) via corresponding back-end metal interconnects (BEOL Interconnect). The chip terminal 125 may include a seed layer 125s (indicated at Figure 1G ), the plating layer 125p (marked on Figure 1G ) and the conductive connection layer 125r (indicated at Figure 1G ), but the present invention is not limited thereto. In one embodiment, the seed layer 125s of the chip terminal 125 may directly contact the chip connection pad 122, and the plating layer 125p may be located between the seed layer 125s and the conductive connection layer 125r, but the present invention is not limited thereto. The chip connection pad 122 may be electrically connected to the corresponding conductive connection member 178 via the corresponding chip terminal 125.

[0088] In one embodiment, the conductive connector 178 may be a solder ball, a conductive bump, or a conductive connector 178 having other forms or shapes. The conductive connector 178 may be formed by ball placement, reflow, and / or other suitable processes.

[0089] In this embodiment, a filling layer 181 may be formed between the second chip 120 and the first patterned insulating layer 160. The filling layer 181 may include capillary underfill (CUF) or other suitable underfill, but the present invention is not limited thereto.

[0090] Please continue to refer to Figure 1D to Figure 1EIn the present embodiment, after the carrier 91 is removed, a plurality of conductive terminals 179 may be formed. The conductive terminal 179 may be a conductive pillar, a solder ball, a conductive bump, or a conductive terminal 179 having other forms or shapes. The conductive terminal 179 may be formed by electroplating, deposition, ball placement, reflow, and / or other suitable processes. The conductive terminal 179 may be electrically connected to the corresponding first circuit portion 151 in the first circuit layer 150 via the corresponding circuit in the redistribution circuit layer 130.

[0091] Please refer to Figure 1E In this embodiment, a singulation process may be performed to at least cut through the redistribution wiring layer 130, the dielectric 140, and the first patterned insulating layer 160. The singulation process may include a dicing process (cutting process), but the present invention is not limited thereto.

[0092] It is worth noting that after the singulation process, similar component symbols will be used for the singulated components. Figure 1D As shown) after singulation, it can be the first chip 110 (as shown Figure 1E As shown), the redistribution wiring layer 130 (as shown Figure 1D As shown) after singulation, it can be a redistribution wiring layer 130 (as shown Figure 1E As shown), dielectric 140 (as Figure 1D As shown) after singulation, it can be a dielectric body 140 (such as Figure 1E As shown), the first patterned insulating layer 160 (as shown Figure 1D As shown) after singulation, it can be the first patterned insulating layer 160 (as shown Figure 1E Other singularized components will follow the same component symbol rules as above and will not be described or specifically shown here.

[0093] It is worth noting that the present invention does not limit the order of setting the second chip 120, forming the plurality of conductive terminals 179, and the singulation process (if any). For example, the plurality of conductive terminals 179 may be formed after the second chip 120 is set, and then the singulation process is performed. For another example, the singulation process may be performed after the second chip 120 is set, and then the plurality of conductive terminals 179 are formed.

[0094] Figure 1F is a schematic cross-sectional view of a packaging structure according to the first embodiment of the present invention. Figure 1Gis a partial cross-sectional schematic diagram of a packaging structure according to a first embodiment of the present invention. Figure 1G It can be corresponding to Figure 1F Enlarged view of area R1 in the middle. Figure 1F and Figure 1G After the above steps, the production of the packaging structure 100 of this embodiment can be substantially completed.

[0095] The package structure 100 includes a first chip 110, a second chip 120, a dielectric 140, a conductive terminal 179, and a first circuit layer 150. The second chip 120 is disposed on the first chip 110 in a manner that the second active surface 120a faces the first active surface 110a. The dielectric 140 covers the first chip 110. The conductive terminal 179 is located on the dielectric 140 and opposite to the second chip 120. The first circuit layer 150 includes a first circuit portion 151 and a second circuit portion 152. The first circuit portion 151 penetrates the dielectric 140. The first chip 110 is electrically connected to the conductive terminal 179 via the first circuit portion 151. The second circuit portion 152 is embedded in the dielectric 140. The second chip 120 is electrically connected to the first chip 110 via the second circuit portion 152. The first patterned insulating layer 160 covers the first circuit layer 150 and is embedded in the dielectric 140.

[0096] In the present embodiment, the first circuit layer 150 may have a conductive top surface 150a, a conductive bottom surface 150b and a conductive side surface 150c. The conductive top surface 150a may be the surface of the first circuit layer 150 that is farthest from the redistribution circuit layer 130. The conductive bottom surface 150b may be the surface of the first circuit layer 150 that is closest to the redistribution circuit layer 130. The conductive side surface 150c may be the surface connecting the conductive top surface 150a and the conductive bottom surface 150b. The first patterned insulating layer 160 may cover a portion of the conductive top surface 150a and a portion of the conductive side surface 150c of the first circuit layer 150. In this way, the possibility of peeling in the first circuit layer 150 can be reduced.

[0097] In the present embodiment, the position of the conductive top surface 150a (generally referring to the virtual surface extending therefrom) may be between the position of the dielectric top surface 140a (generally referring to the virtual surface extending therefrom) and the position of the dielectric bottom surface 140b (generally referring to the virtual surface extending therefrom), and the position of the dielectric top surface 140a (generally referring to the virtual surface extending therefrom) may be between the position of the conductive top surface 150a (generally referring to the virtual surface extending therefrom) and the position of the conductive bottom surface 150b (generally referring to the virtual surface extending therefrom). In other words, the conductive bottom surface 150b of the first circuit layer 150 is not coplanar with the dielectric bottom surface 140b of the dielectric body 140 (i.e., the surface of the dielectric body 140 closest to the redistribution circuit layer 130), and the conductive top surface 150a of the first circuit layer 150 is not coplanar with the dielectric top surface 140a of the dielectric body 140.

[0098] In this embodiment, the signal transmission distance between the first chip 110 and the second chip 120 is substantially the same as the physical distance between the first chip 110 and the second chip 120. For example, the signal between the first chip 110 and the second chip 120 can be transmitted via the corresponding conductive member (such as: the corresponding conductive connection member 178 and the corresponding second line portion 152), and the distance between the chip connection pad 112 of the first chip 110 and the chip terminal 125 of the second chip 120 is substantially equal to the height or thickness of the aforementioned conductive member (such as: the height of the corresponding conductive connection member 178 and the thickness of the corresponding second line portion 152). In this way, the quality and efficiency of signal transmission between the first chip 110 and the second chip 120 may be improved.

[0099] Generally speaking, in a conductor composed of multiple conductive structures, a signal transmitted along the conductor will have a corresponding reflected signal due to discontinuity between the multiple conductive structures (e.g., interfaces or impedance mismatches due to different materials or lattices). This phenomenon can be called return loss. Therefore, compared to the signal transmission between chips in a general rewiring manner, the quality and efficiency of the signal transmission between the first chip 110 and the second chip 120 may be improved through the corresponding conductive connector 178 and the corresponding second line portion 152.

[0100] In one embodiment, the first chip 110 and the second chip 120 may be dies, packaged chips, stacked chip packages, or application-specific integrated circuits (ASICs) with the same or different functions, but the present invention is not limited thereto.

[0101] In one embodiment, the first chip 110 and the second chip 120 may be heterogeneous chips. For example, one of the first chip 110 and the second chip 120 may be a dynamic random access memory chip (DRAM), a static random access memory chip (SRAM) or a high bandwidth memory (HBM) chip, and the other of the first chip 110 and the second chip 120 may be an application-specific integrated circuit chip (ASIC), an application processor (AP), a system on chip (SoC) or other similar high performance computing (HPC) chips, but the present invention is not limited thereto.

[0102] Figure 2 The package structure 200 of the second embodiment is similar to the package structure 100 of the first embodiment, and similar components are denoted by the same reference numerals and have similar functions, materials or formation methods, and description thereof is omitted.

[0103] Please refer to Figure 2 The package structure 200 may include a first chip 110, a second chip 120, a dielectric 140, a conductive terminal 179, a first circuit layer 150, and a mold 282. The mold 282 covers the second chip 120. For example, the mold 282 may cover the second side surface 120c of the second chip 120. In one embodiment, the material of the mold 282 may include epoxy resin or other suitable molding compounds, but the present invention is not limited thereto. The mold 282 is, for example, formed by a molding process, but the present invention is not limited thereto.

[0104] In this embodiment, the molding body 282 may further cover the second back surface 120 b of the second chip 120 , but the present invention is not limited thereto.

[0105] Figure 3 The package structure 300 of the third embodiment is similar to the package structure 200 of the second embodiment, and similar components are denoted by the same reference numerals, have similar functions, materials or formation methods, and description thereof is omitted.

[0106] Please refer to Figure 3 The package structure 300 may include a first chip 110, a second chip 120, a dielectric body 140, a conductive terminal 179, a first circuit layer 150, a mold 382, ​​and a heat sink 384. The mold 382 may expose the second back side 120b of the second chip 120. The heat sink 384 may be thermally coupled to the second chip 120.

[0107] In the present embodiment, a thermal interface material (TIM) 383 may be provided between the second back surface 120 b of the second chip 120 and the heat sink 384 , but the present invention is not limited thereto.

[0108] In one embodiment, the second back surface 120 b of the second chip 120 may directly contact the heat sink 384 , but the present invention is not limited thereto.

[0109] In one embodiment, a heat sink similar to the heat sink 384 may have fins, but the invention is not limited thereto.

[0110] In summary, the chip packaging structure and the manufacturing method of the chip packaging structure of the present invention can have better signal transmission quality or efficiency.

[0111] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A packaging structure, It is characterized in that include: Re-routing the circuit layer; A first chip is located on the redistribution wiring layer and has a first active surface; A second chip having a second active surface, and the second chip is arranged on the first chip in a manner that the second active surface faces the first active surface; A dielectric body, located on the redistribution wiring layer and covering the first chip; A conductive terminal, located on the redistribution wiring layer and opposite to the second chip; The first circuit layer comprises a seed layer and a plating layer disposed on the seed layer, wherein a portion of the seed layer and a portion of the plating layer disposed thereon constitute a first circuit portion, and another portion of the seed layer and another portion of the plating layer disposed thereon constitute a second circuit portion, wherein: The first circuit portion passes through the dielectric body, and the first chip is electrically connected to the conductive terminal via the first circuit portion; The second circuit portion is embedded in the dielectric body, and the second chip is electrically connected to the first chip via the second circuit portion; and A portion of the first wiring portion is embedded in the redistribution wiring layer; and A first patterned insulating layer covers the first circuit layer and is embedded in the dielectric body, wherein: The dielectric body has a dielectric bottom surface, the seed crystal layer of the first circuit layer has a conductive bottom surface, the dielectric bottom surface is parallel to the conductive bottom surface, and the dielectric bottom surface is not coplanar with the conductive bottom surface.

2. The packaging structure according to claim 1, It is characterized in that The first chip includes a first connection pad and a first chip insulation layer located on the first active surface, the first chip insulation layer exposes a portion of the first connection pad, and the second circuit portion directly contacts the first connection pad.

3. The packaging structure according to claim 1, It is characterized in that The second chip includes a second connection pad, a second chip insulation layer and a chip terminal located on the second active surface, the second chip insulation layer exposes a portion of the second connection pad, the chip terminal directly contacts the second connection pad, and the packaging structure further includes: The conductive connecting member is disposed between the first chip and the second chip, and the first chip is electrically connected to the chip terminal of the second chip via the conductive connecting member.

4. The packaging structure according to claim 1, It is characterized in that The first patterned insulating layer covers the conductive top surface and the conductive side surface of the first circuit layer.

5. The packaging structure according to claim 1, It is characterized in that The dielectric body is in contact with the first patterned insulating layer, and an interface is formed between the dielectric body and the first patterned insulating layer.

6. The packaging structure according to claim 1, It is characterized in that Also includes: The second circuit layer is located on the dielectric bottom surface of the dielectric body, and the conductive terminal is electrically connected to the first circuit portion via the second circuit layer.

7. The packaging structure according to claim 6, It is characterized in that Also includes: The second patterned insulating layer covers the second circuit layer. The second patterned insulating layer has an insulating opening, and the first circuit portion fills the insulating opening to contact the second circuit layer.

8. The packaging structure according to claim 7, It is characterized in that An interface is provided between the second circuit layer and the first circuit portion.

9. A method for manufacturing a packaging structure, It is characterized in that include: Provide carrier board; forming a redistribution circuit layer on the carrier; Disposing a first chip on the redistribution circuit layer; forming a dielectric on the redistribution wiring layer to cover the first chip; Forming a first circuit layer on the redistribution circuit layer, wherein the first circuit layer includes a seed layer and a plating layer disposed on the seed layer, wherein a portion of the seed layer and a portion of the plating layer disposed thereon constitute a first circuit portion, another portion of the seed layer and another portion of the plating layer disposed thereon constitute a second circuit portion, wherein the first circuit portion penetrates the dielectric and a portion of the first circuit portion is embedded in the redistribution circuit layer, and the second circuit portion is embedded in the dielectric; forming a first patterned insulating layer on the carrier to cover the first circuit layer and embed the dielectric body; Disposing a second chip on the first chip, with the second active surface of the second chip facing the first active surface of the first chip, and electrically connecting the second chip to the first chip via the second circuit portion; as well as The carrier is removed to form a conductive terminal on the dielectric body relative to the second chip, and the first chip is electrically connected to the conductive terminal via the first circuit portion, wherein: The dielectric body has a dielectric bottom surface, the seed crystal layer of the first circuit layer has a conductive bottom surface, the dielectric bottom surface is parallel to the conductive bottom surface, and the dielectric bottom surface is not coplanar with the conductive bottom surface.

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