Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor element and a method of manufacturing the same. The semiconductor element includes a substrate, a first pad over the substrate, and a first redistribution structure including a first redistribution conductive layer over the first pad and a first redistribution thermal release layer over the first redistribution conductive layer. The first redistribution thermal release layer is configured to maintain a thermal resistance between about 0.04 °C cm 2 / Watt to about 0.25 °C cm 2 / Watt.

Description

TECHNICAL FIELD

[0001] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 100,330, filed November 20, 2020, the contents of which are incorporated herein by reference in their entirety.

[0002] The present disclosure relates to a semiconductor element and a method of manufacturing the same. In particular, the present disclosure relates to a semiconductor element having a thermal release layer and a method of manufacturing the same. BACKGROUND

[0003] Semiconductor elements have been used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. The size of semiconductor elements has been continuously scaled down to meet the demand for increasing computing power. However, various problems arise during the scaling down process, which are continuously increasing. Therefore, there are still challenges in improving quality, yield, performance, and reliability, as well as reducing complexity.

[0004] The above “BACKGROUND” description is provided only for better understanding of the present disclosure and does not admit that the above “BACKGROUND” description discloses the subject matter of the present disclosure, does not form the prior art of the present disclosure, and any description of the above “BACKGROUND” should not be considered as part of the present disclosure. SUMMARY

[0005] One aspect of the present disclosure provides a semiconductor element, comprising: a substrate; a first pad over the substrate; and a first redistribution structure comprising a first redistribution conductive layer over the first pad and a first redistribution thermal release layer over the first redistribution conductive layer. The first redistribution thermal release layer is configured to maintain a thermal resistance between about 0.04 °C cm 2 / Watt to about 0.25 °C cm 2 / Watt.

[0006] In some embodiments, the first redistribution thermal release layer comprises an organic material interstitially mixed with a plurality of carbon nanotubes.

[0007] In some embodiments, the first redistribution thermal release layer comprises a fluoropolymer material interstitially mixed with a plurality of carbon nanotubes.

[0008] In some embodiments, the carbon nanotubes have an aspect ratio between about 1 : 1 to about 1 : 100.

[0009] In some embodiments, the first redistribution conductive layer comprises tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or a combination thereof.

[0010] In some embodiments, the first redistribution conductive layer includes a sublayer located on the first pad and an electroplated layer located between the first redistribution heat release layer and the seed layer.

[0011] In some embodiments, the semiconductor element includes a barrier layer located between the first pad and the first redistribution conductive layer.

[0012] In some embodiments, the thickness of the barrier layer is between about 10 angstroms and about 15 angstroms.

[0013] In some embodiments, the barrier layer comprises titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or a combination thereof.

[0014] In some embodiments, the semiconductor device includes an adjustment layer located between the barrier layer and the first redistribution conductive layer, wherein the adjustment layer includes components containing sp 2 Materials composed of carbon atoms.

[0015] In some embodiments, the conditioning layer comprises graphene or graphite.

[0016] In some embodiments, the first pad includes a bottom located above the substrate and a top located on the bottom, the bottom comprising nickel and the top comprising palladium, cobalt, or a combination thereof.

[0017] In some embodiments, the semiconductor device includes a second pad and a second redistribution structure located above the substrate. The second redistribution structure includes a second redistribution conductive layer on the second pad and a second redistribution heat release layer on the second redistribution conductive layer, and the second redistribution heat release layer is configured to maintain a thermal resistance between approximately 0.04 °C / cm². 2 / Watt to approximately 0.25℃cm 2 Between / Watt.

[0018] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a first pad on the substrate; forming a first redistribution conductive layer on the first pad; and forming a first redistribution heat release layer on the first redistribution conductive layer. The first redistribution conductive layer and the first redistribution heat release layer together form a first redistribution structure, and the first redistribution heat release layer is configured to maintain a thermal resistance between approximately 0.04 °C / cm². 2 / Watt to approximately 0.25℃cm 2 Between / Watt.

[0019] In some embodiments, the first redistribution heat release layer comprises an organic material intermittently mixed with a plurality of carbon nanotubes.

[0020] In some embodiments, the first redistribution heat release layer comprises a fluoropolymer material intermittently mixed with a plurality of carbon nanotubes.

[0021] In some embodiments, the first redistribution conductive layer comprises tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or a combination thereof.

[0022] In some embodiments, the step of forming the first pad includes: forming a bottom passivation layer over the substrate; forming a pad opening along the bottom passivation layer; and forming the first pad in the pad opening.

[0023] In some embodiments, the method of fabricating the semiconductor device includes, prior to the step of forming the first pad in the pad opening, a cleaning process and a passivation process of the pad opening, wherein a process temperature of the cleaning process is between about 250°C and about 350°C.

[0024] In some embodiments, a precursor for the passivation process is dimethylaminotrimethylsilane or tetramethylsilane.

[0025] Due to the design of the semiconductor device disclosed herein, the first redistribution heat dissipation layer and the second redistribution heat dissipation layer can improve the heat dissipation capability of the semiconductor device. As a result, the performance and reliability of the semiconductor device can be improved. Furthermore, due to the presence of the conditioning layer, the power consumption of the semiconductor device can be reduced.

[0026] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0027] This disclosure can be read in conjunction with the following figures and detailed description for better understanding. It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of each feature may be arbitrarily enlarged or reduced.

[0028] Figure 1 A flowchart illustrating a method for fabricating a semiconductor element according to an embodiment of the present disclosure is provided.

[0029] Figure 2 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0030] Figure 3 and Figure 4 It is along Figure 2 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0031] Figure 5 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0032] Figure 6 It is along Figure 5 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0033] Figure 7 An embodiment of the present disclosure is illustrated. Figure 5 A close-up top view of the intermediate semiconductor element in the CU region.

[0034] Figure 8 It is along Figure 7 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0035] Figure 9 An embodiment of the present disclosure is illustrated. Figure 5 A close-up top view of the intermediate semiconductor element in the CU region.

[0036] Figure 10 It is along Figure 9 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0037] Figure 11 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0038] Figure 12 It is along Figure 11 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0039] Figure 13 An embodiment of the present disclosure is illustrated. Figure 11 A close-up top view of the intermediate semiconductor element in the CU region.

[0040] Figure 14 It is along Figure 13 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0041] Figure 15A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0042] Figure 16 It is along Figure 15 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0043] Figure 17 An embodiment of the present disclosure is illustrated. Figure 15 A close-up top view of the intermediate semiconductor element in the CU region.

[0044] Figure 18 It is along Figure 17 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0045] Figure 19 It is along Figure 17 A schematic diagram of the cross section drawn by line B-B' in the diagram.

[0046] Figure 20 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0047] Figure 21 and Figure 22 It is along Figure 20 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0048] Figure 23 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure.

[0049] Figure 24 It is along Figure 23 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor device according to an embodiment of the present disclosure.

[0050] Figures 25 to 27 A top view schematic diagram illustrating a semiconductor device according to an embodiment of the present disclosure is shown.

[0051] The reference numerals in the attached figures are explained as follows:

[0052] 1A: Semiconductor components

[0053] 1B: Semiconductor components

[0054] 1C: Semiconductor components

[0055] 1D: Semiconductor components

[0056] 10: Preparation method

[0057] 101: Substrate

[0058] 103: Interconnect layer

[0059] 105: Components and parts

[0060] 107: First conductive pattern

[0061] 109: Second conductive pattern

[0062] 111: Bottom passivation layer

[0063] 113: Top passivation layer

[0064] 121: First Pad

[0065] 121-1: Bottom

[0066] 121-3: Top

[0067] 121TS: Top surface

[0068] 123: Insulating interface layer

[0069] 123BE: Bottom Edge

[0070] 123SW: tapering sidewall

[0071] 125: Second pad

[0072] 201: First Redistribution Structure

[0073] 203: First redistribution overlapping unit

[0074] 203B: Bottom

[0075] 203CSW-1: First curved sidewall

[0076] 203CSW-3: Second curved sidewall

[0077] 203E-1: First Extension

[0078] 203E-3: Second Extension

[0079] 203SW-1: Third sidewall

[0080] 203SW-3: Fourth sidewall

[0081] 205: First redistributed connection unit

[0082] 207: First redistributed contact unit

[0083] 209: First redistributed conductive layer

[0084] 209-1: Seed layer

[0085] 209-3: Electroplating layer

[0086] 211: First redistribution heat release layer

[0087] 213: Barrier layer

[0088] 215: Adjustment Layer

[0089] 301: Second Redistribution Structure

[0090] 303: Second redistribution overlapping unit

[0091] 305: Second redistributed connection unit

[0092] 307: Second redistributed contact unit

[0093] 309: Second redistributed conductive layer

[0094] 311: Second redistribution heat release layer

[0095] 501: Gasket Opening

[0096] 503: Passivation layer opening

[0097] 503BE: Bottom Edge

[0098] 503TE: Top Edge

[0099] 503SW: tapered sidewall

[0100] 601: First mask layer

[0101] 603: First mask opening

[0102] 603CSW: Curved sidewall

[0103] 605: Second mask layer

[0104] 607: Second mask opening

[0105] D1: Distance

[0106] D2: Distance

[0107] D3: Distance

[0108] D4: Distance

[0109] R1: First Region

[0110] R2: Second Region

[0111] S11: Steps

[0112] S13: Steps

[0113] S15: Steps

[0114] S17: Steps

[0115] S19: Steps

[0116] S21: Steps

[0117] W1: Width

[0118] W2: Width

[0119] X: Direction

[0120] Y: direction

[0121] Z: Direction Detailed Implementation

[0122] The following discloses various embodiments or examples of different components that implement the embodiments of this disclosure. Specific examples of elements and their arrangements are described below to simplify the embodiments of this disclosure. These are merely examples and should not be construed as defining the scope of the embodiments of this disclosure. For example, when the description refers to a first component being formed "on" or "on" a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where other components are formed between them without direct contact. Furthermore, reference numerals and / or designations may be repeated in different embodiments of this disclosure. These repetitions are for simplification and clarity and are not intended to define relationships between the different embodiments and / or structures discussed.

[0123] Furthermore, spatial terms such as "below," "below," "lower," "above," "higher," and similar terms are used here to facilitate the description of the relationship between one element or component shown in the diagram and another. These spatial relation terms are used to cover different orientations of the element in use or operation, beyond the orientation depicted in the diagram. The device may be rotated to different orientations (90 degrees or other orientations), and the spatial relation adjectives used therein can be interpreted in the same way.

[0124] It should be understood that when a component or layer is referred to as being "connected to" or "coupled to" another component or layer, it can be a direct connection or coupling to another component or layer, or there may be an intermediate component or layer.

[0125] It should be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. Unless otherwise stated, these terms are used only to distinguish one element from another. Thus, for example, without departing from the teachings of this disclosure, the first element, first component, or first part discussed below may be referred to as the second element, second component, or second part.

[0126] Unless the context otherwise indicates, the use of terms such as “same,” “equal,” “planar,” or “coplanar” in reference to orientation, layout, location, shape, size, quantity, or other measures does not necessarily imply identical orientation, layout, location, shape, size, quantity, or other measures, but is intended to cover orientation, layout, location, shape, size, quantity, or other measures that are substantially identical within acceptable variations, for example, due to manufacturing processes. The term “substantially” may be used in this document to reflect this meaning. For example, items described as “substantially same,” “substantially equal,” or “substantially planar” may be exactly the same, equal, or planar, or may be the same, equal, or planar within acceptable variations, for example, due to manufacturing processes.

[0127] In this disclosure, a semiconductor element generally refers to an element that can perform a function by utilizing the properties of a semiconductor, and electro-optical elements, light-emitting display elements, semiconductor circuits, and electronic elements are all included in the category of semiconductor elements.

[0128] It should be noted that in the description of this disclosure, "above" or "up" corresponds to the direction of the arrow in the Z direction, and "below" or "down" corresponds to the direction of the arrow opposite to the Z direction.

[0129] Figure 1 A flowchart illustrating a method 10 for fabricating a semiconductor element 1A according to an embodiment of the present disclosure is provided. Figure 2 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 3 and Figure 4 It is along Figure 2 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0130] Reference Figures 1 to 4 In step S11, a substrate 101 may be provided, a bottom passivation layer 111 may be formed on the substrate 101, and a first pad 121 may be formed in the bottom passivation layer 111.

[0131] Reference Figure 2 and Figure 3 The substrate 101 may be a bulk semiconductor substrate. For example, the bulk semiconductor substrate may include elemental semiconductors, such as silicon or germanium; compound semiconductors, such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other group III-V compound semiconductors or group II-VI compound semiconductors.

[0132] In some embodiments, substrate 101 may include a semiconductor-on-insulator (SBI) structure comprising, from bottom to top, a handle substrate, an insulating layer, and a topmost semiconductor material layer. The handle substrate and the topmost semiconductor material layer may comprise the same materials as the bulk semiconductor substrate described above. The insulating layer may be a crystalline or amorphous dielectric material, such as an oxide and / or a nitride. The insulating layer may have a thickness between about 10 nm and about 200 nm.

[0133] It should be noted that the term "about" used to modify the amount of ingredients, components, or reactants used in this disclosure refers to quantitative variations that may occur, for example, through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to negligence or errors in measurement procedures, or differences in the manufacture, source, or purity of the ingredients used in the production of the composition or the implementation of the method. On one hand, the term "about" means within 10% of the reported value. On the other hand, the term "about" means within 5% of the reported value. Furthermore, the term "about" also means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0134] Reference Figure 2 and Figure 3 An interconnect layer 103 can be formed on the substrate 101. The interconnect layer 103 may include a dielectric or insulating layer formed on the bulk semiconductor substrate or the topmost semiconductor material layer. The dielectric or insulating layer may include, for example, semiconductor oxides, semiconductor nitrides, semiconductor oxynitrides, semiconductor carbides, tetraethyl orthosilicate oxide, phosphosilica glass, borophosphosilicate glass, fluorinated silica glass, carbon-doped silicon oxide, amorphous fluorinated carbon, or combinations thereof.

[0135] Reference Figure 2 and Figure 3 This can form component 105 (for clarity, only in...) Figure 3(One is shown in the image) is located in the interconnect layer 103. Component 105 can be, for example, a bipolar junction transistor, a metal-oxide-semiconductor field-effect transistor, a diode, a system large-scale integration, flash memory, dynamic random access memory, static random access memory, electrically erasable programmable read-only memory, an image sensor, a microelectromechanical system, an active component, or a passive component. Component 105 can be electrically isolated or insulated from adjacent component components through an insulating structure such as shallow trench isolation.

[0136] Reference Figure 2 and Figure 3 The first conductive pattern 107 may be formed in the interconnect layer 103 and electrically coupled to one of the component members 105. The first conductive pattern 107 may include a plurality of electrically connected wires and a plurality of conductive vias. The first conductive pattern 107 may include, for example, copper, aluminum, titanium, tungsten, similar materials, or combinations thereof. The interconnect layer 103 may act as an insulator to support and electrically isolate or insulate the first conductive pattern 107.

[0137] Reference Figure 2 and Figure 3 A bottom passivation layer 111 may be formed on the interconnect layer 103. The bottom passivation layer 111 may include, for example, silicon oxide or silicon phosphonate glass. As will be explained later, the bottom passivation layer 111 may serve as a stress buffer between the interconnect layer 103 and the top passivation layer 113. Alternatively, in some embodiments, the bottom passivation layer 111 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, polyimide, polybenzoxazole, silicon phosphonate glass, undoped silicate glass, or fluorosilicone glass.

[0138] Reference Figure 2 and Figure 3 A pad opening 501 can be formed along the bottom passivation layer 111. For ease of description, only one pad opening 501 is described. The fabrication technique for the pad opening 501 may include lithography and subsequent etching processes. A portion of the top surface of the topmost conductor of the first conductive pattern 107 can be exposed through the pad opening 501.

[0139] In some embodiments, it is possible toFigure 2 and Figure 3 A cleaning and passivation process is performed on the intermediate semiconductor element to passivate the sidewalls of the bottom passivation layer 111. In some embodiments, the cleaning process can remove oxides oxidized by oxygen from the air from the top surface of the topmost conductor of the first conductive pattern 107 without damaging it. The cleaning process may include applying a mixture of hydrogen and argon as a remote plasma source to the pad opening 501. The cleaning process temperature may be between about 250°C and about 350°C. The cleaning process pressure may be between about 1 Torr and about 10 Torr. A bias energy may be applied to the device performing the cleaning process. The bias energy may be between about 0 W and 200 W.

[0140] The passivation process may include immersing an intermediate semiconductor device in a precursor such as dimethylaminotrimethylsilane, tetramethylsilane, or similar substances at a process temperature between about 200°C and about 400°C. Ultraviolet radiation may be used to facilitate the passivation process. The passivation process can passivate the sidewalls of the gasket opening 501 exposed by the gasket opening 501 by sealing the surface pores of the gasket opening 501. The passivation process can reduce undesirable sidewall growth that may affect the electrical characteristics of the semiconductor device 1A. As a result, the performance and reliability of the semiconductor device 1A can be improved.

[0141] It should be noted that, in the description of this disclosure, the surface of an element (or component) located at the highest vertical level along the Z direction is referred to as the top surface of the element (or component). The surface of an element (or component) located at the lowest vertical level along the Z direction is referred to as the bottom surface of the element (or component).

[0142] Reference Figure 4 A first pad 121 may be formed in the pad opening 501. For ease of description, only one first pad 121 is described. The top surface 121TS of the first pad 121 may be substantially coplanar with the top surface of the bottom passivation layer 111. The first pad 121 may include, for example, aluminum, copper, an aluminum-copper alloy, an aluminum alloy, or a copper alloy. In some embodiments, the first pad 121 may be designed for transmitting high-speed signals. Alternatively, in some embodiments, the first pad 121 may be designed for transmitting low-speed signals.

[0143] Figure 5 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 6 It is along Figure 5The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 7 An embodiment of the present disclosure is illustrated. Figure 5 A close-up top view of the intermediate semiconductor element in the CU region. Figure 8 It is along Figure 7 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0144] Reference Figure 1 and Figures 5 to 8 In step S13, a top passivation layer 113 can be formed on the bottom passivation layer 111, and a plurality of passivation layer openings 503 can be formed along the top passivation layer 113.

[0145] Reference Figure 5 and Figure 6 A top passivation layer 113 can be formed on the bottom passivation layer 111 and the first pad 121. In some embodiments, the top passivation layer 113 may include, for example, silicon nitride, silicon oxynitride, or silicon nitride oxide. The top passivation layer 113 may serve as a high vapor barrier to prevent moisture from entering from above. Alternatively, in some embodiments, the top passivation layer 113 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, polyimide, polybenzoxazole, phosphosilicate glass, undoped silicate glass, or fluorosilicone glass.

[0146] It should be noted that, in the description of this disclosure, silicon oxynitride refers to a substance comprising silicon, nitrogen, and oxygen, wherein the proportion of oxygen is greater than the proportion of nitrogen. Silicon nitride oxide refers to a substance comprising silicon, oxygen, and nitrogen, wherein the proportion of nitrogen is greater than the proportion of oxygen.

[0147] Reference Figure 5 and Figure 6 A passivation layer opening 503 can be formed along the top passivation layer 113 through a lithography process and subsequent etching process. For ease of description, only one passivation layer opening 503 is described. A portion of the top surface 121TS of the first pad 121 can be exposed through the passivation layer opening 503. In some embodiments, the passivation layer opening 503 may include tapered sidewalls 503SW.

[0148] Reference Figure 7 and Figure 8In some embodiments, in a cross-sectional perspective view, each tapered sidewall 503SW can extend from the bottom edge 503BE of the passivation layer opening 503 to the top edge 503TE of the passivation layer opening 503. In a top perspective view, the bottom edge 503BE of the passivation layer opening 503 can be rectangular, and the top edge 503TE of the passivation layer opening 503 can also be rectangular. The bottom edge 503BE of the passivation layer opening 503 can define the exposed area of ​​the top surface 121TS of the first pad 121.

[0149] In some embodiments, it can be done in a manner similar to that of... Figure 2 and Figure 3 The steps performed on the gasket opening 501 shown involve cleaning and passivation processes on the passivation layer opening 503. The passivation process can reduce unwanted sidewall growth, which may affect the electrical characteristics of the semiconductor device 1A. As a result, the performance and reliability of the semiconductor device 1A can be improved.

[0150] Figure 9 An embodiment of the present disclosure is illustrated. Figure 5 A close-up top view of the intermediate semiconductor element in the CU region. Figure 10 It is along Figure 9 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0151] Reference Figure 1 , Figure 9 and Figure 10 In step S15, an insulating interface layer 123 can be formed on the top passivation layer 113.

[0152] Reference Figure 9 and Figure 10 An insulating interface layer 123 may be conformally formed on the top passivation layer 113 to expose the exposed top surface 121TS of the first pad 121. The insulating interface layer 123 may conformally cover the tapered sidewalls 503SW of the passivation layer opening 503 to form corresponding tapered sidewalls 123SW. The bottom edge 123BE of the insulating interface layer 123 may extend to cover the bottom edge 503BE of the passivation layer opening 503 and contact the edge of the exposed top surface 121TS of the first pad 121.

[0153] The insulating interface layer 123 can provide electrical isolation or insulation for the semiconductor element 1A. In some embodiments, the insulating interface layer 123 can provide additional electrical isolation or insulation between conductive components below and above it. In some embodiments, the insulating interface layer 123 may include a photosensitive polymer material, such as polyimide. Alternatively, in some embodiments, the insulating interface layer 123 may include silicon oxide, silicon nitride, silicon carbide nitride, silicon nitride oxide, or silicon oxynitride.

[0154] Figure 11 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 12 It is along Figure 11 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 13 An embodiment of the present disclosure is illustrated. Figure 11 A close-up top view of the intermediate semiconductor element in the CU region. Figure 14 It is along Figure 13 A schematic diagram of the cross section drawn by line A-A' in the diagram.

[0155] Reference Figure 1 and Figures 11 to 14 In step S17, a first mask layer 601 can be formed on the insulating interface layer 123, and a plurality of first mask openings 603 can be formed along the first mask layer 601.

[0156] Reference Figure 11 and 12 The first mask layer 601 may be a photoresist layer. The first mask opening 603 may define the pattern of the first redistribution structure 201. In a top perspective view, the first mask openings 603 may be spaced apart from each other and may be arranged along the Y direction. For ease of description, only one first mask opening 603 is described.

[0157] Reference Figure 13 and Figure 14 In the top perspective view, the first mask opening 603 may include horizontally arranged curved sidewalls 603CSW. The higher curved sidewall 603CSW may have a convex shape. The lower curved sidewall 603CSW may have a concave shape. The vertical distance parallel to the Y direction between the curved sidewalls 603CSW of the first mask opening 603 may vary along the direction X perpendicular to the Y direction from a relatively narrow distance D1 to a relatively wide distance D2. Therefore, the width parallel to the Y direction between the curved sidewall 603CSW of the first mask opening 603 and an adjacent curved sidewall 603CSW of the first mask opening 603 may vary along the direction X from a relatively wide width W1 to a relatively narrow width W2.

[0158] The portion of the first mask layer 601 with a wider width W1 can provide additional structural support to prevent collapse or deformation. In contrast, the portion of the first mask layer 601 with a narrower width W2 may have relatively low resistance to collapse or deformation. That is, the portion of the first mask layer 601 with a narrower width W2 may be relatively fragile. However, the aforementioned structural support can compensate for the relatively fragile portion of the first mask layer 601, suppressing or reducing collapse or deformation of the first mask layer 601. In other words, even if some portions of the first mask opening 603 are located on the tapered sidewall 123SW of the insulating interface layer 123, the first mask layer 601 and the first mask opening 603 can be structurally stable. As a result, the subsequently fabricated first redistribution structure 201 can have a larger planar area, representing lower surface resistivity and better electrical transport performance.

[0159] Figure 15 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 16 It is along Figure 15 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 17 An embodiment of the present disclosure is illustrated. Figure 15 A close-up top view of the intermediate semiconductor element in the CU region. Figure 18 It is along Figure 17 A schematic diagram of the cross section drawn by line A-A' in the diagram. Figure 19 It is along Figure 17 A schematic diagram of the cross section drawn by line B-B' in the diagram.

[0160] Reference Figure 1 and Figures 15 to 19 In step S19, a first redistribution structure 201 can be formed in the first mask opening 603.

[0161] Reference Figure 15 The first redistribution structure 201 may be formed in the first mask opening 603 and electrically coupled to the first pad 121. In a top perspective view, each first redistribution structure 201 may be a conductive pattern extending from a first region R1 to a second region R2. The first region R1 may be spaced apart from the second region R2. In some embodiments, the first region R1 may correspond to the central region of the semiconductor element 1A, and the second region R2 may correspond to the peripheral region or edge region of the semiconductor element 1A.

[0162] In some embodiments, in a top perspective view, each first redistribution structure 201 may include a first redistribution overlapping unit 203, a first redistribution connecting unit 205, and a first redistribution contact unit 207. The first redistribution overlapping units 203 may be arranged in a row parallel to the Y direction and located in a first region R1. The first redistribution contact units 207 may be arranged in a row parallel to the Y direction and located in a second region R2. The first redistribution connecting unit 205 may connect the first redistribution overlapping units 203 and the first redistribution contact units 207. The first redistribution structure 201 may re-route the first pad 121 to obtain more space for wiring or bumping and prevent the first pad 121 from being affected by wiring or bumping stress.

[0163] Reference Figure 16 In the top perspective view, the first redistribution overlapping unit 203 can be formed on the first pad 121. That is, the first redistribution overlapping unit 203 can overlap perpendicularly with the first pad 121. The first redistribution overlapping unit 203 can be electrically connected to the first pad 121. The first redistribution contact unit 207 can be electrically connected to the first pad 121 through the first redistribution connection unit 205 and the first redistribution overlapping unit 203. The first redistribution contact unit 207 can be used for wiring or bumping to electrically couple the semiconductor element 1A to an external element.

[0164] Reference Figure 16 In the cross-sectional perspective view, each first redistribution structure 201 may include a stacked structure. In some embodiments, each first redistribution structure 201 may include a first redistribution conductive layer 209 and a first redistribution heat release layer 211. The first redistribution heat release layer 211 may be formed on the first redistribution conductive layer 209. The first redistribution conductive layer 209 may include the lower portion of the first redistribution overlapping unit 203, the lower portion of the first redistribution connecting unit 205, and the lower portion of the first redistribution contact unit 207. The first redistribution heat release layer 211 may include the higher portion of the first redistribution overlapping unit 203, the higher portion of the first redistribution connecting unit 205, and the higher portion of the first redistribution contact unit 207.

[0165] In some embodiments, the first redistribution conductive layer 209 may include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof. The first redistribution heat release layer 211 may include a carbon material filled with a flexible material such as a polymer matrix. For example, the first redistribution heat release layer 211 may include generally vertically oriented graphite and carbon nanotubes filled with a fluoropolymer rubber matrix. The aspect ratio of the carbon nanotubes may be between about 1:1 and about 1:100. As another example, the first redistribution heat release layer 211 may include graphitic carbon. As yet another example, the first redistribution heat release layer 211 may include a pyrolytic graphite sheet.

[0166] In some embodiments, the thermal resistance of the first redistribution heat release layer 211, when its thickness is between about 250 μm and about 450 μm, can be less than 0.2 °C / cm². 2 / Watt. In some embodiments, the first redistribution heat release layer 211 may be subjected to a compressive force after wiring or bumping. The compressive force may be between about 30 pounds per square inch (psi) and about 90 psi. The thermal resistance of the first redistribution heat release layer 211 under compressive force may be between about 0.3 °C / cm². 2 / Watt to approximately 0.1℃cm 2 Between / Watt. The first redistribution heat release layer 211 can provide heat dissipation capability for the first redistribution structure 201.

[0167] Reference Figure 17In the top perspective view, the first redistribution overlapping unit 203 may include a first curved sidewall 203CSW-1, a second curved sidewall 203CSW-3, a third sidewall 203SW-1, and a fourth sidewall 203SW-3. The first curved sidewall 203CSW-1 is configured and may have a convex shape. The perpendicular distance parallel to the direction Y between adjacent first curved sidewalls 203CSW-1 of the first redistribution overlapping unit 203 may vary along the direction X from a relatively narrow distance D3 to a relatively wide distance D4. The second curved sidewall 203CSW-3 may be opposite to the first curved sidewall 203CSW-1 and may have a concave shape. That is, the first redistribution overlapping unit 203 may be point-symmetric with respect to its center point. For example, the first curved sidewall 203CSW-1 and the second curved sidewall 203CSW-3 may be mirror-symmetric. The third sidewall 203SW-1 can connect the first edge of the first curved sidewall 203CSW-1 to the first edge of the second curved sidewall 203CSW-3. The fourth sidewall 203SW-3 can connect the second edge of the first curved sidewall 203CSW-1 to the second edge of the second curved sidewall 203CSW-3. The third sidewall 203SW-1 and the fourth sidewall 203SW-3 can be flat and parallel to the Y direction. The first redistribution connection unit 205 can connect the third sidewall 203SW-1.

[0168] Reference Figure 18 In the cross-sectional perspective view, the first curved sidewall 203CSW-1 can be positioned to overlap with the tapering sidewall 123SW between the top edge 503TE and the bottom edge 503BE. (Refer to...) Figures 17 to 19 Although most of the first curved sidewall 203CSW-1 is formed to overlap with the tapered sidewall 123SW, the first edge and the second edge of the first curved sidewall 203CSW-1 can be located outside the top edge 503TE to overlap with the flat top surface of the insulating interface layer 123.

[0169] Reference Figure 18In the cross-sectional perspective view, the first redistribution overlapping unit 203 may include a first extension portion 203E-1 extending from the bottom 203B of the first redistribution overlapping unit 203 to the first curved sidewall 203CSW-1. The bottom 203B may be the portion of the first redistribution overlapping unit 203 that directly contacts the first pad 121. Because the side surface of the first curved sidewall 203CSW-1 corresponding to the first extension portion 203E-1 has a convex shape in the top perspective view, the first extension portion 203E-1 may have a crescent shape in the top perspective view. The first extension portion 203E-1 may be formed to overlap with a portion of the tapered sidewall 123SW. In some embodiments, the distance between the first extension portion 203E-1 and the bottom edge 503BE can be defined by controlling the thickness of the insulating interface layer 123.

[0170] Reference Figure 19 The first redistribution overlapping unit 203 may include a second extension portion 203E-3 extending from the bottom 203B to the third sidewall 203SW-1. The second extension portion 203E-3 may extend to the outer region of the tapered sidewall 123SW to overlap with the horizontal top surface of the insulating interface layer 123.

[0171] Reference Figures 17 to 19 The first redistribution overlapping unit 203 may have a nest-like shape, comprising a bottom 203B, a first extension portion 203E-1, and a second extension portion 203E-3. The first extension portion 203E-1 and the second extension portion 203E-3 may extend from the bottom 203B to cover both the bottom edge 123BE and the bottom edge 503BE. Therefore, even if the first redistribution overlapping unit 203 shifts from its normal position due to process variations, the first pad 121 can still be covered by the first redistribution overlapping unit 203. That is, the overlap margin between the first redistribution overlapping unit 203 and the first pad 121 can be increased to significantly suppress or reduce defects in the first pad 121 that are exposed after the formation of the first redistribution overlapping unit 203.

[0172] After the first redistribution structure 201 is formed, the first mask layer 601 can be removed.

[0173] Figure 20 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 21 and Figure 22 It is along Figure 20 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure. Figure 23 A top view schematic diagram illustrating an intermediate semiconductor element according to an embodiment of the present disclosure. Figure 24 It is alongFigure 23 The schematic cross-sectional view drawn by line A-A' illustrates a portion of the fabrication process of a semiconductor element 1A according to an embodiment of the present disclosure.

[0174] Reference Figure 1 and Figures 20 to 24 In step S21, multiple second redistribution structures 301 can be formed on the insulating interface layer 123.

[0175] Reference Figure 20 and Figure 21 A second mask layer 605 can be formed on the insulating interface layer 123 and the first redistribution structure 201. A second mask opening 607 can be formed along the second mask layer 605. The second mask layer 605 can be a photoresist layer. The second mask opening 607 can define the pattern of the second redistribution structure 301. In a top perspective view, the second mask openings 607 can be spaced apart from each other and can be configured along the Y direction. A portion of the passivation layer opening 503 can be exposed through the second mask openings 607. It should be noted that in a top perspective view, the second mask openings 607 do not overlap with the first redistribution structure 201.

[0176] Reference Figure 22 The second redistribution structure 301 can be formed in the second mask opening 607 and electrically coupled to the second pad 125 (for clarity, in Figure 22 (Only one is shown in the image). The second pad 125 can be electrically coupled to the component member 105 via a second conductive pattern 109 formed in the interconnect layer 103. In some embodiments, the second pad 125 can be designed for transmitting high-speed signals. Alternatively, in some embodiments, the second pad 125 can be designed for transmitting low-speed signals.

[0177] Reference Figure 23 and Figure 24The second mask layer 605 can be removed. In the top perspective view, the first redistribution structure 201 and the second redistribution structure 301 can be spaced apart from each other and can also be electrically insulated or isolated from each other. The first redistribution structure 201 and the second redistribution structure 301 can be arranged alternately along the Y direction. Each second redistribution structure 301 may include a second redistribution overlapping unit 303, a second redistribution connecting unit 305, and a second redistribution contact unit 307. The second redistribution overlapping unit 303 can be arranged in a row parallel to the Y direction and located in the first region R1. The second redistribution contact unit 307 can be arranged in a row parallel to the Y direction and located in the second region R2. The second redistribution connecting unit 305 can connect the second redistribution overlapping unit 303 and the second redistribution contact unit 307. The second redistribution structure 301 can redefine the second pad 125 to obtain more space for wiring or bumps and prevent the second pad 125 from being affected by wiring or bump stress.

[0178] In some embodiments, in a top perspective view, the first redistribution overlapping unit 203 and the second redistribution overlapping unit 303 can be formed on a first region R1 and arranged in two columns parallel to the direction Y. For example, the first redistribution overlapping unit 203 can be arranged in one of the two columns, and the second redistribution overlapping unit 303 can be arranged in the other of the two columns. The first redistribution contact unit 207 and the second redistribution contact unit 307 can be formed on a second region R2 and arranged in a column parallel to the direction Y. Because the first redistribution contact unit 207 and the second redistribution contact unit 307 are formed on the second region R2, the first redistribution connecting unit 205 and the second redistribution connecting unit 305 can be a linear pattern extending from the first region R1 to the second region R2. In this case, the second redistribution connecting unit 305 can be spaced apart from the first redistribution overlapping unit 203, and each second redistribution connecting unit 305 can pass through the area between adjacent first redistribution overlapping units 203. For ease of description, only one second redistribution structure 301 is described.

[0179] Reference Figure 23 and Figure 24In a top perspective view, the second redistribution structure 301 may include a stacked structure. In some embodiments, the second redistribution structure 301 may include a second redistribution conductive layer 309 and a second redistribution heat release layer 311. The second redistribution heat release layer 311 may be formed on the second redistribution conductive layer 309. The second redistribution conductive layer 309 may include a lower portion of the second redistribution overlapping unit 303, a lower portion of the second redistribution connecting unit 305, and a lower portion of the second redistribution contact unit 307. The second redistribution heat release layer 311 may include a higher portion of the second redistribution overlapping unit 303, a higher portion of the second redistribution connecting unit 305, and a higher portion of the second redistribution contact unit 307.

[0180] In some embodiments, the second redistribution conductive layer 309 may include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or combinations thereof. The second redistribution heat release layer 311 may include a carbon material filled with a flexible material such as a polymer matrix. For example, the second redistribution heat release layer 311 may include generally vertically oriented graphite and carbon nanotubes filled with a fluoropolymer rubber matrix. The aspect ratio of the carbon nanotubes may be between about 1:1 and about 1:100. As another example, the second redistribution heat release layer 311 may include graphitic carbon. As yet another example, the second redistribution heat release layer 311 may include pyrolytic graphite sheets.

[0181] In some embodiments, the thermal resistance of the second redistributed heat release layer 311, when its thickness is between about 250 μm and about 450 μm, can be less than 0.2 °C / cm². 2 / Watt. In some embodiments, the second redistribution heat release layer 311 may be subjected to compressive force after wiring or bumping. The compressive force may be between about 30 pounds per square inch (psi) and about 90 psi. The thermal resistance of the second redistribution heat release layer 311 under compressive force may be between about 0.3 °C / cm². 2 / Watt to approximately 0.1℃cm 2 Between / Watt. The second redistribution heat release layer 311 can provide heat dissipation capability for the second redistribution structure 301.

[0182] In some embodiments, the second redistribution overlapping unit 303 may have the same characteristics as... Figures 15 to 19 The structure and shape are similar to the first redistributed overlapping unit 203 shown.

[0183] In some embodiments, the thermal resistance of the second redistribution structure 301 may be the same as that of the first redistribution structure 201. In some embodiments, the thermal resistance of the second redistribution structure 301 may be different from that of the first redistribution structure 201. The thermal resistance of the second redistribution structure 301 and the thermal resistance of the first redistribution structure 201 can be adjusted by their thickness.

[0184] In some embodiments, a first redistribution structure 201 with heat dissipation capability can be used to transmit high-speed signals, while a second redistribution structure 301 with heat dissipation capability can be used to transmit low-speed signals, and vice versa.

[0185] Figures 25 to 27 A top view schematic diagram illustrating semiconductor elements 1B, 1C, and 1D according to an embodiment of the present disclosure is shown.

[0186] Reference Figure 25 Semiconductor element 1B can have similar characteristics to... Figure 19 The structure shown. Figure 25 Zhongyu Figure 19 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0187] Reference Figure 25 The first redistributed conductive layer 209 may include a seed layer 209-1 and an electroplated layer 209-3. The seed layer 209-1 may be disposed on the first pad 121. The electroplated layer 209-3 may be disposed on the seed layer 209-1. The electroplated layer 209-3 may include, for example, tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or a combination thereof.

[0188] Reference Figure 26 Semiconductor element 1C can have similar characteristics to Figure 19 The structure shown. Figure 26 Zhongyu Figure 19 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0189] Reference Figure 26 The first redistribution structure 201 may include a barrier layer 213 and an adjustment layer 215. The barrier layer 213 may be disposed between the first redistribution conductive layer 209 and the first pad 121, and between the first redistribution conductive layer 209 and the insulating interface layer 123. The thickness of the barrier layer 213 may be between about 10 angstroms and about 15 angstroms. In some embodiments, the thickness of the barrier layer 213 may be between about 11 angstroms and about 13 angstroms. The barrier layer 213 may include, for example, titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or combinations thereof. The barrier layer 213 may serve as an adhesive layer between the first pad 121 and the first redistribution conductive layer 209. The barrier layer 213 may also prevent metal ions from the first redistribution conductive layer 209 from diffusing to the top passivation layer 113 or the insulating interface layer 123.

[0190] Reference Figure 26 The adjustment layer 215 may be disposed between the first redistributed conductive layer 209 and the barrier layer 213. In some embodiments, the adjustment layer 215 may include, for example, a layer containing sp2 Materials composed of carbon atoms. In some embodiments, the adjustment layer 215 may include, for example, a material containing carbon having a hexagonal crystal structure. In some embodiments, the adjustment layer 215 may include, for example, graphene, graphite, or similar materials. In some embodiments, the adjustment layer 215 may include, for example, graphene. Because the adjustment layer 215 formed of graphene has good conductivity, the resistance between the first redistributed conductive layer 209 and the first pad 121 can be reduced. Therefore, the power consumption of the semiconductor device 1C can be reduced.

[0191] Reference Figure 27 Semiconductor element 1D can have similar characteristics to Figure 19 The structure shown. Figure 27 Zhongyu Figure 19 Identical or similar elements have been marked with similar reference symbols and repeated descriptions have been omitted.

[0192] Reference Figure 27 The first pad 121 may include a bottom 121-1 and a top 121-3. The bottom 121-1 may be disposed on the interconnect layer 103. The top 121-3 may be disposed on the bottom 121-1. The bottom 121-1 may include nickel. The top 121-3 may include palladium, cobalt, or a combination thereof.

[0193] One aspect of this disclosure provides a semiconductor device, comprising: a substrate; a first pad located above the substrate; and a first redistribution structure including a first redistribution conductive layer on the first pad and a first redistribution heat release layer on the first redistribution conductive layer. The first redistribution heat release layer is configured to maintain a thermal resistance between approximately 0.04 °C / cm². 2 / Watt to approximately 0.25℃cm 2 Between / Watt.

[0194] Another aspect of this disclosure provides a method for fabricating a semiconductor device, comprising: providing a substrate; forming a first pad on the substrate; forming a first redistribution conductive layer on the first pad; and forming a first redistribution heat release layer on the first redistribution conductive layer. The first redistribution conductive layer and the first redistribution heat release layer together form a first redistribution structure, and the first redistribution heat release layer is configured to maintain a thermal resistance between approximately 0.04 °C / cm². 2 / Watt to approximately 0.25℃cm 2 Between / Watt.

[0195] Due to the design of the semiconductor device disclosed herein, the first redistribution heat dissipation layer 211 and the second redistribution heat dissipation layer 311 can improve the heat dissipation capability of the semiconductor device 1A. As a result, the performance and reliability of the semiconductor device 1A can be improved. Furthermore, due to the presence of the conditioning layer 215, the power consumption of the semiconductor device 1C can be reduced.

[0196] It should be noted that the terms “forming,” “formed,” and “form” can refer to and include any method of creating, building, patterning, implanting, or depositing elements, dopants, or materials. Examples of forming methods may include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, co-sputtering, spin coating, diffusion, deposition, growth, implantation, photolithography, dry etching, and wet etching.

[0197] It should be noted that the functions or steps mentioned herein may occur in a different order than those shown in the diagrams. For example, depending on the functions or steps involved, two diagrams displayed consecutively may actually be performed substantially simultaneously or sometimes in reverse order.

[0198] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined by the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0199] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, matter formations, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, matter formations, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Therefore, such processes, machinery, manufacturing, matter formations, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: One substrate; A first pad is located above the substrate; as well as A first redistribution structure includes a first redistribution conductive layer located on the first pad and a first redistribution heat release layer located on the first redistribution conductive layer; A barrier layer is located between the first pad and the first redistributed conductive layer; The first redistributed heat release layer is configured to maintain a thermal resistance of approximately 0.04 °C / cm². 2 / Watt to approximately 0.25℃cm 2 Between / Watt The first redistribution heat release layer includes an organic material that is intermittently mixed with multiple carbon nanotubes. The first redistribution heat release layer comprises a fluoropolymer material intermittently mixed with multiple carbon nanotubes. The aspect ratio of the carbon nanotubes is between about 1:1 and about 1:

100.

2. The semiconductor device of claim 1, wherein the first redistribution conductive layer comprises tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or a combination thereof.

3. The semiconductor device of claim 1, wherein the first redistribution conductive layer comprises a sublayer located on the first pad and an electroplated layer located between the first redistribution heat release layer and the seed layer.

4. The semiconductor device of claim 1, wherein the thickness of the barrier layer is between about 10 angstroms and about 15 angstroms.

5. The semiconductor device of claim 4, wherein the barrier layer comprises titanium, titanium nitride, titanium silicon nitride, tantalum, tantalum nitride, tantalum silicon nitride, or a combination thereof.

6. The semiconductor device of claim 5, further comprising an adjustment layer located between the barrier layer and the first redistribution conductive layer, wherein the adjustment layer comprises a layer containing sp 2 Materials composed of carbon atoms.

7. The semiconductor device of claim 6, wherein the conditioning layer comprises graphene or graphite.

8. The semiconductor device of claim 1, wherein the first pad includes a bottom located above the substrate and a top located on the bottom, the bottom comprising nickel and the top comprising palladium, cobalt, or a combination thereof.

9. The semiconductor device of claim 1, further comprising a second pad and a second redistribution structure located above the substrate, wherein the second redistribution structure includes a second redistribution conductive layer on the second pad and a second redistribution heat release layer on the second redistribution conductive layer, and the second redistribution heat release layer is configured to maintain a thermal resistance between about 0.04 °C / cm². 2 / Watt to approximately 0.25℃cm 2 Between / Watt.

10. A method for fabricating a semiconductor device, comprising: Provide a substrate; A first pad is formed on the substrate; A first redistributed conductive layer is formed on the first pad; as well as A first redistribution heat release layer is formed on the first redistribution conductive layer; A barrier layer is formed between the first pad and the first redistribution conductive layer; The first redistributed conductive layer and the first redistributed heat release layer together form a first redistributed structure, and the first redistributed heat release layer is configured to maintain a thermal resistance between approximately 0.04 °C / cm². 2 / Watt to approximately 0.25℃cm 2 Between / Watt The first redistribution heat release layer includes an organic material that is intermittently mixed with multiple carbon nanotubes. The first redistribution heat release layer comprises a fluoropolymer material intermittently mixed with multiple carbon nanotubes. The aspect ratio of the carbon nanotubes is between about 1:1 and about 1:

100.

11. The method for fabricating a semiconductor element as claimed in claim 10, wherein the first redistribution heat release layer comprises an organic material intermittently mixed with a plurality of carbon nanotubes.

12. The method for fabricating a semiconductor element as claimed in claim 10, wherein the first redistribution heat release layer comprises a fluoropolymer material intermittently mixed with a plurality of carbon nanotubes.

13. The method for fabricating a semiconductor element as claimed in claim 11, wherein the first redistribution conductive layer comprises tungsten, titanium, tin, nickel, copper, gold, aluminum, platinum, cobalt, or a combination thereof.

14. The method for fabricating a semiconductor device as claimed in claim 13, wherein the step of forming the first pad comprises: A bottom passivation layer is formed on the substrate; A liner opening is formed along the bottom passivation layer; as well as The first liner is formed in the liner opening.

15. The method for fabricating a semiconductor device as described in claim 14, further comprising: Prior to the step of forming the first liner in the liner opening, the liner opening is subjected to a cleaning process and a passivation process, wherein the cleaning process is performed at a temperature between about 250°C and about 350°C.

16. The method for fabricating a semiconductor device as described in claim 15, wherein a precursor of the passivation process is dimethylaminotrimethylsilane or tetramethylsilane.

Images