Method and related structure for authenticating integrated circuit using authentication film

Abstract

The present invention relates to methods and related structures for authenticating an integrated circuit using an authentication film. The present disclosure provides a method for authenticating an integrated circuit (IC) structure. The method may include forming a first authentication film (AF) material within the IC structure. The composition of the first AF material differs from adjacent materials within the IC structure. The method may include converting the first AF material into voids within the IC structure. Furthermore, the method may include creating an authentication layout for the IC structure, including locations of voids within the IC structure for authenticating the IC structure.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to authentication of integrated circuits (ICs). More specifically, embodiments of the present disclosure provide structures and methods for authenticating ICs using authentication film (AF) materials. Background Art

[0002] The ability to reverse engineer chips is a growing concern within the microelectronics industry. As reverse engineering becomes more prevalent, counterfeit chips have begun to enter the supply chain. In some cases, external entities with temporary custody of products in the supply chain are able to insert additional circuitry, or "backdoors," into sensitive active parts of the product.

[0003] Counterfeiting and / or tampering occur in many situations. In the example of medical devices, the effects of counterfeit chips can range from harmless effects (e.g., irrelevant data on a display) to serious malfunctions (e.g., unstable pacemaker clocking). In some cases, these effects may be difficult to distinguish from random errors and / or aging degradation. As collaboration between global manufacturers becomes increasingly important for manufacturing efficiency, potential tampering vulnerabilities in the supply chain are becoming increasingly important to manufacturers and consumers. Summary of the Invention

[0004] Some aspects of the present disclosure provide a method for authenticating an integrated circuit (IC) structure, the method comprising: forming a first authentication film (AF) material within the IC structure, wherein the composition of the first AF material is different from that of adjacent materials within the IC structure; converting the first AF material into voids within the IC structure; and creating an authentication map for the IC structure, the authentication map comprising positions of the voids in the IC structure for authenticating the IC structure.

[0005] Other aspects of the present disclosure provide an integrated circuit (IC) structure comprising: a polyimide layer positioned above a plurality of metal wiring layers, the polyimide layer comprising a first region having at least one electro-active element and a second region horizontally distal to the at least one electro-active element; and a void within the second region of the polyimide layer, wherein the position of the void within the polyimide layer defines an authentication pattern of the IC structure.

[0006] Other aspects of the present disclosure disclose an integrated circuit (IC) structure comprising: a polyimide layer; a metal wiring layer located below the polyimide layer, the metal wiring layer comprising a first region having at least one electro-active element and a second region horizontally away from the at least one electro-active element; and a void located within the second region of the metal wiring layer, wherein the position of the void within the metal wiring layer defines an authentication pattern of the IC structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] These and other features of the present disclosure will be more readily understood from the following detailed description of various aspects of the present disclosure, taken in conjunction with the accompanying drawings, which illustrate various embodiments of the present disclosure, in which:

[0008] Figure 1 A cross-sectional view of an IC structure with authentication film (AF) material according to an embodiment of the present disclosure is shown.

[0009] Figure 2 A plan view of an IC structure having an initial pattern formed of AF material according to an embodiment of the present disclosure is shown.

[0010] Figure 3 A cross-sectional view of converting AF material into voids according to an embodiment of the present disclosure is shown.

[0011] Figure 4 A plan view of an IC structure having a void pattern according to an embodiment of the present disclosure is shown.

[0012] Figure 5 A cross-sectional view showing formation of another AF material in portions of the void according to an embodiment of the present disclosure is shown.

[0013] Figure 6 A plan view of an IC structure having a pattern of voids and AF material according to an embodiment of the present disclosure is shown.

[0014] Figure 7 A cross-sectional view of AF material in a metal wiring layer according to an embodiment of the present disclosure is shown.

[0015] Figure 8 A cross-sectional view illustrating converting a portion of AF material in a metal wiring layer into voids according to an embodiment of the present disclosure is shown.

[0016] Figure 9 An illustrative flow chart of a method for authenticating an IC structure according to an embodiment of the present disclosure is shown.

[0017] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended only to depict typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, like reference numerals represent like elements between the drawings. DETAILED DESCRIPTION

[0018] In the following description, reference is made to the accompanying drawings which form a part of the present invention and which illustrate, by way of illustration, specific exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it is understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Therefore, the following description is illustrative only.

[0019] It will be understood that when an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0020] References in the specification to "one embodiment" or "an embodiment" of the present disclosure and other variations thereof mean that the particular features, structures, characteristics, etc. described in conjunction with the embodiment are included in at least one embodiment of the present disclosure. Therefore, the phrases "in one embodiment" or "in an embodiment" and any other variations appearing throughout the specification do not necessarily refer to the same embodiment. It should be understood that the use of any of " / ", "and / or", and "at least one" in the contexts of, for example, "A / B", "A and / or B", and "at least one of A and B" is intended to include selecting only the first listed option (a), or only the second listed option (B), or both options (A and B). As another example, in the case of "A, B, and / or C" and "at least one of A, B, and C," these phrases are intended to encompass selecting only the first listed option (A), or only the second listed option (B), or only the third listed option (C), or only the first and second listed options (A and B), or only the first and third listed options (A and C), or only the second and third listed options (B and C), or all three options (A, B, and C). As will be apparent to one of ordinary skill in the art, this scenario can be extended to many of the listed options.

[0021] Embodiments of the present disclosure relate to methods for authenticating integrated circuit (IC) structures and structures including features for authentication. Methods according to the present disclosure may include forming an authentication film (AF) material (e.g., one or more layers of material capable of being converted into voids by evaporation, etching, and / or other techniques) within the IC structure. The AF material may be formed into one or more regions or patterns. The dimensions of the AF material may be determined based on selective or non-selective processing (e.g., removal) of portions of the AF material. With the AF material in place, a portion or all of the AF material may be converted into voids. The voids may be optically detectable and / or distinguishable from adjacent material using a microscope, while the AF material may not be optically apparent. The method also includes creating an authentication layout for the IC structure, indicating the locations of the voids and, optionally, any portions of the AF material remaining in the IC structure. The authentication layout may be provided only to a recipient of the IC structure, such as via a secure communication channel. The recipient may inspect the IC structure to verify that the voids and, where applicable, the remaining portions of the AF material match corresponding locations within the authentication layout. In some cases, each distinct cell of the IC structure may have a unique authentication layout.

[0022] IC structures according to the present disclosure may include various physical elements and / or other authentication features for implementing methods according to the present disclosure. An IC structure according to the present disclosure may include one or more voids located within an area that is horizontally offset from one or more electro-active elements (e.g., located within a local interconnect or metal wiring layer). The location of the voids may provide an authentication pattern for the IC structure. In further embodiments, portions of the AF material may also be located within the area of ​​the IC structure. Further processing and / or modification of the IC structure may convert any remaining portions of the AF material into voids, thereby indicating unauthenticated processing and / or tampering of the IC structure.

[0023] refer to Figure 1 , embodiments of the present disclosure may include and / or may be implemented on an integrated circuit (IC) structure 100. The methods described herein may produce an IC structure according to one or more embodiments of the present disclosure. IC structure 100 may represent a portion of an initial material distributed across a two-dimensional region in plane XY, and Figure 1A cross-section of IC structure 100 in the XZ plane is shown. IC structure 100 includes a set of metal wiring layers 102 having a plurality of different layers (e.g., a first metal level 104 and a second metal level 106), with various additional layers (not shown) beneath these metal wiring layers. Metal wiring layers 102 may be located above one or more layers containing various devices (e.g., transistors, resistors, capacitors, etc.). The formation and location of these devices are generally understood in the art and are not relevant to the embodiments of the present disclosure and are therefore omitted.

[0024] In addition to several layers of insulating material, the metal wiring layer 102 described herein may also include several metal lines within each layer. The various layers of the metal wiring layer 102 may include active circuits, such as metal lines 108, vias 110, and / or other components, such as conductive interconnects and / or other conductive components. The conductive material of the metal wiring layer 102 (e.g., metal lines 108 and / or vias 110) may include materials such as copper (Cu), aluminum (Al), and / or any other type of conductive material. The conductive material of the metal wiring layer 102 may extend horizontally or vertically through a set of inter-level dielectric (ILD) layers 112. The ILD layer 112 may be formed of any currently known or later developed material for providing electrical insulation, and may include, for example, silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2 (FSG), hydrogenated silicon oxycarbon (SiCOH), porous SiCOH, borophosphosilicate glass (BPSG), silsesquioxane, carbon (C)-doped oxides (i.e., organosilicates) containing atoms of silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H), thermosetting polyarylene ether, spin-coated silicon-carbon polymer materials, near-frictionless carbon (NFC), or multiple layers thereof. The first layer 104 may be the topmost metal layer of the metal wiring layer 102, and the second layer 106 may be the adjacent layer therebelow. The metal wiring layer 102 may have any conceivable number of layers, each layer having its own set of metal lines 108, vias 110, etc.

[0025] IC structure 100 may include a local interconnect (LI) layer 114 located above metal wiring layer 102 for electrically coupling metal wiring layer 102 to other IC components. LI layer 114 may include a polyimide material 116, such as one or more photosensitive polyimide (PSPI), benzocyclobutene (BCB), epoxy resin, polyparaphenylene benzodioxide, or a combination thereof, alone or in any conceivable combination. As noted elsewhere herein, one or more compounds within the polyimide material 116 may be porous or non-porous, and a porous material may allow evaporated materials to pass through the polyimide material 116 in a method according to the present disclosure. The LI layer 114 may itself include one or more LI conductors 118, for example, for connecting the metal lines 108 and / or vias 110 of the metal wiring layer 102 to various interconnect components (e.g., solder bumps and / or solder bumps). 1. The LI conductor 118 of the LI layer 114 may be protected from the polyimide material 116 by various layers of insulating material, and such materials may include an oxide layer 120 formed on the LI conductor 118 and a nitride layer 122 formed between the oxide layer 120 and the polyimide material 116. Depending on the type of IC and / or the intended application of the IC structure 100, the oxide layer 120 and / or the nitride layer 122 may be omitted and / or used in combination with another insulating material.

[0026] Embodiments of the present disclosure may include forming a first authentication film (AF) material 130 within the IC structure 100. In one example, the first AF material 130 is formed above the metal wiring layer 102 and within the LI layer 114, but as discussed in detail elsewhere herein, the first AF material 130 may alternatively be formed within the metal wiring layer 102. The first AF material 130 may, for example, include any type of material that is capable of evaporating under specified conditions and may therefore include one or more carbon-based energy removal film (ERF) materials. In this case, the first AF material 130 may be evaporated by heating to a predetermined temperature that is lower than the phase transition temperature of other materials in the IC structure 100. In this case, the first AF material 130 may include one or more carbon-based organic materials (e.g., porogens) that are deposited by spin coating or chemical vapor deposition (CVD) processes and cured with the aid of ultraviolet light. Such materials may be cured at a temperature between approximately three hundred and four hundred degrees Celsius (°C). In various embodiments, the first AF material 130 may include a carbon-based C x H ycompound, where "x" and "y" represent different numbers of carbon atoms and hydrogen atoms, respectively. In another example, the first AF material 130 may include an oxide film, a nitride film, and / or other materials that can be selectively removed relative to adjacent materials (e.g., the ILD layer 112, the polyimide material 116, etc.). In this case, portions of the first AF material 130 may be removed by forming a mask (not shown) and etching the first AF material 130 through openings in the mask. Regardless of the embodiment, the first AF material 130 may be formed to a thickness of at least about fifty angstroms above the metal wiring layer 102, and in another embodiment, may have a thickness of ten microns (μm) or more above the metal wiring layer 102. Regardless of the embodiment, the composition of the first AF material 130 may be optically indistinguishable from the adjacent materials (e.g., the ILD layer 112, the polyimide material 116) without using enhanced imaging techniques (e.g., thermal imaging, enhanced microscopy, etc.).

[0027] Now refer to Figure 2 , the first AF material 130 can be formed in a first region R1 of the IC structure 100 away from one or more electrically active components, or otherwise separated from active components in a second region R2 of the IC structure 100. Such active components can include LI conductors 118 (e.g., wires, pads, etc. discussed herein) and / or other conductive materials. Figure 2 As shown, multiple regions of the first AF material 130 may be formed in a pattern 132 on the IC structure 100. In one example embodiment, the pattern 132 may include four regions of the first AF material 130 to create a set of different shapes (e.g., a circle, a diamond, a hexagon, a star as shown). Although the first AF material 130 and the pattern 132 are Figure 2 16. The first AF material 130 is shown as being located within the polyimide material 116, but as discussed herein, in other embodiments they may be located within the metal wiring layer 102. Any conceivable number of areas of the first AF material 130 may be formed on the IC structure 100 to create icons, such as easily recognizable symbols, for example, letters, shapes, icons, and / or areas of the first AF material 130 that appear to have no recognizable pattern or shape. Regardless of the arrangement, the pattern 132 of the first AF material 130 may be derived from the design of the IC structure 100. Further processing according to the present disclosure may include converting the first AF material 130 into empty space (discussed herein as "voids") that may be compared to an authenticated layout to verify that the IC structure 100 has not been altered without authorization.

[0028] Figure 3 The first AF material 130 ( Figure 1 、 Figure 2) is converted into voids 140 to authenticate a cross-sectional view of the processing of the IC structure 100. In some embodiments (e.g., where the first AF material 130 comprises an ERF material), methods according to the present disclosure may include subjecting the IC structure 100 to ultraviolet light at an elevated temperature (e.g., three hundred to four hundred degrees Celsius) to evaporate any exposed portions of the first AF material 130. In another example, such as where the first AF material 130 comprises an oxide, the first AF material 130 may be converted into voids 140 by forming a mask on the IC structure 100 and etching the first AF material 130 from the IC structure 100. The conversion of the first AF material 130 into voids 140 does not have any impact on electrically active components in the second region R2 (e.g., conductors within the LI layer 114 and / or the metal wiring layer 102) because the first AF material 130 is located in the first region R1, away from the electrically active components of the IC structure 100. After forming the voids 140, any heat source, etching tool, etc. used for the conversion may be removed from the IC structure 100.

[0029] Steering Figure 4 The conversion of the first AF material 130 into the voids 140 may produce a pattern 142 of voids 140 on the IC structure 100. The voids 140 may be visible relative to adjacent materials (e.g., the ILD layer 112 ( Figure 1 、 Figure 2 ), polyimide material 116) is optically detected. Pattern 142 may include an icon (e.g., a shape, letter, and / or other identifiable structure) that is the same as the icon previously formed in the IC structure 100 by the first AF material 130. Pattern 142 may be entirely contained within a first region R1 of the IC structure, where there are no active elements (e.g., LI conductors 118), so that void 140 does not interfere with active components of the IC structure 100 in a second region R2. Methods according to the present disclosure may include optically analyzing the IC structure 100 (e.g., by a microscope) to locate pattern 142. If pattern 142 is located in the same location as the authentication layout of the IC structure 100, the recipient of the IC structure 100 will know that the product is authentic. In some cases, the conversion of the first AF material 130 into void 140 may be performed by the recipient itself, so that an intermediate recipient of the IC structure 100 that has not received the authentication layout of the IC structure 100 does not know or see the location of pattern 142.

[0030] Now refer to Figure 5Some methods and / or structures according to the present disclosure may include only partially removing and / or reforming the AF material to produce a second AF material 144 on the IC structure 100. In this case, both the voids 140 and the second AF material 144 may be used to authenticate the IC structure 100. Figure 5 1 shows a cross section of the IC structure 100 in which a portion of the void 140 is filled with the second AF material 144. The second AF material 144 can be formed, for example, by forming an additional mask (not shown) and depositing the second AF material 144 into the exposed area of ​​the void 140. In another example, the second AF material 144 can be formed by depositing only the first AF material 130 ( Figure 1 、 Figure 2 ) is converted into a portion of the void 140, for example by controllably applying UV light, etching, etc., to produce a second AF material 144 and the void 140.

[0031] Figure 6 A plan view of an IC structure 100 is shown in which a pattern 142 includes a combination of voids 140 and a second AF material 144. In this case, some voids 140 may be completely free of the second AF material 144, some portions of the second AF material 144 may not include voids 140, and / or different areas may include different amounts of voids 140 and / or second AF material 144 located therein. The distribution of the second AF material 144 across the IC structure 100 may be non-uniform, i.e., different amounts of the second AF material 144 may appear to be randomly or pseudo-randomly distributed across the cross-sectional area of ​​the IC structure 100, or may not have an identifiable pattern without the aid of a certified layout. Optical inspection of the IC structure 100 with the aid of a microscope may allow a user to identify the location of the voids 140 relative to the second AF material 144 and adjacent materials for comparison with a certified layout of the IC structure 100. The presence of the second AF material may allow for multiple stages of authentication, such as by identifying the pattern 144 having the second AF material 144 therein before the second AF material 144 is converted into additional voids. The resulting pattern 142 without the voids 140 can then be authenticated with another authentication layout. In this way, multiple recipients of the IC structure 100 can use the location of the voids 140 and / or the second AF material 144 to authenticate the IC structure 100.

[0032] Now refer to Figure 7, methods according to the present disclosure may include forming a first AF material 130 within the metal wiring layer 102 before forming the LI layer 114 above the metal wiring layer 102. In one example, the first AF material 130 may be formed within portions of the first metal level 104, but the first AF material 130 may additionally or alternatively be formed within the second metal level 106 and / or any other level of the metal wiring layer 105 in the IC structure 100. In this case, the polyimide material 116 or another metal level within the metal wiring layer 102 may cover the top surface of the first AF material 130. Any of the various techniques discussed herein for converting the first AF material 130 into voids 140 may be used on the AF material 130 within the metal wiring layer 102. For example, where the first AF material 130 comprises an oxide material, portions of the metal wiring layer 102 may be removed by etching using a mask at appropriate locations to create voids 140 at target locations. The polyimide material 116 and / or the portion of the metal wiring layer 102 thereunder may also include an opening 150 for evaporating the first AF material 130 upon heating. To allow the evaporated AF material to escape from the IC structure 100, the opening 150 may have a diameter of, for example, at least about one micron, although in other embodiments, the diameter may vary.

[0033] Figure 8 A cross-sectional view of a process of converting the first AF material 130 into voids 140 by evaporation is shown. Here, UV light and / or heat can be applied from an external source to the IC structure 100 to convert the first AF material 130 ( Figure 7 ) to its evaporation temperature. The material composition of the first AF material 130 (e.g., a carbon-based ERF material) can be selected for its ability to evaporate at a temperature so low that it cannot affect other portions of the IC structure 100 (including the active material in the second region R2). At this evaporation temperature, the evaporated portion of the first AF material 130 can exit the IC structure through the opening 150, thereby converting the first AF material 130 into a void 140. The unevaporated portion of the first AF material 130 can remain within the metal wiring layer 102 as the second AF material 144. In the case where the polyimide material 116 includes a porous compound that is permeable to the evaporated portion of the first AF material 130, the opening 150 can be omitted and the void 140 can be formed by passing the evaporated first AF material 130 through the polyimide material 116.

[0034] Figure 9is an illustrative flow chart showing various processes for implementing the method according to the present disclosure. It should be understood that the various processes discussed herein can be implemented in a different order in alternative configurations, with additional steps and / or omitting one or more steps. The method of the present disclosure is operable to form various structures in the first region R1 of the IC structure 100 and can process these structures (e.g., convert them into voids) for authentication via an authentication layout or similar solution for verifying the location of voids in the structure.

[0035] refer to Figure 2 and Figure 9 , the method according to the present disclosure may be included in the IC structure 100, for example, in the polyimide material 116 (or in the metal wiring layer 102, for example, as Figure 7 、 Figure 8 1 . The first AF material 130 formed in process P1 can be located in an electrically inactive portion of the IC structure 100, i.e., in the first region R1 that is physically and electrically separated from the L1 conductor 118 or other active elements within the second region R2. In some embodiments, the multiple regions of the first AF material 130 can be formed in a pattern 132 such that the arrangement of the first AF material 130 is visually identifiable (e.g., a set of icons including shapes, letters, etc.). Because the first AF material 130 is formed of a substantially translucent material, such as an oxide, a carbon-based ERF material, and / or any material having a refractive index similar to a dielectric material, at the conclusion of process P1, the first AF material 130 can be optically indistinguishable from the material on which it is formed (e.g., the polyimide material 116, the ILD layer 112, and / or other insulating structures).

[0036] refer to Figure 4 and Figure 9 , the method of the present disclosure may include forming a first AF material 130 ( Figure 1 、 Figure 2 ) into voids 140 within IC structure 100. The conversion in process P2 may include, for example, heating IC structure 100 to a temperature sufficient to evaporate the organic-based ERF material (e.g., at least about three hundred degrees Celsius) by an external UV heat source and / or other type of heat source. The first AF material 130 located within metal wiring layer 102 may be formed through a hole in polyimide material 116 or, where applicable, through opening 150 ( Figure 7 、 Figure 8) evaporated. In other embodiments, the conversion in process P2 can include etching the first AF material 130 to form the void 140 without etching or otherwise removing other materials positioned adjacent to or beneath the first AF material 130. The void 140 created by removing the first AF material 130 can be optically distinct from the polyimide material 116, the ILD layer 112, or other adjacent materials, for example by being formed from a gas and therefore having a different refractive index. The void 140 is optically detectable by microscopy in other processes described herein.

[0037] refer to Figure 6 and Figure 9 , the method according to the present disclosure may optionally include an additional process P3 of forming a second AF material 144 within the void 140. The formation of the second AF material 144 may include redepositing a carbon-based ERF material, an oxide material, etc. in selected portions of the void 140 without forming the second AF material 144 in other locations. In some embodiments, process P3 may be integrated into process P2, for example, by depositing only the first AF material 130 ( Figure 1 、 Figure 2 ) is converted into voids 140, while the remainder of the material becomes second AF material 144. At the end of process P2 or P3, pattern 142 may be formed within IC structure 100, wherein pattern 142 includes voids 140 or a combination of voids 140 and second AF material 144. Furthermore, pattern 142 may be physically and electrically isolated from electrically active components (e.g., L1 conductor 118) within second region R2 of IC structure 100 and thus may have no operational impact on IC structure 100.

[0038] Methods according to the present disclosure may include a process P4 of creating a certification layout of IC structure 100. The certification layout created in process P4 may include a visual representation, a set of coordinates, and / or other guides for indicating the location of voids 140 in IC structure 100. The location of voids 140 in the certification layout may include a pattern 142. In some cases, the certification layout may include a pattern 142 having both voids 140 and a second AF material 144, and may additionally or alternatively include a pattern 142 without any second AF material 144. In other embodiments, process P4 may include creating multiple certification layouts, each of which may correspond to a different state of IC structure 100, such as a pattern 142 including second AF material 144, a pattern 142 having only voids 140, and so on. The certification layout created in process P4 may be in the form of computer program code stored on a non-transitory storage medium and may therefore be sent to other parties via the Internet or other solutions for sending data from one entity to another.

[0039] The method of the present disclosure is particularly effective for detecting whether an intermediate recipient of the IC structure 100 in the supply chain has tampered with the IC structure 100. Such tampering can elevate the IC structure 100 to the level of the first AF material 130 ( Figure 1 、 Figure 2 ) or the temperature at which the second AF material 144 evaporates, and / or other types of processing that inadvertently remove portions of the first AF material 130 or the second AF material 144 may be performed. Such processing may increase the number of voids 140 and / or change the pattern 142, thereby causing the IC structure 100 to differ from its certified layout. Process P5 according to the present disclosure may include transmitting the IC structure 100 to one or more recipients, such as intended users of a product. The IC structure 100 may be transmitted directly from the manufacturer to the consumer, and / or may be transmitted through one or more intermediate recipients in the product supply chain (e.g., an intermediate manufacturer, a shipper, etc.). Process P6, which may occur before, during, or after process P5, may include providing the certified layout to one or more recipients of the IC structure 100. Providing the certified layout may include, for example, electronically transmitting the certified layout as data from one entity (e.g., the manufacturer of the IC structure 100) to another entity (e.g., the end consumer). In some cases, such as where the consumer already possesses the IC structure 100 and / or its certified layout, processes P5, P6 may be omitted.

[0040] Process P7 in accordance with the methods of the present disclosure may include authenticating IC structure 100 based on the authentication layout created in process P4. Authentication process P7 may include optically inspecting IC structure 100 via a microscope and / or other imaging tool. In one example, process P7 may include optically inspecting IC structure 100 and authenticating IC structure 100 by checking to see whether the location of voids 140 and / or the shape of pattern 142 therein match the authentication layout in process P4. In another example, the recipient of IC structure 100 may authenticate IC structure 100 by heating IC structure 100 to an evaporation temperature as discussed herein and then comparing the location of pattern 142 and / or voids 140 in IC structure 100 to the authentication layout. If the location of pattern 142 and / or voids 140 matches the authentication layout, IC structure 100 is deemed authentic. If the location of pattern 142 and / or voids 140 does not match the authentication layout, IC structure 100 is deemed non-authentic (e.g., manufactured by another entity, tampered with, and / or otherwise not conforming to its original specifications). In either case, the method may end ("Done") and the recipient may use IC structure 100 or notify the manufacturer, if applicable.

[0041] Embodiments of the present disclosure provide several technical and commercial advantages, some of which are discussed herein as examples. As is apparent from the discussion herein, embodiments of the present disclosure allow for the manufacture of an IC structure 100 with built-in authentication features, thereby allowing the IC structure 100 to be optically authenticated without specialized equipment (e.g., imaging tools other than a microscope). Embodiments of the present disclosure also ensure that the authentication features (e.g., voids 140 and / or patterns 142) or portions thereof cannot be detected prior to the occurrence of a predetermined event, such as, for example, raising the temperature of the IC structure 100 to evaporate the target material, etching oxide through a mask, and the like. By using an AF material that is optically indistinguishable from adjacent materials (e.g., polyimide materials, dielectric layers, etc.), it is unlikely or impossible for a third party other than the recipient to detect the AF material. It is also difficult or impossible for a third party to detect the AF material without inadvertently inserting the AF material therein (e.g., the first AF material 130 ( Figure 1 、 2 )) is converted into a void 140 to modify and / or tamper with the IC structure 100.

[0042] Aspects of the present disclosure are described above with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each block of the flowcharts and / or block diagrams, as well as combinations of blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that instructions executed by the processor of the computer or other programmable data processing device create a device for implementing the functions / actions specified in one or more blocks of the flowcharts and / or block diagrams.

[0043] The above-described structures and methods are used for integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in the form of a single-chip package (e.g., a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (e.g., a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices, and central processing units.

[0044] The terms used herein are only used for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "include" and / or "comprise" specify the presence of the features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or the groups they constitute. "Optional" or "optionally" means that the event or situation described subsequently may or may not occur, and that the description includes situations where the event occurs and situations where the event does not occur.

[0045] Approximate language, as used throughout the specification and claims, may be used to modify any quantitative representation that is permissible to vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by one or more terms such as "about," "approximately," and "substantially" is not limited to the precise value specified. In at least some cases, approximate language may correspond to the precision of the instrument used to measure the value. Herein and throughout the specification and claims, range limitations may be combined and / or interchanged, such ranges are identified and include all subranges contained therein unless the context or language indicates otherwise. "Approximately" applied to a particular value of a range applies to both values ​​and may indicate + / - 10% of the stated value unless otherwise dependent upon the precision of the instrument used to measure the value.

[0046] The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present disclosure has been given for purposes of illustration and description, but is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the disclosure. The embodiments were chosen and described in order to best explain the principles and practical application of the disclosure and to enable others skilled in the art to understand the various embodiments of the disclosure with various modifications suitable for the particular use contemplated.

Claims

1. A method for authenticating an integrated circuit (IC) structure, the method comprising: forming a first authentication film (AF) material within the IC structure, wherein the first AF material has a different composition than adjacent materials within the IC structure; converting the first AF material into voids within the IC structure; creating an authentication layout of the IC structure, the authentication layout including a location of the void in the IC structure for authenticating the IC structure; as well as The location of the void in the IC structure is optically detected from outside the IC structure to provide authentication of the IC structure. 2 . The method of claim 1 , wherein forming the first AF material comprises forming the first AF material in a region within a polyimide layer of the IC structure that is horizontally away from at least one electrically active element in the IC structure.

3. The method of claim 1 , wherein the first AF material is formed within a portion of a wiring layer of the IC structure beneath a polyimide layer, wherein the portion of the wiring layer includes at least one opening through the polyimide layer, the at least one opening being sized for evaporation of the first AF material.

4. The method of claim 1, wherein converting the first AF material into the voids comprises evaporating the first AF material.

5. The method of claim 1 , further comprising forming a second AF material within the IC structure, wherein at least a portion of the void does not include the second AF material, and the certification layout further comprises a location of the second AF material in the IC structure. The method of claim 5 , wherein forming the second AF material comprises unevenly distributing the second AF material within the void. The method of claim 1 , wherein the first AF material comprises a carbon-based energy removal film (ERF).

8. The method of claim 1, further comprising providing the certified layout to a recipient of the IC structure.

9. An integrated circuit (IC) structure comprising: a polyimide layer positioned above the plurality of metal wiring layers, the polyimide layer comprising a first region having at least one electroactive element and a second region horizontally spaced away from the at least one electroactive element; as well as a void within the second region of the polyimide layer, wherein the location of the void within the polyimide layer defines an authentication pattern of the IC structure, The location of the void within the polyimide layer can be optically detected from outside the IC structure to provide authentication of the IC structure.

10. The IC structure of claim 9, wherein the void overlies a metal line within one of the plurality of metal wiring layers.

11. The IC structure of claim 9, further comprising an authentication film (AF) material located within the second region of the polyimide layer, wherein the authentication pattern of the IC structure further comprises a location of the AF material.

12. The IC structure of claim 11, wherein the AF material comprises a carbon-based energy removal film (ERF).

13. The IC structure of claim 11, wherein the AF material is non-uniformly distributed within the void.

14. An integrated circuit (IC) structure comprising: polyimide layer; a metal wiring layer located below the polyimide layer, the metal wiring layer including a first region having at least one electroactive element and a second region horizontally away from the at least one electroactive element; as well as a void within the second region of the metal wiring layer, wherein the location of the void within the metal wiring layer defines an authentication pattern of the IC structure, The location of the void within the metal wiring layer can be optically detected from outside the IC structure to provide authentication of the IC structure.

15. The IC structure of claim 14, further comprising an authentication film (AF) material located within the second region of the metal wiring layer, wherein the authentication pattern of the IC structure further comprises a location of the AF material.

16. The IC structure of claim 15, wherein the AF material comprises a carbon-based energy removal film (ERF). The IC structure of claim 15 , wherein the AF material is non-uniformly distributed within the void.

18. The IC structure of claim 15, further comprising at least one opening through the polyimide layer to the metal wiring layer, the at least one opening being sized for evaporation of the AF material.

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