Memory array and method for forming a memory array including memory cell strings

Abstract

A method for forming a memory array includes forming a stack comprising vertically alternating first and second layers. A first insulator layer is above the stack. A first insulator material of the first insulator layer comprises at least one of (a) and (b), wherein (a) includes silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b) includes silicon carbide. Strings of channel material are within the stack and within the first insulator layer. Conductive material is directly against the sides of individual strings of channel material in the first insulator layer. A second insulator layer is formed above the first insulator layer and the conductive material. A second insulator material of the second insulator layer comprises at least one of (a) and (b). Conductive vias are formed and extend through the second insulator layer and are individually electrically coupled directly to the individual strings of channel material through the conductive material. Other aspects of the structure are disclosed, including those not related to the method.

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and methods for forming memory arrays including strings of memory cells. Background Art

[0002] Memory is a type of integrated circuit system used in computer systems to store data. Memory can be fabricated as one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). Sense lines conductively interconnect memory cells along the columns of the array, and access lines conductively interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of sense and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods in the absence of power. Non-volatile memory is conventionally designated as memory having a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. Regardless, the memory cell is configured to hold or store memory in at least two different selectable states. In a binary system, the states are considered to be "0" or "1." In other systems, at least some individual memory cells may be configured to store more than two levels or states of information.

[0004] Field-effect transistors are a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconducting channel region between them. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Applying a suitable voltage to the gate allows current to flow from one of the source / drain regions through the channel region to the other. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field-effect transistors may also include additional structures (e.g., a reversibly programmable charge storage region) as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory that has many uses in modern computers and devices. For example, modern personal computers may have a BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid-state disks, replacing conventional hard drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and provides the ability to remotely upgrade devices for enhanced features.

[0006] NAND may be the basic architecture of integrated flash memory. A NAND cell includes at least one select device coupled in series to a series combination of memory cells (where the series combination is often referred to as a NAND string). NAND architectures can be configured as three-dimensional arrangements of vertically stacked memory cells, each of which includes a reversibly programmable vertical transistor. Control or other circuitry may be formed beneath the vertically stacked memory cells. Other volatile or nonvolatile memory array architectures may also include vertically stacked memory cells, each of which includes a transistor.

[0007] The memory array may be arranged in memory pages, memory blocks, and partial blocks (e.g., sub-blocks) and memory planes, such as shown and described in any of U.S. Patent Application Publications Nos. 2015 / 0228659, 2016 / 0267984, and 2017 / 0140833. A memory block may at least partially define the longitudinal profiles of individual word lines in an individual word line level of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the vertically stacked array of memory cells. The staircase structure includes individual "steps" (alternatively referred to as "steps" or "stairs") that define contact areas for individual word lines, on which vertically extending conductive vias are contacted to provide electrical access to the word lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate under processing according to an embodiment of the present invention and is illustrated by Figure 2 The line 1-1 is obtained.

[0009] Figure 2 is through Figure 1 A diagrammatic cross-sectional view taken along line 2-2 in FIG.

[0010] Figure 3 、 3A , 3B, 4, 4A, 4B, 5 to 7A, 8, 9, 9A to 13A, 14 to 17A are processes according to some embodiments of the present invention Figure 1 and 2 Diagrammatic sequential cross-sectional views and / or enlarged views of the structure or parts thereof.

[0011] Figure 18 、 18A , 19, 19A, 20 and 20A show alternative example method and / or structural embodiments of the present invention. DETAILED DESCRIPTION

[0012] Embodiments of the present invention encompass methods for forming memory arrays, such as NAND or other memory cell arrays with peripheral control circuitry below the array (e.g., under-array CMOS). Embodiments of the present invention encompass so-called "gate-last" or "replacement-gate" processes, so-called "gate-first" processes, and other processes, existing or yet to be developed, that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass memory arrays (e.g., NAND architectures) that are independent of the method of manufacture. Reference Figures 1 to 17A Example method embodiments are described, which may be considered a "gate last" or "replacement gate" process.

[0013] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending transistor and / or memory cell strings are to be formed. Construction 10 includes a base substrate 11 having any one or more of conductive / conductive / conductive, semiconductive / semiconductive / semiconductive, or insulating / insulator / insulating (i.e., herein, electrically insulating) materials. Various materials have been vertically formed over base substrate 11. The materials may be Figure 1 and 2 1. The depicted material may be positioned adjacent to, vertically inward from, or vertically outward from the depicted material. For example, other partially or fully fabricated components of the integrated circuit system may be disposed somewhere above, around, or within base substrate 11. Control and / or other peripheral circuitry for operating components within an array of vertically extending memory cell strings (e.g., array 12) may also be fabricated and may or may not be completely or partially within the array or sub-array. Furthermore, multiple sub-arrays may be fabricated and operated independently, in conjunction, or otherwise relative to each other. In this document, a "sub-array" may also be considered an array.

[0014] A conductor layer 16 comprising conductive material 17 has been formed over substrate 11. Conductor layer 16 may include portions of control circuitry for controlling read and write access to transistors and / or memory cells to be formed within array 12 (e.g., under-array peripheral circuitry and / or a common source line or plate). A stack 18 comprising vertically alternating insulating layers 20 and conductive layers 22 has been formed over conductor layer 16. An example thickness for each of layers 20 and 22 is 22 to 60 nanometers. Only a few layers 20 and 22 are shown, with stack 18 more likely including dozens, hundreds, or more layers 20 and 22. Other circuitry, which may or may not be part of the peripheral and / or control circuitry, may be interposed between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating material for this circuitry may be below the lowest layer of conductive layer 22 and / or above the uppermost layer of conductive layer 22. 1 . For example, one or more select gate layers (not shown) may be interposed between conductor layer 16 and lowermost conductive layer 22, and one or more select gate layers may be above the uppermost layer of conductive layers 22. Regardless, conductive layer 22 (alternatively referred to as the first layer) may not include conductive material, and insulating layer 20 (alternatively referred to as the second layer) may not include insulating material or may be insulating as in the example method embodiments initially described herein (which are "gate last" or "replacement gate") processes. Example conductive layer 22 includes a first material 26 (e.g., silicon nitride), which may be fully or partially sacrificial. Example insulating layer 20 includes a second material 24 (e.g., silicon dioxide), which has a different composition than that of first material 26 and may be fully or partially sacrificial. Uppermost insulating layer 20 and stack 18 may be considered to have a top 21.

[0015] A first insulator layer 70 has been formed above stack 18, and in one embodiment, another layer 71 has been formed above first insulator layer 70. First insulator layer 70 includes a first insulator material 39, which includes at least one of (a) and (b), wherein (a) is silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b) is silicon carbide. In one embodiment, first insulator material 39 includes (a). In one such embodiment, first insulator material 39 includes one and only one of carbon, oxygen, boron, or phosphorus. In another such embodiment, first insulator material 39 includes at least two of carbon, oxygen, boron, and phosphorus. In one embodiment, the one or more of carbon, oxygen, boron, and phosphorus in first insulator material 39 has a total concentration of at least about 2 atomic percent, and in one such embodiment, this total concentration does not exceed about 20 atomic percent. In one embodiment, this total concentration is at least about 4 atomic percent, and in one embodiment, at least about 10 atomic percent. In one embodiment, this total concentration is from about 6 atomic percent to about 11 atomic percent. In one embodiment, first insulator material 39 includes (b). In one embodiment, first insulator material 39 includes both (a) and (b), while another embodiment includes only one of (a) and (b). In one embodiment, insulating layer 20 includes an insulating material (e.g., 24) having a different composition than that of first insulator material 39. In one embodiment and as shown, first insulator layer 70 includes insulating material 42 (e.g., silicon dioxide) therein, which does not include either (a) or (b). Example another layer 71 is shown as including insulating material 24.

[0016] A trench opening 25 has been formed (e.g., by etching) through layer 71, layer 70, insulating layer 20, and conductive layer 22 to conductor layer 16. Trench opening 25 may taper radially inward (not shown), moving deeper into stack 18. In some embodiments, trench opening 25 may partially penetrate conductive material 17 of conductor layer 16, as shown, or may stop atop it (not shown). Alternatively, as an example, trench opening 25 may stop atop or within lowermost insulating layer 20. Extending trench opening 25 to at least the conductive material 17 of conductor layer 16 is to ensure that subsequently formed trench material (not shown) is directly electrically coupled to conductor layer 16, without having to use alternative processes and structures to accomplish this connection when such a connection is desired. An etch stop material (not shown) may be within or atop conductive material 17 of conductor layer 16 to facilitate stopping etching of trench opening 25 relative to conductor layer 16, if desired. This etch stop material may be sacrificial or non-sacrificial. By way of example only and for simplicity, the channel openings 25 are shown arranged in groups or columns of alternating rows of four and five openings 25, and the array is arranged in laterally spaced memory block regions 58 that will comprise laterally spaced memory blocks 58 in the completed circuitry configuration. In this document, "block" is used generically to include "sub-blocks." The memory block regions 58 and resulting memory blocks 58 (not shown) can be considered to be longitudinally elongated and, for example, oriented along direction 55. Otherwise, the memory block regions 58 may not be discernible at this point in the processing. Any alternative existing or yet-to-be-developed arrangements and configurations may be used.

[0017] Transistor channel material may be formed vertically in individual channel openings along the insulating and conductive layers, thereby comprising individual strings of channel material that are directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the resulting example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally interposed between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge passing material. The storage material of each memory cell (e.g., a floating gate material (e.g., doped or undoped silicon) or a charge-trapping material (e.g., silicon nitride, metal dots, etc.)) is vertically arranged along individual charge blocking regions. The insulating charge passing material (e.g., a bandgap-engineered structure comprising a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulating oxides (e.g., silicon dioxide)) is laterally interposed between the channel material and the storage material.

[0018] Figure 3 、 3A, 3B, 4, 4A, and 4B show one embodiment in which charge blocking material 30, storage material 32, and charge passing material 34 have been formed vertically in individual channel openings 25 along insulating layer 20 and conductive layer 22. Transistor materials 30, 32, and 34 (e.g., memory cell materials) may be formed, for example, by depositing respective thin layers of transistor materials 30, 32, and 34 (e.g., memory cell materials) over stack 18 and within individual channel openings 25, and then planarizing this back to at least the top surface of stack 18. In one embodiment, at least some of memory cell materials 30, 32, and / or 34 comprising silicon dioxide and further example memory cell materials are described in more detail below.

[0019] Channel material 36 has also been formed vertically in the first insulator layer 70 in the stack 18 and in the channel opening 25 along the insulating layer 20 and the conductive layer 22, thus comprising, in one embodiment, individual strings of operating channel material 53 having memory cell materials (e.g., 30, 32, and 34) along them. Due to the scale, materials 30, 32, 34, and 36 are collectively shown as Figure 3 and 4 37 and designated only as material 37. Example channel material 36 comprises a suitably doped crystalline semiconductor material, such as one or more of silicon, germanium, and so-called Group III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. A through-etch may be performed, as shown, to remove materials 30, 32, and 34 from the base of channel opening 25 to expose conductor layer 16, such that channel material 36 is directly adjacent to conductive material 17 of conductor layer 16. This through-etch may occur individually with respect to each of materials 30, 32, and 34 (as shown) or may occur collectively with respect to all after deposition of material 34 (not shown). Alternatively, and by way of example only, no through-etch may be performed and channel material 36 may be electrically coupled directly to conductive material 17 of conductor layer 16 via a separate conductive interconnect (not shown). Channel opening 25 is shown as including a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially central portion within channel opening 25 may include a void (not shown) and / or be free of solid material (not shown). Regardless, conductive material 31 (e.g., a conductive plug, such as conductively doped polysilicon) is directly against the side (in one embodiment, the laterally inner side 44) of individual channel material strings 53 in first insulator level 70. In one embodiment and as shown, conductive material 31 protrudes upward from first insulator material 39 in level 70 and, in any case, having a top 62. One or more of materials 30, 32, 34, and 36 may not extend to top 62 (not shown).

[0020] refer to Figure 5 In one embodiment, multiple insulating layers 72, 73, and 74 are formed over first insulator layer 70, conductive material 31, and layer 71. One of the multiple layers (e.g., layer 73) includes second insulator material 41, which includes at least one of (a) and (b), and another of the multiple layers (e.g., one or more of layers 72 and 74) does not include either of (a) and (b) (e.g., includes insulating material 24). In some embodiments, layer 73 is referred to as second insulator layer 73. In one embodiment, first insulator material 39 and second insulator material 41 have the same composition as one another, and in another embodiment, have different compositions from one another. In one embodiment and as shown, second insulator material 41 is not formed directly against top 62 of conductive material 31.

[0021] refer to Figure 6 、 7 7A, horizontally elongated trenches 40 have been formed (e.g., by anisotropic etching) through level 74, second insulator level 73, levels 72 and 71, first insulator level 70 (e.g., insulating material 42 thereof), and into stack 18 to form laterally spaced memory block regions 58. Horizontally elongated trenches 40 may have respective bottoms directly against (atop or within) conductive material 17 of conductor level 16 (as shown) or may have respective bottoms above conductive material 17 of conductor level 16 (not shown).

[0022] The above process shows that the trench opening 25 is formed and filled before the trench 40 is formed. This can be reversed. Alternatively, the trench 40 can be formed between the formation and filling of the trench opening 25 (not ideal). In addition, the above process shows that the first insulator material 39 is formed before the trench 40 is formed, but this can be reversed.

[0023] refer to Figure 8 、 9 , 9A, 10 and 11, and in one embodiment, material 26 (not shown) of conductive layer 22 has been removed, for example, by isotropically etching away material that is ideally selective relative to other exposed materials (e.g., using liquid or vapor H3PO4 as the primary etchant, wherein material 26 is silicon nitride, first insulator material 39 and second insulator material 41 include (a) and / or (b), respectively, and the other materials include one or more oxides or polysilicon). Material 26 (not shown) in conductive layer 22 in the example embodiment is sacrificial and has been replaced with conductive material 48 and has thereafter been removed from trench 40, thereby forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0024] A thin insulating liner (e.g., Al2O3 and not shown) may be formed before forming the conductive material 48. The approximate location of the transistor and / or memory cell 56 is determined by Figure 11 The brackets in the text indicate that some Figure 8 、 9 9A , where the transistors and / or memory cells 56 are substantially annular or ring-shaped in the depicted example. Alternatively, the transistors and / or memory cells 56 may not completely surround the individual channel openings 25 so that each channel opening 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surrounding individual channel openings in individual conductive layers, where each channel opening in the individual conductive layers may have multiple word lines, not shown). The conductive material 48 may be considered to have terminals 50 ( ) corresponding to the control gate regions 52 of the individual transistors and / or memory cells 56. Figure 11 ). Control gate region 52 in the depicted embodiment includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 can be considered as memory structure 65 laterally interposed between control gate region 52 and channel material 36. In one embodiment and as shown with respect to an example "gate-last" process, conductive material 48 of conductive layer 22 is formed after forming channel opening 25 and / or trench 40. Alternatively, for example with respect to a "gate-first" process, conductive material (not shown) of conductive layer 22 can be formed before forming channel opening 25 and / or trench 40.

[0025] A charge blocking region (e.g., charge blocking material 30) is interposed between storage material 32 and individual control gate regions 52. The charge block can have the following functions in a memory cell: in programming mode, the charge block can prevent charge carriers from transferring from the storage material (e.g., floating gate material, charge trapping material, etc.) toward the control gate, and in erase mode, the charge block can prevent charge carriers from flowing from the control gate into the storage material. Thus, the charge block can be used to block charge migration between the control gate region and the storage material of an individual memory cell. As shown, the example charge blocking region comprises insulator material 30. By way of further example, where the storage material (e.g., material 32) is insulating (e.g., where there is no material of different composition between insulating storage material 32 and conductive material 48), the charge blocking region can comprise a laterally (e.g., radially) outer portion of such storage material. Regardless, as an additional example, in the absence of any separating composition insulator material 30, the interface of the storage material with the conductive material of the control gate can be sufficient to function as a charge blocking region. Furthermore, the interface of conductive material 48 and material 30 (when present) in conjunction with insulator material 30 can together serve as a charge blocking region and, alternatively or additionally, can serve as a lateral outer region of an insulating storage material, such as silicon nitride material 32. Example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0026] refer to Figure 12 、 13 , 13A, and 14, and in one embodiment, interposer material 57 has been formed in trench 40 between laterally adjacent memory block regions 58. Interposer material 57 can provide lateral electrical isolation (insulation) between laterally adjacent memory block regions 58 and the final memory block 58. This can include one or more of insulating, semiconducting, and conductive materials and can in any case facilitate shorting of conductive layers 22 to each other in the finished circuitry configuration. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. In one embodiment, interposer material 57 includes a laterally outermost insulating material (e.g., silicon dioxide and / or silicon nitride, not shown) and a laterally inner material (e.g., undoped polysilicon, not shown) of a different composition than the laterally outermost insulating material. In one such embodiment, the laterally inner material is insulating. In one embodiment, interposer material 57 insulates throughout between laterally adjacent memory blocks.

[0027] refer to Figure 15 , and in one embodiment, another insulating layer 75 has been formed over layer 74 and interposer material 57. In one such embodiment, layer 75 comprises another of the multiple layers mentioned above (e.g., along with one or more of layers 72 and 74 in the depicted embodiment), which does not include any of (a) and (b) (e.g., including insulating material 24). Example thicknesses for layers 70, 71, 72, 73, and 75 are 100 to 600 angstroms, and an example thickness for layer 74 is 100 to 200 angstroms.

[0028] In one embodiment, the contact opening is formed through at least the second insulator layer. Figure 16 、 17 17A, which shows contact openings 61 formed through levels 75, 74, 73 (and the second insulator material 41 therein) and 72 (e.g., by etching) to conductive material 31. Thereafter, conductive vias 43 have been formed therein and are individually electrically coupled directly through conductive material 31 (i.e., at least partially) to individual strings of channel material 53. Conductive vias 43 may also directly abut channel material 36, as shown. Due to mask misalignment in the example depicted, contact openings 61 and the conductive vias 43 therein may extend into level 71 (not shown) and to and / or into level 70 (not shown). Alternatively, trenches 40 and / or the intervening fill material 57 therein may be formed sometime after conductive vias 43 are formed (including sometime after contact openings 61 and / or the conductive vias 43 therein are formed).

[0029] Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used with respect to the above-described embodiments.

[0030] Figure 18 and 18A An alternative embodiment configuration 10a is shown in FIG. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences indicated by the suffix "a" or by different numerals. In example configuration 10a, conductive material 31 is not formed to protrude upward from first insulator material 39, and in one such embodiment as shown, conductive material 31 and first insulator material 39 have coplanar, flat tops. Example layer 71 (not shown) is absent. Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0031] Figure 19 and Figure 19A An alternative embodiment configuration 10b is shown in FIG. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences indicated by the suffix "b" or by different numerals. In example configuration 10b, second insulator material 41 of second insulator layer 73 has been formed directly against top 62 of conductive material 31. Example layer 72 is not present (not shown). Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0032] Figure 20 and 20A An alternative embodiment configuration 10c is shown in FIG. Like numerals from the above-described embodiments have been used where appropriate, with some construction differences indicated by the suffix "c" or by different numerals. In example configuration 10c, second insulator material 41 of second insulator layer 73 has been formed directly against top 62 of conductive material 31 in a configuration similar to that of configuration 10b. Example layers 71 and 72 are not present (not shown). Any other attributes or aspects as shown and / or described herein with respect to other embodiments may be used.

[0033] The present invention is directed to addressing the following processing challenges, but is not limited thereto. Consider a scenario in which the insulator material of level 72 and some of the memory cell materials 30, 32, and / or 34 comprise the same material (e.g., silicon dioxide). Without a second insulator material 41 at least somewhat vertically proximate to the tops of the memory cell materials 30, 32, and / or 34, the etching chemistry used to etch contact opening 61 could also etch this type of memory cell material through a slightly misaligned mask, which could extend the contact opening into the conductive material 48 (not shown) of conductive line 29, thereby creating a fatal short circuit when forming conductive via 43. Having second insulator material 41 at least somewhat vertically proximate to the tops of the memory cell materials 30, 32, and / or 34 eliminates or at least reduces this risk.

[0034] Alternative embodiment configurations may be generated from the method embodiments described above or in other ways. Regardless, embodiments of the present invention encompass memory arrays regardless of the manufacturing method. However, such memory arrays may have any of the properties described herein in the method embodiments. Similarly, the above-described method embodiments may incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0035] Embodiments of the present invention include a memory array (e.g., 12) comprising strings (e.g., 49) of memory cells (e.g., 56). The memory array includes a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). A first insulator layer (e.g., 70) is above the stack. A first insulator material (e.g., 39) of the first insulator layer comprises at least one of (a) and (b), wherein (a) includes silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b) includes silicon carbide. Channel material strings (e.g., 53) of the memory cells are within the stack. Channel material (e.g., 36) of the channel material strings is within the first insulator layer. Conductive material (e.g., 31) is within the first insulator layer, directly against the sides (e.g., 44) of the individual strings of channel material. A second insulator layer (e.g., 73) is above the first insulator layer and the conductive material. The second insulator material (e.g., 41) of the second insulator layer includes at least one of (a) and (b). Conductive vias (e.g., 43) extend through the second insulator layer and are individually electrically coupled directly to individual strings of channel material through the conductive material. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0036] The above processing or construction may be viewed relative to an array of components formed as a single stack or single level of such components described above, or within a single stack or single level, or as part of an underlying base substrate (although a single stack / level may have multiple levels). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed anywhere as part of the finished construction, and in some embodiments may be below the array (e.g., under-array CMOS). Regardless, one or more additional such stacks / levels may be provided or fabricated above and / or below those shown in the figures or described above. Furthermore, the component arrays may be identical or different in different stacks / levels, and different stacks / levels may have the same thickness or different thicknesses. Intervening structures (e.g., additional circuitry and / or dielectric layers) may be provided between vertically adjacent stacks / levels. Furthermore, different stacks / levels may be electrically coupled to one another. Multiple stacks / levels may be fabricated separately and sequentially (e.g., one on top of another), or two or more stacks / levels may be fabricated at substantially the same time.

[0037] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic systems can be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting devices, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, and the like.

[0038] In this document, unless otherwise indicated, "vertical," "higher," "up," "down," "top," "above," "bottom," "above," "below," "below," "under," "upward," and "downward" generally refer to a vertical direction. "Horizontal" refers to a general direction along the surface of a primary substrate (i.e., within 10 degrees) and may be relative to the substrate being processed during fabrication, and vertical is a direction generally perpendicular thereto. Reference to "perfectly horizontal" is a direction along the surface of a primary substrate (i.e., not angled thereto) and may be relative to the substrate being processed during fabrication. Furthermore, as used herein, "vertical" and "horizontal" are directions generally perpendicular to one another and are independent of the orientation of the substrate in three-dimensional space. Furthermore, "extending vertically" and "extending vertically" refer to directions that deviate from perfectly horizontal by at least 45°. Furthermore, "extending vertically," "extending vertically," "extending horizontally," "extending horizontally," and the like with respect to a field effect transistor refer to the orientation of the channel length of the transistor along which current flows between the source / drain regions during operation. For bipolar junction transistors, "extending vertically," "extending vertically," "extending horizontally," "extending horizontally," and the like refer to the orientation of the substrate length along which current flows between the emitter and collector during operation. In some embodiments, any components, features, and / or regions extending vertically extend perpendicularly or within 10° of the perpendicular.

[0039] Furthermore, the terms "directly above," "directly below," and "directly beneath" require that the two regions / materials / components have at least some lateral overlap (i.e., horizontally) relative to one another. Furthermore, the use of "above" without a preceding "directly" only requires that some portion of the region / material / component that is above another region / material / component is vertically outside of the other region / material / component (i.e., regardless of whether there is any lateral overlap between the two regions / materials / components). Similarly, the use of "below" and "beneath" without a preceding "directly" only requires that some portion of the region / material / component that is below / beneath another region / material / component is vertically inside of the other region / material / component (i.e., regardless of whether there is any lateral overlap between the two regions / materials / components).

[0040] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any case may be continuously or discontinuously overlying any material. Where one or more example compositions of any material are provided, the material may comprise, consist essentially of, or consist of such one or more compositions. Furthermore, unless otherwise stated, each material may be formed using any suitable technique, whether currently available or yet to be developed, examples being atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation.

[0041] In addition, "thickness" itself (without a directional adjective) is defined as the average straight-line distance perpendicular to the closest surface of the adjacent material or adjacent area of ​​different compositions through a given material or area. In addition, the various materials or areas described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, then unless otherwise indicated, the thickness refers to the average thickness, and due to the variable thickness, this material or area will have a minimum thickness and a maximum thickness. As used herein, for example, if such a material or area is heterogeneous, then "different compositions" only require that the portions of the two materials or areas that can directly abut each other are chemically and / or physically different. If such a material or area is not homogeneous and if the two materials or areas do not directly abut each other, then "different compositions" only require that the portions of the two materials or areas that are closest to each other are chemically and / or physically different. In this document, a material, area or structure is "directly against" another material, area or structure when the materials, areas or structures are in at least some physical contacting contact with each other. In contrast, the terms "over," "on," "adjacent," "along," and "against" without the preceding "directly" encompass "directly against" as well as configurations in which intervening materials, regions, or structures result in the materials, regions, or structures not physically touching each other.

[0042] As used herein, regions, materials, and components are "electrically coupled" to one another if, during normal operation, electrical current can flow continuously from one region, material, and component to another, primarily through the movement of subatomic positive and / or negative charges (when sufficient subatomic positive and / or negative charges are generated). Another electronic component may be between the region, material, and components and electrically coupled to the region, material, and components. In contrast, when the region, material, and components are referred to as being "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled region, material, and components.

[0043] Any use of the terms "row" and "column" in this document is for the purpose of distinguishing one series or orientation of features from another series or orientation of features along which a component has been or may be formed. "Row" and "column" are used synonymously with respect to any series of regions, components, and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel to one another, as can columns. Furthermore, rows and columns can intersect one another at 90° or at one or more other angles (i.e., other than right angles).

[0044] Any of the conductive / conductor / conductive materials herein may be metallic materials and / or conductive-doped semiconductive / semiconductive / semiconductive materials. "Metallic material" refers to any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0045] As used herein, any use of "selective" with respect to etching, removal, deposition, forming, and / or formation refers to such action acting on one material relative to another material at a ratio of at least 2:1 by volume. Furthermore, any use of "selectively depositing," "selectively growing," or "selectively forming" refers to such action acting on one material relative to another material at a ratio of at least 2:1 by volume for at least the first 75 angstroms of deposition, growth, or formation.

[0046] Unless otherwise indicated, the use of "or" herein includes either and both.

[0047] Summarize

[0048] In some embodiments, a method for forming a memory array includes forming a stack comprising vertically alternating first and second layers. A first insulator layer is above the stack. A first insulator material of the first insulator layer comprises at least one of (a) and (b), wherein (a): silicon, nitrogen and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel material strings are in the stack and in the first insulator layer. Conductive material is directly against the sides of individual ones of the channel material strings in the first insulator layer. A second insulator layer is formed above the first insulator layer and the conductive material. A second insulator material of the second insulator layer comprises at least one of (a) and (b). Conductive vias are formed and extend through the second insulator layer and are individually electrically coupled directly to the individual channel material strings through the conductive material.

[0049] In some embodiments, a method for forming a memory array includes forming a stack comprising vertically alternating first and second layers. A first insulator layer is formed above the stack. A first insulator material of the first insulator layer comprises at least one of (a) and (b), wherein (a) includes silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b) includes silicon carbide. Channel material strings are formed in the stack and in the first insulator layer. Conductive material is directly against the sides of individual strings of channel material in the first insulator layer. Multiple insulating layers are formed above the first insulator layer and the conductive material. One of the multiple layers includes a second insulator material, the second insulator material including at least one of (a) and (b), and another of the multiple layers does not include either of (a) and (b). Contact openings are etched through the one layer and the other layer, and thereafter conductive vias are formed in the contact openings, each conductive via being electrically coupled directly to the individual strings of channel material through the conductive material.

[0050] In some embodiments, a memory array comprises a vertical stack comprising alternating insulating and conductive layers. A first insulator layer is above the stack. A first insulator material of the first insulator layer comprises at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. Channel material strings of memory cells are in the stack. The channel material of the channel material strings is in the first insulator layer. The conductive material in the first insulator layer is directly against the sides of individual strings of channel material. A second insulator layer is above the first insulator layer and the conductive material. A second insulator material of the second insulator layer comprises at least one of (a) and (b). Conductive vias extend through the second insulator layer and are individually electrically coupled directly to individual strings of channel material through the conductive material.

Claims

1. A method for forming a memory array, comprising: forming a stack (18) comprising vertically alternating first and second layers (20, 22), with a first insulator layer (70) above the stack; a first insulator material (39) of the first insulator layer comprising at least one of (a) and (b), wherein (a) is silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b) is silicon carbide; strings of channel material (53) are in the stack and in the first insulator layer, and conductive material (31) is directly against the side of individual strings of channel material in the first insulator layer; forming a second insulating layer (73) above the first insulating layer (70) and the conductive material (31), wherein the second insulating material (41) of the second insulating layer comprises at least one of (a) and (b), and the first insulating material (39) and the second insulating material (41) of the first insulating layer (70) and the second insulating layer (73) do not directly abut against each other; and Conductive vias (43) are formed extending through the second insulator layer, the conductive vias being individually electrically coupled directly to the individual strings of channel material through the conductive material. 2 . The method of claim 1 , comprising forming the first insulator material and the second insulator material to have the same composition as each other. 3 . The method of claim 1 , comprising forming the first insulator material and the second insulator material to have different compositions from each other. The method of claim 1 , comprising forming the second insulator material directly against the top of the conductive material. The method of claim 1 , wherein the second insulator material is not formed directly against the top of the conductive material. The method of claim 1 , comprising forming the conductive material to protrude upwardly from the first insulator material. The method of claim 1 , wherein the conductive material is not formed to protrude upward from the first insulator material.

8. The method of claim 7, wherein the conductive material and the first insulator material have coplanar flat tops.

9. The method of claim 1 , comprising forming horizontally elongated trenches through the first insulator level, through the second insulator level, and into the stack to form laterally spaced memory block regions, and An interposer material is formed in the trench.

10. The method of claim 9, comprising forming the horizontally elongated trench through insulating material in the first insulator layer, the insulating material not comprising either (a) or (b).

11. The method according to claim 1 , comprising: forming the first layer to include a sacrificial material; selectively etching the sacrificial material from the first level relative to the second level; and The sacrificial material from the first level is replaced with conductive material of individual conductive lines in the first level.

12. The method of claim 1, wherein the first insulator material comprises (a).

13. The method of claim 12, wherein the one or more of carbon, oxygen, boron, and phosphorus in the first insulator material has a total concentration of at least about 2 atomic percent.

14. The method of claim 13, wherein the total concentration does not exceed about 20 atomic percent.

15. The method of claim 13, wherein the one or more of carbon, oxygen, boron, and phosphorus in the first insulator material has a total concentration of at least about 4 atomic percent.

16. The method of claim 15, wherein the total concentration is at least about 10 atomic percent.

17. The method of claim 12, wherein the one or more of the first insulator materials comprises carbon.

18. The method of claim 12, wherein the one or more of the first insulator materials comprises oxygen.

19. The method of claim 12, wherein the one or more of the first insulator materials comprises boron.

20. The method of claim 12, wherein the one or more of the first insulator materials comprises phosphorus.

21. The method of claim 12, wherein the one or more of the first insulator materials include only one of carbon, oxygen, boron, and phosphorus.

22. The method of claim 12, wherein the one or more of the first insulator materials include at least two of carbon, oxygen, boron, and phosphorus.

23. The method of claim 1, wherein the first insulator material comprises (b).

24. The method of claim 1, wherein the first insulator material comprises both (a) and (b).

25. The method of claim 1, wherein the second insulator material comprises (a).

26. The method of claim 1, wherein the second insulator material comprises (b).

27. A method for forming a memory array, comprising: forming a stack comprising vertically alternating first and second layers; forming a first insulator layer over the stack, wherein a first insulator material of the first insulator layer comprises at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide; forming strings of channel material in the stack and in the first insulator level, conductive material directly against sides of individual strings of channel material in the first insulator level; forming a plurality of insulating layers over the first insulating layer and the conductive material, one of the plurality of insulating layers comprising a second insulating material, the second insulating material comprising at least one of (a) and (b), the first insulating material and the second insulating material of the first insulating layer and the one of the plurality of insulating layers not directly abutting against each other, and another of the plurality of insulating layers not comprising either (a) or (b); and Contact openings are etched through the one and the other of the plurality of insulating levels and thereafter conductive vias are formed in the contact openings, the conductive vias individually electrically coupled directly to the individual strings of channel material through the conductive material.

28. The method of claim 27, comprising forming said one of said plurality of insulating levels directly against a top of said conductive material.

29. The method of claim 27, wherein the one of the plurality of insulating levels is not formed directly against a top of the conductive material.

30. A memory array comprising: A vertical stack comprising alternating insulating and conductive layers; a first insulator layer above the vertical stack, wherein a first insulator material of the first insulator layer comprises at least one of (a) and (b), wherein (a) is silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b) is silicon carbide; a channel material string of a memory cell in the vertical stack, the channel material of the channel material string being in the first insulator level; conductive material directly against the sides of individual strings of channel material in the first insulator level; a second insulator layer above the first insulator layer and the conductive material, wherein the second insulator material of the second insulator layer comprises at least one of (a) and (b), and the first insulator material and the second insulator material of the first insulator layer and the second insulator layer, respectively, do not directly abut against each other; and Conductive vias extend through the second insulator layer, the conductive vias individually electrically coupling directly to the individual strings of channel material through the conductive material.

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