MEMS package structure and packaging process

Abstract

The application relates to the technical field of electronic packaging, and discloses a MEMS packaging structure and a packaging process, wherein the packaging structure comprises a substrate wafer and a cap wafer; a first thermal resistance layer is arranged on the substrate wafer; a first insulating layer is arranged on the first thermal resistance layer; and a bonding layer is arranged between the cap wafer and the first insulating layer; a through hole is arranged on the substrate wafer at a position corresponding to the first thermal resistance layer; an electrode material is filled in the through hole to form a current welding electrode; and the electrode material is connected with the first thermal resistance layer. The packaging structure can heat the thermal resistance layer to a certain temperature by directly inputting current into the current welding electrode, and then transfer the heat to the bonding layer through the insulating layer; the temperature can be controlled by adjusting the current size; the traditional packaging technology needs to use a heating substrate system for heating, and the whole wafer device does not need to be heated, so that the heat damage and the device layer failure caused by the whole packaging structure heating to the chip internal device layer are avoided.

Description

Technical Field

[0001] This invention relates to the field of electronic packaging technology, and more specifically, to a MEMS packaging structure and packaging process. Background Technology

[0002] In the field of high-vacuum MEMS packaging, there are high requirements for the compatibility of packaging processes and the sealing performance of packaging structures. The compatibility between the packaging process and the chip device layer determines whether the chip's performance will be degraded or even damaged during the tape-out process. Therefore, selecting a suitable packaging process is of great significance for the performance protection and stable operation of the chip device layer. A suitable packaging process and packaging structure can provide a stable and safe working environment for the chip device layer, protecting the chip from physical, chemical, biological, and other destructive factors, and greatly extending the lifespan of the chip for high-performance operation.

[0003] Currently, MEMS metal bonding packaging is the mainstream form of MEMS wafer-level packaging technology. It mainly uses two metals as bonding solders, one with a high melting point and the other with a low melting point. The two metals are deposited on the bonding ring and heated and pressurized, causing the two metal layers with different melting points to react and generate intermetallic compounds to form a tightly sealed welding layer. Finally, a stable, safe, high-vacuum sealed environment is formed to provide a stable long-term working environment for the chip.

[0004] However, traditional metal bonding has the following drawbacks:

[0005] 1. Metal bonding generally requires heating and pressurizing the entire device layer. Different metal bonding processes require different temperatures, generally between 200℃ and 450℃. For example, the Au-Sn bonding temperature, which has excellent vacuum packaging performance, is around 300-400℃. Therefore, device layers that cannot withstand process temperatures of 300℃ cannot use Au-Sn combination metal bonding processes. They can only use other metal combinations with lower bonding temperatures but weaker bonding shear forces, which will affect the performance and lifespan of the chip device to some extent.

[0006] 2. Traditional metal bonding mainly uses a heating substrate of similar size to the wafer to heat the entire wafer during the heating process. Such a heating system is relatively wasteful in terms of cost, and it is not possible to flexibly control the rise and fall of the substrate heating temperature during the bonding process. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to overcome the defects of the prior art and provide a MEMS packaging structure that does not require heating the entire wafer device.

[0008] This invention also provides a MEMS packaging process.

[0009] The objective of this invention is achieved through the following technical solution:

[0010] A MEMS packaging structure includes a substrate wafer and a cap wafer. The substrate wafer has a first thermal resistance layer and a first insulating layer. A bonding layer is disposed between the cap wafer and the first insulating layer. A through-hole is formed on the substrate wafer at a position corresponding to the first thermal resistance layer. The through-hole is filled with electrode material to form a current welding electrode. The electrode material is connected to the first thermal resistance layer.

[0011] Furthermore, a second thermal resistance layer and a second insulating layer are sequentially disposed between the cap wafer and the bonding layer, with the second thermal resistance layer in contact with the cap wafer; a through hole is formed on the cap wafer at the corresponding position of the second thermal resistance layer, and the through hole is filled with cap electrode material to form a current welding electrode, with the cap electrode material connected to the second thermal resistance layer.

[0012] A MEMS packaging process using current bonding includes the following steps:

[0013] S1. Etch through holes on the substrate wafer;

[0014] S2. A conductive material is deposited in the through-hole of the substrate wafer to form a current welding electrode;

[0015] S3. A metal thin film layer is deposited on the current bonding electrode of the substrate wafer as a thermal resistance layer, and the metal thin film layer is patterned.

[0016] S4. An insulating thin film layer is grown on the patterned metal thin film layer formed in S3. The patterned insulating thin film layer and the patterned metal thin film layer are consistent.

[0017] S5. Etch bonding rings into the deep silicon of the capped wafer;

[0018] S6. Deposit bonding solder on the insulating thin film layer of the substrate wafer and pattern the bonding solder;

[0019] S7. Plate bonding solder at the bonding ring position of the cap wafer;

[0020] S8. Apply current to the welding electrode and perform current welding bonding and packaging on the substrate wafer and the cap wafer in a vacuum environment.

[0021] Furthermore, the metal thin film layer is made of Pt material and is deposited using a stripping process.

[0022] Furthermore, the insulating film layer is made of AlN material, and the patterning process for the insulating film layer is dry etching.

[0023] Furthermore, the bonding solder is deposited using vapor deposition or electroplating processes.

[0024] Furthermore, the bonding solder can be a metallic or non-metallic solder.

[0025] Furthermore, the bonding solder on the cap wafer is formed by vapor deposition or electroplating using a stripping process.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] 1) The packaging structure of this application can directly heat the thermal resistance layer to a certain temperature by applying current to the current bonding electrode, and then transfer the heat to the bonding layer through the insulating layer. The temperature can be controlled by the current magnitude, which overturns the traditional packaging technology that requires a heating substrate system for heating. It does not require heating the entire wafer device, thus avoiding thermal damage and device failure caused by heating the entire packaging structure to the internal device layer of the chip.

[0028] 2) The localized bonding ring heating area formed by the TSV-type current soldering packaging process of this application will not affect the performance of the device layer. Therefore, the range of metal solders with different melting points is much wider than that of traditional packaging methods, and the process compatibility is stronger, which can avoid the impact of high temperature of metal bonding on the device. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the MEMS packaging structure described in Example 1;

[0030] Figure 2 This is a schematic diagram of the MEMS packaging structure described in Example 2;

[0031] Figure 3 This is a schematic diagram of the MEMS packaging process described in Example 1. Detailed Implementation

[0032] The present invention will be further described below with reference to specific embodiments. The accompanying drawings are for illustrative purposes only and are schematic diagrams, not actual pictures, and should not be construed as limiting the present patent. In order to better illustrate the embodiments of the present invention, some parts in the drawings may be omitted, enlarged or reduced, and do not represent the actual product size. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the drawings.

[0033] Example 1

[0034] like Figure 1The MEMS packaging structure shown includes a substrate wafer 1 and a cap wafer 2. A first thermal resistance layer 3 is provided on the substrate wafer 1, and a first insulating layer 4 is provided on the first thermal resistance layer 3. A bonding layer 5 is provided between the cap wafer 2 and the first insulating layer 4. A through hole 11 is formed on the substrate wafer 1 at the corresponding position of the first thermal resistance layer 3. The through hole 11 is filled with electrode material 6 to form a current welding electrode. The electrode material 6 is connected to the first thermal resistance layer 3.

[0035] Current is applied to the welding electrode, causing the first thermal resistance layer to generate heat and rise in temperature. The first insulating layer acts as a heat-conducting layer. The first insulating layer is made of a material with good insulation and strong thermal conductivity. The first insulating layer transfers the temperature to the bonding layer. When the first thermal resistance layer heats up to the temperature required for bonding of the bonding layer, the bonding and encapsulation can be completed.

[0036] This packaging structure eliminates the need for heating the substrate wafer and cap wafer as a whole, effectively saving process costs. During the packaging process, the temperature can be controlled by adjusting the applied voltage or current, offering flexible temperature control and a simple and easy-to-operate packaging process.

[0037] Example 2

[0038] See Figure 2 In this embodiment, based on Embodiment 1, a second thermal resistance layer 7 and a second insulating layer 8 are sequentially provided between the cap wafer 2 and the bonding layer 5. The second thermal resistance layer 7 is in contact with the cap wafer 2. A through-hole 21 is formed on the cap wafer 2 at the corresponding position of the second thermal resistance layer 7. The through-hole 21 is filled with cap electrode material 9 to form a current bonding electrode, and the cap electrode material 9 is connected to the second thermal resistance layer 7. Compared with Embodiment 1, the packaging structure of this embodiment can further improve the bonding and packaging efficiency because heating can be performed both above and below the bonding layer.

[0039] Example 3

[0040] A packaging process for the MEMS packaging structure described in Embodiment 1 is provided, which employs current bonding packaging, specifically TSV-type current bonding. The packaging process is described in [reference needed]. Figure 3 It includes the following steps:

[0041] S1. Perform standard RCA cleaning on the substrate wafer, rinse with deionized water, and purge with nitrogen.

[0042] S2. On the substrate wafer, the areas where vias need to be made are exposed by processes such as spin coating, photolithography, and development. Vertical vias are etched using deep silicon etching equipment. The size of the vias can be selected between 10um and 100um.

[0043] S3. A Cu seed layer is deposited at the via location of the substrate wafer using a PVD device, and then Cu is filled into the via using an electroplating process to form a current welding electrode.

[0044] S4.a) A metal thin film layer is deposited as a thermal resistance layer at the current bonding electrode of the substrate wafer using a lift-off process, and the metal thin film layer is then patterned. Generally, Pt metal with high thermal conductivity and high thermal resistance is selected as the metal thin film layer. The morphology of the patterned thermal resistance layer is slightly larger than that of the bonding layer.

[0045] b) Perform standard RCA cleaning on the capped wafer, rinse with deionized water, and purge with nitrogen.

[0046] S5.a) Deposit a high thermal conductivity AlN or other insulating thin film layer with good insulation and high thermal conductivity on the patterned metal thin film layer formed in S4 to separate the thermal resistance layer and the bonding solder. Then, use dry etching to pattern the insulating thin film layer. The morphology and size of the patterned insulating thin film layer are consistent with the thermal resistance layer.

[0047] b) After the capped wafer is homogenized, exposed, developed, and baked, deep silicon etching is performed to etch out deep cavities and bonding rings.

[0048] S6.a) Deposit the metal or non-metal solder to be bonded on the insulating thin film layer of the substrate wafer using a vapor deposition or electroplating process, and pattern the bonding solder using a stripping process.

[0049] b) Similarly, a stripping process is used to vapor-deposit or electroplate solder for bonding at the bonding ring position of the capping wafer;

[0050] The above-mentioned solders include metal solders with a combination of several of Ti, Ni, Cu, Sn, Au, and Pt, and non-metallic solders include glass pastes or resin-based non-metallic materials used for temporary bonding.

[0051] S7. Apply current to the welding electrodes and perform current bonding and packaging process on the substrate wafer and the cap wafer in a vacuum environment. Use a pressure substrate with energized electrodes to perform high vacuum current bonding and packaging in a high vacuum environment.

[0052] The TSV current-bonding packaging process of this application mainly involves heating the metal thin film layer (thermal resistance layer) under the bonding ring by passing current through it. The bonding process occurs when the thermal resistance layer reaches the required bonding temperature, thus avoiding heating the entire wafer device. The current bonding only locally heats the bonding ring area, providing excellent protection for the heat-sensitive device layer. The locally heated bonding ring area formed by current bonding has virtually no impact on the device layer's performance. Therefore, the range of solder combinations with different melting points is far wider than that used in traditional packaging, offering strong process compatibility. The best solder combination for bonding performance can be selected without considering the possibility of high-temperature damage to the device layer during bonding.

[0053] The packaging process can integrate incompatible high-temperature-sensitive chips and metal solders with high bonding temperatures and high shear strength onto a single wafer for metal bonding without damaging the chip structure. This solves the current problem of incompatibility between metal bonding packaging and some chip structure processes, and reduces performance degradation or failures caused by the high-temperature environment of the bonding packaging process on the chip device layers.

[0054] Furthermore, compared to traditional heating systems, this TSV-type MEMS current-bonding packaging structure is simpler and more convenient in terms of heating process. It does not require complex heating, cooling, and temperature control systems. Instead, it uses the magnitude of the current to regulate and stabilize the temperature, greatly reducing equipment costs, process costs, and process time. In addition, this packaging process can perform secondary or multiple current-bonding bonding on individual chips with substandard bonding strength, gaps in the bonding ring, or insufficient bonding, improving chip production capacity and the sustainability of chip use.

[0055] Obviously, the above embodiments are merely examples to clearly illustrate the technical solutions of the present invention, and are not intended to limit the implementation of the present invention. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively describe all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A MEMS packaging structure, characterized in that, The packaging structure includes a substrate wafer and a cap wafer. A first thermal resistance layer is provided on the substrate wafer, and a first insulating layer is provided on the first thermal resistance layer. A bonding layer is provided between the cap wafer and the first insulating layer. A through-hole is formed on the substrate wafer at a position corresponding to the first thermal resistance layer. The through-hole is filled with electrode material to form a current welding electrode. The electrode material is connected to the first thermal resistance layer. The packaging process of the MEMS packaging structure adopts current bonding packaging, which specifically includes the following steps: S1. Etch through holes on the substrate wafer; S2. A conductive material is deposited in the through-hole of the substrate wafer to form a current welding electrode; S3. A metal thin film layer is deposited on the current bonding electrode of the substrate wafer as a thermal resistance layer, and the metal thin film layer is patterned. S4. An insulating thin film layer is grown on the patterned metal thin film layer formed in S3. The patterned insulating thin film layer and the patterned metal thin film layer are consistent. S5. Etch bonding rings into the deep silicon of the capped wafer; S6. Deposit bonding solder on the insulating thin film layer of the substrate wafer and pattern the bonding solder; S7. Plate bonding solder at the bonding ring position of the cap wafer; S8. Apply current to the welding electrodes and perform current welding bonding and encapsulation of the substrate wafer and the cap wafer in a vacuum environment; The metal thin film layer is made of Pt material and is deposited using a stripping process.

2. The MEMS packaging structure according to claim 1, characterized in that, A second thermal resistance layer and a second insulating layer are sequentially disposed between the cap wafer and the bonding layer, with the second thermal resistance layer in contact with the cap wafer; a through hole is formed on the cap wafer at the corresponding position of the second thermal resistance layer, and the through hole is filled with cap electrode material to form a current welding electrode, with the cap electrode material connected to the second thermal resistance layer.

3. The MEMS packaging structure according to claim 1, characterized in that, The insulating film layer is made of AlN material, and the patterning process of the insulating film layer is dry etching.

4. The MEMS packaging structure according to claim 1, characterized in that, The bonding solder is deposited using vapor deposition or electroplating processes.

5. The MEMS packaging structure according to claim 1 or 4, characterized in that, The bonding solder is a metallic or non-metallic solder.

6. The MEMS packaging structure according to claim 1, characterized in that, The bonding solder on the cap wafer is formed by vapor deposition or electroplating using a stripping process.

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