A non-volatile storage device, a programming method, and a memory system

Abstract

Embodiments of the present application disclose a non-volatile storage device, including: a peripheral circuit, which is coupled to a memory cell array and is configured to perform successive first programming and second programming on the memory cell array for a first physical page and a second physical page in a cache programming manner; the peripheral circuit includes a plurality of page buffers respectively coupled to bit lines, and each page buffer includes: a main latch, (N - 1) data latches, and a cache latch coupled to a data path; the main latch is configured to be able to store first non-physical page information; the peripheral circuit is further configured to, during the programming of the first physical page, when the programming verification of the 2<supgt;(N - M)< / supgt;th memory state passes, make the identifiers of the corresponding first to 2<supgt;(N - M)< / supgt;th memory states stored in the main latch different from the identifiers of the corresponding 2<supgt;(N - M)< / supgt; + 1 to 2<supgt;N< / supgt;th memory states, where M is an integer greater than or equal to 1 and less than or equal to (N - 2).

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and particularly to a non-volatile storage device, a programming method, and a memory system. Background Art

[0002] In a non-volatile storage device, data is first quickly stored in a cache latch and then moved to a data latch. In related technologies, during a single programming process of writing data into the physical array of a flash memory, only one movement of page data from the cache latch to the data latch can be achieved. As a result, when the number of data pages to be programmed and written into the physical array is more than one, after the programming ends, the movement of page data from the cache latch to the data latch needs to be carried out separately, making the efficiency of writing data into the memory cell array low and the programming lack continuity. Summary of the Invention

[0003] In view of this, the main object of the present application is to provide a non-volatile storage device, a programming method, and a memory system.

[0004] To achieve the above object, the technical solution of the present application is realized as follows:

[0005] An embodiment of the present application provides a non-volatile storage device, including:

[0006] A memory cell array, in which the memory cells are arranged in rows and columns, and each memory cell is configured to store N-bit data, where N is an integer greater than 1;

[0007] A peripheral circuit, coupled to the memory cell array, configured to perform successive first programming and second programming on the memory cell array for a first physical page and a second physical page in a cache programming manner, and program a selected memory cell row based on N logical pages of the first physical page / second physical page during the first programming / second programming;

[0008] The peripheral circuit includes a plurality of page buffers respectively coupled to bit lines, and each page buffer includes: a main latch, (N - 1) data latches, and a cache latch coupled to a data path; wherein, the main latch is configured to be able to store first non-physical page information; the (N - 1) data latches and the one cache latch are used to temporarily store programming data of N logical pages to be written as N page latches during the process of performing the programming on N logical pages of the first physical page / second physical page;

[0009] The peripheral circuit is further configured to: during the process of programming the first physical page, complete the 1st to 2nd (N-M)During the programming operation of a memory state, a programming verification operation is performed on the programming operation corresponding to the second (N-M) memory state. When the programming verification of the second (N-M) memory state passes, the identifiers of the corresponding first to second (N-M) memory states stored in the master latch are made different from the identifiers of the corresponding second (N-M) +1 to second N memory states, and at least one of the N page latches is released to cache the programming data of at least one logical page of the N logical pages of the second physical page; and during the programming of the first physical page, the programming data of one logical page among the N logical pages of the second physical page is stored in the released one page latch, where M is an integer greater than or equal to 1 and less than or equal to (N - 2).

[0010] An embodiment of the present application further provides a non - volatile storage device, including:

[0011] A memory cell array, in which the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to store N - bit data, where N is an integer greater than 1;

[0012] Peripheral circuits, which are configured to perform successive first programming and second programming on the memory cell array in a cache programming manner for the first physical page and the second physical page respectively, and program the selected memory cell rows based on the N logical pages of the first physical page / second physical page during the first programming / second programming;

[0013] The peripheral circuits include a plurality of page buffers respectively coupled to bit lines, and each page buffer includes: a master latch, a bias latch, (N - 1) data latches, and a cache latch coupled to a data path. Among them, the bias latch is configured to be able to store second non - physical page information; the (N - 1) data latches and the one cache latch are used to temporarily store the programming data of the N logical pages to be written as N page latches during the process of performing the programming on the N logical pages of the first physical page / second physical page;

[0014] The peripheral circuits are further configured to: during the programming of the first physical page, disable the bit - line biasing function to release the bias latch to replace one of the N page latches for programming verification of the memory state, and release one of the N page latches to cache the programming data of one logical page of the N logical pages of the second physical page; and during the programming of the first physical page, store the programming data of one logical page among the N logical pages of the second physical page in the released one page latch.

[0015] An embodiment of the present application also provides a programming method for a non-volatile storage device. The non-volatile storage device includes a memory cell array and a peripheral circuit. The memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to store N bits of data, where N is an integer greater than 1. The peripheral circuit includes a plurality of page buffers respectively coupled to bit lines. The method includes:

[0016] Storing N logical pages of a first physical page corresponding to a current first programming in N page latches, where the N page latches include (N - 1) data latches in the page buffer and one cache latch coupled to a data path;

[0017] Storing first non-physical page information in a main latch in the page buffer;

[0018] During the process of performing the first programming on the first physical page, when programming operations for the 1st to the 2nd (N-M) memory states are completed, performing a programming verification operation on the programming operation corresponding to the 2nd (N-M) memory state. When the programming verification for the 2nd (N-M) memory state passes, making the identifiers stored in the main latch corresponding to the 1st to the 2nd (N-M) memory states different from the identifiers corresponding to the (2nd (N-M) + 1)th to the 2nd N memory states, and releasing at least one of the N page latches to cache programming data of at least one logical page of N logical pages of a second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N - 2); and

[0019] Before performing a second programming on the second physical page subsequent to the first programming in a cache programming manner and during the process of performing the first programming on the first physical page, storing the programming data of one logical page among the N logical pages of the second physical page in a released page latch.

[0020] An embodiment of the present application also provides another programming method for a non-volatile storage device. The non-volatile storage device includes a memory cell array and a peripheral circuit. The memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to store N bits of data, where N is an integer greater than 1. The peripheral circuit includes a plurality of page buffers respectively coupled to bit lines. The method includes:

[0021] Storing N logical pages of a first physical page corresponding to a current first programming in N page data latches, where the N page latches include (N - 1) data latches in the page buffer and one cache latch coupled to a data path;

[0022] Store the second non-physical page information in the bias latch in the page buffer;

[0023] During the process of programming the first physical page, disable the bit line bias function to release the bias latch to replace one of the N page latches for programming verification of the memory state, and release one of the N page latches;

[0024] Before the second programming of the second physical page subsequent to the first programming in cache programming mode and during the first programming of the first physical page, store the programming data of one of the N logical pages of the second physical page in the released page latch.

[0025] This application also provides a memory system, including:

[0026] At least one non-volatile storage device as described in any one of the above and a controller coupled to the non-volatile storage device and configured to control the non-volatile storage device.

[0027] Applying the non-volatile storage device, programming method and memory system provided by the embodiments of this application has the following technical effects: During the first programming process, the non-volatile storage device temporarily stores the programming data of various types of logical pages required for the second programming in the page latch. At the beginning of the second programming, there is no need to wait or reduce the waiting time, realizing the writing of the programming data of various types of logical pages of multiple physical pages during one programming process, improving the efficiency of data writing and the continuity between programming processes. Description of the Drawings

[0028] Figure 1 Schematic diagram of data writing of a non-volatile storage device provided for the related art;

[0029] Figure 2 Block diagram of a system with a non-volatile storage device provided by an embodiment of this application;

[0030] Figure 3A Schematic diagram of a memory card shown according to an exemplary embodiment of this application;

[0031] Figure 3B Schematic diagram of a solid state drive (SSD) shown according to an exemplary embodiment of this application;

[0032] Figure 4 Block diagram of a non-volatile storage device including a memory cell array and peripheral circuits provided by an embodiment of this application;

[0033] Figure 5Detailed block diagram of the page buffer in a programming operation provided by an embodiment of the present application;

[0034] Figure 6 State encoding table of user data without encoding conversion in the page latch provided by an embodiment of the present application;

[0035] Figure 7 Encoded state table after encoding conversion of the programming data of the temporarily stored logical page provided by an embodiment of the present application;

[0036] Figure 8 Encoded state table when the LV3 programming verification is passed and the DS function of the main latch is changed provided by an embodiment of the present application;

[0037] Figure 9 Encoded state table after the LV5 programming verification is passed provided by an embodiment of the present application;

[0038] Figure 10 Encoded state table after the LV6 programming verification is passed provided by an embodiment of the present application;

[0039] Figure 11 Specific implementation process schematic diagram of the programming method of the non-volatile storage device provided by another embodiment of the present application;

[0040] Figure 12 Encoded state table after encoding conversion of the programming data of the temporarily stored logical page provided by an embodiment of the present application;

[0041] Figure 13 Encoded state table after the LV4 programming verification is passed provided by an embodiment of the present application;

[0042] Figure 14 Encoded state table when the LV5 programming verification is passed and the DS function of the main latch is changed provided by an embodiment of the present application;

[0043] Figure 15 Encoded state table after the LV6 programming verification is passed provided by an embodiment of the present application;

[0044] Figure 16 Encoded state table after encoding conversion of the programming data of the temporarily stored logical page provided by an embodiment of the present application;

[0045] Figure 17 Encoded state table when the LV7 programming verification is passed and the DS function of the main latch is changed provided by an embodiment of the present application;

[0046] Figure 18 Encoded state table after the LV11 programming verification is passed provided by an embodiment of the present application;

[0047] Figure 19 The encoding status table provided by an embodiment of the present application, where the LV13 programming verification is passed and the DS function of the main latch is changed;

[0048] Figure 20 The encoding status table provided by an embodiment of the present application after the LV14 programming verification is passed;

[0049] Figure 21 The encoding status table after the programming data of the temporarily stored logic page is encoded and converted by an embodiment of the present application;

[0050] Figure 22 The encoding status table provided by an embodiment of the present application after the LV8 programming verification is passed;

[0051] Figure 23 The encoding status table provided by an embodiment of the present application after the LV12 programming verification is passed

[0052] Figure 24 The encoding status table provided by an embodiment of the present application when the LV13 programming verification is passed and the DS function of the main latch is changed;

[0053] Figure 25 The encoding status table provided by an embodiment of the present application after the LV14 programming verification is passed;

[0054] Figure 26 The encoding status table provided by an embodiment of the present application when the LV5 programming verification is passed and the bit line bias function is disabled;

[0055] Figure 27 The encoding status table provided by an embodiment of the present application after the LV6 programming verification is passed;

[0056] Figure 28 The schematic diagram of the specific implementation process of the programming method of the non-volatile storage device provided by an embodiment of the present application;

[0057] Figure 29 The encoding status table provided by an embodiment of the present application when the LV13 programming verification is passed and the bit line bias function is disabled;

[0058] Figure 30 The encoding status table provided by an embodiment of the present application after the LV14 programming verification is passed. Detailed implementation manners

[0059] The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the embodiments provided herein are only used to explain the present application and are not used to limit the present application. In addition, the embodiments provided below are partial embodiments for implementing the present application, rather than all embodiments for implementing the present application. In the case of different conflicts, the technical solutions described in the embodiments of the present application can be implemented in any combination.

[0060] It should be noted that in the embodiments of the present application, the term "including", "comprising" or any other variant is intended to cover non-exclusive inclusion, so that a method or device including a series of elements not only includes the elements clearly recorded, but also includes other elements not clearly listed, or also includes elements inherent to the implementation manner or device. Without more limitations, the element defined by the statement "including one..." does not exclude the existence of other related elements in the method or device including the element (such as steps in the method or units in the device, and the units can be partial circuits, partial processors, partial programs or software, etc.).

[0061] In a non-volatile storage device, data is first quickly stored in a cache latch and then moved to a data latch. A schematic diagram of data writing in a related non-volatile storage device is as Figure 1 shown. The time when the programming data of a logical page page3 of the second physical page is moved into the data latch is hidden in the first programming process. That is, in the first programming process of writing data into the physical array of the flash memory, only the movement of the programming data of one logical page out of the three logical pages of the second physical page from the cache latch to the data latch can be realized. When the number of physical pages programmed into the physical array is more than one, it is necessary to wait for the end of the programming and then separately move the programming data of the other two logical pages in the second physical page from the cache latch to the data latch, resulting in low efficiency of writing data into the memory cell array and lack of continuity in programming. The solution provided by the present disclosure enables the programming data of various types of logical pages required in the second programming to be temporarily stored in the page latch during the first programming process, without waiting or reducing waiting at the beginning of the second programming, improving the continuity between programming processes.

[0062] Figure 2 A block diagram of an exemplary system 200 with a non-volatile storage device is shown in accordance with some aspects of the present disclosure. The system 200 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 2As shown, the system 200 may include a host 208 and a memory system 202. The memory system 202 includes one or more non-volatile storage devices 204 and a controller 206. The non-volatile storage device 204 includes a memory cell array and a plurality of page buffers. The host 208 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)). The host 208 may be configured to send data to or receive data from the non-volatile storage device 204.

[0063] The non-volatile storage device 204 can be any non-volatile storage device disclosed in the present disclosure. According to some embodiments, the controller 206 is coupled to the non-volatile storage device 204 and the host 208 and is configured to control the storage device. The controller 206 can manage the data stored in the storage device and communicate with the host 208. In some embodiments, the controller 206 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a CompactFlash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the controller 206 is designed to operate in a high-duty-cycle environment such as a Solid State Drive (SSD) or an Embedded MultiMediaCard (eMMC), which are used as data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc., as well as enterprise storage devices. The controller 206 can be configured to control the operations of the non-volatile storage device 204, such as read, erase, and program operations. The controller 206 can also be configured to manage various functions regarding the data stored in or to be stored in the non-volatile storage device 204, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the controller 206 is also configured to process the Error Correction Code (ECC) regarding the data read from or written to the non-volatile storage device 204. The controller 206 can also perform any other suitable functions, such as formatting the non-volatile storage device 204. The controller 206 can communicate with external devices (e.g., the host 208) according to a specific communication protocol. For example, the controller 206 can communicate with external devices through at least one of various interface protocols, such as the USB protocol, the MMC protocol, the Peripheral Component Interconnect (PCI) protocol, the PCI Express (PCI-E) protocol, the Advanced Technology Attachment (ATA) protocol, the Serial ATA protocol, the Parallel ATA protocol, the Small Computer System Interface (SCSI) protocol, the Enhanced Small Disk Interface (ESDI) protocol, the Integrated Drive Electronics (IDE) protocol, the Firewire protocol, etc. The controller 206 can be specifically implemented by a microprocessor, a microcontroller (also known as a microcontroller unit (MCU)), a Central Processing Unit (CPU), a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Programmable Logic Device (PLD), a state machine, a gated logic unit, discrete hardware circuits, or a combination thereof, as well as other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0064] The controller 206 and one or more non-volatile storage devices 204 may be integrated into various types of storage devices, for example, including within the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 202 may be implemented and packaged into different types of terminal electronic products. In one example as shown in Figure 3A , the controller 206 and a single non-volatile storage device 204 may be integrated into a memory card 302. The memory card 302 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 302 may also include a memory card connector 304 that couples the memory card 302 to a host (e.g., the host 208 in Figure 2 ). In another example as shown in Figure 3B , the controller 206 and multiple non-volatile storage devices 204 may be integrated into an SSD 306. The SSD 306 may also include an SSD connector 308 that couples the SSD 306 to a host (e.g., the host 208 in Figure 2 ). In some embodiments, the storage capacity and / or operating speed of the SSD 306 is greater than the storage capacity and / or operating speed of the memory card 302.

[0065] Figure 4 A block diagram of a non-volatile storage device including a storage cell array 401 and a peripheral circuit 400 in an embodiment of the present application is shown. The peripheral circuit 400 includes a page buffer / sense amplifier 404, a column decoder / bit line (BL) driver 406, a row decoder / word line (WL) driver 408, a voltage generator 410, a control logic 412, a register 414, an interface 416, and a data bus 418. It should be understood that in some examples, additional peripheral circuits not shown in Figure 4 may also be included.

[0066] The page buffer / sense amplifier 404 may be configured to read data from the memory cell array 401 and program (write) data to the memory cell array 401 according to control signals from the control logic 412. In one example, the page buffer / sense amplifier 404 may store the programming data (write data, also referred to herein as "data page") of a logical page to be programmed into a physical page of the memory cell array 401. As described in detail below and consistent with the scope of the present application, in a programming operation, the page buffer / sense amplifier 404 may include a plurality of page buffers respectively coupled to bit lines, each page buffer including (N - 1) data latches and a cache latch coupled to the data path for temporarily storing segments of N-bit data received from the data bus 418 and providing the segments of N-bit data to corresponding selected memory cells through the corresponding bit lines in a cache programming manner.

[0067] The column decoder / bit line (BL) driver 406 may be configured to be controlled by the control logic 412 and select one or more NAND memory strings by applying bit line voltages generated from the voltage generator 410. The row decoder / word line (WL) driver 408 may also be configured to drive word lines using word line voltages generated from the voltage generator 410. The voltage generator 410 may be configured to be controlled by the control logic 412 and generate word line voltages (e.g., read voltages, programming voltages, channel pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 401.

[0068] The control logic 412 may be coupled to each of the peripheral circuits described above and be configured to control the operation of each peripheral circuit. The register 414 may be coupled to the control logic 412 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses for controlling the operation of each peripheral circuit. The interface 416 may be coupled to the control logic 412 and act as a control buffer. The control logic 412 may be implemented by a microcontroller (also known as a microcontroller unit (MCU)), a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a programmable logic device (PLD), a state machine, a gated logic unit, discrete hardware circuits, or a combination thereof, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below.

[0069] Please refer to Figure 4, the peripheral circuit 400 is configured to perform a first programming and a second programming on the memory cell array 401 for the first physical page and the second physical page in a cache programming manner successively, and program the selected memory cell rows based on the N logical pages of the first physical page / second physical page during the first programming / second programming process. In some embodiments, user data is transmitted to the page buffer / sense amplifier 404 through the data bus 418, and the page buffer / sense amplifier 404 is configured to convert the user data into programming data for each logical page to be programmed into the selected memory cell rows based on a preset rule. During the ongoing first programming operation, the programming data of the N logical pages of the first physical page can be temporarily stored in the page buffer / sense amplifier 404.

[0070] Figure 5 FIG. shows a detailed block diagram of the page buffer / sense amplifier 404 in a programming operation in an embodiment of the present application. In some embodiments, the page buffer / sense amplifier 404 includes a plurality of page buffer circuits 502, and each page buffer circuit 502 is coupled to a corresponding one of the bit lines BL. In other words, each page buffer circuit 502 can be coupled to the memory cells (e.g., a certain memory cell string) of the corresponding column through the corresponding bit line BL, and is configured to temporarily store the programming data of the N logical pages of the first physical page / second physical page for programming the selected memory cell rows during the programming operation. In some embodiments, the page buffer circuit 502 is further configured to preprocess the user data received from the data bus 418 (as Figure 4 shown) and convert it into programming data for the N logical pages of the first physical page / second physical page to be programmed into the selected memory cell rows based on a preset rule.

[0071] As Figure 5 shown, each page buffer circuit 502 may include (N - 1) data latches (D1 to Dn - 1) 508 and a cache latch (DC) 506 coupled to the data path, and the (N - 1) data latches 508 and the one cache latch 506 are used to temporarily store the programming data to be written to the N logical pages as N page latches during the process of programming the N logical pages of the first physical page / second physical page.

[0072] Each page buffer circuit 502 may further include a plurality of memory cells for storing non - physical page information. The non - physical page information refers to other information except the programming data of the logical pages in the physical page, which is different from, for example, the programming data of the N logical pages. The non - physical page information can be used to assist in implementing the data programming process of the physical page during the programming process, and generally is not temporarily stored in the data latches. As Figure 5As shown, in some embodiments, the page buffer circuit 502 includes a main latch (DS) 512 configured to store verification information and programming information, and a bias latch (DL) 510 configured to store voltage bias information of the corresponding bit lines. Each page buffer circuit 502 may further include a bias circuit 504, which is coupled to the corresponding bit line BL and is configured to apply a bit line voltage to the corresponding selected memory cell row coupled to the corresponding bit line BL during a programming operation.

[0073] In an embodiment of the present application, a non-volatile storage device includes: a memory cell array, where the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to store, for example, 3-bit data; a peripheral circuit, which is coupled to the memory cell array, and the peripheral circuit is configured to perform successive first programming and second programming on the memory cell array in a cache programming manner for a first physical page and a second physical page, and to program a selected memory cell row based on three logical pages of the first physical page / second physical page during the first programming / second programming, and the three logical pages are respectively a lower page (LP), a middle page (MP), and an upper page (UP); the peripheral circuit includes a plurality of page buffers respectively coupled to bit lines, and each page buffer includes: a main latch DS, two data latches D1, D2, and a cache latch DC coupled to a data path; wherein, the main latch DS is configured to be able to store first non-physical page information; the two data latches D1, D2, and the one cache latch DC are used to temporarily store programming data to be written to the three logical pages as three page latches during the process of performing the programming on the three logical pages of the first physical page / second physical page; the peripheral circuit is further configured to: during the process of programming the first physical page, when the programming operations of the first to second (N-M) memory states are completed, perform a programming verification operation on the programming operation of the corresponding second (N-M) memory state, and when the programming verification of the second (N-M) memory state passes, cause the main latch to perform non-target verification, that is, cause the identifiers stored in the main latch corresponding to the first to second (N-M) memory states to be different from the corresponding second (N-M) +1 to second Nidentifying a memory state, and releasing at least one of the N page latches to cache programming data of at least one logical page of N logical pages of a second physical page; and during the programming of the first physical page, storing the programming data of one logical page among the N logical pages of the second physical page in a released page latch, where M is an integer greater than or equal to 1 and less than or equal to (N - 2) (for example, for TLC, N = 3, M = 1). In a specific embodiment, the non-volatile storage device includes a three-dimensional NAND flash memory device.

[0074] In an embodiment of the present application, the peripheral circuit is further configured to use an incremental step pulse programming (ISPP) method to perform a programming operation on the 1st to 2nd (N-M) memory states during the programming of the first physical page / second physical page. In a specific example, for example, for TLC, N = 3, M = 1, the peripheral circuit is further configured to use an incremental step pulse programming (ISPP) method to perform a programming operation on the 1st to 2nd 2 memory states during the programming of the first physical page / second physical page.

[0075] In a specific embodiment, each memory cell has 8 memory states (levels) and can therefore store three-bit data. Each memory state can correspond to one of 2 3 threshold voltage (Vth) ranges of the memory cell. On the other hand, each memory state can correspond to one of 2 3 segments of the three-bit data to be stored in the selected memory cell row. Specifically, please refer to Figure 6 , Figure 6 which is a state encoding table for temporarily storing user data in a page latch provided by an embodiment of the present application, showing an example of binary encoding of a one-to-one mapping between 8 memory states (LV0 to LV7) and 8 segments. Each segment of the three-bit data can be composed of three-bit binary encoding, and the three-bit binary encoding comes from 3 logical pages respectively, and the 3 logical pages are the low page (LP), the middle page (MP), and the high page (UP). It can be seen that the 3 page latches store the programming data of the low, middle, and high logical pages in sequence. The page latch D1 stores the low page LP, the page latch D2 stores the middle page MP, and the page latch DC stores the high page UP. In one example, the memory state LV1 can correspond to a segment with the encoding 011. In another example, the memory state LV7 can correspond to another segment with the encoding 101. Figure 7 This is an encoding state table after encoding and converting the programming data of the logical pages stored in the page latch according to a preset rule in an embodiment of the present application. After encoding and conversion, as shown in Figure 7As shown, LVl is encoded from 011 to 001, where 011 comes from LP / MP / UP in sequence respectively. Similarly, the encoding order of other memory states is LP / MP / UP. LV2 is encoded from 001 to 101, LV3 is encoded from 000 to 011, LV4 is encoded from 010 to 000, and so on. LV5 is encoded from 110 to 010, LV6 is encoded from 100 to 100, and LV7 is encoded from 101 to 110.

[0076] In the embodiment of the present application, the peripheral circuit is further configured to: before programming verification of the second memory state among the two memory states, store the programming data of a corresponding logical page among the N logical pages of the first physical page in at least one of the N page latches; and after programming verification of the second memory state among the two memory states, store the programming data of a logical page among the N logical pages of the second physical page in at least one of the N page latches. In a specific embodiment, before programming verification of the fourth memory state LV3 among the eight memory states, DC can store the programming data of a logical page (current UP) among the three logical pages of the first physical page, and D1 can store the programming data of the corresponding logical page (current LP) of the first physical page, and D2 can store the programming data of the corresponding logical page (current MP) of the first physical page. And after programming verification of the fourth memory state LV3 among the eight memory states, store the programming data of a logical page among the three logical pages of the second physical page in the three page latches. For details, please refer to N the second N-1 memory state, store the programming data of a corresponding logical page among the N logical pages of the first physical page in at least one of the N page latches; and after programming verification of the second N memory state, store the programming data of a logical page among the N logical pages of the second physical page in at least one of the N page latches. In a specific embodiment, before programming verification of the fourth memory state LV3 among the eight memory states, DC can store the programming data of a logical page (current UP) among the three logical pages of the first physical page, and D1 can store the programming data of the corresponding logical page (current LP) of the first physical page, and D2 can store the programming data of the corresponding logical page (current MP) of the first physical page. And after programming verification of the fourth memory state LV3 among the eight memory states, store the programming data of a logical page among the three logical pages of the second physical page in the three page latches. For details, please refer to N-1 Figure 8 Figure 8 .

[0077] In the embodiment of the present application, the peripheral circuit is configured to: after programming verification of the second N memory state among the two memory states, perform non-target verification on the main latch DS, that is, make the identifiers stored in the main latch DS corresponding to the first to the second N-1 memory states different from the identifiers corresponding to the second (N-1) memory state to the second (N-1) memory state. Specifically, please refer to N Figure 8 Figure 8, after programming verification of the fourth memory state among the eight memory states (i.e., the fourth memory state LV3 has been verified), the identifiers corresponding to the first to fourth memory states stored in the master latch DS are made different from the identifiers corresponding to the fifth to eighth memory states, that is, the identifiers of the memory states that have passed the programming verification in the master latch are different from the identifiers of the memory states that have not passed the programming verification. When DS is 1, it indicates that the programming verification of this memory state has passed, and when DS is 0, it indicates that the programming verification of this memory state has not passed. LV3 programming verification passed (LV3pass) means that in the three page latches, the segments corresponding to the memory states LV0 to LV3 have all been written. Among them, all the binary codes in LV0 to LV3 can be updated to 1, and the coding state table is as Figure 8 shown. At this time, there are still 4 memory states LV4, LV5, LV6, and LV7 that have not passed the programming verification. Since each bit of each logical page has two possible states, 0 and 1, a physical unit composed of two page latches has 4 possible states (2 2 = 4). Since the identifier of the memory state that has not passed the programming verification in the master latch DS for non-target verification is 0, the combination of the two page latches and the master latch DS for non-target verification can have the codes 000, 001, 010, and 011, which represent LV4, LV5, LV6, and LV7 respectively. In other words, after the LV3 programming verification passes, only two page latches and the master latch DS for non-target verification are needed to distinguish the 4 memory states LV4, LV5, LV6, and LV7. Therefore, after the LV3 programming verification passes, the page latch DC can be released to enable the released page latch to cache the programming data of the lower page LP of the second physical page, and the coding state table is as Figure 8 shown.

[0078] In one embodiment, each page buffer further includes: a bias latch configured to store voltage bias information of a corresponding bit line.

[0079] In the embodiments of the present application, the peripheral circuit is further configured to: make the identifiers corresponding to the first to second (N-M) memory states stored in the master latch different from the corresponding second (N-M) +1 to second NAfter identifying the memory states, the bit lines are floated during programming to dump the first non-physical page information in the master latch. In some embodiments, the first non-physical page information includes verification information and programming information. Since the master latch DS is used to identify the memory states that have passed programming verification and those that have not after the LV3 programming verification passes, it is no longer possible to continue storing the first non-physical page information in the original master latch DS. Floating the bit lines during programming can idle the bias latch to dump the first non-physical page information in the master latch.

[0080] In the embodiments of the present application, after the LV5 programming verification passes, it means that the segments corresponding to the memory states LV0 - LV5 in the three page latches have been written. At this time, there are still 2 memory states LV6 and LV7 that have not passed programming verification. Since each bit of each logical page has two possible states, 0 and 1, the master latch DS and the page latch D2 can form the codes 00 and 01, which can respectively represent the memory states LV6 and LV7 that have not passed programming verification. Therefore, after the LV5 programming verification passes, the page latch D1 can be released so that the released page latch caches the middle page MP of the next physical page. The coding status table is as Figure 9 shown.

[0081] In the embodiments of the present application, the peripheral circuit is further configured to: after programming verification of the penultimate memory state among the 2 N memory states, release N of the page latches so that N of the page latches cache the programming data of each page of the N logical pages of the second physical page. In a specific embodiment, after programming verification of the penultimate memory state among 8 memory states (i.e., the 7th memory state (LV6) has been verified), release 3 of the page latches so that 3 of the page latches cache the programming data of each page (the next LP, the next MP, the next UP) of the 3 logical pages of the second physical page, as Figure 10As shown, when the programming verification of LV6 is passed, i.e., DS is 1, the page latch D2 can release the programming data of the middle page MP of the second physical page, and further release the page latch DC to cache the programming data of the upper page UP of the second physical page. At this time, 3 page latches are released to store all the programming data of each of the three logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, and the page latch DC caches the programming data of the upper page UP of the second physical page. And thereafter, whether DS is 1 can be used to determine whether the programming verification of LV7 is passed. If DS is 1, it means that the programming verification of LV7 is passed, indicating that the data of LV0 to LV7 have been written into the selected storage unit, and the first programming is completed. At this time, the programming data of the 3 logical pages to be written in the second programming have been cached in 3 page latches and can directly enter the second programming process. If DS is 0, the verification fails and the programming verification judgment continues. Since after the programming verification of LV6, 3 page latches can cache the programming data of each of the 3 logical pages (the next LP, the next MP, and the next UP) of the second physical page, the second physical page can become ready during the first programming operation. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without a data loading window.

[0082] Based on the non-volatile storage device provided in the above embodiment of the present application, an embodiment of the present application also provides a programming method for a non-volatile storage device. Wherein, the non-volatile storage device includes a storage cell array and a peripheral circuit; the storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to store N-bit data, where N is an integer greater than 1; the peripheral circuit includes a plurality of page buffers respectively coupled to bit lines; the method includes: storing N logical pages of a first physical page corresponding to the current first programming in N page latches, the N page latches including (N - 1) data latches in the page buffer and a cache latch coupled to the data path; storing first non-physical page information in a main latch of the page buffer; during the process of performing the first programming on the first physical page, when the programming operations of the 1st to the 2nd (N-M) memory states are completed, a programming verification operation is performed on the programming operation corresponding to the 2nd (N-M) memory state. When the programming verification of the 2nd (N-M) memory state passes, the identifiers stored in the main latch corresponding to the 1st to the 2nd (N-M) memory states are made different from the corresponding 2nd (N-M) +1 to the 2nd Nidentification of a memory state, and releasing at least one of the N page latches to cache programming data of at least one logical page of N logical pages of a second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N - 2); and storing programming data of one logical page among the N logical pages of the second physical page in the released one page latch before a second programming of the second physical page in a cache programming manner subsequent to the first programming and during a process of the first programming of the first physical page.

[0083] Figure 11 is a schematic diagram of a specific implementation process of a programming method for a non-volatile storage device provided by an embodiment of the present application, as Figure 11 shown, the programming method specifically includes the following steps:

[0084] Step S101: Store N logical pages of a first physical page corresponding to a current first programming in N page latches, where the N page latches include (N - 1) data latches in the page buffer and one cache latch coupled to a data path;

[0085] After storing programming data of three logical pages, namely LP, MP, and UP, in the page latches, perform encoding conversion on the programming data stored in the page latches according to a preset rule to obtain binary codes corresponding to different memory states. Specifically, please refer to Figure 7 .

[0086] Step S102: Store first non-physical page information in a main latch of the page buffer. Here, the first non-physical page information includes verification information and programming information;

[0087] In step S101, each storage unit is configured to store 3-bit data in one of 8 memory states. Before programming verification of the 4th memory state among the 8 memory states, store programming data of a corresponding one of the 3 logical pages of the first physical page in at least one of the 3 page latches; in a specific embodiment, before programming verification of the 4th memory state LV3 among the 8 memory states, DC can store programming data of one (current UP) of the 3 logical pages of the first physical page corresponding to the current first programming, and D1 can store programming data of the corresponding logical page (current LP) of the first physical page, and D2 can store programming data of the corresponding logical page (current MP) of the first physical page. And after programming verification of the 4th memory state among the 8 memory states, store programming data of one logical page among the 3 logical pages of the second physical page in at least one of the 3 page latches. In a specific example, please refer to Figure 8, after programming verification of the fourth memory state LV3 among the eight memory states, store the programming data of one of the three logical pages of the second physical page in at least one of the three page latches.

[0088] Step S103: During the first programming of the first physical page, when the programming operations of the 1st to 2nd (N-M) memory states are completed, perform a programming verification operation on the programming operation corresponding to the 2nd (N-M) memory state. When the programming verification of the 2nd (N-M) memory state passes, make the identifiers of the corresponding 1st to 2nd (N-M) memory states stored in the master latch different from the identifiers of the corresponding 2nd (N-M) +1 to 2nd N memory states, and release at least one of the N page latches to cache the programming data of at least one of the N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N - 2); and

[0089] Before the second programming of the second physical page subsequent to the first programming in a cache programming manner and during the first programming of the first physical page, store the programming data of one logical page among the N logical pages of the second physical page in the released one page latch.

[0090] In the above step S103, taking TLC as an example, N = 3 and M = 1. The first programming / second programming of the first physical page / second physical page includes: performing programming operations on the 1st to 2nd 2 memory states using the Incremental Step Pulse Programming (ISPP) programming method.

[0091] In the embodiment of the present application, before programming verification of the 2nd N memory state among the 2 N-1 memory states, store the programming data of the corresponding one logical page among the N logical pages of the first physical page in at least one of the N page latches; and before programming verification of the 2nd N memory state among the 2 N-1After programming verification of the memory states, the programming data of one logical page among the N logical pages of the second physical page is stored in at least one of the N page latches. In a specific embodiment, before programming verification of the 4th memory state LV3 among 8 memory states, DC can store the programming data of one logical page (current UP) among the 3 logical pages of the first physical page, and D1 can store the programming data of the corresponding logical page (current LP) of the first physical page, and D2 can store the programming data of the corresponding logical page (current MP) of the first physical page. And after programming verification of the 4th memory state LV3 among 8 memory states, the programming data of one logical page among the 3 logical pages of the second physical page is stored in the 3 page latches. For details, please refer to Figure 8 。

[0092] In the embodiment of the present application, after programming verification of the 2 N nd memory state among the N-1 memory states, non-target verification is performed on the master latch DS, that is, the identifiers of the master latch DS corresponding to the 1st to 2nd (N-1) memory states are different from the identifiers corresponding to the 2nd (N-1) +1 to 2nd N memory states. Specifically, please refer to Figure 8 . After programming verification of the 4th memory state among 8 memory states (that is, the 4th memory state LV3 has been verified), the identifiers of the master latch DS corresponding to the 1st to 4th memory states are different from the identifiers corresponding to the 5th to 8th memory states, that is, the identifiers of the memory states that have passed programming verification and those that have not passed programming verification in the master latch are different. When DS is 1, it means that the programming verification of this memory state has passed, and when DS is 0, it means that the programming verification of this memory state has not passed. LV3 programming verification passed (LV3 pass) means that in the three page latches, the segments corresponding to the memory states LV0 to LV3 are all written in. Among them, all the binary codes in LV0 to LV3 can be updated to 1. The coding state table is as Figure 8 shown. At this time, there are still 4 memory states LV4, LV5, LV6, and LV7 that have not passed programming verification. Since one bit of each logical page has two possible states, 0 and 1, the physical unit composed of two page latches has 4 possible states (2 2= 4), since the identifier of the memory state that has passed the programmed verification in the main latch DS for non-target verification is 0, the combination of the two page latches and the main latch DS for non-target verification can have the encodings 000, 001, 010, and 011, which represent LV4, LV5, LV6, and LV7 respectively. In other words, after the LV3 programmed verification passes, only two page latches and the main latch DS for non-target verification are needed to distinguish the four memory states of LV4, LV5, LV6, and LV7. Therefore, after the LV3 programmed verification passes, the page latch DC can be released so that the released page latch caches the programming data of the lower page LP of the second physical page. The encoding status table is as Figure 8 shown.

[0093] In the embodiment of the present application, when the programmed verification of the 2 (N-M) th memory state passes, the identifiers of the corresponding 1st to 2 (N-M) th memory states stored in the main latch are made different from the identifiers of the corresponding 2 (N-M) +1 to 2 N th memory states, including: after the programmed verification of the 2 N th memory state among the 2 N-1 memory states, the main latch is made to perform non-target verification. The non-target verification is to make the identifiers of the corresponding 1st to 2 (N-1) th memory states stored in the main latch different from the identifiers of the corresponding 2 (N-1) +1 to 2 N th memory states. Specifically, please refer to Figure 8 . After the programmed verification of the 4th memory state among the 8 memory states (i.e., the 4th memory state LV3 has been verified), the main latch DS is made to perform non-target verification. The non-target verification is to make the identifiers of the corresponding 1st to 4th memory states stored in the main latch different from the identifiers of the corresponding 5th to 8th memory states. When DS is 1, it indicates that the memory state has passed the programmed verification, and when DS is 0, it indicates that the memory state has not passed the programmed verification.

[0094] In the embodiment of the present application, after the main latch performs non-target verification, the bit line is floated during programming to dump the first non-physical page information in the main latch. Since the non-target verification performed after the LV3 programmed verification passes makes the main latch identify the memory states that have passed the programmed verification and the memory states that have not passed the programmed verification, the first non-physical page information in the original main latch DS cannot be stored continuously. After the main latch performs non-target verification, floating the bit line during programming can idle the bias latch so as to dump the first non-physical page information in the main latch.

[0095] In an embodiment of the present application, after programming verification of the penultimate memory state among the two memory states, N page latches are released so that the N page latches cache the programming data of each of the N logical pages of the second physical page. In a specific embodiment, after programming verification of the penultimate memory state among eight memory states (i.e., the seventh memory state (LV6) has been verified), three page latches are released so that the three page latches cache the programming data of each of the three logical pages (next LP, next MP, next UP) of the second physical page. As N shown, when the programming verification of LV6 passes, i.e., DS is 1, the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page, and then the page latch DC can be further released to cache the programming data of the upper page UP of the second physical page. At this time, three page latches are released to store all the programming data of each of the three logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, and the page latch DC caches the programming data of the upper page UP of the second physical page. And thereafter, whether DS is 1 can be used to determine whether the programming verification of LV7 passes. If DS is 1, it means that the programming verification of LV7 passes, indicating that the data of LV0 to LV7 have been written into the selected storage unit, and this programming ends. At this time, the programming data of the three logical pages to be written in the second programming are already in the page latches and can directly enter the second programming process. If DS is 0, the verification fails and the programming verification continues to be judged. Figure 10

[0096] In another embodiment of the present application, different from the above embodiment, after the peripheral circuit included in the non-volatile storage device stores the programming data of three logical pages in three page latches, the programming data of the logical pages stored in the page latches is encoded and converted according to a preset rule to obtain as Figure 12 shown by Figure 6 ​The encoded status table after encoding conversion. Each memory state before encoding conversion consists of three - bit binary encoding, coming from LP / MP / UP respectively. After encoding conversion, Lv1 is encoded from 011 to 001, where 011 comes from LP / MP / UP in sequence. Similarly, the encoding order of other memory states is LP / MP / UP. Lv2 is encoded from 001 to 101, Lv3 is encoded from 000 to 011, Lv4 is encoded from 010 to 110, and so on. Lv5 is encoded from 110 to 000, Lv6 is encoded from 100 to 100, and Lv7 is encoded from 101 to 010. In a specific embodiment, before programming verification of Lv4 among 8 memory states, DC can store the programming data of one of the 3 logical pages of the first physical page (current UP), and D1 can store the programming data of the corresponding logical page (current LP) of the first physical page, and D2 can store the programming data of the corresponding logical page (current MP) of the first physical page. Lv4 programming verification passed (Lv4 pass) means that the segments corresponding to the memory states Lv0 - Lv4 in the three page latches are all written in. Among them, all binary encodings in Lv0 to Lv4 can be updated to 1, and the encoding status table is as Figure 13 shown, because they are no longer needed in the first programming operation. At this time, there are still 3 memory states Lv5, Lv6, and Lv7 that have not passed programming verification. Since one bit of each logical page has 2 possible states of 0 and 1, a physical unit composed of two page latches has 4 possible states (2 2 = 4). Excluding the encoding 11 that is the same as the memory state that has passed programming verification, there are still encodings 00, 10, and 01 that can represent Lv5, Lv6, and Lv7 respectively. In other words, after Lv4 programming verification passes, only two page latches are needed to distinguish the 3 memory states of Lv5, Lv6, and Lv7. Therefore, after Lv4 programming verification passes, the page latch DC can be released to replace the programming data of the current high page UP with the programming data of the low page LP of the second physical page.

[0097] In the embodiment of the present application, the peripheral circuit is further configured to: after programming verification of the third - last memory state among the 2 N memory states, perform non - target verification on the master latch. The non - target verification is to make the identifiers stored in the master latch corresponding to the 1st to the 2 N - 2 memory states different from the identifiers corresponding to the 2 N - 1st to the 2 NIdentification of a memory state. In a specific embodiment, after programming verification of the third-to-last memory state among 8 memory states (i.e., the sixth memory state (LV5) has been verified), the master latch DS is made to perform non-target verification. The non-target verification is to make the identification of the master latch storing the corresponding first to sixth memory states different from the identification of the corresponding seventh to eighth memory states. When DS is 1, it indicates that the programming verification of this memory state has passed; when DS is 0, it indicates that the programming verification of this memory state has not passed. It can be as follows Figure 14 shown for update Figure 13 of the binary encoding, where all data bits in LV5 can be updated to 1 because they are no longer needed in the current first programming operation. As Figure 14 shown, at this time, DS being 1 indicates that the programming verification of LV5 has passed. At this time, the master latch DS and the page latch D2 can form the encodings 00 and 01, which can represent LV6 and LV7 respectively. In other words, after the programming verification of LV5 passes, only one page latch and the master latch DS for non-target verification are needed to distinguish the two memory states of LV6 and LV7. Therefore, after the programming verification of LV5 passes, the page latch D1 can be released to cache the programming data of the low page LP of the second physical page, and further the page latch DC can be released to cache the programming data of the middle page MP of the second physical page. That is to say, the next LP can be transferred from DC to D1, and the programming data of the next MP can be cached in DC. It should be noted that when the master latch DS performs target verification, the status bit being programmed and verified is 1, while other status bits are 0.

[0098] Since the non-target verification performed after the verification of LV5 passes makes the identification of the master latch storing the corresponding first to sixth memory states different from the identification of the corresponding seventh to eighth memory states, the first non-physical page information in the original master latch DS cannot be stored continuously. After the master latch DS performs non-target verification, the bit lines are floated during programming to make the bias latch DL idle so as to dump the first non-physical page information in the master latch DS.

[0099] In the embodiment of the present application, the peripheral circuit is further configured to: when programming the 2 NAfter programming verification of the penultimate memory state among the N memory states, release the N page latches so that the N page latches cache the programming data of each of the N logical pages of the second physical page. In a specific embodiment, after programming verification of the penultimate memory state among 8 memory states (i.e., the 7th memory state (LV6) has been verified), release 3 of the page latches so that the 3 page latches cache the programming data of each of the 3 logical pages (next LP, next MP, next UP) of the second physical page, as Figure 15 shown. When the programming verification of LV6 passes, DS is 1, then the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page, and then the page latch DC can be further released to cache the programming data of the upper page UP of the second physical page. At this time, 3 page latches are released to store all the programming data of each of the three logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, and the page latch DC caches the programming data of the upper page UP of the second physical page. And thereafter, whether DS is 1 can be used to determine whether the programming verification of LV7 passes. If DS is 1, it means that the programming verification of LV7 passes, indicating that the data of LV0 to LV7 have been written into the selected storage unit, and the first programming ends. At this time, the programming data of the 3 logical pages to be written in the second programming have been cached in 3 page latches and can directly enter the second programming process. If DS is 0, the verification fails and the programming verification judgment continues. Since after the programming verification of LV6, 3 page latches can cache the programming data of each of the 3 logical pages (next LP, next MP, and next UP) of the second physical page, the second physical page can become ready during the first programming operation. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without a data loading window.

[0100] Based on the non-volatile storage device provided in the above embodiments of the present application, an embodiment of the present application also provides a programming method for a non-volatile storage device. The programming method specifically includes the following steps:

[0101] Step S201: Store the N logical pages of the first physical page corresponding to the current first programming in N page latches, where the N page latches include (N - 1) data latches in the page buffer and one cache latch coupled to the data path;

[0102] After storing the programming data of the three logical pages LP, MP, and UP in the page latches, perform encoding conversion on the programming data stored in the page latches according to a preset rule to obtain binary codes corresponding to different memory states. Specifically, please refer toFigure 12 。

[0103] Step S202: Store the first non-physical page information in the main latch of the page buffer. Here, the first non-physical page information includes verification information and programming information;

[0104] Step S203: During the first programming of the first physical page, when the programming operations of the 1st to 2nd (N-M) memory states are completed, perform a programming verification operation on the programming operation corresponding to the 2nd (N-M) memory state. When the programming verification of the 2nd (N-M) memory state passes, make the identifiers of the corresponding 1st to 2nd (N-M) memory states stored in the main latch different from the identifiers of the corresponding 2nd (N-M) +1 to 2nd N memory states, and release at least one of the N page latches to cache the programming data of at least one logical page of the N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N - 2); and

[0105] Before the second programming of the second physical page in a cache programming manner subsequent to the first programming and during the first programming of the first physical page, store the programming data of one logical page among the N logical pages of the second physical page in the released one page latch.

[0106] In the above step S203, taking TLC as an example, N = 3 and M = 1. The first programming / second programming of the first physical page / second physical page includes: performing programming operations on the 1st to 2nd 2 memory states using the Incremental Step Pulse Programming (ISPP) programming method.

[0107] In the embodiment of the present application, when the programming verification of the 2nd (N-M) memory state passes, making the identifiers of the corresponding 1st to 2nd (N-M) memory states stored in the main latch different from the identifiers of the corresponding 2nd (N-M) +1 to 2nd N memory states includes: after performing programming verification on the penultimate 3rd memory state among the 2 N memory states, making the main latch perform non-target verification, where the non-target verification is to make the identifiers of the corresponding 1st to 2 N -2 memory states stored in the main latch different from the identifiers of the corresponding 2 N -1 to 2 N memory states. Specifically, please refer toFigure 14 , after programming verification of the third-to-last memory state among the 8 memory states (i.e., the third-to-last memory state LV5 has been verified), the master latch DS is made to perform non-target verification. The non-target verification is to make the identifiers of the corresponding first to sixth memory states stored in the master latch different from the identifiers of the corresponding seventh to eighth memory states. When DS is 1, it indicates that the programming verification of this memory state passes; when DS is 0, it indicates that the programming verification of this memory state fails.

[0108] In the embodiment of the present application, after the non-target verification of the master latch, the bit lines are floated during programming to dump the first non-physical page information in the master latch. Since the non-target verification performed after the programming verification of LV3 makes the master latch used to identify the memory states that have passed the programming verification and the memory states that have not passed the programming verification, it is impossible to continue storing the first non-physical page information in the original master latch DS. After the non-target verification of the master latch DS, the bit lines are floated during programming to idle the bias latch DL so as to dump the first non-physical page information in the master latch DS.

[0109] In the embodiment of the present application, after programming verification of the second-to-last memory state among the N 2 memory states, N page latches are released to enable the N page latches to cache the programming data of each page in the N logical pages of the second physical page. In a specific embodiment, after programming verification of the second-to-last memory state among the 8 memory states (i.e., the seventh memory state (LV6) has been verified), 3 page latches are released to enable the 3 page latches to cache the programming data of each page (next LP, next MP, next UP) in the 3 logical pages of the second physical page, as Figure 15As shown, when the programming verification of LV6 is passed, i.e., DS is 1, the page latch D2 can release the programming data of the middle page MP of the second physical page cached in it, and further release the page latch DC to cache the programming data of the upper page UP of the second physical page. At this time, 3 page latches are released to store all the programming data of each of the three logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, and the page latch DC caches the programming data of the upper page UP of the second physical page. And thereafter, whether DS is 1 can be used to determine whether the programming verification of LV7 is passed. If DS is 1, it means that the programming verification of LV7 is passed, indicating that the data of LV0 to LV7 have been written into the selected storage unit, and the first programming is completed. At this time, the programming data of the 3 logical pages to be written in the second programming have been cached in 3 page latches and can directly enter the second programming process. If DS is 0, the verification fails and the programming verification continues to be judged.

[0110] An embodiment of the present application further provides a non-volatile storage device, which includes: a storage cell array, where the storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to store, for example, 4-bit data; a peripheral circuit, which is coupled to the storage cell array, and the peripheral circuit is configured to perform successive first programming and second programming on the storage cell array in a cache programming manner for the first physical page and the second physical page, and program the selected storage cell row based on 4 logical pages of the first physical page / the second physical page during the first programming / the second programming process, and the 4 logical pages are respectively the lower page (LP), the middle page (MP), the upper page (UP), and the extra page (XP); the peripheral circuit includes a plurality of page buffers respectively coupled to bit lines, and each page buffer includes: a main latch DS, three data latches D1, D2, D3, and a cache latch DC coupled to a data path; wherein, the main latch DS is configured to be able to store the first non-physical page information; the three data latches D1, D2, D3, and the one cache latch DC are used as 4 page latches to temporarily store the programming data to be written to the 4 logical pages during the process of performing the programming on the 4 logical pages of the first physical page / the second physical page; the peripheral circuit is further configured to: during the process of programming the first physical page, perform a programming verification operation on the programming operation corresponding to the second memory state when completing the programming operation of the first to second (N-M) memory states, and perform a programming verification operation on the programming operation corresponding to the second memory state during the programming operation of the second (N-M) memory state, and during the second (N-M)When the programming verification of the memory states is passed, the master latch is enabled, even if the identifiers of the corresponding first to second (N-M) memory states stored in the master latch are different from the identifiers of the corresponding second (N-M) +1 to second N memory states, and at least one of the four page latches is released to cache the programming data of at least one logical page of the four logical pages of the second physical page; and during the programming of the first physical page, the programming data of one logical page among the four logical pages of the second physical page is stored in the released one page latch.

[0111] In a specific embodiment, each memory cell has 16 memory states (levels) and thus can store four-bit data. Each memory state can correspond to one of the 2 4 threshold voltage (Vth) ranges of the memory cell. On the other hand, each memory state can correspond to one of the 2 4 fragments of the four-bit data to be stored in the selected row of memory cells. In a specific embodiment, the programming data of the logical page stored in the page latch is encoded and converted according to a preset rule to obtain the encoding corresponding to different memory states. Specifically, refer to Figure 16 which shows an example of the binary encoding of the one-to-one mapping between 16 memory states (LV0 to LV15) and 16 fragments after encoding conversion. Each fragment of the four-bit data can be composed of four-bit binary encoding, and the four-bit binary encoding comes from the four logical pages respectively, and the four logical pages are the low page LP, the middle page MP, the high page UP, and the extra page XP. It can be seen that the four page latches store the programming data of the four logical pages in sequence. The page latch D1 stores the low page LP, the page latch D2 stores the middle page MP, the page latch D3 stores the high page UP, and the page latch DC stores the extra page XP. After encoding conversion, as Figure 16 shown, the encoding of LVl is 0001, where 0001 comes from LP / MP / UP / XP in sequence. Similarly, the encoding order of other memory state bits is LP / MP / UP / XP. The encoding of LV2 is 1001, and so on. The encoding of LV7 is 1011, the encoding of LV8 is 0000, and the encoding of LV15 is 1110.

[0112] In the embodiment of the present application, the peripheral circuit is configured to: before the programming verification of the second N memory state among the 2 N-1 memory states, store the programming data of the corresponding one logical page among the N logical pages of the first physical page in at least one of the N page latches; and during the programming of the second N memory state among the 2N-1 After programming verification of a memory state, the programming data of one logical page among the N logical pages of the second physical page is stored in at least one of the N page latches. In a specific embodiment, before programming verification of the 8th memory state LV7 among 16 memory states, the DC can store the programming data of one logical page (current XP) among the 4 logical pages of the first physical page, and D1 can store the programming data of the corresponding logical page (current LP) of the first physical page, D2 can store the programming data of the corresponding logical page (current MP) of the first physical page, and D3 can store the programming data of the corresponding logical page (current UP) of the first physical page. And after programming verification of the 8th memory state LV7 among 16 memory states, the programming data of one logical page among the 4 logical pages of the second physical page is stored in the 4 page latches. For details, please refer to Figure 17 .

[0113] In the embodiments of the present application, the peripheral circuit is further configured to: after programming verification of the 2 N nd memory state among the N-1 2 memory states, perform non-target verification on the master latch DS, that is, make the identifiers of the corresponding 1st to 2nd (N-1) nd memory states stored in the master latch DS different from the identifiers of the corresponding 2 (N-1) +1 to 2 N nd memory states. Specifically, please refer to Figure 17 . After programming verification of the 8th memory state among 16 memory states (that is, the 8th memory state LV7 has been verified), make the identifiers of the corresponding 1st to 8th memory states stored in the master latch DS different from the identifiers of the corresponding 9th to 16th memory states, that is, make the identifiers of the memory states that have passed programming verification in the master latch different from the identifiers of the memory states that have not passed programming verification. When DS is 1, it indicates that the programming verification of this memory state has passed, and when DS is 0, it indicates that the programming verification of this memory state has not passed. At this time, the master latch DS and the page latches D1, D2, and D3 can form the codes 0000, 0001, 0010, 0011, 0100, 0101, 0110, and 0111, which can respectively represent LV8 to LV15. In other words, after the programming verification of LV7 passes, only three page latches and the master latch DS for non-target verification are needed to distinguish the 8 memory states of LV8 to LV15. Therefore, after the programming verification of LV7 passes, the page latch DC can be released to cache the programming data of the low page LP of the second physical page. The coding state table is as Figure 17As shown, at this time, DS being 1 indicates that the LV7 programming verification is passed, and the page latch DC can be released to cache the programming data of the low page LP of the second physical page.

[0114] Since the non-target verification performed after the LV7 programming verification is passed causes the master latch to be used to identify the memory states that have passed the programming verification and those that have not, the first non-physical page information in the original master latch DS cannot be stored continuously. After the non-target verification of the master latch DS, the bit lines are floated during programming to make the bias latch idle, thereby dumping the first non-physical page information in the master latch DS.

[0115] In the embodiment of the present application, passing the LV11 programming verification means that the segments corresponding to the memory states LV0 to LV11 in the four page latches are all written. At this time, there are still 4 memory states LV12, LV13, LV14, and LV15 that have not passed the programming verification. Since one bit of each logical page has two possible states, 0 and 1, two page latches have 4 possible states (2 2 = 4). During the non-target verification process, for the status bits DS of the unprogrammed verifications, they are all 0, and DS is 1 only when the status bit passes the programming verification. At this time, the master latch DS and the page latches D2 and D3 can form the encodings 000, 001, 010, and 011, which can respectively represent LV12 to LV15. In other words, after the LV11 programming verification is passed, only two page latches and the master latch DS for non-target verification are needed to distinguish the 4 memory states of LV12 to LV15. Therefore, after the LV11 programming verification is passed, the page latch D1 can be released to cache the programming data of the low page LP of the second physical page, and further the page latch DC can be released to cache the programming data of the middle page MP of the second physical page. The encoding status table is as Figure 18 shown.

[0116] Similarly, after the LV13 programming verification is passed, there are still 2 memory states LV14 and LV15 that have not passed the programming verification. During the non-target verification process, for the status bits DS of the unprogrammed verifications, they are all 0, and DS is 1 only when the status bit passes the programming verification. At this time, the master latch DS and the page latch D3 can form the encodings 00 and 01, which can respectively represent LV14 and LV15. In other words, after the LV13 programming verification is passed, only one page latch D3 and the master latch DS for non-target verification are needed to distinguish the 2 memory states of LV14 and LV15. Therefore, after the LV13 programming verification is passed, the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page, and further the page latch DC can be released to cache the programming data of the high page UP of the second physical page. The encoding status table is as Figure 19 shown.

[0117] In an embodiment of the present application, the peripheral logic circuit is further configured to: after programming verification of the second-to-last memory state among the two memory states, release N page latches, so that the N page latches cache the programming data of each of the N logical pages of the second physical page. In a specific embodiment, after programming verification of the second-to-last memory state among 16 memory states (i.e., the 15th memory state (LV14) has been verified), release 4 page latches, so that the 4 page latches cache the programming data of each of the 4 logical pages (next LP, next MP, next UP, next XP) of the second physical page. As N shown, when the programming verification of LV14 passes, i.e., DS is 1, the page latch D3 can be released to cache the programming data of the upper page UP of the second physical page, and then the page latch DC can be further released to cache the programming data of the extra page XP of the second physical page. At this time, 4 page latches are released to store the programming data of each of the four logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, the page latch D3 caches the programming data of the upper page UP of the second physical page, and the page latch DC caches the programming data of the extra page XP of the second physical page. And thereafter, whether DS is 1 can be used to determine whether the programming verification of LV15 passes. If DS is 1, it means that the programming verification of LV15 passes, indicating that the data of LV0 to LV15 has been written into the memory cell array, and the first programming is completed. At this time, the programming data of the four logical pages to be written in the second programming has been cached in 4 page latches and can directly enter the second programming process. If DS is 0, it fails and continues to perform programming verification judgment. Figure 20 In another embodiment of the present application, after the peripheral circuit included in the non-volatile storage device stores the programming data of 4 logical pages in 4 page latches, the programming data of the logical pages stored in the page latches is encoded and converted according to a preset rule to obtain an encoded state table after encoding conversion as shown in

[0118] shown, as Figure 21 shown, and obtain the encoded state table after encoding conversion as shown in Figure 21As shown, the data encoding of LV1 is 0001, where 0001 comes from LP / MP / UP / XP in sequence. Similarly, the encoding order of other memory states is LP / MP / UP / XP. The encoding of LV2 is 1001, and so on. The encoding of LV8 is 1110, and the encoding of LV15 is 1100. In a specific embodiment, before programming verification of LV8 among the 16 memory states, DC can store the programming data of one of the 4 logical pages (current XP) of the first physical page, and D1 can store the programming data of the corresponding logical page (current LP) of the first physical page, D2 can store the programming data of the corresponding logical page (current MP) of the first physical page, and D3 can store the programming data of the corresponding logical page (current UP) of the first physical page. LV8 programming verification passed (LV8 pass) means that the segments corresponding to the storage states LV0 to LV8 in the four page latches are all written in. At this time, there are still 7 memory states LV9, LV10, LV11 to LV15 that have not passed the programming verification. Since one bit of each logical page has two possible states, 0 and 1, there are 8 possible states for the three page latches (2 3 = 8). Excluding the encoding 111 that is the same as the memory state that has passed the programming verification, there are still 7 encodings that can represent LV9, LV10, LV11 to LV15 respectively. In other words, after LV8 programming verification passes, only three page latches are needed to distinguish the 7 memory states of LV9, LV10, LV11 to LV15. Therefore, after LV8 programming verification passes, the page latch DC can be released to store the programming data of the low page LP of the second physical page in the released page latch. The encoding state table is as Figure 22 shown.

[0119] Similarly, after LV12 programming verification passes, there are still 3 memory states LV13, LV14, LV15 that have not passed the programming verification. Since one bit of each logical page has two possible states, 0 and 1, there are 4 possible states for the two page latches (2 2 = 4). Excluding the encoding 11 that is the same as the memory state that has passed the programming verification, there are still 3 encodings, 00, 01, and 10, that can represent LV13, LV14, LV15 respectively. In other words, after LV12 programming verification passes, only two page latches are needed to distinguish the 3 memory states of LV13, LV14, LV15. Therefore, after LV12 programming verification passes, the page latch D1 can be released so that the released page latch D1 caches the programming data of the low page LP of the second physical page, thereby further releasing the page latch DC to cache the programming data of the middle page MP of the second physical page. The encoding state table is as Figure 23 shown.

[0120] In the embodiment of the present application, the peripheral circuit is specifically configured to: after programming verification of the third-to-last memory state among the 16 memory states, cause the master latch to perform non-target verification, where the non-target verification is to make the identifiers of the corresponding first to second N -2 memory states stored in the master latch different from the identifiers of the corresponding second N -1 to second N memory states. In a specific embodiment, after programming verification of the third-to-last memory state among the 16 memory states (i.e., the 14th memory state (LV13) has been verified), cause the master latch DS to perform non-target verification. The non-target verification is to make the identifiers of the corresponding first to 14th memory states stored in the master latch different from the identifiers of the corresponding 15th to 16th memory states. When DS is 1, it indicates that the programming verification of this memory state passes; when DS is 0, it indicates that the programming verification of this memory state fails. It can be updated Figure 24 as shown Figure 23 binary encoding, where all data bits in LV13 can be updated to 1 because they are no longer needed in the current first programming operation. As Figure 24 shown, at this time, the master latch DS and the page latch D3 can form the encodings 01 and 00, which can represent LV14 and LV15 respectively. In other words, after the programming verification of LV13 passes, only one page latch D3 and the master latch DS for non-target verification are needed to distinguish the two memory states of LV14 and LV15. Therefore, after the programming verification of LV13 passes, the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page, and further release the page latch DC to cache the programming data of the upper page UP of the second physical page. That is to say, the next MP can be transferred from DC to D2, and the programming data of the next UP can be cached in DC.

[0121] Since the non-target verification performed after the verification of LV13 passes makes the identifiers of the corresponding first to 14th memory states stored in the master latch different from the identifiers of the corresponding 15th to 16th memory states, it is impossible to continue storing the first non-physical page information in the original master latch DS. After the non-target verification of the master latch DS, the bit lines are floated during programming to idle the bias latch DL so as to dump the first non-physical page information in the master latch DS.

[0122] In the embodiment of the present application, the peripheral logic circuit is further configured to: after programming verification of the 2 NAfter programming verification of the penultimate memory state among the N memory states, release the N page latches so that the N page latches cache the programming data of each of the N logical pages of the second physical page. In a specific embodiment, after programming verification of the penultimate memory state among 16 memory states (i.e., the 15th memory state (LV14) has been verified), release 4 page latches so that the 4 page latches cache the programming data of each of the 4 logical pages (next LP, next MP, next UP, next XP) of the second physical page, as Figure 25 shown, when the programming verification of LV14 passes, DS is 1, then the page latch D3 can be released to cache the programming data of the upper page UP of the second physical page, and then the page latch DC can be further released to cache the programming data of the additional page XP of the second physical page. Then 4 page latches are released at this time to store all the programming data of the four logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, the page latch D3 caches the programming data of the upper page UP of the second physical page, and the page latch DC caches the programming data of the additional page XP of the second physical page. And thereafter, whether DS is 1 can be used to determine whether the programming verification of LV15 passes. If DS is 1, it means that the programming verification of LV15 passes, indicating that the data of LV0 to LV15 have been written into the selected storage unit, and the first programming ends. At this time, the programming data of the four logical pages to be written in the second programming have been cached in 4 page latches and can directly enter the second programming process. If DS is 0, it fails and continues to perform the programming verification judgment.

[0123] An embodiment of the present application also provides a non-volatile storage device, including: a memory cell array, where the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to store 3-bit data; a peripheral circuit configured to perform successive first programming and second programming on the memory cell array in a cache programming manner for a first physical page and a second physical page, respectively, and to program a selected memory cell row based on 3 logical pages of the first physical page / second physical page during the first programming / second programming, where the 3 logical pages are a low page LP, a middle page MP, and a high page UP; the peripheral circuit includes a plurality of page buffers respectively coupled to bit lines, and each page buffer includes: a main latch, a bias latch DL, (N - 1) data latches, and a cache latch coupled to a data path, where the bias latch is configured to be able to store second non-physical page information; the (N - 1) data latches and the one cache latch are used to temporarily store programming data to be written to N logical pages as N page latches during the process of performing the programming on N logical pages of the first physical page / second physical page (for example, for TLC, N = 3); the peripheral circuit is configured to: during the process of programming the first physical page, disable the bit line bias function to release the bias latch to replace one of the N page latches for programming verification of the memory state, and release one of the N page latches to cache programming data of one logical page of the N logical pages of the second physical page; and, during the process of programming the first physical page, store the programming data of one logical page of the N logical pages of the second physical page in the released one page latch. In a specific embodiment, the non-volatile storage device includes a three-dimensional NAND flash memory device.

[0124] In an embodiment of the present application, the peripheral circuit is further configured to use an incremental step pulse programming (ISPP) programming method to perform a programming operation on the 1st to 2nd (N-M) memory states during the process of programming the first physical page / second physical page.

[0125] In an embodiment of the present application, the second non-physical page information includes voltage bias information of the corresponding bit line.

[0126] In an embodiment of the present application, the peripheral circuit is further configured to: during the programming of the 2 N memory states, the (2 N-1Before programming verification of the (+1) memory states, store the programming data of a corresponding logical page among the N logical pages of the first physical page in at least one of the page latches. In a specific embodiment, before programming verification of the 5th memory state LV4 among 8 memory states, the DC can store the programming data of one (current UP) of the 3 logical pages of the first physical page, and D1 can store the programming data of the corresponding logical page (current LP) of the first previous physical page, and D2 can store the programming data of the corresponding logical page (current MP) of the second physical page. Perform the same encoding conversion on the programming data of different logical pages stored in the page latches. Figure 12 the same N After programming verification of the (2 N-1 +1) memory states among the 2 memory states, store one logical page among the N logical pages of the second physical page in at least one of the N page latches. That is, after the LV4 programming verification passes, release the page latch DC so that the released page latch caches the programming data of the low page LP of the second physical page. The encoding status table is as Figure 13 shown.

[0127] In the embodiment of the present application, the peripheral circuit is further configured to: disable the bit line biasing function after programming verification of the penultimate 3rd memory state among the 2 N memory states. In a specific embodiment, after programming verification of the penultimate 3rd memory state LV5 among 8 memory states, disable the bit line biasing function. Figure 26 The encoding status table after disabling the bit line biasing function provided by the embodiment of the present application shows that after disabling the bit line biasing function, the bias latch DL is idle and can be used to replace a page latch for programming verification of memory states. Then, the page latch D1 can be released to cache the programming data of the low page LP of the second physical page, and further the page latch DC can be released to cache the programming data of the middle page MP of the second physical page.

[0128] In the embodiment of the present application, the peripheral circuit is further configured to: reduce the step increment of the programming voltage after disabling the bit line biasing function. Since the bit line biasing function itself is to narrow the width of the threshold voltage distribution of the memory cells, after disabling the bit line biasing function, compensation can be made by reducing the step increment of the programming voltage. In this way, not only can the bias latch replace a page latch, but also the function of the non-volatile storage device is not affected.

[0129] In the embodiment of the present application, the main latch DS is configured to store verification information and programming information.

[0130] In the embodiment of the present application, the peripheral circuit is further configured to: when using the 2N After programming verification of the second-to-last memory state among the N memory states, release the N page latches so that the data latch caches each of the N logical pages of the next physical page. In a specific embodiment, after verifying the second-to-last memory state among 8 memory states (i.e., the 7th memory state (LV6) has been verified), release 3 of the page latches so that the 3 page latches cache the programming data of each of the 3 logical pages of the second physical page (the next LP, the next MP, the next UP). The encoding state table is as Figure 27 shown. When the programming verification of LV6 passes, there is still 1 memory state LV7 that has not passed the programming verification. Since one bit of each logical page has 2 possible states, 0 and 1, 1 latch has 2 possible states (2 1 = 2). In other words, after the programming verification of LV6 passes, only 1 bias latch DL is needed to determine whether the programming verification of LV7 passes. Therefore, after the programming verification of LV6 passes, the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page, and then the page latch DC can be further released to cache the programming data of the upper page UP of the second physical page. Then 3 page latches are released at this time to store all the programming data of each of the three logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, and the page latch DC caches the programming data of the upper page UP of the second physical page. And thereafter, it can be determined whether the programming verification of LV7 passes by whether DL is 1. If DL is 1, it means that the programming verification of LV7 passes, indicating that the data of LV0 - LV7 has been written into the selected storage unit, and the first programming ends. At this time, the programming data of the 3 logical pages to be written in the second programming has been cached in the page latches and can directly enter the second programming process. If DL is 0, the verification fails and the programming verification continues to be judged.

[0131] Based on the non-volatile storage device provided in the above embodiments of the present application, an embodiment of the present application further provides a programming method for a non-volatile storage device. The non-volatile storage device includes a memory cell array and a peripheral circuit. The memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to store N bits of data, where N is an integer greater than 1. The peripheral circuit includes a plurality of page buffers respectively coupled to bit lines. The method includes: storing N logical pages of a first physical page corresponding to a current first programming in N page latches, where the N page latches include (N - 1) data latches in the page buffer and a cache latch coupled to a data path; storing second non-physical page information in a bias latch in the page buffer; during the programming of the first physical page, disabling the bit line bias function to release the bias latch to replace one of the N page latches for programming verification of the memory state, and releasing one of the N page latches; before a second programming of a second physical page subsequent to the first programming in a cache programming mode and during the first programming of the first physical page, storing programming data of one of the N logical pages of the second physical page in the released page latch.

[0132] Figure 28 It is a schematic diagram of the specific implementation process of the programming method for the non-volatile storage device provided in the embodiment of the present application, as Figure 28 shown. The programming method specifically includes the following steps:

[0133] Step S301: Store N logical pages of a first physical page corresponding to a current first programming in N page latches, where the N page latches include (N - 1) data latches in the page buffer and a cache latch coupled to a data path;

[0134] After storing the programming data of the LP, MP, and UP three logical pages in the page latch, perform encoding conversion on the page data stored in the data latch according to a preset rule to obtain binary codes corresponding to different memory states. For details, please refer to Figure 12 .

[0135] In the above step S301, each storage cell is configured to store 3-bit data in one of eight memory states. Before programming verification of the fifth memory state LV4 among the eight memory states, the DC can store the programming data of one (current UP) of the three logical pages of the first physical page, and D1 can store the programming data of the corresponding logical page (current LP) of the first physical page, and D2 can store the programming data of the corresponding logical page (current MP) of the first physical page. Subsequently, the same coding conversion is performed on the programming data of different logical pages temporarily stored in the page latch, and after the LV4 programming verification passes, the page latch DC is released so that the released page latch caches the programming data of the low page LP of the second physical page, and the coding status table is referred to Figure 12 is the same, and after the LV4 programming verification passes, the page latch DC is released so that the released page latch caches the programming data of the low page LP of the second physical page, and the coding status table is referred to Figure 13 .

[0136] Step S302: Store the second non-physical page information in the bias latch in the page buffer. Here, the second non-physical page information includes the voltage bias information of the corresponding bit line.

[0137] Step S303: During the programming of the first physical page, disable the bit line bias function to release the bias latch to replace one of the N page latches for programming verification of the memory state, and release one of the N page latches; before the second programming of the second physical page subsequent to the first programming in the cache programming mode and during the first programming of the first physical page, store the programming data of one of the N logical pages of the second physical page in the released page latch.

[0138] In the above step S303, the first programming / second programming of the first physical page / second physical page includes: performing a programming operation on the 1st to 2nd (N-M) memory states using the incremental step pulse programming (ISPP) method.

[0139] In the above step S303, the disabling of the bit line bias function includes: disabling the bit line bias function after programming verification of the third-to-last memory state among the two N memory states. Specifically, please refer to Figure 26 , after programming verification of the third-to-last memory state LV5 among the eight memory states, disable the bit line bias function. Figure 26The following is the encoding status table after disabling the bit line biasing function provided by the embodiments of the present application. It can be seen that after disabling the bit line biasing function, the bias latch DL is idle and can be used to replace a page latch for memory state identification. Then, the page latch D1 can be released to cache the programming data of the lower page LP of the second physical page, and further the page latch DC can be released to cache the programming data of the middle page MP of the second physical page.

[0140] In the embodiments of the present application, after disabling the bit line biasing function, the step increment of the programming voltage is reduced. Since the bit line biasing function itself is to narrow the width of the threshold voltage distribution of the memory cells, after disabling the bit line biasing function, compensation can be made by reducing the step increment of the programming voltage. In this way, not only can the bias latch be used to replace a page latch, but also the function of the non-volatile storage device is not affected. In the embodiments of the present application, after programming and verifying the second-to-last memory state among the 2 N memory states, N page latches are released so that the N page latches cache the programming data of each of the N logical pages of the second physical page. In a specific embodiment, after programming and verifying the second-to-last memory state among 8 memory states (i.e., the 7th memory state (LV6) has been verified), 3 page latches are released so that the 3 page latches cache the programming data of each of the 3 logical pages (next LP, next MP, next UP) of the second physical page. The encoding status table is as Figure 27 shown. When the programming verification of LV6 passes, there is still 1 memory state LV7 that has not passed the programming verification. Since one bit of each logical page has two possible states, 0 and 1, 1 latch has 2 possible states (2 1= 2), that is to say, after the programming verification of LV6 is passed, only 1 bias latch DL is needed to determine whether the programming verification of LV7 is passed. Therefore, after the programming verification of LV6 is passed, the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page, and then the page latch DC can be further released to cache the programming data of the upper page UP of the second physical page. At this time, 3 page latches are released to store the programming data of each of the three logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, and the page latch DC caches the programming data of the upper page UP of the second physical page. And then whether DL is 1 can be used to determine whether the programming verification of LV7 is passed. If DL is 1, it means that the programming verification of LV7 is passed, indicating that the segments corresponding to LV0 to LV7 are all written into the selected storage unit, and the first programming is completed. At this time, the programming data of the 3 logical pages to be written in the second programming has been cached in the page latches and can directly enter the second programming process. If DL is 0, the verification fails and the programming verification judgment continues. Since after the programming verification of LV6, 3 page latches can cache the programming data of each of the 3 logical pages (next LP, next MP, and next UP) of the second physical page, the second physical page can become ready during the first programming operation. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without a data loading window.

[0141] Another non-volatile storage device is also provided in an embodiment of the present application. After the peripheral circuit included in the non-volatile storage device stores the programming data of 4 logical pages in 4 page latches, the programming data of the logical pages stored in the page latches is encoded and converted according to a preset to obtain as Figure 21 the encoded status table shown.

[0142] In an embodiment of the present application, before the programming verification of LV8 among 16 memory states, DC can store the programming data of one (current XP) of the 4 logical pages of the first physical page, and D1 can store the programming data of the corresponding logical page (current LP) of the first physical page, D2 can store the programming data of the corresponding logical page (current MP) of the first physical page, and D3 can store the programming data of the corresponding logical page (current UP) of the first physical page. After the programming verification of LV8 is passed, the page latch DC is released so that the released page latch caches the programming data of the lower page LP of the second physical page, and the encoded status table is as Figure 22 shown. After the programming verification of LV12 is passed, the page latch D1 is released to cache the programming data of the lower page LP of the second physical page, and then the page latch DC is further released to cache the programming data of the middle page MP of the second physical page, and the encoded status table is asFigure 23 as shown

[0143] In the embodiment of the present application, the peripheral circuit is further configured to: after programming verification is performed in the third - last memory state among the 2 N memory states, disable the bit - line biasing function. In a specific embodiment, after programming verification is performed on the third - last memory state LV13 among 16 memory states, the bit - line biasing function is disabled to release the bias latch DL to replace one of the four page data latches for programming verification of the memory state, and to release one of the four page latches to cache the programming data of one logical page among the four logical pages of the second physical page; and, during the process of programming the first physical page, the programming data of one logical page among the four logical pages of the second physical page is stored in the released one page latch. Figure 29 The coding state table after disabling the bit - line biasing function provided by the embodiment of the present application is shown. It can be seen that after the bit - line biasing function is disabled, the bias latch DL is idle and can be used to replace one of the four page latches for programming verification of the memory state. Then, the page latch D2 can be released to cache the programming data of the middle page MP of the second physical page, and further the page latch DC can be released to cache the programming data of the upper page UP of the second physical page.

[0144] In the embodiment of the present application, the peripheral circuit is further configured to: after disabling the bit - line biasing function, reduce the step increment of the programming voltage. Since the bit - line biasing function itself is to narrow the width of the threshold voltage distribution of the memory cell, after disabling the bit - line biasing function, compensation can be made by reducing the step increment of the programming voltage. In this way, not only can the bias latch be used to replace one of the data latches, but also the function of the non - volatile storage device is not affected.

[0145] In the embodiment of the present application, after programming verification is performed on the second - last memory state among the 2 N memory states, N of the page latches are released so that the N page latches cache the programming data of each of the N logical pages of the second physical page. In a specific embodiment, after programming verification is performed on the second - last memory state among 16 memory states (i.e., after verifying the 15th memory state (LV14)), 4 of the page latches are released so that the 4 page latches cache the programming data of each of the four logical pages (next LP, next MP, next UP, next XP) of the second physical page. The coding state table is as Figure 30As shown, when the programming verification of LV14 is passed, there is still 1 memory state LV15 that has not passed the programming verification. Since each bit of each logical page has two possible states, 0 and 1, 1 latch has 2 possible states (2 1 = 2). In other words, after the programming verification of LV6 is passed, only 1 bias latch DL is needed to determine whether the programming verification of LV7 is passed. Therefore, after the programming verification of LV14 is passed, the page latch D3 can be released to cache the programming data of the upper page UP of the second physical page, and then the page latch DC can be further released to cache the programming data of the extra page XP of the second physical page. At this time, 4 page latches are released to store all the programming data of each of the four logical pages of the second physical page. At this time, the page latch D1 caches the programming data of the lower page LP of the second physical page, the page latch D2 caches the programming data of the middle page MP of the second physical page, the page latch D3 caches the programming data of the upper page UP of the second physical page, and the page latch DC caches the programming data of the extra page XP of the second physical page. And then it can be determined whether the programming verification of LV15 is passed by whether DL is 1. If DL is 1, it means that the programming verification of LV15 is passed, indicating that the segments corresponding to LV0 to LV15 are all written into the selected storage unit, and the first programming ends. At this time, the programming data of the 4 logical pages to be written in the second programming has been cached in 4 page latches and can directly enter the second programming process. If DL is 0, the verification fails and the programming verification judgment continues.

[0146] The solution provided by the embodiment of the present application makes the programming data of various types of logical pages required in the second programming be temporarily stored in the page latch during the first programming process, that is, during the first programming operation, the second physical page can be made ready. Therefore, at the end of the first programming operation, the second programming operation based on the second physical page can be seamlessly triggered without a data loading window.

[0147] The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present application, and all should be covered by the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A non-volatile storage device, characterized in that, comprising: a storage cell array, wherein the storage cells in the storage cell array are arranged in rows and columns, and each storage cell is configured to store N bits of data, where N is an integer greater than 1; a peripheral circuit, the peripheral circuit being coupled to the storage cell array, the peripheral circuit being configured to perform successive first programming and second programming on the storage cell array in a cache programming manner for a first physical page and a second physical page, respectively, and to program a selected storage cell row based on N logical pages of the first physical page / second physical page during the first programming / second programming; the peripheral circuit includes a plurality of page buffers respectively coupled to bit lines, and each page buffer includes: a main latch, (N - 1) data latches, and a cache latch coupled to a data path; wherein, the main latch is configured to be able to store first non-physical page information; the (N - 1) data latches and the one cache latch are used to temporarily store programming data to be written to N logical pages as N page latches during the process of performing the programming on N logical pages of the first physical page / second physical page; The peripheral circuit is further configured to: during the programming of the first physical page, when the programming operations of the first to second (N-M) memory states are completed, perform a programming verification operation on the programming operation of the corresponding second (N-M) memory state. When the programming verification of the second (N-M) memory state passes, make the identifiers of the corresponding first to second (N -M) memory states stored in the main latch different from the identifiers of the corresponding second (N-M) +1 to second N memory states, and release at least one of the N page latches to cache the programming data of at least one logical page of the N logical pages of the second physical page; and during the programming of the first physical page, store the programming data of one logical page among the N logical pages of the second physical page in the released one page latch, where M is an integer greater than or equal to 1 and less than or equal to (N - 2).

2. The non-volatile storage device according to claim 1, characterized in that, The peripheral circuit is further configured to use an incremental step pulse programming (ISPP) method to perform a programming operation on the 1st to 2nd (N-M) memory states during the programming of the first physical page / second physical page.

3. The non-volatile storage device according to claim 1, characterized in that, the first non-physical page information includes verification information and programming information.

4. The non-volatile storage device according to claim 1, characterized in that, The peripheral circuit is specifically configured to: after programming and verifying the second N memory state among two N-1 memory states, make the identifiers of the first to second (N-1) memory states stored in the master latch different from the identifiers of the second (N -1) +1 to second N memory states; or After programming verification is performed on the third-to-last memory state among the two N memory states, the identifiers of the first to second N -2 memory states stored in the master latch are made different from the identifiers of the second N -1 to second N memory states.

5. The non-volatile storage device according to claim 4, characterized in that, The peripheral circuit is further configured to: after making the identifiers of the corresponding first to second (N-M) memory states stored in the master latch different from the identifiers of the corresponding second (N-M) +1 to second N memory states, float the bit lines during programming to dump the first non-physical page information in the master latch.

6. The non-volatile storage device according to claim 4, characterized in that, The peripheral circuit is further configured to: before programming verification of the second memory state among the two memory states, store programming data of a corresponding one of the N logical pages in at least one of the N page latches; and N before programming verification of the second memory state among the two memory states, store programming data of a corresponding one of the N logical pages in at least one of the N page latches; and N-1 before programming verification of the second memory state among the two memory states, store programming data of a corresponding one of the N logical pages in at least one of the N page latches; and After programming verification of the second memory state among the two memory states, store the programming data of one logical page among the N logical pages of the second physical page in at least one of the N page latches. N After programming verification of the second memory state among the two memory states, store the programming data of one logical page among the N logical pages of the second physical page in at least one of the N page latches. N-1 After programming verification of the second memory state among the two memory states, store the programming data of one logical page among the N logical pages of the second physical page in at least one of the N page latches.

7. The non-volatile storage device according to claim 6, characterized in that, The peripheral circuit is further configured to: after programming verification of the second-to-last memory state among the two memory states, release N of the page latches to enable the N page latches to cache the programming data of each of the N logical pages of the second physical page. N After programming verification of the second-to-last memory state among the two memory states, release N of the page latches to enable the N page latches to cache the programming data of each of the N logical pages of the second physical page.

8. The non-volatile storage device according to claim 1, characterized in that, each storage cell is configured to store 3 bits of data, and the peripheral circuit is further configured to program a selected storage cell row based on 3 logical pages of the first physical page / second physical page; 2 of the data latches and the one cache latch are used to temporarily store programming data to be written to 3 logical pages as 3 page latches during the process of performing the programming on 3 logical pages of the first physical page / second physical page.

9. The non-volatile storage device according to claim 1, characterized in that, each storage cell is configured to store 4 bits of data, and the peripheral circuit is further configured to program a selected storage cell row based on 4 logical pages of the first physical page / second physical page; 3 of the data latches and the one cache latch are used to temporarily store programming data to be written to 4 logical pages as 4 page latches during the process of performing the programming on 4 logical pages of the first physical page / second physical page.

10. The non-volatile storage device according to claim 1, characterized in that, each page buffer further includes: a bias latch, the bias latch being configured to store voltage bias information of a corresponding bit line.

11. The non-volatile storage device according to claim 1, characterized in that, The non-volatile storage device includes a three-dimensional NAND flash memory device.

12. A non-volatile storage device, characterized in that, it includes: a memory cell array, the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is configured to store N-bit data, where N is an integer greater than 1; a peripheral circuit, which is configured to perform successive first programming and second programming on the memory cell array for the first physical page and the second physical page in a cache programming manner, and program the selected memory cell rows based on N logical pages of the first physical page / second physical page during the first programming / second programming; the peripheral circuit includes a plurality of page buffers respectively coupled to bit lines, and each page buffer includes: a main latch, a bias latch, (N-1) data latches, and a cache latch coupled to a data path, wherein the bias latch is configured to be able to store second non-physical page information; the (N-1) data latches and the one cache latch are used to temporarily store the programming data to be written to the N logical pages as N page latches during the process of performing the programming on the N logical pages of the first physical page / second physical page once; the peripheral circuit is further configured to: during the process of programming the first physical page, disable the bit line bias function to release the bias latch to replace one of the N page latches for programming verification of the memory state, and release one of the N page latches to cache the programming data of one logical page of the N logical pages of the second physical page; and, during the process of programming the first physical page, store the programming data of one logical page of the N logical pages of the second physical page in the released page latch.

13. The non-volatile storage device according to claim 12, characterized in that, The peripheral circuit is further configured to use an Incremental Step Pulse Programming (ISPP) method to perform programming operations on the 1st to 2nd (N-M) memory states during the programming of the first physical page / second physical page.

14. The non-volatile storage device according to claim 12, characterized in that, the peripheral circuit is further configured to: after disabling the bit line bias function, reduce the step increment of the programming voltage.

15. The non-volatile storage device according to claim 12, characterized in that, the second non-physical page information includes voltage bias information of the corresponding bit line.

16. The non-volatile storage device according to claim 12, characterized in that, The peripheral circuit is further configured to: after programming and verifying the third-to-last memory state among 2 N memory states, disable the bit line biasing function.

17. The non-volatile storage device according to claim 16, characterized in that, The peripheral circuit is further configured to: before programming verification of the (2 N +1)-th memory state among the 2 N-1 memory states, store programming data of a corresponding one of the N logical pages in at least one of the N page latches; and In the 2 N The memory state (2 N-1 After performing program verification on the first and second memory states of the second physical page, one logical page of the N logical pages of the second physical page is stored in at least one of the N page latches.

18. The non-volatile storage device according to claim 17, characterized in that, The peripheral circuit is further configured to: after programming verification of the second-to-last memory state among the two memory states, release N of the page latches to enable the N page latches to cache the programming data of each of the N logical pages of the second physical page. N After programming verification of the second-to-last memory state among the two memory states, release N of the page latches to enable the N page latches to cache the programming data of each of the N logical pages of the second physical page.

19. The non-volatile storage device according to claim 12, characterized in that, each memory cell is configured to store 3-bit data, and the peripheral circuit is further configured to program the selected memory cell rows based on 3 logical pages of the first physical page / second physical page; 2 of the data latches and the one cache latch are used to temporarily store the programming data to be written to the 3 logical pages as 3 page latches during the process of performing the programming on the 3 logical pages of the first physical page / second physical page once.

20. The non-volatile storage device according to claim 12, characterized in that, Each memory cell is configured to store 4-bit data, and the peripheral circuit is further configured to program a selected row of memory cells based on 4 logical pages of a first physical page / a second physical page; 3 of the data latches and the one cache latch are used to temporarily store programming data to be written to 4 logical pages as 4 page latches during one process of programming the 4 logical pages of the first physical page / a second physical page.

21. The non-volatile storage device according to claim 12, wherein, the master latch is configured to store verification information and programming information.

22. The non-volatile storage device according to claim 12, wherein, the non-volatile storage device includes a 3D NAND flash memory device.

23. A programming method for a non-volatile storage device, wherein, the non-volatile storage device includes a memory cell array and a peripheral circuit; the memory cells in the memory cell array are arranged in rows and columns, each memory cell is configured to store N-bit data, N is an integer greater than 1; the peripheral circuit includes a plurality of page buffers respectively coupled to bit lines; characterized in that the method includes: Storing N logical pages of a first physical page corresponding to a current first programming in N page latches, the N page latches including (N - 1) data latches in the page buffer and one cache latch coupled to a data path; Storing first non-physical page information in a master latch in the page buffer; During the first programming of the first physical page, when the programming operations of the 1st to 2nd (N-M) memory states are completed, a programming verification operation is performed on the programming operation corresponding to the 2nd (N-M) memory state. When the programming verification of the 2nd (N-M) memory state passes, the identifiers of the 1st to 2nd (N-M) memory states stored in the master latch are made different from the identifiers of the 2nd (N-M) +1 to 2nd N memory states, and at least one of the N page latches is released to cache the programming data of at least one logical page of the N logical pages of the second physical page, where M is an integer greater than or equal to 1 and less than or equal to (N - 2); and Before a second programming of a second physical page subsequent to the first programming and during a process of performing the first programming on the first physical page, storing programming data of one logical page among N logical pages of the second physical page in a released one of the page latches.

24. The method according to claim 23, wherein, Performing the first programming on the first physical page / the second programming on the second physical page includes: Program the 1st to 2nd (N-M) memory states using the Incremental Step Pulse Programming (ISPP) programming method.

25. The method according to claim 23, wherein, the first non-physical page information includes verification information and programming information.

26. The method according to claim 23, wherein, When the programming verification of the second (N-M) memory state passes, the identifiers of the first to second (N-M) memory states stored in the master latch are made different from the identifiers of the second (N-M) +1 to second N memory states, including: After programming verification of the second of the two memory states, such that the identifiers of the first to second memory states stored in the master latch are different from the identifiers of the second + 1 to second memory states; or N the second of the two N-1 memory states, such that the identifiers of the first to second (N-1) memory states stored in the master latch are different from the identifiers of the second (N-1) + 1 to second N memory states; or After programming verification is performed on the third-to-last memory state among the two memory states, the identifiers of the first to second N -2 memory states stored in the master latch are made different from the identifiers of the second N -1 to second N memory states. N ​ 27. The method according to claim 26, wherein, After making the identifiers of the corresponding first to second (N-M) memory states stored in the master latch different from the identifiers of the corresponding second (N-M) +1 to second N memory states, the method further includes: During programming, floating the bit lines to dump the first non-physical page information in the master latch.

28. The method according to claim 26, wherein, The method further includes: Before programming verification of the second of the two memory states, store the programming data of a corresponding one of the N logical pages of the first physical page in at least one of the N page latches; and after programming verification of the second of the two memory states, store the programming data of one of the N logical pages of the second physical page in at least one of the N page latches. N second of the two N-1 Before programming verification of the second of the two memory states, store the programming data of a corresponding one of the N logical pages of the first physical page in at least one of the N page latches; and after programming verification of the second of the two memory states, store the programming data of one of the N logical pages of the second physical page in at least one of the N page latches. N second of the two N-1 Before programming verification of the second of the two memory states, store the programming data of a corresponding one of the N logical pages of the first physical page in at least one of the N page latches; and after programming verification of the second of the two memory states, store the programming data of one of the N logical pages of the second physical page in at least one of the N page latches.

29. The method according to claim 28, wherein, The method further includes: After programming verification is performed on the second-to-last memory state among the two memory states, N of the page latches are released so that N of the page latches cache the programming data of each of N logical pages of a second physical page. N After programming verification is performed on the second-to-last memory state among the two memory states, N of the page latches are released so that N of the page latches cache the programming data of each of N logical pages of a second physical page.

30. A programming method for a non-volatile storage device, wherein, the non-volatile storage device includes a memory cell array and a peripheral circuit; the memory cells in the memory cell array are arranged in rows and columns, each memory cell is configured to store N-bit data, N is an integer greater than 1; the peripheral circuit includes a plurality of page buffers respectively coupled to bit lines; characterized in that the method includes: Store N logical pages of a first physical page corresponding to a current first programming in N page latches, where the N page latches include (N - 1) data latches in the page buffer and one cache latch coupled to a data path; Store second non - physical page information in a bias latch in the page buffer; During the process of programming the first physical page, disable the bit - line biasing function to release the bias latch to replace one of the N page latches for programming verification of the memory state, and release one of the N page latches; Before a second programming of a second physical page subsequent to the first programming in a cache programming mode and during the process of the first programming of the first physical page, store programming data of one logical page among the N logical pages of the second physical page in the released page latch.

31. The method according to claim 30, wherein, Performing the first programming on the first physical page / the second programming on the second physical page includes: Program the 1st to 2nd (N-M) memory states using the Incremental Step Pulse Programming (ISPP) programming method.

32. The method according to claim 30, wherein, The method further includes: After disabling the bit - line biasing function, reduce the step increment of the programming voltage.

33. The method according to claim 30, wherein, The second non - physical page information includes voltage biasing information of corresponding bit lines.

34. The method according to claim 30, wherein, Disabling the bit - line biasing function includes: After programming verification of the third-to-last memory state among two memory states, the bit line bias function is disabled. N After programming verification of the third-to-last memory state among two memory states, the bit line bias function is disabled.

35. The method according to claim 34, wherein, The method further includes: In the 2 N The memory state (2 N-1 +1) memory states before performing program verification, storing programming data of a corresponding one of the N logical pages of the first physical page in at least one of the N page latches; and In the 2 N The memory state (2 N-1 After performing program verification on the first and second memory states of the second physical page, program data of one logical page of the N logical pages of the second physical page is stored in at least one of the N page latches.

36. The method according to claim 35, wherein, The method further includes: After programming verification of the second-to-last memory state among the two memory states, release N of the page latches so that the N page latches cache the programming data of each of the N logical pages of the second physical page. N After programming verification of the second-to-last memory state among the two memory states, release N of the page latches so that the N page latches cache the programming data of each of the N logical pages of the second physical page.

37. A memory system, comprising: At least one non - volatile storage device according to any one of claims 1 to 11 or at least one non - volatile storage device according to any one of claims 12 to 22; and A controller coupled to the non - volatile storage device and configured to control the non - volatile storage device.

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