Fan-out packaged devices

Abstract

The present application discloses a fan-out packaging device, comprising: a first chip; a plurality of blocking members disposed around the periphery of the first chip; a plurality of conductive pillars disposed around the periphery of the plurality of blocking members; wherein the height of the conductive pillars is greater than the height of the blocking members; and a plastic encapsulation layer covering at least the periphery of the side surfaces of the first chip, the blocking members, and the conductive pillars, with the first chip, the blocking members, and the conductive pillars forming an integral structure through the plastic encapsulation layer. By using the above-described device, the present application can reduce the probability of chip warping in a fan-out packaging device.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a fan-out packaging device. Background Art

[0002] In traditional fan-out packaging methods, after the chip is plastic-sealed, the plastic sealing material in the packaging structure shrinks and deforms, which easily causes the chip to shift within the packaging structure, reducing the chip's service life. Summary of the Invention

[0003] The main technical problem solved by the present application is to provide a fan-out packaging device that can reduce the probability of chip warping in the fan-out packaging device.

[0004] In order to solve the above technical problems, a technical solution adopted in this application is: to provide a fan-out packaging device, including: a first chip; a plurality of blocking members, arranged around the periphery of the first chip; a plurality of conductive columns, arranged around the periphery of the plurality of blocking members; wherein the height of the conductive columns is greater than the height of the blocking members; a plastic encapsulation layer, covering at least the side periphery of the first chip, the blocking members and the conductive columns, and the first chip, the blocking members and the conductive columns form an integral structure through the plastic encapsulation layer.

[0005] Wherein, the blocking member has conductive properties, and the blocking member and the conductive column are formed of the same material.

[0006] Wherein, a plurality of blocking members are connected to each other to form an annular structure.

[0007] The fan-out packaging device further includes: insulating glue, which at least covers at least a portion of the side surface of the blocking member, and the plastic encapsulation layer covers the insulating glue.

[0008] Among them, the first chip includes a first functional surface and a first non-functional surface arranged in back to back, the conductive column, the blocking member and the plastic encapsulation layer are arranged flush with the first non-functional surface, and the first functional surface is located in the plastic encapsulation layer; the fan-out packaging device also includes: at least one second chip, including a second functional surface and a second non-functional surface arranged in back to back; the second functional surface faces the first functional surface, the second functional surface spans at least part of the first functional surface, and at least part of the blocking member adjacent to at least part of the first functional surface, and the pads on the second functional surface are electrically connected to the pads on the first functional surface at corresponding positions and the blocking member; bottom filling glue at least covers the gap between the second functional surface of the second chip and the carrier board and the blocking member.

[0009] Wherein, the side of the plastic packaging layer facing away from the first functional surface is flush with the second non-functional surface and the conductive pillar.

[0010] The first chip includes a first functional surface and a first non-functional surface disposed opposite to each other, the conductive pillar, the blocking member and the plastic packaging layer are disposed flush with the first functional surface, and the first non-functional surface is located within the plastic packaging layer.

[0011] In which, the fan-out device also includes: a first redistribution layer, located on the surface of the plastic encapsulation layer adjacent to the first functional surface; wherein, the first redistribution layer is electrically connected to at least the first chip and one end of the conductive column; a second redistribution layer, located on the surface of the plastic encapsulation layer adjacent to the first non-functional surface; wherein, the second redistribution layer is electrically connected to the other end of the conductive column.

[0012] Among them, the fan-out packaging device also includes: a first electrical connector, located on the side of the first redistribution layer away from the plastic packaging layer, and electrically connected to the first redistribution layer; a second electrical connector, located on the side of the second redistribution layer away from the plastic packaging layer, and electrically connected to the second redistribution layer.

[0013] The height of the plastic encapsulation layer is the same as the height of the conductive column, and both ends of the conductive column in the length direction are exposed from the plastic encapsulation layer.

[0014] The beneficial effects of this application are as follows: Unlike the prior art, the fan-out package device proposed in this application has multiple blocking members disposed around the periphery of the first chip. These blocking members help limit the movement of the plastic encapsulation material in the plastic encapsulation layer, thereby reducing the deformation of the plastic encapsulation material due to shrinkage and the probability of chip warping. In addition, the conductive pillars can achieve a three-dimensional vertical interconnect structure, which helps to reduce the height of the fan-out package device. The design of blocking members and conductive pillars of different heights can also effectively save material costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0016] Figure 1 This is a schematic structural diagram of an embodiment of a fan-out packaging device of the present application;

[0017] Figure 2 This is a schematic structural diagram of another embodiment of the fan-out packaging device of the present application;

[0018] Figure 3 This is a flow chart of an embodiment of a method for preparing a fan-out packaging device of the present application;

[0019] Figure 4 yes Figure 3 Steps S101-S105 correspond to a schematic structural diagram of an embodiment;

[0020] Figure 5 is a flow chart corresponding to an embodiment after step S105;

[0021] Figure 6 yes Figure 5 Steps S201-S202 correspond to a structural diagram of an embodiment. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0023] See also Figure 1 , Figure 1 It is a structural diagram of an embodiment of the fan-out packaging device proposed in this application. The fan-out packaging device provided in this application includes: a first chip 100, multiple blocking members 20, multiple conductive columns 30 and a plastic encapsulation layer 50.

[0024] Specifically, the first chip 100 includes a first functional surface 101 and a first non-functional surface 102 disposed opposite to each other, and a plurality of first pads 103 are disposed on the first functional surface 101. In this embodiment, there may be multiple first chips 100, and the chip types may be the same or different.

[0025] A plurality of blocking members 20 are arranged around the periphery of the first chip 100. Figure 1 As shown in , multiple blocking members 20 can be arranged at intervals. Of course, in other embodiments, multiple blocking members 20 can also be connected to each other to form an annular structure. That is, in this case, multiple blocking members 20 are equivalent to forming a circular ring or other annular structure arranged around the side periphery of the first chip 100. The blocking member 20 helps to limit the movement of the molding compound in the molding layer 50 to reduce the deformation of the molding compound due to shrinkage and reduce the probability of chip warping. In addition, the blocking member 20 is conductive, and its material can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. This design method allows the blocking member 20 to be prepared and formed simultaneously with the conductive column 30 to reduce the difficulty of process preparation.

[0026] Multiple conductive pillars 30 are arranged around the periphery of the multiple blocking members 20, and the height of the conductive pillars 30 is greater than that of the blocking members 20. The conductive pillars 30 can realize a three-dimensional vertical interconnection structure, which is conducive to reducing the height of the fan-out packaging device. The design of blocking members 20 and conductive pillars 30 of different heights can also effectively save material costs. Optionally, the material of the conductive pillars 30 can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. When the blocking member 20 is conductive, the conductive pillars 30 and the blocking member 20 can be formed of the same material.

[0027] The plastic encapsulation layer 50 covers at least the outer side surfaces of the first chip 100, the barrier 20, and the conductive pillars 30. The first chip 100, the barrier 20, and the conductive pillars 30 form a monolithic structure through the plastic encapsulation layer 50. The conductive pillars 30, the barrier 20, and the plastic encapsulation layer 50 are flush with the first non-functional surface 102, and the first functional surface 101 is located within the plastic encapsulation layer 50. The height of the plastic encapsulation layer 50 is the same as that of the conductive pillars 30, and both ends of the conductive pillars 30 in the longitudinal direction are exposed from the plastic encapsulation layer 50. The plastic encapsulation layer 50 can be made of epoxy resin, for example, and the plastic encapsulation layer 50 can provide a certain degree of secure protection for the components within the package structure.

[0028] In the fan-out package device provided herein, a plurality of blocking members 20 are disposed around the periphery of the first chip 100. These blocking members 20 help limit the movement of the molding compound in the molding layer 50, thereby reducing the deformation of the molding compound due to shrinkage and the probability of warping of the first chip 100. Furthermore, the conductive pillars 30 can achieve a three-dimensional vertical interconnect structure, which helps reduce the height of the fan-out package device. The design of blocking members 20 and conductive pillars 30 of different heights can also effectively save material costs.

[0029] In one embodiment, see Figure 1 The fan-out package device provided herein further includes insulating adhesive 40, which covers at least a portion of the side surfaces of the barrier 20. The plastic encapsulation layer 50 covers the insulating adhesive 40. The insulating adhesive 40 can provide a certain position limiting and protective function for the barrier 20. Optionally, the insulating adhesive 40 can be applied by dispensing, and the outer surface of the insulating adhesive 40 can be a curved surface.

[0030] In another embodiment, please refer to Figure 1The fan-out device provided in the present application further includes at least one second chip 200, including a second functional surface 201 and a second non-functional surface 202 disposed opposite to each other, and a plurality of second pads 203 are disposed on the second functional surface 201. The second functional surface 201 faces the first functional surface 101, and the second functional surface 201 spans at least a portion of the first functional surface 101 and at least a portion of the blocking member 20 adjacent to at least a portion of the first functional surface 101. The second pads 203 on the second functional surface 201 are electrically connected to the first pads 103 on the first functional surface 101 at corresponding positions and the blocking member 20 at corresponding positions. The electrical connection between the second pads 203 and the first pads 103 can be facilitated by providing conductive bumps between the second pads 203 and the first pads 103 at corresponding positions. The plastic encapsulation layer 50 can fix and protect the second chip 200; the side of the plastic encapsulation layer 50 facing away from the first functional surface 101 is flush with the second non-functional surface 202 and one end of the conductive column 30, which helps to reduce the thickness of the fan-out packaged device and improve the heat dissipation effect. In this embodiment, the number of second chips 200 can be 1, 2, 3, etc., and the second chip 200 and the first chip 100 can exchange information, thereby improving the functionality of the fan-out device. In addition, an underfill 55 is provided at least between the second functional surface 201 of the second chip 200 and the carrier 10, and the barrier 20 is located in the underfill 55 to fix and protect the first chip 100, the second chip 200 and the barrier 20. Specifically, in this application mode, the vertical cross-section of the underfill 55 is trapezoidal, which can improve the stability of the fan-out device; in other application modes, the vertical cross-section of the underfill 55 can also be rectangular, etc. Optionally, the side of the underfill 55 facing away from the first non-functional surface 102 can be flush with the second functional surface 201 of the second chip 200, or can be higher than the second functional surface 201 of the second chip 200, which is not limited in this application. In addition, in other embodiments, the underfill 55 can also be omitted.

[0031] In another embodiment, please refer to Figure 1 , the fan-out device provided in this application also includes:

[0032] The first redistribution layer 60 is located on the surface of the plastic encapsulation layer 50 adjacent to the first non-functional surface 102. The first redistribution layer 60 is electrically connected to at least the first chip 100 and one end of the conductive pillar 30. The first redistribution layer 60 includes a dielectric layer and a patterned metal layer, and can have one or more layers. The first redistribution layer 60 can be electrically connected to the first chip 100 and the second chip 200, thereby facilitating electrical connection of other devices to the first chip 100 and the second chip 200 through the first redistribution layer 60.

[0033] The second redistribution layer 70 is located on the surface of the plastic encapsulation layer 50 adjacent to the first functional surface 101. The second redistribution layer 70 is electrically connected to the other end of the conductive pillar 30. The second redistribution layer 70 also includes a dielectric layer and a patterned metal layer, and the number of layers of the second redistribution layer 70 can be one or more. Based on the connection between the first redistribution layer 60 and the second redistribution layer 70 via the conductive pillar 30, the second redistribution layer 70 is also electrically connected to the first chip 100 and the second chip 200, so that both opposite sides of the fan-out device can achieve electrical connection with the first chip 100 and the second chip 200.

[0034] In another embodiment, please refer to Figure 1 , the fan-out packaging device provided in this application also includes:

[0035] The first electrical connector 80 is located on the side of the first redistribution layer 60 facing away from the plastic encapsulation layer 50 and is electrically connected to the first redistribution layer 60. The second electrical connector 90 is located on the side of the second redistribution layer 70 facing away from the plastic encapsulation layer 50 and is electrically connected to the second redistribution layer 70. A plurality of solder balls 85 are provided between the first electrical connector 80 and the first redistribution layer 60, and between the second electrical connector and the second redistribution layer 70. The first electrical connector 80 and the second electrical connector 90 can be made of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, or the like. The first electrical connector 80 and the second electrical connector 90 facilitate connection between the fan-out device and a substrate or other devices.

[0036] In the above embodiment, Figure 1 The first functional surface 101 of the first chip 100 is located in the plastic encapsulation layer 50, and the first non-functional surface 102 of the first chip 100 is flush with one side surface of the plastic encapsulation layer 50. Of course, in other embodiments, the first non-functional surface 102 of the first chip 100 can also be located in the plastic encapsulation layer 50, and the first functional surface 101 of the first chip 100 is flush with one side surface of the plastic encapsulation layer 50. For details, please refer to Figure 2 , Figure 2 This is a schematic diagram of another embodiment of the fan-out package device of the present application. The fan-out package device provided in the present application includes:

[0037] The first chip 100 includes a first functional surface 101 and a first non-functional surface 102 disposed opposite to each other. A plurality of first pads 103 are disposed on the first functional surface 101. In this embodiment, there may be multiple first chips 100, and the chip types may be the same or different.

[0038] A plurality of blocking members 20 are arranged around the periphery of the first chip 100, and the plurality of blocking members 20 can be arranged at intervals. Of course, in other embodiments, the plurality of blocking members 20 can also be connected to each other to form an annular structure, that is, in this case, the plurality of blocking members 20 are equivalent to forming a circular ring or other annular structure arranged around the side periphery of the first chip 100. The blocking member 20 helps to limit the movement of the molding compound in the molding layer 50 to reduce the deformation of the molding compound due to shrinkage and reduce the probability of core warping. One end of the blocking member 20 is flush with one side of the first functional surface 101 of the first chip 100. The blocking member 20 is conductive, and its material can be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper.

[0039] A plurality of conductive pillars 30 are disposed around the plurality of blocking members 20. The height of the conductive pillars 30 is greater than that of the blocking members 20. Optionally, the conductive pillars 30 may be made of one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. When the conductive pillars 30 are conductive, the conductive pillars 30 and the blocking members 20 may be formed of the same material.

[0040] The plastic encapsulation layer 50 covers at least the outer side surfaces of the first chip 100, the barrier 20, and the conductive pillars 30. The first chip 100, the barrier 20, and the conductive pillars 30 form an integrated structure through the plastic encapsulation layer 50. The plastic encapsulation layer 50 can be made of epoxy resin, etc., and the formation of the plastic encapsulation layer 50 can provide a certain degree of fixation and protection for the components within the package structure. In this case, the first non-functional surface 102 of the first chip 100 can also be located within the plastic encapsulation layer 50, and the first functional surface 101 of the first chip 100 is flush with a side surface of the plastic encapsulation layer 50.

[0041] In one embodiment, see Figure 2 The fan-out package device proposed in this application further includes insulating adhesive 40, which covers at least a portion of the side surfaces of the barrier 20. The plastic encapsulation layer 50 covers the insulating adhesive 40. The insulating adhesive 40 can provide a certain degree of position limiting and protection for the barrier 20. Optionally, the insulating adhesive 40 can be applied by dispensing, and the outer surface of the insulating adhesive can be a curved surface.

[0042] In another embodiment, please refer to Figure 2 , the fan-out device proposed in this application also includes:

[0043] The first redistribution layer 60 is located on the surface of the plastic encapsulation layer 50 adjacent to the first functional surface 101. The first redistribution layer 60 is electrically connected to at least the first chip 100, the barrier 20, and one end of the conductive pillar 30. The first redistribution layer 60 includes a dielectric layer and a patterned metal layer, and can have one or more layers. The provision of the first redistribution layer 60 facilitates electrical connection between the first chip 100 and other devices.

[0044] The second redistribution layer 70 is located on the surface of the plastic encapsulation layer 50 adjacent to the first non-functional surface 102. The second redistribution layer 70 is electrically connected to the other end of the conductive pillar 30. The second redistribution layer 70 also includes a dielectric layer and a patterned metal layer, and can have one or more layers. Since the first redistribution layer 60 and the second redistribution layer 70 are connected via the conductive pillar 30, the second redistribution layer 70 is also electrically connected to the first chip 100.

[0045] In another embodiment, please refer to Figure 2 , the fan-out packaging device proposed in this application also includes:

[0046] The first electrical connector 80 is located on the side of the first redistribution layer 60 facing away from the plastic encapsulation layer 50 and is electrically connected to the first redistribution layer 60. The second electrical connector 90 is located on the side of the second redistribution layer 70 facing away from the plastic encapsulation layer 50 and is electrically connected to the second redistribution layer 70. A plurality of solder balls 85 are provided between the first electrical connector 80 and the first redistribution layer 60, and between the second electrical connector and the second redistribution layer 70. The first electrical connector 80 and the second electrical connector 90 can be made of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, or the like. The first electrical connector 80 and the second electrical connector 90 facilitate connection between the fan-out device and a substrate or other devices.

[0047] The following is a specific application scenario to illustrate the above Figure 1 The specific preparation process of fan-out packaged devices is described in detail. Figure 3 and Figure 4 , Figure 3 This is a flow chart of an embodiment of a method for preparing a fan-out packaging device of the present application. Figure 4 for Figure 3 Steps S101-S105 correspond to a schematic structural diagram of an embodiment, wherein the fan-out packaging method includes:

[0048] S101: Provide a carrier board 10, wherein the carrier board 10 includes a first surface 11 and a second surface 12 disposed opposite to each other.

[0049] Specifically, if Figure 4 As shown in FIG. 1 a , the material of the carrier 10 can be a relatively hard material such as metal, silicon, plastic, etc., and the first surface 11 of the carrier 10 is preferably horizontal.

[0050] S102 : Disposing at least one first chip 100 on one side of the first surface 11 of the carrier 10 .

[0051] Specifically, the first chip 100 includes a first functional surface 101 and a first non-functional surface 102 that are disposed opposite to each other, and a plurality of pads 103 are disposed on the first functional surface 101. Figure 4 As shown in b, Figure 4 b is only indicative. Figure 4 Only one first chip 100 is shown in FIG. b. In this embodiment, 1, 2, 3, etc. first chips 100 may be arranged at intervals on one side of the first surface 11 of the carrier 10.

[0052] S103 : a plurality of blocking members 20 and a plurality of conductive pillars 30 are arranged on a side of the carrier 10 where the first chip 100 is arranged.

[0053] Specifically, if Figure 4 As shown in Figure c, multiple blocking members 20 are disposed around the periphery of the first chip 100; multiple conductive pillars 30 are disposed around the periphery of the multiple blocking members 20. The conductive pillars 30 are taller than the blocking members 20. Furthermore, the blocking members 20 are conductive and are formed of the same material as the conductive pillars 30. The material may be one or more of titanium, tantalum, chromium, tungsten, copper, aluminum, nickel, gold, etc., preferably titanium or copper. The provision of the conductive pillars 30 facilitates the realization of a three-dimensional vertical interconnect structure for fan-out devices, and the provision of the blocking members 20 helps improve the stability of fan-out devices.

[0054] Furthermore, in this embodiment, the fan-out package device further includes insulating adhesive 40, which covers at least a portion of the side surfaces of the barrier 20 to provide a certain degree of fixation and protection for the barrier 20. The insulating adhesive 40 can be formed by dripping adhesive, and due to the surface tension of the adhesive, the surface of the insulating adhesive 40 is curved. Alternatively, the insulating adhesive 40 can be formed around the periphery of multiple barriers 20 by methods such as dispensing adhesive. The insulating adhesive 40 can be cylindrical, conical, or other shapes, which are not limited herein.

[0055] In this embodiment, the plurality of blocking members 20 and the plurality of conductive pillars 30 can be formed by disposing a photoresist layer on the first surface 11 of the carrier 10. Specifically, a first photoresist layer can be formed on the first surface 11, exposed and developed to form a first via hole, and then filled with a conductive metal to form the blocking members 20. Furthermore, a second photoresist layer can be formed on the side of the first photoresist layer facing away from the carrier 10, and a portion of the second photoresist layer and the first photoresist layer can be exposed and developed simultaneously to form a second via hole, and then filled with a conductive metal to form the conductive pillar 30 having a height higher than the blocking members 20. Alternatively, a photoresist layer having a groove can be disposed on the first surface 11 of the carrier 10, and exposed and developed to form a first via hole and a second via hole, wherein the first via hole is located at the bottom of the groove and the second via hole is located on the sidewall of the groove. The first via hole and the second via hole can be simultaneously filled with a conductive metal to form the blocking members 20 and the conductive pillar 30, and the conductive pillar 30 can be taller than the blocking members 20. Alternatively, the blocking member 20 and the conductive pillar 30 may be formed by depositing a first photoresist layer and a second photoresist layer on the first surface 11 of the carrier 10. One of the first photoresist layer and the second photoresist layer may be a positive photoresist and the other a negative photoresist. The specific implementation process is not further described here. Furthermore, after forming the blocking member 20 and the conductive pillar 30 using the photoresist, a portion of the photoresist surrounding the blocking member 20 may be retained to serve as an insulating adhesive 40 to secure and protect the blocking member 20.

[0056] S104 : Dispose at least one second chip 200 on one side of the first functional surface 101 of the first chip 100 , and form an underfill between at least the second functional surface of the second chip and the carrier.

[0057] Specifically, if Figure 4 As shown in d, Figure 4 d is only indicative. Figure 4 Only two second chips 200 are shown in Figure d, but the fan-out package device proposed in this application can also be provided with 1, 2, 3, etc. second chips 200. The second chip 200 includes a second functional surface 201 and a second non-functional surface 202 disposed opposite to each other; the second functional surface 201 faces the first functional surface 101, and the second functional surface 201 spans at least a portion of the first functional surface 101 and at least a portion of the blocking member 20 adjacent to at least a portion of the first functional surface 101. The second pad 203 on the second functional surface 201 is electrically connected to the first pad 103 and the blocking member 20 at a corresponding position on the first functional surface.

[0058] Furthermore, an underfill 55 is formed at least between the second functional surface 201 of the second chip 200 and the carrier 10, and the barrier 20 is located within the underfill 55. Optionally, the side of the underfill 55 facing away from the carrier 10 may be flush with the second functional surface 201 of the second chip 200, or may be higher than the second functional surface 201 of the second chip 200. Furthermore, in other embodiments, the underfill 55 may not be provided, and step S105 may be performed directly after the second chip 200 is disposed.

[0059] S105 : forming a plastic packaging layer 50 on the side of the carrier 10 where the first chip 100 is disposed.

[0060] Specifically, if Figure 4 As shown in FIG. 4 , the fan-out package device proposed in the present application further includes a plastic layer 50, which covers at least the side periphery of the first chip 100, the insulating glue 40, the blocking member 20 and the conductive column 30. The first chip 100, the blocking member 20 and the conductive column 30 form an integral structure through the plastic layer 50. The conductive column 30, the blocking member 20 and the plastic layer 50 are arranged flush with the first non-functional surface 102, and the first functional surface 101 is located within the plastic layer 50. In addition, the side of the plastic layer 50 away from the carrier 10 can be ground so that the side of the plastic layer 50 away from the first functional surface 101 is flush with the second non-functional surface 202 and the conductive column 30. Furthermore, the plastic layer 50 outside the conductive column 30 is cut to obtain a single fan-out package device.

[0061] In another application, before step S105 , the first functional surface 101 of the first chip 100 may be oriented toward the carrier 10 , and then the plastic encapsulation layer 50 is formed on the side of the carrier 10 where the first chip 100 is disposed in step S105 .

[0062] See also Figure 5 and Figure 6 , Figure 5 is a flow chart corresponding to an embodiment after step S105, Figure 6 for Figure 5 Steps S201-S202 correspond to a schematic structural diagram of an embodiment, and after step S105, the following steps are further included:

[0063] S201 : removing the carrier 10 , and providing a first redistribution layer 60 and a second redistribution layer 70 .

[0064] See also Figure 6 a. The first redistribution layer 60 is located on the surface of the plastic encapsulation layer 50 adjacent to the first non-functional surface 102. The first redistribution layer 60 is electrically connected to at least the first chip 100 and one end of the conductive pillar 30. The second redistribution layer 70 is located on the surface of the plastic encapsulation layer 50 adjacent to the first functional surface 101.

[0065] S202 : a first electrical connector 80 is provided on a side of the first redistribution layer 60 away from the plastic packaging layer 50 , and a second electrical connector 90 is provided on a side of the second redistribution layer 70 away from the plastic packaging layer 50 .

[0066] Specifically, see Figure 6 b. The first electrical connector 80 is located on the side of the first redistribution layer 60 facing away from the plastic encapsulation layer 50 and is electrically connected to the first redistribution layer 60. The second electrical connector 90 is located on the side of the second redistribution layer 70 facing away from the plastic encapsulation layer 50 and is electrically connected to the second redistribution layer 70. A plurality of solder balls 85 are disposed between the first redistribution layer 60 and the first electrical connector 80, and between the second redistribution layer 70 and the second electrical connector 90.

[0067] Of course, in another preparation process, before the above step S105, the first functional surface 101 of the first chip 100 can also be placed toward the carrier 10, and the plastic encapsulation layer 50 can be formed on the side of the carrier where the first chip 100 is placed in step S105. Figure 5 The middle step is to set the redistribution layer and the electrical connection body.

[0068] The above description is only an implementation method of the present application and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the description and drawings of this application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A fan-out packaging device, characterized in that: include: First Chip; A plurality of blocking members are arranged around the periphery of the first chip; A plurality of conductive pillars are arranged around the periphery of the plurality of blocking members; wherein the height of the conductive pillars is greater than the height of the blocking members; a plastic encapsulation layer, covering at least the periphery of the side surfaces of the first chip, the blocking member, and the conductive pillar, wherein the first chip, the blocking member, and the conductive pillar form an integral structure through the plastic encapsulation layer; Wherein, the blocking member has conductive properties, and the blocking member and the conductive column are formed of the same material; The first chip includes a first functional surface and a first non-functional surface disposed opposite to each other, the conductive pillar, the barrier and the plastic encapsulation layer are disposed flush with the first non-functional surface, and the first functional surface is located within the plastic encapsulation layer; the fan-out package device further includes: at least one second chip, including a second functional surface and a second non-functional surface disposed opposite to each other; the second functional surface faces the first functional surface, the second functional surface spans at least a portion of the first functional surface and at least a portion of the barrier adjacent to at least a portion of the first functional surface, and a second pad on the second functional surface is electrically connected to the first pad on the first functional surface and the barrier at a corresponding position; In which, the fan-out packaging device further includes: a first redistribution layer, located on the surface of the plastic encapsulation layer adjacent to the first non-functional surface; wherein, the first redistribution layer is electrically connected to at least the first chip and one end of the conductive column; a second redistribution layer, located on the surface of the plastic encapsulation layer adjacent to the first functional surface; wherein, the second redistribution layer is electrically connected to the other end of the conductive column.

2. The fan-out package device according to claim 1, wherein: A plurality of the blocking members are connected to each other to form an annular structure.

3. The fan-out package device according to claim 1, wherein: Also includes: The insulating adhesive at least covers at least a portion of the side surface of the blocking member, and the plastic sealing layer covers the insulating adhesive.

4. The fan-out package device according to claim 1, wherein: The fan-out packaging device further includes: The underfill at least covers the gap between the second functional surface of the second chip and the carrier board and the blocking member.

5. The fan-out package device according to claim 4, characterized in that The side of the plastic packaging layer facing away from the first functional surface is flush with the second non-functional surface and the conductive pillar.

6. The fan-out package device according to claim 1, wherein: Also includes: a first electrical connector, located on a side of the first redistribution layer away from the plastic packaging layer and electrically connected to the first redistribution layer; The second electrical connector is located on a side of the second redistribution layer away from the plastic packaging layer and is electrically connected to the second redistribution layer.

7. The fan-out package device according to claim 1, wherein: The height of the plastic packaging layer is the same as that of the conductive pillar, and both ends of the conductive pillar in the length direction are exposed from the plastic packaging layer.

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