Array substrate, display panel, and display device

Abstract

The present application provides an array substrate, a display panel, and a display device, which belong to the field of display technology. The problem to be solved is to increase the channel length of a driving transistor. The adopted solution is: the array substrate includes multiple pixel driving circuits, the pixel driving circuit includes at least a driving transistor, the array substrate includes: a substrate, a semiconductor layer, and a first gate conductive layer, the semiconductor layer includes an active layer pattern of the driving transistor, the first gate conductive layer includes a gate pattern of the driving transistor, wherein the active layer pattern of the driving transistor includes a first pattern and a second pattern connected to each other, the first pattern extends along a first direction, the second pattern extends along a second direction, the first direction and the second direction intersect, the gate pattern of the driving transistor overlaps with the first pattern and the second pattern, and the position where the first pattern and the second pattern are connected is exposed; the above-mentioned array substrate is used for a display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light, thereby achieving display.

[0003] Application Contents

[0004] In order to overcome the defects in the above-mentioned prior art, the present application provides an array substrate, a display panel and a display device, which can increase the channel length of the driving transistor in the array substrate, improve the mobility of the driving transistor, set the driving transistor as a dual-gate transistor, and improve the photoelectric performance of the driving transistor.

[0005] To achieve the above objectives, this application adopts the following technical solutions:

[0006] According to a first aspect of the present application, an array substrate is provided, comprising a plurality of pixel driving circuits, each of which includes at least a driving transistor. The array substrate comprises: a substrate, a semiconductor layer disposed on one side of the substrate, and a first gate conductive layer disposed on a side of the semiconductor layer away from the substrate, the semiconductor layer including an active layer pattern of the driving transistor, and the first gate conductive layer including a gate pattern of the driving transistor. The active layer pattern of the driving transistor includes a first pattern and a second pattern connected to each other, the first pattern extending along a first direction, the second pattern extending along a second direction, the first direction and the second direction intersecting, the gate pattern of the driving transistor overlapping both the first pattern and the second pattern, and exposing a location where the first pattern and the second pattern are connected.

[0007] In this application, the gate pattern of the driving transistor overlaps with both the first pattern and the second pattern, so that the channel length of the driving transistor is the sum of the channel length formed by the overlap of the gate pattern of the driving transistor and the first pattern, and the channel length formed by the overlap of the gate pattern of the driving transistor and the second pattern. This increases the channel length of the driving transistor, which is beneficial for improving the mobility of the driving transistor and enhancing the stability of the driving transistor. In addition, the gate pattern of the driving transistor exposes the location where the first pattern and the second pattern are connected, and the driving transistor is a dual-gate transistor, which improves the stability of the output current and enhances the optoelectronic performance of the driving transistor.

[0008] In some embodiments, the gate pattern of the driving transistor includes a third pattern and a fourth pattern that are connected. The extension directions of the third pattern and the fourth pattern are both parallel to the first direction, one end of the third pattern along the first direction overlaps with the second pattern, and the other end of the third pattern along the first direction is close to one side of the first pattern and connected to one side of the fourth pattern along the second direction, and the fourth pattern overlaps with the first pattern.

[0009] In some embodiments, the fourth pattern is farther away from the boundary of one end of the second pattern along the first direction than the third pattern is farther away from the boundary of one end of the second pattern along the first direction.

[0010] In some embodiments, the first direction and the second direction are perpendicular to each other.

[0011] In some embodiments, the overlapped portion of the third pattern and the second pattern has a size ranging from 5 μm to 30 μm along the second direction. The overlapped portion of the fourth pattern and the first pattern has a size ranging from 5 μm to 25 μm along the first direction.

[0012] In some embodiments, the array substrate further includes a second gate conductive layer disposed on a side of the first gate conductive layer away from the substrate, the second gate conductive layer including a plurality of constant voltage patterns, the plurality of constant voltage patterns being configured to receive a constant voltage signal, wherein the constant voltage pattern overlaps at a position where the first pattern and the second pattern are connected.

[0013] In some embodiments, the pixel driving circuit further includes a first reset transistor and a compensation transistor. The semiconductor layer further includes an active layer pattern of the first reset transistor and an active layer pattern of the compensation transistor, the active layer pattern of the first reset transistor including a fifth pattern, a sixth pattern, and a seventh pattern connected in sequence, with the fifth pattern and the seventh pattern located on the same side of the sixth pattern along the second direction, and the active layer pattern of the compensation transistor including an eighth pattern and a ninth pattern connected, with the extension directions of the eighth pattern and the ninth pattern intersecting.

[0014] The first gate conductive layer also includes a plurality of first scanning signal lines and a plurality of second scanning signal lines, the first scanning signal lines overlap with the fifth pattern and the seventh pattern and expose the sixth pattern, and the second scanning signal lines overlap with the eighth pattern and the ninth pattern and expose the position where the eighth pattern and the ninth pattern are connected.

[0015] In some embodiments, the second gate conductive layer further includes a plurality of first initial signal lines and a plurality of second initial signal lines, the first initial signal lines overlap with the sixth pattern, and the second initial signal lines overlap with the positions where the eighth pattern and the ninth pattern are connected.

[0016] In some embodiments, the pixel driving circuit further includes a write transistor, a second reset transistor, a first emission control transistor, and a second emission control transistor, and the semiconductor layer further includes an active layer pattern of the write transistor, an active layer pattern of the second reset transistor, an active layer pattern of the first emission control transistor, and an active layer pattern of the second emission control transistor. The first gate conductive layer further includes a plurality of emission control signal lines and a plurality of third scan signal lines, the second initial signal line overlaps with the active layer pattern of the write transistor, the third scan signal line overlaps with the active layer pattern of the second reset transistor, and the emission control signal line overlaps with the active layer pattern of the first emission control transistor and the active layer pattern of the second emission control transistor.

[0017] In some embodiments, the pixel driving circuit also includes a capacitor, the first gate conductive layer also includes a first plate of the capacitor, the first plate of the capacitor serves as the gate pattern of the driving transistor, and the second gate conductive layer also includes a second plate of the capacitor, the second plate of the capacitor is the constant voltage pattern.

[0018] In some embodiments, the array substrate further comprises: a first source / drain metal layer disposed on a side of the second gate conductive layer away from the substrate, and a second source / drain metal layer disposed on a side of the first source / drain metal layer away from the substrate, wherein the first source / drain metal layer comprises a plurality of first power signal lines, and the second source / drain metal layer comprises a plurality of second power signal lines and a plurality of data lines. A second power signal line is connected to a first power signal line through a via, and the orthographic projections of the connected second power signal line and the first power signal line on the substrate overlap.

[0019] In some embodiments, the second source / drain metal layer further includes a plurality of planar patterns, and the planar patterns are connected to the second power signal line.

[0020] A second aspect of the present application provides a display panel, which includes the array substrate as described above.

[0021] In some embodiments, the display panel also includes an anode layer arranged on the array substrate, the anode layer includes multiple anodes, the array substrate includes a second source-drain metal layer, the second source-drain metal layer includes multiple flat patterns, the multiple flat patterns are arranged corresponding to the multiple anodes, and the orthographic projection of one of the anodes on the substrate coincides with the orthographic projection of one of the flat patterns on the substrate.

[0022] The display panel further includes a light-emitting layer disposed on a side of the anode layer away from the substrate. The light-emitting layer includes a plurality of light-emitting portions. The orthographic projection of one light-emitting portion on the substrate falls within the orthographic projection of one anode on the substrate.

[0023] A third aspect of the present application provides a display device, which includes the display panel as described above.

[0024] The array substrate, display panel and display device provided in the present application have driving transistors in their pixel circuits that are all dual-gate transistors, which increases the channel length of the driving transistor, is beneficial to improving the mobility of the driving transistor, improves the stability of the driving transistor, and improves the stability of the output current and the photoelectric performance of the driving transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 A structural diagram of a display device provided in some embodiments of the present application;

[0027] Figure 2 A structural diagram of a display panel provided in some embodiments of the present application;

[0028] Figure 3 Another structural diagram of a display panel provided in some embodiments of the present application;

[0029] Figure 4 A cross-sectional view of a display panel provided in some embodiments of the present application;

[0030] Figure 5a A structural diagram showing a semiconductor layer provided in some embodiments after a first gate conductive layer is stacked on the semiconductor layer;

[0031] Figure 5b Another structural diagram after a first gate conductive layer is stacked on the semiconductor layer provided in some embodiments;

[0032] Figure 6 Another structural diagram after a first gate conductive layer is stacked on the semiconductor layer provided in some embodiments;

[0033] Figure 7 A structural diagram of a pixel circuit provided in some embodiments of the present application;

[0034] Figure 8 Structural diagrams of semiconductor layers provided for some embodiments of the present application;

[0035] Figure 9 A structural diagram of a first gate conductive layer provided in some embodiments of the present application;

[0036] Figure 10 A structural diagram showing a semiconductor layer provided by some embodiments of the present application after a first gate conductive layer is stacked on the semiconductor layer;

[0037] Figure 11 A structural diagram showing a semiconductor layer provided by some embodiments of the present application after a first gate conductive layer is stacked on the semiconductor layer;

[0038] Figure 12 A structural diagram of another pixel circuit provided in some embodiments of the present application;

[0039] Figure 13 A structural diagram showing a semiconductor layer provided by some embodiments of the present application after a first gate conductive layer is stacked on the semiconductor layer;

[0040] Figure 14 A structural diagram of a second gate conductive layer provided in some embodiments of the present application;

[0041] Figure 15 A structural diagram showing a second gate conductive layer stacked on a first gate conductive layer provided in some embodiments of the present application;

[0042] Figure 16 A structural diagram showing a second gate conductive layer stacked on a first gate conductive layer provided in some embodiments of the present application;

[0043] Figure 17 A structural diagram showing a second gate conductive layer provided by some embodiments of the present application after an interlayer dielectric layer is stacked on the second gate conductive layer;

[0044] Figure 18 A structural diagram showing a second gate conductive layer provided by some embodiments of the present application after an interlayer dielectric layer is stacked on the second gate conductive layer;

[0045] Figure 19 A structural diagram of a first source / drain metal layer provided in some embodiments of the present application;

[0046] Figure 20A structural diagram of a first source / drain metal layer stacked on an interlayer dielectric layer provided in some embodiments of the present application;

[0047] Figure 21 A structural diagram of a first source / drain metal layer stacked on an interlayer dielectric layer provided in some embodiments of the present application;

[0048] Figure 22 A structural diagram showing a first planarization layer stacked on a first source / drain metal layer provided in some embodiments of the present application;

[0049] Figure 23 A structural diagram showing a first planarization layer stacked on a first source / drain metal layer provided in some embodiments of the present application;

[0050] Figure 24 A structural diagram of a second source / drain metal layer provided in some embodiments of the present application;

[0051] Figure 25 A structural diagram showing a second planarization layer stacked on a second source / drain metal layer provided in some embodiments of the present application;

[0052] Figure 26 A structural diagram of the anode layer provided for some embodiments of the present application;

[0053] Figure 27 This is a structural diagram of an anode layer stacked on a second planarization layer provided in some embodiments of the present application. DETAILED DESCRIPTION

[0054] To make the above-mentioned purposes, features, and advantages of the present application more clearly understood, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0055] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "some embodiments", "example", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0056] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0057] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0058] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices being configured to perform additional tasks or steps.

[0059] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0060] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0061] Some embodiments of the present application provide a display device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a car computer, a wearable display device, or a watch. Figure 1 As shown, the display device 1000 may be a mobile phone. The embodiment of the present application does not impose any particular limitation on the specific form of the above-mentioned display device.

[0062] In some examples, the display device may also be an electroluminescent display device or a photoluminescent display device. In the case where the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot electroluminescent display device (QLED). In the case where the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0063] The display device 1000 includes a display panel 100. Figure 2 As shown, the display panel 100 includes a display area AA (Active Area, AA area for short; also called an effective display area) and a peripheral area BB located on at least one side of the display area AA. Among them, a plurality of sub-pixels 10 and a plurality of signal lines are arranged in the display area AA, and the plurality of sub-pixels 10 are arranged in the display area AA according to specified rules. For example, the plurality of sub-pixels 10 are arranged in N rows and M columns. At this time, the sub-pixels 10 arranged in a row along the horizontal direction X are called a row of sub-pixels, and the sub-pixels 10 arranged in a row along the vertical direction Y are called a column of sub-pixels. Among them, the sub-pixel 10 is the smallest unit for displaying the picture in the display panel 100, and each sub-pixel 10 can display a single color, such as red, green or blue. By adjusting the brightness of different sub-pixels 10, the color superposition can realize the display of multiple colors. Among them, as Figure 3 As shown, each sub-pixel 10 includes a light emitting device 50 and a pixel driving circuit 20 for driving the light emitting device 50 to emit light.

[0064] For example, see again Figure 3The plurality of signal lines include a plurality of scanning signal lines GL, a plurality of data lines DL, a plurality of emission control lines EL, a plurality of initial signal lines Vinit, and a plurality of first voltage signal lines VDD. Exemplarily, the plurality of scanning signal lines GL, the plurality of initial signal lines Vinit, and the plurality of emission control lines EL extend along a horizontal direction X, while the plurality of data lines DL and the plurality of first voltage signal lines VDD extend along a vertical direction Y. The plurality of sub-pixels 10, the plurality of scanning signal lines GL, the plurality of emission control lines EL, the plurality of data lines DL, the plurality of initial signal lines Vinit, and the plurality of first voltage signal lines VDD are all disposed in the display area AA.

[0065] In some embodiments, as Figure 4 As shown, the display panel 100 includes an array substrate 30, a light-emitting device layer 3, and an encapsulation layer 4. The array substrate 30 is provided with a plurality of transistors and capacitors included in the pixel driving circuit 20, and the light-emitting device layer 3 includes a plurality of light-emitting devices 50. The array substrate 30 includes: a substrate 1 and a plurality of pixel circuit layers 2 stacked in sequence on the substrate 1. The pixel circuit layer 2 includes a functional layer and an insulating layer located between adjacent functional layers. The functional layer may include a semiconductor layer, a gate conductive layer, and a source / drain metal layer. The semiconductor layer, the gate conductive layer, and the source / drain metal layer are used to form a plurality of pixel driving circuits 20 in the display panel 100. The plurality of pixel driving circuits 20 may be formed in the display area AA of the display panel 100. The light-emitting device 50 is provided on the side of the pixel driving circuit 20 away from the substrate 1.

[0066] The pixel driving circuit 20 includes a plurality of transistors, wherein the active layer of each transistor is located in the semiconductor layer 201, the active layer includes a channel region Sg, and the gate of each transistor is located in the first gate conductive layer 203, wherein the first gate conductive layer 203 includes, for example, a plurality of signal lines, and the portion of a signal line that passes through the active layer of a certain transistor can serve as the gate of the transistor, where "passing through" refers to the portion where the orthographic projections of the two on the substrate 1 overlap. When manufacturing the transistor, a semiconductor layer 201 can be first formed on the substrate 1, and then a first gate conductive layer 203 can be formed on a side of the semiconductor layer 201 away from the substrate 1. The position where the first gate conductive layer 203 overlaps with the semiconductor layer 201 is the position where the first gate conductive layer 203 "passes through" the semiconductor layer 201. For example, the gate of the transistor is arranged to overlap with the channel region Sg of the transistor.

[0067] It should be noted that the "orthographic projection" in this article refers to the projection produced by projection lines that are perpendicular to the projection plane and parallel to each other.

[0068] It can be seen that the pixel driving circuit 20 is mainly composed of transistors. Therefore, the size of the space occupied by the transistor can determine the size of the space occupied by the pixel driving circuit 20. For example, the space occupied by the transistor includes the lateral area size parallel to the plane where the substrate 1 is located and the longitudinal area size in the direction perpendicular to the plane where the substrate 1 is located. The longitudinal area size is mainly related to the thickness of the film layer included in the array substrate 30. In this application, the focus is on the lateral area size of the transistor and the pixel driving circuit 20 parallel to the plane where the substrate 1 is located. The lateral area size is the area of ​​the positive projection of the transistor on the substrate 1. Hereinafter, the area of ​​the positive projection of the transistor on the substrate 1 will be collectively referred to as the area of ​​the transistor. The same applies to the area of ​​the pixel driving circuit 20 and the area of ​​the transistor channel.

[0069] Within a display panel 100 of the same size, the greater the number of sub-pixels 10, the higher the pixel density (PPI) of the display panel 100, thereby providing a better display quality. The number of sub-pixels 10 is related to the area of ​​the sub-pixels 10; that is, the smaller the area of ​​each sub-pixel 10, the greater the number of sub-pixels 10 within the same size, and the higher the pixel density (PPI) of the display panel 200.

[0070] Generally, when the drive thin film transistor (DTFT) in the pixel driving circuit operates in the saturation region, if the channel of the drive thin film transistor (DTFT) is longer, it is beneficial to improve the mobility of the drive thin film transistor (DTFT) and thus improve the stability of the drive thin film transistor (DTFT). Figure 5a and Figure 5b As shown, in the related art, the channel of the driving transistor DTFT of the pixel driving circuit 20 generally adopts a horizontal straight channel design or a vertical straight channel design. Figure 5a As shown, the channel of the driving transistor DTFT of the pixel driving circuit 20 adopts a horizontal straight channel, and its channel length is length d1. Figure 5b As shown, the channel of the driving transistor DTFT of the pixel driving circuit 20 adopts a longitudinal straight channel, and its channel length is length d2. Relative to the area of ​​the driving transistor DTFT, the area of ​​the channel of the driving transistor DTFT is limited. Such a design results in a shorter channel length of the driving transistor DTFT, which will have an adverse effect on the display effect of the product.

[0071] However, if Figure 6As shown, the channel of the driving transistor DTFT is designed to be in the shape of a Chinese character "J". The channel length d3 of the driving transistor DTFT includes the sum of the contour lengths of the Chinese character "J". That is, the channel length d3 is the sum of the five channel lengths forming the Chinese character "J". The five channels include a first channel region Sg1, a second channel region Sg2, a third channel region Sg3, a fourth channel region Sg4 and a fifth channel region Sg5 connected in sequence. The channel length d3 is equal to the sum of the first channel length d31, the second channel length d32, the third channel length d33, the fourth channel length d33 and the fifth channel length d35, that is, d3 = d31 + d32 + d33 + d34 + d35. In the limited area occupied by the driving transistor, the channel length of the driving transistor DTFT is increased. However, the "J"-shaped channel occupies a large area of ​​the pixel space, which directly leads to a larger area occupied by the DTFT, and thus a larger space occupied by the sub-pixel 10, which is not conducive to achieving a high pixel density (Pixels Per Inch, PPI) for the display panel 100. Under the condition of reducing the area occupied by the transistor occupied by the driving transistor DTFT, the "J"-shaped channel has many corners J, which are generally 90° corners formed by the semiconductor layer 201. The formation of corners J is relatively difficult and presents technical barriers.

[0072] Based on the above problems, the solution of this application is introduced in detail below.

[0073] In some embodiments, the pixel driving circuit 20 in the present application may be a circuit including 2T1C, 7T1C, or 6T1C, where T represents a transistor, and the number before T represents the number of transistors, and C represents a capacitor, and the number before C represents the number of capacitors. For example, 7T1C represents 7 transistors and 1 capacitor. The following description takes the pixel driving circuit in the 7T1C mode as an example.

[0074] like Figure 7 As shown, the pixel driving circuit 20 includes: a storage subcircuit 21, a driving subcircuit 22, a first reset subcircuit 23, a compensation subcircuit 24, a data writing subcircuit 25, a first light-emitting control subcircuit 26, a second light-emitting control subcircuit 27 and a second reset subcircuit 28.

[0075] The driving sub-circuit 22 is configured to generate a driving current.

[0076] The storage sub-circuit 21 is electrically connected to the driving sub-circuit 22 and the first voltage signal terminal VDD; the storage sub-circuit 21 is configured to store the received signal and maintain the potential of the connection terminal between the storage sub-circuit 21 and the driving sub-circuit 22 .

[0077] The first reset sub-circuit 23 is electrically connected to the driving sub-circuit 22, the first scanning signal line GL1 and the second initial signal line Vinit2; the first reset sub-circuit 23 is configured to transmit the second initialization signal Vini2 received at the second initial signal line Vinit2 to the driving sub-circuit 22 in response to the first scanning signal Scan1 received at the first scanning signal line GL1.

[0078] The compensation sub-circuit 24 is electrically connected to the driving sub-circuit 22 and the second scan signal line GL2 ; the compensation sub-circuit 24 is configured to perform threshold compensation on the driving sub-circuit 22 in response to the second scan signal Scan2 received at the second scan signal line GL2 .

[0079] Hereinafter, the node electrically connected to the driving subcircuit 22, the storage subcircuit 21, the first reset subcircuit 23, and the compensation subcircuit 24 is referred to as the first node N1. The first reset subcircuit 23 can transmit the second initialization signal Vini2 to the first node N1 to reset the first node N1.

[0080] It should be noted that in the circuits provided in the embodiments of the present application, the nodes do not represent actual components, but rather represent the junction points of related electrical connections in the circuit diagram. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0081] Exemplarily, the storage sub-circuit 21 includes a capacitor Cst, a first plate Cst1 of the capacitor Cst is electrically connected to the first node N1, and a second plate Cst2 of the capacitor Cst is electrically connected to the first voltage signal line VDD.

[0082] Exemplarily, the driving sub-circuit 22 includes a driving transistor DTFT, which includes a control electrode, a first electrode, and a second electrode. The control electrode of the driving transistor DTFT is electrically connected to the first node N1.

[0083] It should be noted that the control electrode of the transistor of the present application is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present application can be structurally indistinguishable. For example, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; for example, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0084] Exemplarily, the first reset sub-circuit 23 includes a first reset transistor T1, which includes a control electrode, a first electrode and a second electrode. The control electrode of the first reset transistor T1 is electrically connected to the first scanning signal line GL1, the first electrode of the first reset transistor T1 is electrically connected to the second initial signal line Vinit2, and the second electrode of the first reset transistor T1 is electrically connected to the first node N1.

[0085] Exemplarily, the compensation sub-circuit 24 includes a compensation transistor T2, which includes a control electrode, a first electrode, and a second electrode. The control electrode of the compensation transistor T2 is electrically connected to the second scanning signal line GL2, the first electrode of the compensation transistor T2 is electrically connected to the second electrode of the driving transistor DTFT, and the second electrode of the compensation transistor T2 is electrically connected to the first node N1.

[0086] Hereinafter, the node where the first electrode of the compensation transistor T2 and the second electrode of the driving transistor DTFT are electrically connected is referred to as a second node N2.

[0087] The data writing sub-circuit 25 is electrically connected to the second scanning signal line GL2, the driving sub-circuit 22 and the data line DL. The data writing sub-circuit 25 is configured to transmit the data signal Data received at the data line DL to the driving sub-circuit 22 in response to the second scanning signal Scan2 received at the second scanning signal line GL2.

[0088] The first light-emitting control sub-circuit 26 is electrically connected to the light-emitting control line EL, the first voltage signal line VDD and the driving sub-circuit 22. The first light-emitting control sub-circuit 26 is configured to transmit the first voltage signal received at the first voltage signal line VDD to the driving sub-circuit 22 in response to the light-emitting control signal EM received at the light-emitting control line EL.

[0089] Hereinafter, the node where the driving sub-circuit 22 is electrically connected to the data writing sub-circuit 25 and the first light emitting control sub-circuit 26 is referred to as a third node N3.

[0090] Exemplarily, the data writing sub-circuit 25 includes a writing transistor T4, which includes a control electrode, a first electrode and a second electrode. The control electrode of the writing transistor T4 is electrically connected to the second scanning signal line GL2, the first electrode of the writing transistor T4 is electrically connected to the data line DL, and the second electrode of the writing transistor T4 is electrically connected to the third node N3.

[0091] The first light-emitting control subcircuit 26 includes a first light-emitting control transistor T5, which includes a control electrode, a first electrode, and a second electrode. The control electrode of the first light-emitting control transistor T5 is electrically connected to the light-emitting control line EL, the first electrode of the first light-emitting control transistor T5 is electrically connected to the first voltage signal line VDD, and the second electrode of the first light-emitting control transistor T5 is electrically connected to the third node N3.

[0092] The second reset sub-circuit 28 is electrically connected to the third scan signal line GL3, the first initial signal line Vinit1 and the light-emitting device 50. The second reset sub-circuit 28 is configured to, in response to the third scan signal Scan1 received at the third scan signal line GL3, transmit the first initialization signal Vini1 received at the first initial signal line Vinit1 to the light-emitting device 50 to reset the light-emitting device 50.

[0093] The second light-emitting control sub-circuit 27 is electrically connected to the light-emitting control line EL, the driving sub-circuit 22 and the light-emitting device 50. The second light-emitting control sub-circuit 27 is configured to receive the driving signal output by the driving sub-circuit 22 in response to the light-emitting control signal EM received at the light-emitting control line EL, and transmit the driving signal to the light-emitting device 50 to control the light-emitting device 50 to emit light.

[0094] In some examples, the second reset sub-circuit 28 and the second light emitting control sub-circuit 27 are both coupled to the anode of the light emitting device 50 , and the cathode of the light emitting device 50 is electrically connected to the second voltage signal line VSS.

[0095] Hereinafter, the node where the light emitting device 50 is electrically connected to the second reset sub-circuit 28 and the second light emitting control sub-circuit 27 is referred to as a fourth node N4.

[0096] Exemplarily, the second reset sub-circuit 28 includes a second reset transistor T7, which includes a control electrode, a first electrode and a second electrode. The control electrode of the second reset transistor T7 is electrically connected to the third scanning signal line GL3, the first electrode of the second reset transistor T7 is electrically connected to the first initial signal line Vinit1, and the second electrode of the second reset transistor T7 is electrically connected to the fourth node N4.

[0097] The second light-emitting control subcircuit 27 includes a second light-emitting control transistor T6, which includes a control electrode, a first electrode, and a second electrode. The control electrode of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line EL, the first electrode of the second light-emitting control transistor T6 is electrically connected to the second node N2, and the second electrode of the second light-emitting control transistor T6 is electrically connected to the fourth node N4.

[0098] In some embodiments, the transistors included in each of the above sub-circuits are of the same on / off type. For example, the driving transistor DTFT, the first reset transistor T1, the compensation transistor T2, the write transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 are all P-type transistors or N-type transistors. For example, the above transistors are all low-temperature polysilicon thin film transistors (LTPTs). The N-type transistor is turned on when the gate receives a high voltage signal, while the P-type transistor is turned on when the gate receives a low voltage signal. It should be noted that the “high voltage signal” and “low voltage signal” mentioned above are popular terms. Generally speaking, the conduction condition of an N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage. The threshold voltage of the N-type transistor is a positive value, and the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The conduction condition of a P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage. The threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage. The gate voltage signal that turns on the P-type transistor is called a low voltage signal. The high and low in “high voltage signal” and “low voltage signal” are relative to a reference voltage (e.g., 0V). This application is explained by taking the above-mentioned transistors as N-type transistors as an example.

[0099] The following describes the film layer structures included in the array substrate 30 .

[0100] In some embodiments, see again Figure 4 The substrate 1 of the array substrate 30 can be a single-layer structure or a multi-layer structure. Figure 4 As shown, the substrate 1 may include a flexible base layer 101 and a buffer layer 102 stacked in sequence. For another example, the substrate 1 may include multiple flexible base layers 101 and multiple buffer layers 102 arranged alternately. The flexible base layer 101 may be made of polyimide, and the buffer layer 102 may be made of silicon nitride and / or silicon oxide to achieve the effect of blocking water, oxygen, and alkaline ions.

[0101] The pixel circuit layer 2 includes a semiconductor layer 201, a first gate insulating layer 202, a first gate conductive layer 203, a second gate insulating layer 204, a second gate conductive layer 205, an interlayer dielectric layer 206, a first source-drain metal layer 207, a passivation layer 208, a first planarization layer 209, a second source-drain metal layer 210 and a second planarization layer 220, which are stacked in sequence on the substrate 1.

[0102] Optionally, there may be only one source / drain metal layer (eg, only the first source / drain metal layer 207 or only the second source / drain metal layer 210 ), and correspondingly, there may be only one planarization layer (eg, only the first planarization layer 209 or only the second planarization layer 220 ).

[0103] The pixel circuit layer 2 includes a plurality of pixel driving circuits 20 , and each sub-pixel 10 includes a corresponding pixel driving circuit 20 .

[0104] Each pixel driving circuit 20 is provided with a plurality of transistors and a plurality of capacitors Cst. Figure 4 Only one of the transistors and one corresponding capacitor Cst are shown as an example.

[0105] The transistor includes a control electrode, a first electrode, a second electrode and an active layer, wherein the control electrode of the transistor is located in the first gate conductive layer 203 , and the first electrode and the second electrode of the transistor are located in the first source-drain metal layer 207 . The active layer of the transistor is located in the semiconductor layer 201 .

[0106] The capacitor Cst includes a first plate Cst1 and a second plate Cst2 , wherein the first plate Cst1 is located in the first gate conductive layer 203 , and the second plate Cst2 is located in the second gate conductive layer 205 .

[0107] The light emitting device layer 3 includes an anode layer 301 , a pixel defining layer 302 , a light emitting layer 303 and a cathode layer 304 , which are sequentially arranged on a side of the pixel circuit layer 2 away from the substrate 1 .

[0108] The light emitting device layer 3 is provided with a plurality of light emitting devices 50. The light emitting device 50 includes an anode in the anode layer 301, a cathode in the cathode layer 304, and a light emitting pattern in the light emitting layer 303. The cathode in the cathode layer 304 is configured to transmit a low level voltage.

[0109] Exemplarily, in addition to the light-emitting pattern, the light-emitting layer 303 also includes one or more layers of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL).

[0110] For example, the anode of the light emitting device 50 may be electrically connected to the first electrode or the second electrode of the transistor.

[0111] Encapsulation layer 4 may include a first encapsulation sublayer 401, a second encapsulation sublayer 402, and a third encapsulation sublayer 403, stacked sequentially away from substrate 1. Exemplarily, the materials of first and third encapsulation sublayers 401 and 403 include inorganic materials, while the material of second encapsulation sublayer 402 includes organic materials. First and third encapsulation sublayers 401 and 403 function as water vapor and oxygen barriers, while second encapsulation sublayer 402 has a certain degree of flexibility and functions as a moisture absorber.

[0112] The above content introduces the film layer distribution of the display panel 100. The following describes the layout structure of the display panel 100. It should be noted that: Figures 8 to 11 、 Figures 13 to 27 Only the functional layers included in the array substrate 30 are shown, and each functional layer includes a functional pattern. The insulating film layer between two adjacent functional layers is not shown. The insulating film layer is, for example, a gate insulating layer, etc. Exemplarily, the insulating film layer is a complete film layer covering the entire area of ​​the array substrate 30.

[0113] like Figures 8 to 11 、 Figures 13 to 27 As shown, the display panel 100 includes a stacked arrangement of patterned film layers, forming a Figure 12 The individual transistors in the equivalent circuit diagram are shown.

[0114] In some embodiments, the array substrate 30 includes a plurality of pixel driving circuits 20, such as Figure 7 and Figure 12 As shown, the pixel driving circuit 20 includes a driving transistor DTFT, which is specifically as described above and will not be repeated here.

[0115] In some embodiments, the array substrate 30 includes a substrate 1 and a semiconductor layer 201 disposed on one side of the substrate 1. Figure 8 and Figure 10 As shown, the semiconductor layer 201 includes an active layer pattern 211 of a driving transistor DTFT.

[0116] Exemplarily, the material of the semiconductor layer 201 includes low-temperature polysilicon.

[0117] In some embodiments, the array substrate 30 further includes a first gate conductive layer 203 disposed on a side of the semiconductor layer 201 away from the substrate 1. Figure 9 and Figure 10 As shown, the first gate conductive layer 203 includes a gate pattern 231 of the driving transistor DTFT.

[0118] For example, a first gate insulating layer 202 is provided between the semiconductor layer 201 and the first gate conductive layer 203 (see Figure 4 As shown), the first gate insulating layer 202 may be made of silicon oxide (SiO2).

[0119] In some examples, such as Figure 11 As shown, the active layer pattern 211 of the driving transistor DTFT includes a first pattern 211a and a second pattern 211b connected to each other. The first pattern 211a extends along a first direction X, and the second pattern 211b extends along a second direction Y. The first direction X and the second direction Y intersect. The gate pattern 231 of the driving transistor DTFT overlaps with both the first pattern 211a and the second pattern 211b, and exposes a position 211c where the first pattern 211a and the second pattern 211b are connected.

[0120] In some examples, see again Figure 11 The first direction X and the second direction Y are perpendicular, the first pattern 211a and the second pattern 211b intersect to form an "L"-shaped structure, and the gate pattern 231 of the driving transistor DTFT overlaps with both the first pattern 211a and the second pattern 211b. In other words, the orthographic projection of the gate pattern 231 of the driving transistor DTFT on the substrate 1 overlaps with the orthographic projection of the first pattern 211a on the substrate 1, and the orthographic projection of the gate pattern 231 of the driving transistor DTFT on the substrate 1 overlaps with the orthographic projection of the second pattern 211b on the substrate 1.

[0121] The gate pattern 231 of the driving transistor DTFT overlaps with the first pattern 211a and the second pattern 211b to form the gate of the driving transistor DTFT. The gate pattern 231 of the driving transistor DTFT does not overlap with a location 211c where the first pattern 211a and the second pattern 211b are connected. In other words, the orthographic projection of the gate pattern 231 of the driving transistor DTFT on the substrate 1 does not overlap with the orthographic projection of a location 211c where the first pattern 211a and the second pattern 211b are connected.

[0122] In some embodiments, see again Figure 11 The active layer pattern 211 of the driving transistor DTFT includes a first channel region, a second channel region, and a conductive region. The first channel region is the portion of the first pattern 211a of the driving transistor DTFT that overlaps with the gate pattern 231 of the driving transistor DTFT. The second channel region is the portion of the second pattern 211b of the driving transistor DTFT that overlaps with the gate pattern 231 of the driving transistor DTFT. The portion of the active layer pattern 211 of the driving transistor DTFT other than the first and second channel regions is a conductive region. The gate pattern 231 of the driving transistor DTFT exposes a location 211c where the first pattern 211a and the second pattern 211b connect, indicating that a conductive region exists between the first and second channel regions of the active layer pattern 211 of the driving transistor DTFT.

[0123] The above design of the active layer pattern 211 and the gate pattern 231 of the driving transistor DTFT is equivalent to designing the driving transistor DTFT as a dual-gate transistor. For example, Figure 12 As shown, the driving transistor DTFT includes a first sub-transistor T31 and a second sub-transistor T32. The control electrode of the first sub-transistor T31 is electrically connected to the first node N1, and the second electrode of the first sub-transistor T31 is electrically connected to the first electrode of the second sub-transistor T32; the control electrode of the second sub-transistor T32 is electrically connected to the first node N1. It can be understood that the control electrode of the driving transistor DTFT is the control electrode of the first sub-transistor T31 and the control electrode of the second sub-transistor T32, the first electrode of the driving transistor DTFT is the first electrode of the first sub-transistor T31, and the second electrode of the driving transistor DTFT is the second electrode of the second sub-transistor T32.

[0124] The present application designs the driving transistor DTFT as a dual-gate transistor, which can increase the on-state current of the driving transistor DTFT, improve the stability of the driving transistor DTFT, increase the anti-interference ability and greater load driving ability, and at the same time design the driving transistor DTFT as a dual-gate transistor to increase the threshold voltage V th The reduction in absolute value is conducive to the driving transistor DTFT operating at a lower operating voltage, and the dual-gate design of the driving transistor DTFT increases the charging range of the data line, which can improve the picture quality display effect and improve the photoelectric performance of the driving transistor DTFT.

[0125] It should be noted that the first direction X and the second direction Y may intersect but are not perpendicular to each other, and this is not limited here.

[0126] By designing the active layer pattern 211 of the driving transistor DTFT into a first pattern 211a and a second pattern 211b connected to each other, the driving transistor DTFT includes a first sub-transistor T31 formed by the first pattern 211a and a second sub-transistor T32 formed by the second pattern 211b. Figure 13As shown, the channel length d4 of the driving transistor DTFT includes the channel length d41 of the first sub-transistor T31 and the channel length d42 of the second sub-transistor T32, that is, d4 = d41 + d42. The "L" channel formed in this application increases the channel length compared to the horizontal straight channel and the vertical straight channel described above, which is beneficial for improving the mobility of the driving transistor DTFT and improving the stability of the driving transistor DTFT. Compared with the "J"-shaped channel described above, the "L" channel formed in this application has fewer corners in the active layer pattern 211, which reduces the difficulty of formation and can optimize pixel space design. Therefore, this application ensures the channel length d4 of the driving transistor DTFT while achieving a high pixel density (Pixels Per Inch, PPI) of the display panel 100. The driving transistor DTFT is a dual-gate transistor, which improves the stability of the output current and improves the optoelectronic performance of the driving transistor DTFT.

[0127] In addition, since the brightness of the light-emitting device in the sub-pixel is related to the driving current generated by the driving transistor, and the driving current is controlled by the data signal transmitted by the data line DL, the increase in the channel length of the driving transistor can increase the data voltage range of the data signal, thereby improving the control ability of the driving transistor over the light-emitting device, thereby improving the display effect of the display panel.

[0128] For example, Figure 5a 、 Figure 5b and Figure 11 As shown, under the condition of the same resolution, the channel length d1 of the driving transistor DTFT using a horizontal straight channel is 19.25 μm, the channel length d2 of the driving transistor DTFT using a vertical straight channel is 17.38 μm, and the channel length d4 of the driving transistor DTFT using the "L" channel designed in this application is 20.69 μm, which significantly increases the channel length of the driving transistor DTFT.

[0129] In some embodiments, see again Figure 13 The gate pattern 231 of the driving transistor DTFT includes a third pattern 231a and a fourth pattern 231b connected to each other. The extension directions of the third pattern 231a and the fourth pattern 231b are both parallel to the first direction X. One end of the third pattern 231a along the first direction X overlaps with the second pattern 211b. The other end of the third pattern 231a along the first direction X is close to one side of the first pattern 211a and is connected to one side of the fourth pattern 231b along the second direction Y. The fourth pattern 231b overlaps with the first pattern 211a.

[0130] In some examples, see again Figure 13With the first direction X and the second direction Y perpendicular, the third pattern 231a and the fourth pattern 231b are arranged along the second direction Y. The portion where the fourth pattern 231b overlaps the first pattern 211a forms the gate of the first sub-transistor T31, and the portion where one end of the third pattern 231a overlaps the second pattern 211b along the first direction X forms the gate of the second sub-transistor T32. In contrast to the "L"-shaped structure formed by the intersection of the first and second patterns 211a and 211b, the gate pattern 231 formed by the third and fourth patterns 231a and 231b resembles an inverted "L"-shaped structure. The "L"-shaped and inverted "L"-shaped structures overlap, exposing the location 211c where the first and second patterns 211a and 211b connect, thereby forming the driving transistor DTFT into a dual-gate transistor and improving the optoelectronic performance of the driving transistor DTFT.

[0131] In some embodiments, see again Figure 13 The fourth pattern 231b is farther from the boundary LL1 of one end of the second pattern 211b along the first direction X than the boundary LL2 of one end of the third pattern 231a is farther from the second pattern 211b along the first direction X.

[0132] Exemplarily, the overlapping portion of the fourth pattern 231b and the first pattern 211a forms the gate of the first sub-transistor T31, and the overlapping portion of the fourth pattern 231b and the first pattern 211a forms the channel of the first sub-transistor T31. The fourth pattern 231b is positioned farther from the boundary LL1 at one end of the second pattern 211b along the first direction X than the boundary LL2 at one end of the second pattern 211b along the first direction X of the third pattern 231a. Furthermore, the fourth pattern 231b is positioned farther from the second pattern 211b along the first direction X. This can extend the length of the overlapping portion of the fourth pattern 231b and the first pattern 211a, thereby increasing the channel length d41 of the first sub-transistor T31. While ensuring the optoelectronic performance of the driving transistor DTFT, the channel length d4 of the driving transistor DTFT is further lengthened, which is more conducive to improving the mobility and data voltage range of the driving transistor DTFT, thereby enhancing the stability of the driving transistor DTFT.

[0133] In some embodiments, as Figure 13 As shown, the overlapping portion of the third pattern 231a and the second pattern 211b has a dimension along the second direction Y ranging from 5 μm to 30 μm, that is, the channel length d42 of the second sub-transistor T32 ranges from 5 μm to 30 μm. Exemplarily, the channel length d42 of the second sub-transistor T32 is 5 μm, 15 μm, 20 μm, 25 μm, or 30 μm, etc., but this is not limited here.

[0134] The overlapping portion of the fourth pattern 231b and the first pattern 211a has a dimension along the first direction X ranging from 5 μm to 25 μm. That is, the channel length d41 of the first sub-transistor T31 ranges from 5 μm to 25 μm. For example, the channel length d41 of the first sub-transistor T31 is 5 μm, 10 μm, 15 μm, 20 μm, or 25 μm, etc., although this is not limiting.

[0135] In some embodiments, as Figures 14 to 16 As shown, the array substrate 30 also includes a second gate conductive layer 205 arranged on the side of the first gate conductive layer 203 away from the substrate 1, and the second gate conductive layer 205 includes a plurality of constant voltage patterns 251, and the plurality of constant voltage patterns 251 are configured to receive constant voltage signals, wherein the constant voltage pattern 251 overlaps with the position 211c where the first pattern 211a and the second pattern 211b are connected.

[0136] For example, Figure 4 As shown, a second gate insulating layer 204 is provided between the first gate conductive layer 203 and the second gate conductive layer 205 .

[0137] In some examples, the constant voltage pattern 251 of the second gate conductive layer 205 is the second plate Cst2 of the capacitor Cst. The details are described below and are not repeated here.

[0138] It should be noted that a constant voltage signal refers to a signal whose voltage amplitude is a constant, continuous signal, such as a DC voltage source. The constant voltage pattern 251 overlaps with the location 211c where the first pattern 211a and the second pattern 211b are connected. In other words, the orthographic projection of the constant voltage pattern 251 on the substrate 1 covers the orthographic projection of the location 211c where the first pattern 211a and the second pattern 211b are connected on the substrate 1. This can reduce signal fluctuations at the location 211c of the active layer pattern of the driving transistor exposed by the gate pattern, reduce the effects of parasitic capacitance and light on the stability of the signal, and further improve the stability of the driving transistor.

[0139] In some implementations, such as Figure 7 and Figure 12 As shown, the pixel driving circuit 20 further includes a first reset transistor T1 and a compensation transistor T2 , which are described in detail above and will not be repeated here.

[0140] like Figure 11As shown, the semiconductor layer 201 further includes an active layer pattern 212 of the first reset transistor T1 and an active layer pattern 213 of the compensation transistor T2. The active layer pattern 212 of the first reset transistor T1 includes a fifth pattern 212a, a sixth pattern 212b, and a seventh pattern 212c connected in sequence, and the fifth pattern 212a and the seventh pattern 212c are located on the same side of the sixth pattern 212b along the second direction Y. The active layer pattern 213 of the compensation transistor T2 includes an eighth pattern 213a and a ninth pattern 213b connected to each other, and the extension directions of the eighth pattern 213a and the ninth pattern 213b intersect.

[0141] For example, see again Figure 11 The fifth pattern 212a and the seventh pattern 212c extend along the second direction Y, and the sixth pattern 212b extends along the first direction X. The fifth pattern 212a, the sixth pattern 212b, and the seventh pattern 212c form an inverted "U"-shaped structure. The eighth pattern 213a extends along the second direction Y, and the ninth pattern 213b extends along the first direction X. The eighth pattern 213a and the ninth pattern 213b form an inverted "L"-shaped structure.

[0142] like Figure 16 As shown, the first gate conductive layer 203 further includes a plurality of first scan signal lines GL1 and a plurality of second scan signal lines GL2. The first scan signal lines GL1 overlap with both the fifth pattern 212a and the seventh pattern 212c, and expose the sixth pattern 212b. The second scan signal lines GL2 overlap with both the eighth pattern 213a and the ninth pattern 213b, and expose the connection between the eighth pattern 213a and the ninth pattern 213b.

[0143] In some examples, see again Figure 11 The active layer pattern 212 of the first reset transistor T1 includes a first channel region, a second channel region, and a conductive region. The first channel region is the portion of the fifth pattern 212a of the first reset transistor T1 that overlaps with the gate pattern of the first reset transistor T1. The second channel region is the portion of the seventh pattern 212c of the first reset transistor T1 that overlaps with the gate pattern of the first reset transistor T1. The portion of the active layer pattern 212 of the first reset transistor T1 other than the first and second channel regions is a conductive region. The gate pattern of the first reset transistor T1 exposes the sixth pattern 212b, meaning that a conductive region exists between the first and second channel regions of the active layer pattern 212 of the first reset transistor T1.

[0144] The above design of the active layer pattern 212 and the gate pattern of the first reset transistor T1 is equivalent to designing the first reset transistor T1 as a dual-gate transistor. For example, in some examples, such as Figure 12As shown, the first reset transistor T1 is a dual-gate transistor, comprising a third sub-transistor T11 and a fourth sub-transistor T12. The control electrode of the third sub-transistor T11 is electrically connected to the first scanning signal line GL1, the first electrode of the third sub-transistor T11 is electrically connected to the second initial signal line Vinit2, and the second electrode of the third sub-transistor T11 is electrically connected to the first electrode of the fourth sub-transistor T12. The control electrode of the fourth sub-transistor T12 is electrically connected to the first scanning signal line GL1, and the second electrode of the fourth sub-transistor T12 is electrically connected to the control electrode of the drive transistor DTFT. It can be understood that the control electrode of the first reset transistor T1 is the control electrode of the third sub-transistor T11 and the fourth sub-transistor T12, the first electrode of the first reset transistor T1 is the first electrode of the third sub-transistor T11, and the second electrode of the first reset transistor T1 is the second electrode of the fourth sub-transistor T12.

[0145] It can be understood that the part where the first scanning signal line GL1 overlaps with the fifth pattern 212a forms the gate of the third sub-transistor T11, and the part where the first scanning signal line GL1 overlaps with the seventh pattern 212c forms the gate of the fourth sub-transistor T12. The first scanning signal line GL1 provides the first scanning signal Scan1 to the first reset transistor T1, which can also be called a reset signal.

[0146] In some embodiments, see again Figure 11 The active layer pattern 213 of the compensation transistor T2 includes a first channel region, a second channel region, and a conductive region. The first channel region is the portion of the eighth pattern 213a of the compensation transistor T2 that overlaps with the gate pattern of the compensation transistor T2, and the second channel region is the portion of the ninth pattern 213b of the compensation transistor T2 that overlaps with the gate pattern of the compensation transistor T2. The portion of the active layer pattern 213 of the compensation transistor T2 other than the first and second channel regions is a conductive region. The gate pattern of the compensation transistor T2 exposes the location where the eighth pattern 213a and the ninth pattern 213b connect, i.e., a conductive region exists between the first and second channel regions of the active layer pattern 213 of the compensation transistor T2.

[0147] The above design of the active layer pattern 213 and the gate pattern of the compensation transistor T2 is equivalent to designing the compensation transistor T2 as a dual-gate transistor. For example, Figure 12As shown, the compensation transistor T2 is a dual-gate transistor, comprising a fifth sub-transistor T21 and a sixth sub-transistor T22. The control electrode of the fifth sub-transistor T21 is electrically connected to the second scan signal line GL2, the first electrode of the fifth sub-transistor T21 is electrically connected to the second electrode of the drive transistor DTFT, and the second electrode of the fifth sub-transistor T21 is electrically connected to the first electrode of the sixth sub-transistor T22. The control electrode of the sixth sub-transistor T22 is electrically connected to the second scan signal line GL2, and the second electrode of the sixth sub-transistor T22 is electrically connected to the control electrode of the drive transistor DTFT. It can be understood that the control electrode of the compensation transistor T2 is the control electrode of the fourth sub-transistor T12 and the sixth sub-transistor T22, the first electrode of the compensation transistor T2 is the first electrode of the fifth sub-transistor T21, and the second electrode of the compensation transistor T2 is the second electrode of the sixth sub-transistor T22.

[0148] It can be understood that the part where the second scan signal line GL2 overlaps with the eighth pattern 213a forms the gate of the fifth sub-transistor T21, and the part where the second scan signal line GL2 overlaps with the ninth pattern 213b forms the gate of the sixth sub-transistor T22. The second scan signal line GL2 provides the second scan signal Scan2 to the compensation transistor T2.

[0149] In some embodiments, as Figure 16 As shown, the second gate conductive layer 205 further includes a plurality of first initial signal lines Vinit1 and a plurality of second initial signal lines Vinit2. The first initial signal line Vinit1 overlaps with the sixth pattern 212b of the first reset transistor T1, and the second initial signal line Vinit2 overlaps with the eighth pattern 213a and the ninth pattern 213b at the connection position.

[0150] The orthographic projection of the first initial signal line Vinit1 on the substrate 1 covers the orthographic projection of the sixth pattern 212 b on the substrate 1 , which can prevent the first reset transistor T1 from being affected by other signals and causing signal jumps.

[0151] like Figure 14 and Figure 16 As shown, the second initial signal line Vinit2 includes a main portion V1 and multiple first shielding patterns V2 and multiple second shielding patterns V3 connected to the main portion. A first shielding pattern V2 overlaps with the eighth pattern 213a and the ninth pattern 213b of a compensation transistor T2 where they connect. The first shielding pattern V2 prevents the compensation transistor T2 from being affected by other signals and causing signal jumps. The second shielding pattern V3 is used to protect the third conductive pattern M3 from interference from the data signal Data. The third conductive pattern M3 is described below and is not further elaborated here.

[0152] In some embodiments, as Figure 7 and Figure 12 As shown, the pixel driving circuit 20 further includes a writing transistor T4, a second reset transistor T7, a first light emission control transistor T5 and a second light emission control transistor T6. The details are as described above and will not be repeated here.

[0153] See again Figure 16 The semiconductor layer 201 further includes an active layer pattern 214 of the write transistor T4, an active layer pattern 217 of the second reset transistor T7, an active layer pattern 215 of the first emission control transistor T5, and an active layer pattern 216 of the second emission control transistor T6. The first gate conductive layer 203 further includes a plurality of emission control signal lines EM and a plurality of third scan signal lines GL3. The second initial signal line Vinit2 overlaps with the active layer pattern 214 of the write transistor T4, the third scan signal line GL3 overlaps with the active layer pattern 217 of the second reset transistor T7, and the emission control signal line EM overlaps with the active layer pattern 215 of the first emission control transistor T5 and the active layer pattern 216 of the second emission control transistor T6.

[0154] A portion of the second initial signal line Vinit2 overlapping with the active layer pattern 214 of the write transistor T4 forms the gate of the write transistor T4, a portion of the third scan signal line GL3 overlapping with the active layer pattern 217 of the second reset transistor T7 forms the gate of the second reset transistor T7, a portion of the light-emitting control signal line EM overlapping with the active layer pattern 215 of the first light-emitting control transistor T5 forms the gate of the first light-emitting control transistor T5, and a portion of the light-emitting control signal line EM overlapping with the active layer pattern 216 of the second light-emitting control transistor T6 forms the gate of the second light-emitting control transistor T6.

[0155] It should be noted that if Figure 15 and Figure 16 As shown, the first scan signal line GL1 electrically connected to the first reset transistor T1 in the current row of pixel driving circuits 20 actually multiplexes the third scan signal line GL3 of the previous row of pixel driving circuits 20. The first scan signal line GL1 transmits the third scan signal Scan3 of the previous row of pixel driving circuits 20 and uses it as the first scan signal Scan1 of the current row of pixel driving circuits 20, which can also be called the reset signal of the current row of pixel driving circuits 20. The third scan signal Scan3 transmitted by the third scan signal line GL3 serves as the first scan signal Scan1 of the next row of pixel driving circuits 20, that is, the reset signal.

[0156] In some embodiments, see again Figure 12 The pixel driving circuit 20 further includes a capacitor Cst, the specific contents of which are as described above and will not be repeated here.

[0157] like Figure 16As shown, the first gate conductive layer 203 also includes a first plate Cst1 of a capacitor Cst, which serves as a gate pattern 231 of the driving transistor DTFT. The second gate conductive layer 205 also includes a second plate Cst2 of the capacitor Cst, which serves as a constant voltage pattern 251.

[0158] The overlapping portion of the first electrode plate Cst1 of the capacitor Cst and the first gate conductive layer 203 forms the driving transistor DTFT, that is, the first electrode plate Cst1 of the capacitor Cst also serves as the gate of the driving transistor DTFT.

[0159] The second plate Cst2 of the capacitor Cst and the first plate Cst1 of the capacitor Cst in the first gate conductive layer 203 together form the capacitor Cst.

[0160] like Figure 16 As shown, the second plate Cst2 of the capacitor Cst is provided with a first via hole H1 to expose a portion of the first gate conductive layer 203 corresponding to the driving transistor DTFT.

[0161] like Figure 17 and Figure 18 As shown, an interlayer dielectric layer 206 (not shown in the figure) is provided on the side of the second gate conductive layer 205 away from the substrate 1, and a plurality of vias are provided on the interlayer dielectric layer 206, namely the second via H2 to the eleventh via H11. The functions of the second via H2 to the eleventh via H11 are as follows and are not repeated here. Among them, the sixth via H6 penetrates the interlayer dielectric layer 206 and the second gate insulating layer 204, exposing the first gate conductive layer 203, for example, the sixth via H6 penetrates the first gate conductive layer 203, and the other vias except the sixth via H6 penetrate the interlayer dielectric layer 206, the second gate insulating layer 204 and the first insulating layer 202, exposing the semiconductor layer 201, for example, the first via H2 penetrates the semiconductor layer 201.

[0162] In some embodiments, as Figures 19 to 21 As shown, the array substrate 30 further includes a first source-drain metal layer 207 disposed on a side of the second gate conductive layer 205 away from the substrate 1 . The first source-drain metal layer 207 includes a plurality of first power signal lines VDD1 .

[0163] like Figure 21 As shown, the first power signal line VDD1 is electrically connected to the second plate Cst2 of the capacitor Cst through the seventh via H7, and the first power signal line VDD1 is also electrically connected to the first electrode of the first light-emitting control transistor T5 through the eighth via H8, thereby realizing the electrical connection between the capacitor Cst and the first light-emitting control transistor T5.

[0164] The first source-drain metal layer 207 further includes a plurality of conductive patterns, namely, a first conductive pattern M1 , a second conductive pattern M2 , a third conductive pattern M3 , a fifth conductive pattern M5 and a sixth conductive pattern M6 .

[0165] like Figure 21 As shown, one end of the first conductive pattern M1 is electrically connected to the first electrode of the first reset transistor T1 through the second via H2, and the other end is electrically connected to the second initial signal line Vinit2 through the third via H3, thereby realizing the electrical connection between the second initial signal line Vinit2 and the first reset transistor T1.

[0166] The second conductive pattern M2 is electrically connected to the first electrode of the write transistor T4 through the fourth via hole H4.

[0167] One end of the third conductive pattern M3 is electrically connected to the first electrode Cst1 of the capacitor Cst (i.e., the gate of the driving transistor DTFT) through the sixth via H6 and the first via H1, and the other end of the third conductive pattern M3 is electrically connected to the second electrode of the first reset transistor T1 and the second electrode of the compensation transistor T2 through the fifth via H5, thereby electrically connecting the first reset transistor T1, the compensation transistor T2, the capacitor Cst, and the driving transistor DTFT.

[0168] The second conductive pattern M2 is located in the portion of the fourth via hole H4, and a second shielding pattern V3 is arranged between the portion of the third conductive pattern M3 located in the fifth via hole H5. The second shielding pattern V3 and the second initial signal line Vinit2 transmit the same constant voltage signal source, which can protect the third conductive pattern M3 from the influence of the signal transmitted by the second conductive pattern, thereby improving the stability of the potential of the first plate Cst1 of the capacitor Cst connected to the third conductive pattern M3 (equivalent to improving the stability of the potential of the first node N1 in the pixel driving circuit 20, thereby ensuring the stability of the driving current output by the driving transistor DTFT).

[0169] See the following description of the second source / drain metal layer 210 and Figure 27 The second source / drain metal layer 210 includes a data line DL, which is connected to the second conductive pattern M2 through a twelfth via H12. This electrically connects the data line DL to the first electrode of the write transistor T4, thereby transmitting the data signal Data to the write transistor T4. In other words, the second conductive pattern M2 transmits the data signal Data, and the second shielding pattern V3 prevents interference from the data signal Data on the third conductive pattern M3.

[0170] And, see again Figure 21The third conductive pattern M3 does not overlap with the first pattern 211a and the second pattern 211b of the active layer pattern 211. In other words, the "L"-shaped channel design of the driving transistor DTFT ensures that the orthographic projection of the third conductive pattern M3 on the substrate 1 does not overlap with the orthographic projection of the channel of the driving transistor DTFT on the substrate 1. The portion of the film layer where the orthographic projection of the first electrode plate Cst1 of the driving transistor DTFT on the substrate 1 does not overlap with the orthographic projection of the channel of the driving transistor DTFT on the substrate 1 is relatively flat. This relatively flat region is conducive to the formation of the sixth via H6, thereby improving the effectiveness of the connection between the third conductive pattern M3 and the first electrode plate Cst1 through the sixth via H6, enabling the third conductive pattern to be stably connected to the first electrode plate Cst1, while further improving the stability of the driving transistor DTFT.

[0171] The fifth conductive pattern M5 is electrically connected to the second electrode of the second light emission control transistor T6 and the second electrode of the second reset transistor T7 through the ninth via hole H9.

[0172] One end of the sixth conductive pattern M6 is electrically connected to the first initial signal line Vinit1 through the tenth via H10 , and the other end of the sixth conductive pattern M6 is electrically connected to the first electrode of the second reset transistor T7 through the eleventh via H11 , thereby achieving electrical connection between the second reset transistor T7 and the first initial signal line Vinit1 .

[0173] For example, Figure 22 and Figure 23 As shown, a first planarization layer 209 is provided on the side of the first source / drain metal layer 207 away from the substrate 1 (not shown in the figure, specifically as shown in FIG. Figure 4 As shown), a plurality of via holes are provided on the first planarization layer 209, namely the twelfth via hole H12 to the fourteenth via hole H14, and the functions of the second via hole H2 to the eleventh via hole H11 are as follows and are not repeated here.

[0174] It should be noted that Figure 22 The numbers of the twelfth through hole H12 to the fourteenth through hole H14 are not marked. For details, please refer to Figure 23 .

[0175] For example, a passivation layer 208 is further provided between the first source / drain metal layer 207 and the first planarization layer 209. Figure 4 shown.

[0176] In some embodiments, as Figure 24 and Figure 25As shown, the array substrate 30 further includes a second source-drain metal layer 210 disposed on a side of the first source-drain metal layer 207 away from the substrate 1. The second source-drain metal layer 210 includes a plurality of second power signal lines VDD2 and a plurality of data lines DL. A second power signal line VDD2 is connected to a first power signal line VDD1 through a via, and the orthographic projections of the connected second power signal line VDD2 and first power signal line VDD1 on the substrate 1 overlap.

[0177] It can be understood that the second source-drain metal layer 210 is disposed on a side of the first planarization layer 209 away from the substrate 1 .

[0178] The second power signal line VDD2 is electrically connected to the first power signal line VDD1 through the thirteenth via H13, thereby realizing electrical connection among the second power signal line VDD2, the first power signal line VDD1, the first electrode of the first light emitting control transistor T5, and the first electrode plate Cst1 of the capacitor Cst.

[0179] It can be understood that the first power signal line VDD1 and the second power signal line VDD2 form a first voltage signal line VDD for transmitting a first voltage signal.

[0180] The design of overlapping orthographic projections of the connected second power signal line VDD2 and the first power signal line VDD1 on the substrate 1 can reduce resistance and improve the photoelectric performance of the product.

[0181] The data line DL is connected to the second conductive pattern M2 through the twelfth via hole H12 , thereby electrically connecting the data line DL to the first electrode of the write transistor T4 .

[0182] In some embodiments, see again Figure 24 , the second source-drain metal layer 210 further includes a seventh conductive pattern M7.

[0183] The seventh conductive pattern M7 is electrically connected to the fifth conductive pattern M5 through the fourteenth via hole H14 , thereby achieving electrical connection between the seventh conductive pattern M7 and the second light emission control transistor T6 and the second reset transistor T7 .

[0184] In some embodiments, see again Figure 24 and Figure 25 The second source / drain metal layer 210 further includes a plurality of planar patterns M8 , and the planar patterns M8 are connected to the second power signal line VDD2 .

[0185] It can be understood that the planar pattern M8 transmits the same signal as the first voltage signal line VDD.

[0186] The display panel 100 of the present application includes the array substrate 30 as described above. Figure 4 、 Figure 26 and Figure 27 As shown, the display panel 100 further includes an anode layer 301 disposed on the array substrate 30 , and the anode layer 301 includes a plurality of anodes M301 .

[0187] As described above, the array substrate 30 includes the second source-drain metal layer VDD2 , and the second source-drain metal layer VDD2 includes a plurality of planar patterns M8 .

[0188] The plurality of flat patterns M8 are arranged corresponding to the plurality of anodes M301 , and the orthographic projection of one anode M301 on the substrate 1 coincides with the orthographic projection of one flat pattern M8 on the substrate 1 .

[0189] Providing a flat pattern M8 at a position corresponding to the anode M301 can ensure the flatness of the film layer and help improve color deviation.

[0190] See again Figure 4 The display panel 100 further includes a light emitting layer 303 disposed on a side of the anode layer 301 away from the substrate. The light emitting layer 303 includes a plurality of light emitting portions, and the orthographic projection of one light emitting portion on the substrate 1 falls within the orthographic projection of one anode M301 on the substrate 1.

[0191] like Figure 26 and Figure 27 As shown, the light emitting portion is arranged at a position corresponding to the box K, and the orthographic projection of one light emitting portion on the substrate 1 falls within the orthographic projection of one anode M301 on the substrate 1 .

[0192] It should be noted that Figures 8 to 10 、 Figures 14 and 15 、 Figure 17 、 Figures 19 to 22 and Figures 24 to 27 , is a film layer layout diagram arranged in a 2×4 periodic arrangement, which generally displays RGBG or BGRG as one period. Among them, R, G and B are the three primary colors, such as red, green and blue.

[0193] It should be noted that, see again Figure 4 A second planarization layer 220 is provided on the side of the second source / drain metal layer 210 away from the substrate 1. Figure 25 As shown, a plurality of via holes, namely the fifteenth via hole H15 , are provided on the second planarization layer 220 (not shown in the figure).

[0194] The anode M301 is electrically connected to the seventh conductive pattern M7 through the fifteenth via H15, thereby realizing an electrical connection between the anode M301 and the second electrode of the second light-emitting control transistor T6 and the second electrode of the second reset transistor T7, thereby realizing an electrical connection between the pixel driving circuit 20 and the light-emitting device 50, so that the pixel driving circuit 20 can be used to transmit a first voltage signal to the anode M301 of the light-emitting device 50 to drive the light-emitting device 50 to emit light.

[0195] The beneficial effects of the display panel 100 are the same as those of the array substrate 30 provided above, and are not described in detail here.

[0196] The display device includes the display panel 100 described above. The beneficial effects of the display device are the same as those of the array substrate 30 provided above, and are not described in detail here.

[0197] The display device provided by the embodiments of the present application can be any device that displays an image, whether in motion (e.g., video) or fixed (e.g., still image), and whether text or. More specifically, it is expected that the embodiments may be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0198] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. An array substrate, characterized in that: The array substrate comprises a plurality of pixel driving circuits, each of which includes at least a driving transistor; and the array substrate comprises: substrate; a semiconductor layer disposed on one side of the substrate, wherein the semiconductor layer includes an active layer pattern of the driving transistor; a first gate conductive layer disposed on a side of the semiconductor layer away from the substrate, the first gate conductive layer comprising a gate pattern of the driving transistor; The active layer pattern of the driving transistor includes a first pattern and a second pattern connected to each other, the first pattern extends along a first direction, the second pattern extends along a second direction, the first direction and the second direction intersect, and the gate pattern of the driving transistor overlaps with both the first pattern and the second pattern, and exposes a position where the first pattern and the second pattern are connected; The array substrate also includes: a second gate conductive layer arranged on a side of the first gate conductive layer away from the substrate, the second gate conductive layer including a plurality of constant voltage patterns, the plurality of constant voltage patterns being configured to receive a constant voltage signal; wherein the constant voltage pattern overlaps at a position where the first pattern and the second pattern are connected.

2. The array substrate according to claim 1, wherein: The gate pattern of the driving transistor includes a third pattern and a fourth pattern connected to each other; The extension directions of the third pattern and the fourth pattern are both parallel to the first direction, one end of the third pattern along the first direction overlaps with the second pattern, the other end of the third pattern along the first direction is close to one side of the first pattern and is connected to one side of the fourth pattern along the second direction, and the fourth pattern overlaps with the first pattern.

3. The array substrate according to claim 2, wherein: The fourth pattern is farther away from the boundary of one end of the second pattern along the first direction than the third pattern is farther away from the boundary of one end of the second pattern along the first direction.

4. The array substrate according to claim 2, wherein: The size of the portion where the third pattern and the second pattern overlap along the second direction ranges from 5 μm to 30 μm; The size of the portion where the fourth pattern overlaps the first pattern along the first direction ranges from 5 μm to 25 μm.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The first direction and the second direction are perpendicular to each other.

6. The array substrate according to claim 1, wherein: The pixel driving circuit further includes a first reset transistor and a compensation transistor; The semiconductor layer further includes an active layer pattern of the first reset transistor and an active layer pattern of the compensation transistor; The active layer pattern of the first reset transistor includes a fifth pattern, a sixth pattern, and a seventh pattern connected in sequence, and the fifth pattern and the seventh pattern are located on the same side of the sixth pattern along the second direction; the active layer pattern of the compensation transistor includes an eighth pattern and a ninth pattern connected, and the extension directions of the eighth pattern and the ninth pattern intersect; The first gate conductive layer also includes a plurality of first scanning signal lines and a plurality of second scanning signal lines; the first scanning signal line overlaps with the fifth pattern and the seventh pattern, and exposes the sixth pattern; the second scanning signal line overlaps with the eighth pattern and the ninth pattern, and exposes the position where the eighth pattern and the ninth pattern are connected.

7. The array substrate according to claim 6, wherein: The second gate conductive layer further includes a plurality of first initial signal lines and a plurality of second initial signal lines; The first initial signal line overlaps with the sixth pattern; The second initial signal line overlaps with the eighth pattern and the ninth pattern at a location where the second initial signal line is connected.

8. The array substrate according to claim 7, wherein: The pixel driving circuit further includes a write transistor, a second reset transistor, a first light emission control transistor and a second light emission control transistor; The semiconductor layer further includes an active layer pattern of the write transistor, an active layer pattern of the second reset transistor, an active layer pattern of the first light emission control transistor, and an active layer pattern of the second light emission control transistor; The first gate conductive layer further includes a plurality of light emitting control signal lines and a plurality of third scanning signal lines; The second initial signal line overlaps with the active layer pattern of the write transistor; The third scan signal line overlaps with the active layer pattern of the second reset transistor; The light emission control signal line overlaps with the active layer pattern of the first light emission control transistor and the active layer pattern of the second light emission control transistor.

9. The array substrate according to claim 1, wherein: The pixel driving circuit further includes a capacitor; The first gate conductive layer further includes a first plate of the capacitor, and the first plate of the capacitor serves as a gate pattern of the driving transistor; The second gate conductive layer further includes a second plate of the capacitor, and the second plate of the capacitor is the constant voltage pattern.

10. The array substrate according to claim 1, wherein: The array substrate further includes: a first source-drain metal layer provided on a side of the second gate conductive layer away from the substrate, wherein the first source-drain metal layer includes a plurality of first power signal lines; a second source-drain metal layer disposed on a side of the first source-drain metal layer away from the substrate, wherein the second source-drain metal layer includes a plurality of second power signal lines and a plurality of data lines; Wherein, one of the second power signal lines is connected to one of the first power signal lines through a via, and the orthographic projections of the connected second power signal line and the first power signal line on the substrate overlap.

11. The array substrate according to claim 10, wherein: The second source-drain metal layer further includes a plurality of planar patterns, and the planar patterns are connected to the second power signal line.

12. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 11.

13. The display panel according to claim 12, wherein: The display panel further comprises: an anode layer provided on the array substrate, the anode layer comprising a plurality of anodes; The array substrate includes a second source-drain metal layer, the second source-drain metal layer includes a plurality of flat patterns, the plurality of flat patterns are arranged corresponding to the plurality of anodes, and an orthographic projection of one of the anodes on the substrate coincides with an orthographic projection of one of the flat patterns on the substrate; The display panel further includes a light-emitting layer disposed on a side of the anode layer away from the substrate, the light-emitting layer including a plurality of light-emitting portions, and an orthographic projection of one light-emitting portion on the substrate falls within an orthographic projection of one anode on the substrate.

14. A display device, characterized in that: include: The display panel according to claim 12 or 13.

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