A silicon carbide and silicon heterojunction low power IGBT

Abstract

The present invention relates to a silicon carbide and silicon heterojunction low-power IGBT, which includes a collector structure; the collector structure is a multilayer structure, which is sequentially composed of a P+ collector, an N+ buffer layer B located above the P+ collector, an N+ buffer layer A located above the N+ buffer layer B, an N drift region located above the N+ buffer layer A, and a surface structure located above the drift region from the bottom layer to the top layer; the P+ collector and the N+ buffer layer B are both made of silicon material, and the N+ buffer layer A, the N drift region, and the surface structure are all made of silicon carbide material. It is designed that the part above the N+ buffer layer A is made of silicon carbide, and the part below the N+ buffer layer B is made of silicon material, so that the drift region part utilizes the high breakdown voltage characteristics of silicon carbide, the collector part utilizes the high injection efficiency of silicon material, and the buffer layer utilizes the heterojunction interface defects to accelerate carrier recombination, so that the IGBT has ultra-low turn-on and turn-off losses.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductors, and in particular to a silicon carbide and silicon heterojunction low-power IGBT. Background Art

[0002] In recent years, with the continuous development of power electronic systems, higher requirements have been placed on the power devices in the system. Insulated gate bipolar transistors (IGBTs) have become one of the mainstream power switching devices in the medium and high power range due to their advantages such as easy gate drive, high input impedance, high current density, and low saturation voltage drop.

[0003] However, as a bipolar device, its switching speed is slower than that of a unipolar device, which results in additional switching losses, especially the turn-off losses caused by the tail current, which is one of the main sources of losses in IGBT devices. Summary of the invention

[0004] In order to solve the above problems, the present invention proposes a silicon carbide and silicon heterojunction low-power IGBT.

[0005] The technical solution of the present invention:

[0006] A silicon carbide and silicon heterojunction low-power IGBT, comprising a collector structure; the collector structure is a multi-layer structure, which comprises, from the bottom layer to the top layer, a P+ collector, an N+ buffer layer B located above the P+ collector, an N+ buffer layer A located above the N+ buffer layer B, an N drift region located above the N+ buffer layer A, and a surface structure located above the N drift region.

[0007] The P+ collector and the N+ buffer layer B are both made of silicon material, and the N+ buffer layer A, the N drift region, and the surface structure are all made of silicon carbide material.

[0008] The surface structure includes several P-type base regions, all of which are embedded in the top of the N drift region, a JFET region is formed between adjacent P-type base regions, two N+ emitter regions and one P+ emitter region are arranged on each P-type base region, wherein the N+ emitter region is close to the edge of the P-type base region, the P+ emitter region is located between the two N+ emitter regions, and a gate is arranged above each JFET region; the surface structure also includes a top emitter arranged above the JFET region, the gate, the N+ emitter region, and the P+ emitter region.

[0009] The P+ emitter region is deeply diffused, and its depth is less than that of the P-type base region.

[0010] The advantages of the present invention are reasonable design and ingenious conception. The part above the N+ buffer layer A is designed to be made of silicon carbide, and the part of the N+ buffer layer B and below is made of silicon material. In this way, the drift region part utilizes the high breakdown voltage characteristics of silicon carbide, the collector part utilizes the high injection efficiency of silicon material, and the buffer layer utilizes the heterojunction interface defects to accelerate carrier recombination, so that the IGBT has ultra-low turn-on and turn-off losses. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the collector structure.

[0012] In the figure, there are P+ collector 9, N+ buffer layer B 8, N+ buffer layer A 7, N drift region 6, surface structure 5, P base region 51, N+ emitter region 53, P+ emitter region 54, emitter 55, JFET region, and gate 57. DETAILED DESCRIPTION

[0013] As shown in the figure, a silicon carbide and silicon heterojunction low-power IGBT includes a collector structure; the collector structure is a multi-layer structure, which includes, from the bottom layer to the top layer, a P+ collector 9, an N+ buffer layer B 8 located above the P+ collector 9, an N+ buffer layer A 7 located above the N+ buffer layer B 8, an N drift region 6 located above the N+ buffer layer A 7, and a surface structure 5 located above the N drift region 6; the P+ collector 9 and the N+ buffer layer B 8 are all made of silicon material, and the N+ buffer layer A 7, the N drift region 6, and the surface structure 5 are all made of silicon carbide material.

[0014] The surface structure 5 includes a plurality of P-type base regions 51, all of which are embedded in the top of the N drift region 6, and a JFET region 56 is formed between adjacent P-type base regions 51. Two N+ emitter regions 53 and one P+ emitter region 54 are arranged on each P-type base region 51, wherein the N+ emitter region 53 is close to the edge of the P-type base region 51, and the P+ emitter region 54 is located between the two N+ emitter regions 53. A gate 57 is arranged above each JFET region 56; the surface structure 5 also includes a top emitter 55 arranged above the JFET region 56, the gate 57, the N+ emitter region 53, and the P+ emitter region 54; the P+ emitter region 54 is deeply diffused, and its depth is less than the P-type base region 51.

[0015] The technical elements described in this specification or drawings are technically useful alone or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the technology exemplified in this specification or drawings achieves multiple purposes at the same time, and achieving one of the purposes itself has technical usefulness.

Claims

1. A silicon carbide and silicon heterojunction low power IGBT, comprising a collector structure; characterized in that: The collector structure is a multi-layer structure, which includes, from the bottom layer to the top layer, a P+ collector, an N+ buffer layer B located above the P+ collector, an N+ buffer layer A located above the N+ buffer layer B, an N drift region located above the N+ buffer layer A, and a surface structure located above the N drift region; The P+ collector and N+ buffer layer B are made of silicon material, and the N+ buffer layer A, N drift region and surface structure are made of silicon carbide material; The surface structure includes a plurality of P-type base regions, all of which are embedded on the top of the N-drift region, a JFET region is formed between adjacent P-type base regions, two N+ emitter regions and one P+ emitter region are arranged on each P-type base region, wherein the N+ emitter region is close to the edge of the P-type base region, the P+ emitter region is located between the two N+ emitter regions, and a gate is arranged above each JFET region; the surface structure also includes a top emitter arranged above the JFET region, the gate, the N+ emitter region, and the P+ emitter region; The P+ emitter region is deeply diffused, and its depth is less than that of the P-type base region.

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