Flip-chip light emitting diode chip and method of manufacturing the same

Abstract

The application provides a flip light-emitting diode chip and a preparation method thereof, and relates to the chip technical field. The light-emitting diode chip comprises, from bottom to top, a substrate, an epitaxial layer, a current blocking layer, a current spreading layer, a first conductive metal layer, a DBR reflection layer, a second conductive metal layer, an insulating protective layer and a bonding metal layer. The first conductive metal layer comprises a first N-type conductive metal and a first P-type conductive metal. In a single light-emitting diode chip, the quantity ratio of the first N-type conductive metal to the first P-type conductive metal is 1:2-1:30. The application can solve the technical problem that the first N-type conductive metal and the first P-type conductive metal have a large spacing, which leads to difficult and uneven current diffusion. In the case of large voltage input in a large lightning surge test, the current cannot rapidly spread, leading to chip burnout failure.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a flip-chip light-emitting diode and its fabrication method. Background Technology

[0002] Light-emitting diodes (LEDs) are widely used in various lighting fields due to their advantages such as energy saving, high brightness, high durability, long life, and lightweight.

[0003] Among them, flip-chip LEDs emit light from the sapphire surface. The refractive index of sapphire is lower than that of gallium nitride, which reduces some of the total internal reflection of light. In addition, the addition of a reflector on the chip surface of the flip-chip LED increases the chip brightness. Flip-chip LEDs have a steadily increasing market share due to their high external quantum efficiency, and their applications are gradually maturing.

[0004] However, as Figure 1 As shown, in existing flip-chip LED fabrication, the ratio of P-type to N-type conductive metal in the first conductive metal layer is relatively small, and the diameters of individual first N-type conductive metal 11 and first P-type conductive metal 12 are relatively large, with a large gap between the first N-type conductive metal 11 and the first P-type conductive metal 12. This leads to difficulties and uneven current diffusion. Under large lightning surge tests and high voltage input, the current cannot diffuse rapidly, causing the chip to burn out and fail. A diagram of chip burnout using existing technology is shown below. Figure 2 . Summary of the Invention

[0005] Based on this, the purpose of the present invention is to provide a flip-chip light-emitting diode and its fabrication method, which aims to solve the technical problems described in the background art.

[0006] One aspect of the present invention is to provide a flip-chip light-emitting diode, wherein the light-emitting diode chip comprises, from bottom to top, a substrate, an epitaxial layer, a current blocking layer, a current spreading layer, a first conductive metal layer, a DBR reflective layer, a second conductive metal layer, an insulating protective layer, and a bonding metal layer;

[0007] The first conductive metal layer includes a first N-type conductive metal and a first P-type conductive metal. In a single light-emitting diode chip, the ratio of the first N-type conductive metal to the first P-type conductive metal is 1:2 to 1:30.

[0008] According to one aspect of the above technical solution, the diameters of the first N-type conductive metal and the first P-type conductive metal are 3-40 μm.

[0009] According to one aspect of the above technical solution, the lateral and longitudinal center distance between the first N-type conductive metal and the first P-type conductive metal is 30-200μm.

[0010] According to an aspect of the above technical solution, the total area of the first conductive metal layer is 1%-15% of the area of the light emitting diode chip.

[0011] According to an aspect of the above technical solution,

[0012] The total area of the first conductive metal layer is 2.85% of the area of the light emitting diode chip.

[0013] The number ratio of the first N-type conductive metal to the first P-type conductive metal is 1:4.5.

[0014] The diameter of the first N-type conductive metal and the first P-type conductive metal is 15μm.

[0015] The lateral center distance of the first N-type conductive metal and the first P-type conductive metal is 35-80μm.

[0016] The longitudinal center distance of the first N-type conductive metal and the first P-type conductive metal is 35-80μm.

[0017] According to an aspect of the above technical solution,

[0018] The total area of the first conductive metal layer is 2% of the area of the light emitting diode chip.

[0019] The number ratio of the first N-type conductive metal to the first P-type conductive metal is 1:8.

[0020] The diameter of the first N-type conductive metal and the first P-type conductive metal is 10μm.

[0021] The lateral center distance and the longitudinal center distance of the first N-type conductive metal and the first P-type conductive metal are both 51μm.

[0022] According to an aspect of the above technical solution,

[0023] The total area of the first conductive metal layer is 1% of the area of the light emitting diode chip.

[0024] The number ratio of the first N-type conductive metal to the first P-type conductive metal is 1:25.

[0025] The diameter of the first N-type conductive metal is 3μm, and the diameter of the first P-type conductive metal 262 is 40μm.

[0026] The lateral center distance of the first N-type conductive metal and the first P-type conductive metal is 62μm, and the longitudinal center distance of the first N-type conductive metal and the first P-type conductive metal is 31μm.

[0027] Another aspect of the present application provides a method for preparing a flip-chip light emitting diode chip, for manufacturing the flip-chip light emitting diode chip as described in the above technical solution, the method comprising:

[0028] providing a substrate, and growing an epitaxial layer on the substrate;

[0029] forming a pattern on the surface of the epitaxial layer by photolithography, etching the epitaxial layer by inductively coupled plasma to expose a Mesa step, and removing the surface photoresist;

[0030] depositing a current blocking material on the surface of the epitaxial layer, forming a pattern on the surface of the current blocking material by photolithography, performing BOE etching, and forming a current blocking layer from the remaining current blocking material after etching, and then removing the surface photoresist;

[0031] then sputtering a current spreading material, forming a pattern on the surface of the current spreading material by photolithography, then performing etching of the current spreading material, forming a current spreading layer from the remaining current spreading material after etching, and then removing the surface photoresist;

[0032] then coating a negative photoresist on the surface, forming a pattern by photolithography, evaporating a first conductive metal layer, peeling off the excess metal, removing the photoresist, and forming a first N-type conductive metal and a first P-type conductive metal;

[0033] then evaporating a DBR reflective layer, forming a pattern by photolithography, and forming N-type DBR vias and P-type DBR vias by inductively coupled plasma etching;

[0034] then coating a negative photoresist on the surface, forming a pattern by photolithography, evaporating a second conductive metal layer, peeling off the excess metal, removing the photoresist, and forming a second N-type conductive metal and a second P-type conductive metal;

[0035] then depositing an insulating protective layer, forming a pattern by photolithography, and forming N-type insulating protective layer vias and P-type insulating protective layer vias by inductively coupled plasma etching;

[0036] then coating a negative photoresist on the surface, forming a pattern by photolithography, evaporating a bonding metal layer, peeling off the excess metal, removing the photoresist, and forming an N-type bonding metal and a P-type bonding metal.

[0037] According to an aspect of the above technical solution, in the method:

[0038] the N-type bonding metal is electrically connected to the second N-type conductive metal through the N-type insulating protective layer vias, and the P-type bonding metal is electrically connected to the second P-type conductive metal through the P-type insulating protective layer vias.

[0039] According to an aspect of the above technical solution, in the method:

[0040] The second N-type conductive metal forms an electrical connection with the first N-type conductive metal through the N-type DBR through hole, and the second P-type conductive metal forms an electrical connection with the first P-type conductive metal through the P-type DBR through hole.

[0041] Compared with the prior art, the flip light emitting diode chip and the preparation method thereof have the beneficial effects that by increasing the proportion of the number of the first P-type conductive metal layer and the first N-type conductive metal layer in a single light emitting diode chip, the center distance between the first P-type conductive metal layer and the first N-type metal layer can be shortened without changing the preparation cost and photoelectric performance of the existing flip light emitting diode chip, the migration distance of holes in the P-type semiconductor is shortened, the lateral diffusion ability of the current is improved, the chip anti-lightning surge ability is greatly improved, and the reliability of the chip is enhanced. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a top view of a first conductive metal layer of a traditional flip light emitting diode chip;

[0043] Figure 2 is a burnout diagram of a lightning surge test of a traditional flip light emitting diode chip;

[0044] Figure 3 is a structure schematic diagram of a flip light emitting diode chip in embodiments 1-4 of the present application;

[0045] Figure 4 is a top view of a first conductive metal layer of a flip light emitting diode chip in embodiment 1 of the present application;

[0046] Figure 5 is a top view of a first conductive metal layer of a flip light emitting diode chip in embodiment 2 of the present application;

[0047] Figure 6 is a top view of a first conductive metal layer of a flip light emitting diode chip in embodiment 3 of the present application;

[0048] MARK NO.

[0049] Substrate 21, epitaxial layer 22, Mesa step 23, current blocking layer 24, current spreading layer 25, first conductive metal layer 26, first N-type conductive metal 261, first P-type conductive metal 262, DBR reflection layer 27, second conductive metal layer 28, second N-type conductive metal 281, second P-type conductive metal 282, insulating protective layer 29, bonding metal layer 30, N-type bonding metal 301, P-type bonding metal 302;

[0050] The following detailed description will further explain the present application with reference to the above mentioned drawings. DETAILED DESCRIPTION

[0051] For the purpose of promoting an understanding of the present application, the present application will be described with reference to the drawings. The present application is illustrated by a number of embodiments. However, the present application can be realized in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Embodiment 1

[0052] Embodiment 1

[0053] Please refer to Figure 3 and Figure 4 The first embodiment of the present application provides a flip-chip light emitting diode, in the embodiment:

[0054] The light emitting diode chip comprises, in order from bottom to top, a substrate 21, an epitaxial layer 22, a current blocking layer 24, a Mesa step 23, a current spreading layer 25, a first conductive metal layer 26, a DBR reflective layer 27, a second conductive metal layer 28, an insulating protective layer 29, and a bonding metal layer 30.

[0055] The second conductive metal layer 28 comprises a second N-type conductive metal 281 and a second P-type conductive metal 282, and the bonding metal layer 30 comprises an N-type bonding metal 301 and a P-type bonding metal 302.

[0056] In an optional embodiment, the substrate 21 comprises, but is not limited to, Al2O3, GaN, Si, SiC, GaAs; the epitaxial layer 22 comprises, in order from bottom to top, a buffer layer, an N-type semiconductor layer, an active layer, and a P-type semiconductor layer; wherein the epitaxial layer 22 is etched by inductively coupled plasma to expose the Mesa step 23; the current blocking layer 24 comprises, but is not limited to, SiO2, Ti3O5, SiN; the current spreading layer 25 comprises, but is not limited to, ITO (indium tin oxide), Ag; the first conductive metal layer 26 comprises, but is not limited to, Cr, Al, Ni, Ti, Pt, Au, and a stack of these metals; the DBR reflective layer 27 comprises, but is not limited to, a stack of SiO2 and Ti3O5, and a stack of SiO2 and SiN; the second conductive metal layer 28 comprises, but is not limited to, Cr, Al, Ni, Ti, Pt, Au, and a stack of these metals; the insulating protective layer 29 comprises, but is not limited to, SiO2, Ti3O5, SiN; and the bonding metal layer 30 comprises, but is not limited to, Cr, Al, Ni, Ti, Pt, Au, and a stack of these metals.

[0057] The first conductive metal layer 26 includes two first N-type conductive metals 261. Within a single light-emitting diode chip, the ratio of the first N-type conductive metals 261 to the first P-type conductive metals 262 is 1:2 to 1:30. That is, the first P-type conductive metals 262 are more than twice the number of the first N-type conductive metals 261 (only integer multiples are allowed), and the number of first P-type conductive metals 262 is greater than the number of first N-type conductive metals 261.

[0058] Furthermore, the diameters of the first N-type conductive metal 261 and the first P-type conductive metal 262 are 3-40 μm, the horizontal and vertical center distances of the first N-type conductive metal 261 and the first P-type conductive metal 262 are 30-200 μm, and the total area of ​​the first conductive metal layer 26 is 1%-15% of the area of ​​the light-emitting diode chip.

[0059] As an example, and not a limitation, in this embodiment, the total area of ​​the first conductive metal layer 26 is 2.85% of the area of ​​the light-emitting diode chip;

[0060] The ratio of the number of the first N-type conductive metal 261 to the number of the first P-type conductive metal 262 is 1:4.5. It should be understood that the number of the first N-type conductive metal 261 is only an integer, and there is no case where the number of the first N-type conductive metal 261 is not an integer. Therefore, the above-mentioned ratio of the number of the first N-type conductive metal 261 to the number of the first P-type conductive metal 262 is 1:4.5, which can be rewritten as 2:9.

[0061] The diameters of the first N-type conductive metal 261 and the first P-type conductive metal 262 are both 15 μm, meaning that the diameters of the first N-type conductive metal 261 and the first P-type conductive metal 262 can be equal.

[0062] The lateral center-to-center distance and longitudinal center-to-center distance between the first N-type conductive metal 261 and the first P-type conductive metal 262 are both 35-80 μm.

[0063] like Figure 4 As shown, the lateral center-to-center distance between the first N-type conductive metal 261 and the first P-type conductive metal 262 is denoted as X, and the longitudinal center-to-center distance between them is denoted as Y. The values ​​of X and Y can be equal or unequal. That is, the changes in the quantity and spacing of the first N-type conductive metal 261 and the first P-type conductive metal 262 affect their arrangement and distribution, thus allowing for various arrangement patterns.

[0064] Compared with the prior art, the flip light-emitting diode chip has the beneficial effects that: by increasing the number ratio of the first N-type conductive metal 261 and the first P-type conductive metal 262, reducing the diameter of the single first N-type conductive metal 261 and the first P-type conductive metal 262, and reducing the lateral and longitudinal center distance of the first N-type conductive metal 261 and the first P-type conductive metal 262, the current diffusion of the flip light-emitting diode chip is more simple and uniform; in the case of large lightning surge test and large voltage input, the current can rapidly diffuse, thereby improving the overall reliability of the chip; and the application aims to increase the lightning surge resistance of the flip light-emitting diode chip without increasing the existing cost and changing the existing photoelectric performance of the chip.

[0065] Embodiment two

[0066] Please combine Figure 3 With Figure 5 The second embodiment of the application provides a flip light-emitting diode chip, the flip light-emitting diode chip shown in the embodiment is basically the same as the flip light-emitting diode chip shown in the first embodiment, and the difference lies in that:

[0067] In the embodiment, the total area of the first conductive metal layer 26 is 2% of the area of the light-emitting diode chip;

[0068] The number ratio of the first N-type conductive metal 261 and the first P-type conductive metal 262 is 1:8;

[0069] The diameter of the first N-type conductive metal 261 and the first P-type conductive metal 262 is 10 μm;

[0070] The lateral and longitudinal center distance of the first N-type conductive metal 261 and the first P-type conductive metal 262 is 51 μm.

[0071] In the embodiment, by increasing the number ratio of the first N-type conductive metal 261 and the first P-type conductive metal 262, the number of the first P-type conductive metal 262 is further increased, the lightning surge resistance of the flip light-emitting diode chip is improved, thereby improving the overall reliability of the chip, and the lightning surge resistance of the flip light-emitting diode chip can be effectively increased without increasing the existing cost and changing the existing photoelectric performance of the chip.

[0072] Embodiment three

[0073] Please combine Figure 3 With Figure 6The third embodiment of the present application provides a flip light emitting diode chip, the flip light emitting diode chip shown in the embodiment is basically consistent with the structure of the flip light emitting diode chip shown in the first and second embodiments, and the difference lies in that:

[0074] In the embodiment, the total area of the first conductive metal layer 26 is 1% of the area of the flip light emitting diode chip;

[0075] The number ratio of the first N-type conductive metal 261 to the first P-type conductive metal 262 is 1:25;

[0076] The diameter of the first N-type conductive metal 261 is 40 μm, and the diameter of the first P-type conductive metal 262 is 3 μm;

[0077] The lateral center distance between the first N-type conductive metal 261 and the first P-type conductive metal 262 is 62 μm, and the longitudinal center distance between the first N-type conductive metal 261 and the first P-type conductive metal 262 is 31 μm.

[0078] In the embodiment, by increasing the number ratio of the first N-type conductive metal 261 to the first P-type conductive metal 262, the number of the first P-type conductive metal 262 is further increased, the lightning surge capacity of the flip light emitting diode chip is improved, and the overall reliability of the chip is improved, so that the lightning surge capacity of the flip light emitting diode chip can be effectively increased without increasing the existing cost and without changing the existing photoelectric performance of the chip.

[0079] In some embodiments of the present application, as shown in Table 1, the lightning surge capacity of the conventional flip light emitting diode chip and the flip light emitting diode chip using the embodiments of the present application is compared:

[0080] Table 1

[0081] The number ratio of the first N-type conductive metal to the first P-type conductive metal Lightning static surge resistance (unit: V) 1:1.5 (prior art) 55V 1:2.5 (part of embodiments of the present application) 65V 1:4.5 (part of embodiments of the present application) 80V 1:8 (part of embodiments of the present application) 110V 1:15 (part of embodiments of the present application) 150V 1:25 (part of embodiments of the present application) 190V 1:30 (part of embodiments of the present application) 195V

[0082] In summary, by using the flip light emitting diode chip of the above embodiments of the present application, the number ratio of the first N-type conductive metal to the first P-type conductive metal is increased, the diameter of the single first N-type conductive metal and the first P-type conductive metal is reduced, and the lateral and longitudinal distances between the first N-type conductive metal and the first P-type conductive metal are reduced, so that the current diffusion of the flip light emitting diode chip is more simple and uniform; in the case of large lightning surge test and large voltage input, the current can rapidly diffuse, thereby improving the overall reliability of the chip; the present application aims to increase the lightning surge capacity of the flip light emitting diode chip without increasing the existing cost and without changing the existing photoelectric performance of the chip.

[0083] Embodiment four

[0084] The fourth embodiment of the present application provides a method for preparing a flip-chip light emitting diode chip. The method is used for preparing the flip-chip light emitting diode chip described in the above embodiments. The method comprises steps S10-S60:

[0085] Step S10, providing a substrate, and growing an epitaxial layer on the substrate;

[0086] Step S20, forming a pattern on the surface of the epitaxial layer by photolithography, etching the epitaxial layer by inductively coupled plasma, exposing a Mesa step, and removing the surface photoresist;

[0087] Step S30, depositing a current blocking material on the surface of the epitaxial layer, forming a pattern on the surface of the current blocking material by photolithography, performing BOE etching, forming a current blocking layer by the remaining current blocking material after etching, and then removing the surface photoresist;

[0088] Step S40, then sputtering a current spreading material, forming a pattern on the surface of the current spreading material by photolithography, then performing etching of the current spreading material, forming a current spreading layer by the remaining current spreading material after etching, and then removing the surface photoresist;

[0089] Step S50, then coating a negative photoresist on the surface, forming a pattern by photolithography, evaporating a first conductive metal layer, peeling off the excess metal, removing the photoresist, and forming a first N-type conductive metal and a first P-type conductive metal;

[0090] Step S20, then evaporating a DBR reflective layer, forming a pattern by photolithography, and forming N-type DBR through holes and P-type DBR through holes by inductively coupled plasma etching;

[0091] Step S20, then coating a negative photoresist on the surface, forming a pattern by photolithography, evaporating a second conductive metal layer, peeling off the excess metal, removing the photoresist, and forming a second N-type conductive metal and a second P-type conductive metal;

[0092] Step S20, then depositing an insulating protective layer, forming a pattern by photolithography, and forming N-type insulating protective layer through holes and P-type insulating protective layer through holes by inductively coupled plasma etching;

[0093] Step S20, then coating a negative photoresist on the surface, forming a pattern by photolithography, evaporating a bonding metal layer, peeling off the excess metal, removing the photoresist, and forming an N-type bonding metal and a P-type bonding metal.

[0094] In the method described in the embodiment, specifically:

[0095] The N-type bonding metal is electrically connected with the second N-type conductive metal through the N-type insulating protective layer through hole, and the P-type bonding metal is electrically connected with the second P-type conductive metal through the P-type insulating protective layer through hole.

[0096] Further, in the method:

[0097] The second N-type conductive metal is electrically connected with the first N-type conductive metal through the N-type DBR through hole, and the second P-type conductive metal is electrically connected with the first P-type conductive metal through the P-type DBR through hole.

[0098] Specifically, in the embodiment, the manufacturing steps of the flip-chip light emitting diode chip include:

[0099] First, an epitaxial layer is grown on a substrate;

[0100] Then, a pattern is formed on the surface of the epitaxial layer by photolithography, and then ICP (inductively coupled plasma) etching is performed to expose the Mesa step, and then the surface photoresist is removed;

[0101] Then, SiO2 is deposited, and then a pattern is formed on the surface of the SiO2 by photolithography, and then BOE etching is performed, and the remaining SiO2 after etching is used as a current blocking layer, and then the surface photoresist is removed;

[0102] Then, ITO (indium tin oxide) is sputtered, and then a pattern is formed on the surface of the ITO by photolithography, and then ITO etching is performed, and the remaining ITO after etching is used as a current spreading layer, and then the surface photoresist is removed;

[0103] Then, a negative photoresist is coated on the surface, and then a pattern is formed by photolithography, and then a first conductive metal layer is evaporated, and then the excess metal is stripped off, and the photoresist is removed, to form a first N-type conductive metal and a first P-type conductive metal;

[0104] Then, a DBR reflective layer is evaporated, and then a pattern is formed by photolithography, and then ICP etching is performed to form an N-type DBR through hole and a P-type DBR through hole;

[0105] Then, a negative photoresist is coated on the surface, and then a pattern is formed by photolithography, and then a second conductive metal layer is evaporated, and then the excess metal is stripped off, and the photoresist is removed, to form a second N-type conductive metal and a second P-type conductive metal;

[0106] Then, an insulating protective layer is deposited, and then a pattern is formed by photolithography, and then ICP etching is performed to form an N-type insulating protective layer through hole and a P-type insulating protective layer through hole;

[0107] Then the surface is coated with a negative photoresist, then photoetching is performed to form a pattern, then a bonding metal layer is evaporated, then the excess metal is stripped off, and the photoresist is removed, thereby forming N-type bonding metal and P-type bonding metal.

[0108] In summary, by increasing the quantity ratio of the first N-type conductive metal and the first P-type conductive metal, reducing the diameter of the single first N-type conductive metal and the first P-type conductive metal, and reducing the horizontal and vertical spacing of the first N-type conductive metal and the first P-type conductive metal, the current diffusion of the flip-chip light emitting diode chip is more simple and uniform; in the case of large voltage input in a larger lightning surge test, the current can quickly diffuse, thereby improving the overall reliability of the chip; the present application aims to increase the lightning surge resistance of the flip-chip light emitting diode chip without increasing the existing cost and changing the existing chip photoelectric performance.

[0109] In the description of the present specification, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present specification, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner.

[0110] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the present application. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the present application patent should be subject to the appended claims.

Claims

1. A flip-chip light-emitting diode, characterized in that: The light-emitting diode chip comprises, from bottom to top, a substrate, an epitaxial layer, a current blocking layer, a current spreading layer, a first conductive metal layer, a DBR reflective layer, a second conductive metal layer, an insulating protective layer, and a bonding metal layer. The first conductive metal layer includes a first N-type conductive metal and a first P-type conductive metal. In a single light-emitting diode chip, the ratio of the first N-type conductive metal to the first P-type conductive metal is 1:2 to 1:

30. The diameters of the first N-type conductive metal and the first P-type conductive metal are 3-40 μm, the horizontal and vertical center-to-center distances of the first N-type conductive metal and the first P-type conductive metal are 30-200 μm, and the total area of ​​the first conductive metal layer is 1%-15% of the area of ​​the light-emitting diode chip.

2. The flip-chip LED according to claim 1, characterized in that: The total area of ​​the first conductive metal layer is 2.85% of the area of ​​the light-emitting diode chip; The ratio of the first N-type conductive metal to the first P-type conductive metal is 1:4.5; The diameters of the first N-type conductive metal and the first P-type conductive metal are both 15 μm; The lateral center-to-center distance between the first N-type conductive metal and the first P-type conductive metal is 35-80 μm; The longitudinal center-to-center distance between the first N-type conductive metal and the first P-type conductive metal is 35-80 μm.

3. The flip-chip LED according to claim 2, characterized in that: The total area of ​​the first conductive metal layer is 2% of the area of ​​the light-emitting diode chip; The ratio of the first N-type conductive metal to the first P-type conductive metal is 1:8; The diameters of the first N-type conductive metal and the first P-type conductive metal are both 10 μm; The lateral center-to-center distance and the longitudinal center-to-center distance between the first N-type conductive metal and the first P-type conductive metal are both 51 μm.

4. The flip-chip LED according to claim 1, characterized in that: The total area of ​​the first conductive metal layer is 1% of the area of ​​the light-emitting diode chip; The ratio of the first N-type conductive metal to the first P-type conductive metal is 1:25; The diameter of the first N-type conductive metal is 3 μm, and the diameter of the first P-type conductive metal 262 is 40 μm; The lateral center-to-center distance between the first N-type conductive metal and the first P-type conductive metal is 62 μm, and the longitudinal center-to-center distance between the first N-type conductive metal and the first P-type conductive metal is 31 μm.

5. A method for fabricating a flip-chip light-emitting diode, characterized in that, The method for fabricating a flip-chip light-emitting diode according to any one of claims 1-4, the method comprising: A substrate is provided on which an epitaxial layer is grown; Patterns are formed on the surface of the epitaxial layer by photolithography, and the epitaxial layer is etched by inductively coupled plasma to expose the Mesa steps and remove the surface photoresist. A current blocking material is deposited on the surface of the epitaxial layer, a pattern is formed on the surface of the current blocking material by photolithography, BOE etching is performed, the remaining current blocking material after etching forms a current blocking layer, and then the surface photoresist is removed. Next, a current spreading material is sputtered, and then a pattern is formed on the surface of the current spreading material using photolithography. Then, the current spreading material is etched, and the remaining current spreading material after etching forms a current spreading layer. Finally, the surface photoresist is removed. Next, negative photoresist is coated on the surface, a pattern is formed by photolithography, the first conductive metal layer is deposited by evaporation, excess metal is stripped off, and the photoresist is removed to form the first N-type conductive metal and the first P-type conductive metal. Next, the DBR reflective layer is deposited by vapor deposition, the pattern is formed by photolithography, and the N-type DBR via and P-type DBR via are formed by inductively coupled plasma etching. Next, a negative photoresist is coated on the surface, a pattern is formed by photolithography, a second conductive metal layer is deposited by evaporation, excess metal is stripped off, and the photoresist is removed to form a second N-type conductive metal and a second P-type conductive metal. Next, an insulating protective layer is deposited, a pattern is formed by photolithography, and N-type and P-type insulating protective layer vias are formed by inductively coupled plasma etching. Next, negative photoresist is coated on the surface, a pattern is formed by photolithography, a bonding metal layer is deposited by vapor deposition, excess metal is stripped off, and the photoresist is removed to form N-type bonding metal and P-type bonding metal.

6. The method for fabricating a flip-chip light-emitting diode according to claim 5, characterized in that, In the method: The N-type bonding metal is electrically connected to the second N-type conductive metal through the through-hole of the N-type insulating protective layer, and the P-type bonding metal is electrically connected to the second P-type conductive metal through the through-hole of the P-type insulating protective layer.

7. The method for fabricating a flip-chip light-emitting diode according to claim 5, characterized in that, In the method: The second N-type conductive metal is electrically connected to the first N-type conductive metal through the N-type DBR via, and the second P-type conductive metal is electrically connected to the first P-type conductive metal through the P-type DBR via.

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