TLB management method, device, equipment and storage medium

Abstract

The present invention discloses a TLB management method, apparatus, device, and storage medium. The method comprises: when a virtual address is received, comparing its identification field with the identification field of a TLB table entry, the identification field of the TLB table entry including a start identification field and a granularity size field; when a TLB table entry exists containing the virtual address, obtaining a physical address based on the TLB table entry and returning it to a processor; when a TLB miss occurs, after the physical address is returned, merging consecutive page table entries in the processor cache to generate a first TLB table entry; if a second TLB table entry exists in the TLB that is consecutive to the first TLB table entry, merging the two entries into a third TLB table entry; if not, inserting the first TLB table entry into the TLB. The present invention implements TLB management supporting multi-granularity pages. Furthermore, by merging page table entries and TLB entries, the coverage of the TLB is effectively expanded.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a TLB management method, apparatus, device and storage medium. Background Art

[0002] To meet the growing memory demands of applications in the current big data era, hybrid memory, combining DRAM (Dynamic Random Access Memory) and NVM (Non-volatile Memory), is being used to expand available memory. Due to NVM's shortcomings, such as high write latency and limited write times, it's often necessary to store hot pages in DRAM and cold pages in NVM to improve overall system performance.

[0003] To address the problem of processors frequently accessing memory to obtain physical addresses, which leads to reduced system performance, the TLB typically performs virtual-to-physical address translation when the processor needs to obtain a physical address. This process then returns the physical address to the processor, reducing the number of memory accesses required. While hybrid memory expands available memory, it also increases the processing pressure on the TLB (Translation Lookaside Buffer) during virtual-to-physical address translation. Due to the limited number of TLB entries stored in the TLB, the TLB's coverage is limited. As available memory expands, the probability of TLB misses increases, increasing the number of processor memory accesses and degrading system performance. Currently, a common approach is to utilize large page technology within memory to expand TLB coverage. However, when using large page technology within hybrid memory, the management granularity of large page technology conflicts with the page migration granularity of hybrid memory. This results in ineffective page migrations between DRAM and NVM, as well as page fragmentation. When applications use pages of different granularities, managing these pages through the TLB is ineffective.

[0004] In order to solve the problems existing in large page technology, the existing technology usually provides a dedicated TLB for each page granularity, so that the TLB supports the management of multi-granularity pages. However, the existing technology is only applicable to applications with pages of less granularity. When the page granularity of the application is large, it is difficult to maintain a dedicated TLB for each page granularity in the limited TLB space, and the space utilization of the TLB is low. Summary of the Invention

[0005] The present invention provides a TLB management method, apparatus, device, and storage medium. By adding a start identifier field for recording the starting virtual addresses of pages of different granularities and a granularity size field for recording the page granularity in a TLB table entry, the TLB supports the management of multi-granularity pages. This eliminates the need for a dedicated TLB for each page granularity, avoids the need to maintain a dedicated TLB for each page granularity within the limited TLB space, and improves TLB space utilization. Furthermore, when no TLB entry contains the virtual address, after the processor obtains the physical address from memory, the TLB coverage is effectively expanded by merging page table entries and TLB entries.

[0006] In order to solve the above technical problems, a first aspect of an embodiment of the present invention provides a TLB management method, including:

[0007] When receiving a virtual address sent by the processor, compare the identification field of the virtual address with the identification field of a TLB table entry stored in the TLB to determine whether there is a TLB table entry containing the virtual address; wherein the TLB table entry includes at least one page, and the identification field of the TLB table entry includes a start identification field for recording a start virtual address of the page and a granularity size field for recording a page granularity of the page;

[0008] When there is a TLB table entry containing the virtual address, obtaining a physical address having a mapping relationship with the virtual address according to the TLB table entry containing the virtual address, and returning the physical address to the processor;

[0009] When no TLB entry contains the virtual address, after the processor obtains the physical address from the memory, based on a plurality of page table entries pre-stored in the processor cache, merge consecutive page table entries from the plurality of page table entries into consecutive page table entries; and generate a first TLB entry based on the consecutive page table entries;

[0010] Determine whether there is a second TLB table entry continuous with the first TLB table entry in the TLB table entries stored in the TLB; if the second TLB table entry exists, merge the first TLB table entry and the second TLB table entry into a third TLB table entry, and replace the second TLB table entry with the third TLB table entry; if the second TLB table entry does not exist, insert the first TLB table entry into the TLB.

[0011] As a preferred solution, the identification field of the virtual address includes an index field, a high-bit identification field and a virtual address field;

[0012] The identification field of the TLB table entry also includes a high-bit identification field;

[0013] Then, comparing the identification field of the virtual address with the identification field of the TLB entry stored in the TLB specifically includes:

[0014] Determining a TLB group in the TLB according to an index field of the virtual address;

[0015] Comparing the high-order flag field of the virtual address with the high-order flag field of the TLB table entry stored in the TLB group, and determining whether there is a matching TLB table entry in the TLB group whose high-order flag field is the same as the high-order flag field of the virtual address;

[0016] When there is at least one matching TLB table entry in the TLB group, the virtual address range of each matching TLB table entry is obtained according to the start identification field and the granularity size field of each matching TLB table entry; and the virtual address field of the virtual address is compared with the virtual address range of each matching TLB table entry.

[0017] As a preferred solution, the step of merging consecutive page table entries from the plurality of page table entries pre-stored in the processor cache into consecutive page table entries specifically includes:

[0018] Determining whether there are consecutive page table entries in the plurality of page table entries according to physical page frame numbers of the plurality of page table entries pre-stored in the processor cache;

[0019] When there are continuous page table entries in the plurality of page table entries, the continuous page table entries in the plurality of page table entries are merged into continuous page table entries.

[0020] As a preferred solution, the determining whether there is a second TLB entry continuous with the first TLB entry among the TLB entries stored in the TLB; if the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry; and if the second TLB entry does not exist, inserting the first TLB entry into the TLB, specifically includes:

[0021] Obtaining a virtual address range of a TLB entry stored in the TLB according to a start identifier field and a granularity size field of the TLB entry stored in the TLB;

[0022] Obtaining a virtual address range of the first TLB table entry according to the start identifier field and the granularity size field of the first TLB table entry;

[0023] determining, based on a virtual address range of a TLB entry stored in the TLB, the virtual address range of the first TLB entry, a physical page frame number of a TLB entry stored in the TLB, and the physical page frame number of the first TLB entry, whether there is a second TLB entry continuous with the first TLB entry in the TLB entry stored in the TLB;

[0024] If the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry;

[0025] If the second TLB entry does not exist, insert the first TLB entry into the TLB.

[0026] As a preferred solution, the method further comprises:

[0027] When a new page needs to be allocated to the dynamic random access memory, determining, based on virtual address fields of a plurality of page table entries in the processor cache and the virtual address field of the new page that needs to be allocated to the dynamic random access memory, whether there is a first page table entry in the plurality of page table entries that is continuous with the virtual address field of the new page that needs to be allocated to the dynamic random access memory;

[0028] When the first page table entry exists, obtaining the physical page frame number of the first page table entry, and determining whether consecutive physical page frame numbers adjacent to the physical page frame number of the first page table entry are in an unallocated state;

[0029] When the continuous physical page frame numbers are in an unallocated state, allocating the continuous physical page frame numbers to new pages that need to be allocated to the dynamic random access memory, so that the physical page frame numbers of the new pages that need to be allocated to the dynamic random access memory are the continuous physical page frame numbers;

[0030] When a new page needs to be allocated to a non-volatile memory, based on a continuous physical page frame number space preset in the non-volatile memory, according to the reserved physical page frame numbers of multiple page table entries in the dynamic random access memory and the virtual address field of the new page that needs to be allocated to the non-volatile memory, the reserved physical page frame number is allocated to the new page that needs to be allocated to the non-volatile memory, so that the physical page frame number of the new page that needs to be allocated to the non-volatile memory is the reserved physical page frame number; wherein, the continuous physical page frame number space includes multiple continuous physical page frame numbers, and the reserved physical page frame numbers of the multiple page table entries in the dynamic random access memory have a one-to-one correspondence with the multiple continuous physical page frame numbers.

[0031] As a preferred solution, the method further comprises:

[0032] When it is detected that the non-volatile memory migrates its pages to the dynamic random access memory, a new TLB entry is generated according to the migrated page, and the new TLB entry is inserted into the TLB.

[0033] As a preferred solution, the TLB includes a first-level TLB and a second-level TLB, and the first-level TLB is used to store a portion of TLB entries in the second-level TLB;

[0034] Then, determining whether there is a second TLB entry continuous with the first TLB entry in the TLB table entries stored in the TLB; if the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB table entry, and replacing the second TLB entry with the third TLB entry; if the second TLB entry does not exist, inserting the first TLB entry into the TLB, specifically includes:

[0035] Obtaining a virtual address range of a TLB entry stored in the secondary TLB according to a start identifier field and a granularity size field of the TLB entry stored in the secondary TLB;

[0036] Obtaining a virtual address range of the first TLB table entry according to the start identifier field and the granularity size field of the first TLB table entry;

[0037] Determining, based on the virtual address range of the TLB entry stored in the secondary TLB, the virtual address range of the first TLB entry, the physical page frame number of the TLB entry stored in the secondary TLB, and the physical page frame number of the first TLB entry, whether there is a second TLB entry continuous with the first TLB entry in the TLB entry stored in the secondary TLB;

[0038] If the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry;

[0039] If the second TLB entry does not exist, inserting the first TLB entry into the second-level TLB.

[0040] A second aspect of an embodiment of the present invention provides a TLB management device, including:

[0041] a TLB table entry lookup module configured to, upon receiving a virtual address sent by the processor, compare an identification field of the virtual address with an identification field of a TLB table entry stored in the TLB to determine whether there is a TLB table entry containing the virtual address; wherein the TLB table entry includes at least one page, and the identification field of the TLB table entry includes a start identification field for recording a start virtual address of the page and a granularity size field for recording a page granularity of the page;

[0042] a physical address returning module, configured to, when there is a TLB table entry containing the virtual address, obtain a physical address having a mapping relationship with the virtual address according to the TLB table entry corresponding to the virtual address, and return the physical address to the processor;

[0043] a page table entry merging module configured to, when no TLB entry contains the virtual address, merge consecutive page table entries from a plurality of page table entries pre-stored in a processor cache into consecutive page table entries after the processor obtains the physical address from the memory; and generate a first TLB entry based on the consecutive page table entries;

[0044] A TLB table entry merging module is used to determine whether there is a second TLB table entry continuous with the first TLB table entry in the TLB table entries stored in the TLB; if the second TLB table entry exists, merge the first TLB table entry and the second TLB table entry into a third TLB table entry, and replace the second TLB table entry with the third TLB table entry; if the second TLB table entry does not exist, insert the first TLB table entry into the TLB.

[0045] A third aspect of an embodiment of the present invention provides a terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the TLB management method as described in any one of the first aspects when executing the computer program.

[0046] A fourth aspect of an embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the TLB management method as described in any one of the first aspects.

[0047] Compared to the prior art, the beneficial effect of the embodiments of the present invention is that by adding a start identification field for recording the starting virtual address of pages of different granularities and a granularity size field for recording the page granularity in the TLB table entry, the TLB supports the management of multi-granularity pages, eliminating the need to provide a dedicated TLB for each granularity of page, avoiding the need to maintain a dedicated TLB for each page granularity in the limited TLB space, and improving the space utilization of the TLB. In addition, when no TLB table entry contains the virtual address, after the processor obtains the physical address from the memory, the page table entry and TLB table entry merge are performed to effectively expand the coverage of the TLB. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 This is a flow chart of a TLB management method provided by an embodiment of the present invention;

[0049] Figure 2 is a schematic diagram of a small-granularity page provided by an embodiment of the present invention;

[0050] Figure 3 1 is a schematic diagram of the structure of a TLB entry provided by an embodiment of the present invention;

[0051] Figure 4 This is a logical diagram of a TLB lookup process provided by an embodiment of the present invention;

[0052] Figure 5 This is a logical diagram of a TLB entry merging process provided by an embodiment of the present invention;

[0053] Figure 6 Schematic diagram of a page table entry merging process and a TLB entry merging process provided by an embodiment of the present invention;

[0054] Figure 7 It is a structural diagram of a TLB management device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0056] See also Figure 1 The first aspect of the embodiment of the present invention provides a TLB management method, including steps S1 to S4, which are specifically as follows:

[0057] Step S1, when a virtual address sent by a processor is received, comparing an identification field of the virtual address with an identification field of a TLB table entry stored in a TLB to determine whether there is a TLB table entry containing the virtual address; wherein the TLB table entry includes at least one page, and the identification field of the TLB table entry includes a start identification field for recording a start virtual address of the page and a granularity size field for recording a page granularity of the page;

[0058] Step S2: when there is a TLB entry containing the virtual address, obtaining a physical address having a mapping relationship with the virtual address according to the TLB entry containing the virtual address, and returning the physical address to the processor;

[0059] Step S3: when no TLB entry contains the virtual address, after the processor obtains the physical address from the memory, based on a plurality of page table entries pre-stored in the processor cache, merge consecutive page table entries from the plurality of page table entries into a continuous page table entry; and generate a first TLB entry based on the continuous page table entries;

[0060] Step S4, determining whether there is a second TLB entry continuous with the first TLB entry in the TLB table entries stored in the TLB; if the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry; if the second TLB entry does not exist, inserting the first TLB entry into the TLB.

[0061] It should be noted that when performing address translation operations in the TLB, the virtual address usually includes three parts, namely the tag part, the index part and the page offset part. The index part is used to locate different TLB groups in the TLB, and the tag part and the page offset part are used to match the correct TLB table entry in the specified TLB group and obtain the corresponding physical address. However, since the application uses multi-granularity pages, the page offset parts corresponding to different page granularities are different, so the corresponding index parts are also different. For example, if the page granularity is 4KB, the index part corresponds to bits 12-14 of the virtual address. If the page granularity is 2MB, the index part corresponds to bits 21-23 of the virtual address. Therefore, the uncertainty of the page granularity makes it impossible to determine the position of the index part, and thus it is impossible to effectively obtain the physical address that has a mapping relationship with the virtual address, resulting in invalid operation of the TLB.

[0062] In order to uniformly manage pages of different granularities, the embodiment of the present invention determines the TLB management granularity according to the access characteristics of the application. For example, if the application occupies a large amount of memory and has strong access continuity, the TLB management granularity is determined to be 2MB.

[0063] Furthermore, because the small-granularity pages within a large-granularity page have the same index field and high-bit flag field, these small-granularity pages will correspond to the same TLB entry, making it impossible to distinguish the pages in the TLB entry. To address this problem, an embodiment of the present invention introduces two additional flag fields for each TLB entry: a start flag field for recording the starting virtual address of the page and a granularity size field for recording the page granularity of the page. When a virtual address sent by the processor is received, the flag field of the virtual address is compared with the flag field of the TLB entry stored in the TLB to determine whether there is a TLB entry containing the virtual address; wherein the TLB entry includes at least one page, and the flag field of the TLB entry includes a start flag field for recording the starting virtual address of the page and a granularity size field for recording the page granularity of the page. Although the small-granularity pages within a large-granularity page have the same index field and high-bit flag field, each small-granularity page has different fields for representing the virtual address, so they can be distinguished by the start flag field for recording the starting virtual address of the page. Preferably, the TLB entry further includes a physical page frame number of a starting page in the fine-granularity page, ie, a PFN field.

[0064] For example, see Figure 2 , P1 and P2 are two small-granularity pages with different granularity in the same large-granularity page, and their information is recorded as follows Figure 3 In the TLB table entry, High_Tag represents the high-order identification field, Start_Tag represents the starting identification field, and Size represents the granularity size field. Table entry A records the information of P1, and table entry B records the information of P2. P1 is a 4KB small-granularity page. The content recorded in the starting identification field of table entry A is 0xA, indicating that P1 is page No. 10, and the content recorded in the granularity size field is 0x1, indicating that the page granularity of P1 is 1. P2 contains 5 consecutive small-granularity pages, namely page No. 3 to page No. 7. Therefore, the content recorded in the starting identification field of table entry B is 0x3, indicating that the starting page of P2 is page No. 3, and the content recorded in the granularity size field is 0x5, indicating that the page granularity of P2 is 5.

[0065] Furthermore, when there is a TLB entry containing the virtual address, a physical address having a mapping relationship with the virtual address is obtained based on the TLB entry containing the virtual address, and the physical address is returned to the processor. Specifically, the physical address having a mapping relationship with the virtual address is obtained based on the PFN field of the TLB entry corresponding to the virtual address, and the physical address is returned to the processor.

[0066] Furthermore, in order to allow as many consecutive pages as possible to be represented by a single TLB entry, in an embodiment of the present invention, when there is no TLB entry containing the virtual address, after the processor obtains the physical address from the memory, the processor merges the consecutive page table entries in the multiple page table entries into a continuous page table entry based on the multiple page table entries pre-stored in the processor cache; and generates a first TLB entry based on the continuous page table entries. It should be noted that when there is no TLB entry containing the virtual address to be converted, the processor will access the page table entry in the memory and find the page table entry containing the virtual address to be converted, obtain the corresponding physical address based on the page table entry, and extract the multiple page table entries that are continuous with the page table entry into the processor cache. Since the page table entry merging process is performed after the physical address is returned, it will not affect the system performance.

[0067] Furthermore, since TLB table entries with consecutive addresses will be mapped to the same TLB group, occupying multiple TLB table entries, resulting in a waste of TLB space, in order to solve this problem, an embodiment of the present invention determines whether there is a second TLB table entry that is continuous with the first TLB table entry in the TLB table entries stored in the TLB after the first TLB table entry is generated; if the second TLB table entry exists, the first TLB table entry and the second TLB table entry are merged into a third TLB table entry, and the second TLB table entry is replaced with the third TLB table entry; if the second TLB table entry does not exist, the first TLB table entry is inserted into the TLB.

[0068] An embodiment of the present invention provides a TLB management method that implements TLB support for multi-granularity page management by adding a start identifier field for recording the starting virtual address of pages of different granularities and a granularity size field for recording the page granularity to the TLB table entry. This eliminates the need to provide a dedicated TLB for each page granularity, avoids maintaining a dedicated TLB for each page granularity within the limited TLB space, and improves TLB space utilization. Furthermore, when no TLB table entry contains the virtual address, after the processor obtains the physical address from memory, the TLB coverage is effectively expanded by merging page table entries and TLB entries.

[0069] like Figure 4As shown, this is a logical diagram of the TLB search process. Figure 4 The High_Tag of the virtual address represents the high-order identification field of the virtual address, the Index represents the index field of the virtual address, the Low_Tag represents the virtual address field of the virtual address, and the Offset represents the offset of the virtual address. The Low_Tag and the Offset together constitute the virtual address field of the virtual address. Figure 4 The High_Tag of the TLB table entry represents the high-order identification field of the TLB table entry, the Start_Tag represents the starting identification field of the TLB table entry, the Size represents the granularity size field of the TLB table entry, and the PFN represents the physical page frame number of the TLB table entry.

[0070] As a preferred solution, the identification field of the virtual address includes an index field, a high-bit identification field and a virtual address field;

[0071] The identification field of the TLB table entry also includes a high-bit identification field;

[0072] Then, comparing the identification field of the virtual address with the identification field of the TLB entry stored in the TLB specifically includes:

[0073] Determining a TLB group in the TLB according to an index field of the virtual address;

[0074] Comparing the high-order flag field of the virtual address with the high-order flag field of the TLB table entry stored in the TLB group, and determining whether there is a matching TLB table entry in the TLB group whose high-order flag field is the same as the high-order flag field of the virtual address;

[0075] When there is at least one matching TLB table entry in the TLB group, the virtual address range of each matching TLB table entry is obtained according to the start identification field and the granularity size field of each matching TLB table entry; and the virtual address field of the virtual address is compared with the virtual address range of each matching TLB table entry.

[0076] It should be noted that the embodiment of the present invention compares the identification field of the virtual address with the identification fields of all TLB entries in the same TLB group in parallel to save comparison time.

[0077] As a preferred solution, the step of merging consecutive page table entries from the plurality of page table entries pre-stored in the processor cache into consecutive page table entries specifically includes:

[0078] Determining whether there are consecutive page table entries in the plurality of page table entries according to physical page frame numbers of the plurality of page table entries pre-stored in the processor cache;

[0079] When there are continuous page table entries in the plurality of page table entries, the continuous page table entries in the plurality of page table entries are merged into continuous page table entries.

[0080] like Figure 5 As shown in FIG, it is a logical diagram of the TLB table entry merging process, High_Tag represents the high-order identification field of the TLB table entry, Start_Tag represents the starting identification field of the TLB table entry, Size represents the granularity size field of the TLB table entry, and PFN represents the physical page frame number of the TLB table entry.

[0081] As a preferred solution, the determining whether there is a second TLB entry continuous with the first TLB entry among the TLB entries stored in the TLB; if the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry; and if the second TLB entry does not exist, inserting the first TLB entry into the TLB, specifically includes:

[0082] Obtaining a virtual address range of a TLB entry stored in the TLB according to a start identifier field and a granularity size field of the TLB entry stored in the TLB;

[0083] Obtaining a virtual address range of the first TLB table entry according to the start identifier field and the granularity size field of the first TLB table entry;

[0084] determining, based on a virtual address range of a TLB entry stored in the TLB, the virtual address range of the first TLB entry, a physical page frame number of a TLB entry stored in the TLB, and the physical page frame number of the first TLB entry, whether there is a second TLB entry continuous with the first TLB entry in the TLB entry stored in the TLB;

[0085] If the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry;

[0086] If the second TLB entry does not exist, insert the first TLB entry into the TLB.

[0087] For example, Figure 6As shown, the TLB entry A currently stored in the TLB contains 5 consecutive pages from page 3 to page 7. When page 8 is accessed, the embodiment of the present invention detects that pages 8 to 10 are continuous, performs a page table entry (PTE) merge operation, merges the 3 page table entries into a continuous page table entry, and generates a TLB entry B with a Start_Tag of 0x8. In addition, since these small-grained pages all belong to the same large-grained page and have the same High_Tag as TLB entry A, TLB entry B will be mapped to the same TLB group as TLB entry A. During the TLB entry merging process, TLB entry A and TLB entry B will be merged into TLB entry C. The old TLB entry A will be replaced by the new TLB entry C and will have a larger coverage range. Among them, High_Tag represents the high-order identification field of the TLB table entry, Start_Tag represents the starting identification field of the TLB table entry, Size represents the granularity size field of the TLB table entry, PFN represents the physical page frame number of the TLB table entry, and Next_Tag represents the starting identification field of the next TLB table entry continuous with the current TLB table entry.

[0088] As a preferred solution, the method further comprises:

[0089] When a new page needs to be allocated to the dynamic random access memory, determining, based on virtual address fields of a plurality of page table entries in the processor cache and the virtual address field of the new page that needs to be allocated to the dynamic random access memory, whether there is a first page table entry in the plurality of page table entries that is continuous with the virtual address field of the new page that needs to be allocated to the dynamic random access memory;

[0090] When the first page table entry exists, obtaining the physical page frame number of the first page table entry, and determining whether consecutive physical page frame numbers adjacent to the physical page frame number of the first page table entry are in an unallocated state;

[0091] When the continuous physical page frame numbers are in an unallocated state, allocating the continuous physical page frame numbers to new pages that need to be allocated to the dynamic random access memory, so that the physical page frame numbers of the new pages that need to be allocated to the dynamic random access memory are the continuous physical page frame numbers;

[0092] When a new page needs to be allocated to a non-volatile memory, based on a continuous physical page frame number space preset in the non-volatile memory, according to the reserved physical page frame numbers of multiple page table entries in the dynamic random access memory and the virtual address field of the new page that needs to be allocated to the non-volatile memory, the reserved physical page frame number is allocated to the new page that needs to be allocated to the non-volatile memory, so that the physical page frame number of the new page that needs to be allocated to the non-volatile memory is the reserved physical page frame number; wherein, the continuous physical page frame number space includes multiple continuous physical page frame numbers, and the reserved physical page frame numbers of the multiple page table entries in the dynamic random access memory have a one-to-one correspondence with the multiple continuous physical page frame numbers.

[0093] Specifically, the effectiveness of the page table entry merging process and the TLB entry merging process is limited by the limited number of consecutive pages in the memory. To further improve the feasibility of the two merging processes, when a new page needs to be allocated to the dynamic random access memory, an embodiment of the present invention determines, based on the virtual address fields of multiple page table entries in the processor cache and the virtual address field of the new page to be allocated to the dynamic random access memory, whether there is a first page table entry in the multiple page table entries that is continuous with the virtual address field of the new page to be allocated to the dynamic random access memory;

[0094] When the first page table entry exists, obtaining the physical page frame number of the first page table entry, and determining whether consecutive physical page frame numbers adjacent to the physical page frame number of the first page table entry are in an unallocated state;

[0095] When the continuous physical page frame numbers are in an unallocated state, allocating the continuous physical page frame numbers to new pages that need to be allocated to the dynamic random access memory, so that the physical page frame numbers of the new pages that need to be allocated to the dynamic random access memory are the continuous physical page frame numbers;

[0096] When a new page needs to be allocated to a non-volatile memory, based on a continuous physical page frame number space preset in the non-volatile memory, according to the reserved physical page frame numbers of multiple page table entries in the dynamic random access memory and the virtual address field of the new page that needs to be allocated to the non-volatile memory, the reserved physical page frame number is allocated to the new page that needs to be allocated to the non-volatile memory, so that the physical page frame number of the new page that needs to be allocated to the non-volatile memory is the reserved physical page frame number; wherein, the continuous physical page frame number space includes multiple continuous physical page frame numbers, and the reserved physical page frame numbers of the multiple page table entries in the dynamic random access memory have a one-to-one correspondence with the multiple continuous physical page frame numbers.

[0097] It should be noted that in NVM (Non-volatile Memory), given its significantly greater capacity than DRAM (Dynamic Random Access Memory), embodiments of the present invention reserve NVM space for consecutive pages to further enhance page continuity. For example, 2MB of consecutive physical page frame number space is reserved in NVM for 512 consecutive fine-grained pages, allowing these 512 consecutive fine-grained pages to be placed contiguously.

[0098] If a new page is allocated for the dynamic random access memory and the non-volatile memory and the above method cannot be used to allocate an ideal physical page frame number for the new page, the physical page frame number in an unallocated state is allocated to the new page according to the conventional allocation method.

[0099] As a preferred solution, the method further comprises:

[0100] When it is detected that the non-volatile memory migrates its pages to the dynamic random access memory, a new TLB entry is generated according to the migrated page, and the new TLB entry is inserted into the TLB.

[0101] Specifically, page migration between NVM and DRAM will cause the TLB table entry to be updated, and different migration methods will result in different update results. For page migration from DRAM to NVM, since the migrated page is a cold page, there is no need to generate a new TLB table entry based on the migrated page and insert it into the TLB. If the TLB table entry corresponding to the migrated page is originally stored in the TLB, the TLB table entry will be invalidated; for page migration from NVM to DRAM, since the migrated page is a hot page, it is necessary to generate a new TLB table entry based on the migrated page and insert the TLB table entry into the TLB to update the TLB table entry. It should be noted that during the page migration process, the large-grained page in NVM may be divided into multiple small-grained pages. In this case, it is still only necessary to generate a new TLB table entry based on the migrated page and insert it into the TLB. The page that has not been migrated is regarded as a cold page, and a new TLB table entry should not be inserted into the TLB, resulting in the TLB space being occupied.

[0102] As a preferred solution, the TLB includes a first-level TLB and a second-level TLB, and the first-level TLB is used to store a portion of TLB entries in the second-level TLB;

[0103] Then, determining whether there is a second TLB entry continuous with the first TLB entry in the TLB table entries stored in the TLB; if the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB table entry, and replacing the second TLB entry with the third TLB entry; if the second TLB entry does not exist, inserting the first TLB entry into the TLB, specifically includes:

[0104] Obtaining a virtual address range of a TLB entry stored in the secondary TLB according to a start identifier field and a granularity size field of the TLB entry stored in the secondary TLB;

[0105] Obtaining a virtual address range of the first TLB table entry according to the start identifier field and the granularity size field of the first TLB table entry;

[0106] Determining, based on the virtual address range of the TLB entry stored in the secondary TLB, the virtual address range of the first TLB entry, the physical page frame number of the TLB entry stored in the secondary TLB, and the physical page frame number of the first TLB entry, whether there is a second TLB entry continuous with the first TLB entry in the TLB entry stored in the secondary TLB;

[0107] If the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry;

[0108] If the second TLB entry does not exist, inserting the first TLB entry into the second-level TLB.

[0109] It should be noted that the first-level TLB, as a cache for the second-level TLB, generally has a smaller capacity than the second-level TLB and is used to store a portion of the TLB entries in the second-level TLB. During address translation, a TLB entry search is first performed in the first-level TLB. If a TLB miss occurs in the first-level TLB, the search continues in the second-level TLB. This embodiment of the present invention performs TLB entry merging operations only in the second-level TLB, resulting in lower latency for TLB entry searches in the first-level TLB.

[0110] See also Figure 7 A second aspect of an embodiment of the present invention provides a TLB management device, including:

[0111] The TLB entry lookup module 701 is configured to, upon receiving a virtual address sent by the processor, compare an identification field of the virtual address with an identification field of a TLB entry stored in the TLB to determine whether there is a TLB entry containing the virtual address; wherein the TLB entry includes at least one page, and the identification field of the TLB entry includes a start identification field for recording a start virtual address of the page and a granularity size field for recording a page granularity of the page;

[0112] A physical address returning module 702 is configured to, when there is a TLB entry containing the virtual address, obtain a physical address having a mapping relationship with the virtual address according to the TLB entry corresponding to the virtual address, and return the physical address to the processor;

[0113] A page table entry merging module 703 is configured to, when no TLB entry contains the virtual address, merge consecutive page table entries from a plurality of page table entries pre-stored in a processor cache into consecutive page table entries after the processor obtains the physical address from the memory; and generate a first TLB entry based on the consecutive page table entries;

[0114] The TLB table entry merging module 704 is used to determine whether there is a second TLB table entry continuous with the first TLB table entry in the TLB table entries stored in the TLB; if the second TLB table entry exists, merge the first TLB table entry and the second TLB table entry into a third TLB table entry, and replace the second TLB table entry with the third TLB table entry; if the second TLB table entry does not exist, insert the first TLB table entry into the TLB.

[0115] As a preferred solution, the identification field of the virtual address includes an index field, a high-bit identification field and a virtual address field;

[0116] The identification field of the TLB table entry also includes a high-bit identification field;

[0117] Then, the TLB entry lookup module 701 is used to compare the identification field of the virtual address with the identification field of the TLB entry stored in the TLB, specifically including:

[0118] Determining a TLB group in the TLB according to an index field of the virtual address;

[0119] Comparing the high-order flag field of the virtual address with the high-order flag field of the TLB table entry stored in the TLB group, and determining whether there is a matching TLB table entry in the TLB group whose high-order flag field is the same as the high-order flag field of the virtual address;

[0120] When there is at least one matching TLB table entry in the TLB group, the virtual address range of each matching TLB table entry is obtained according to the start identification field and the granularity size field of each matching TLB table entry; and the virtual address field of the virtual address is compared with the virtual address range of each matching TLB table entry.

[0121] As a preferred solution, the page table entry merging module 703 is used to merge consecutive page table entries in the multiple page table entries pre-stored in the processor cache into consecutive page table entries, specifically including:

[0122] Determining whether there are consecutive page table entries in the plurality of page table entries according to physical page frame numbers of the plurality of page table entries pre-stored in the processor cache;

[0123] When there are continuous page table entries in the plurality of page table entries, the continuous page table entries in the plurality of page table entries are merged into continuous page table entries.

[0124] As a preferred solution, the TLB entry merging module 704 is configured to determine whether there is a second TLB entry continuous with the first TLB entry among the TLB entries stored in the TLB; if the second TLB entry exists, merge the first TLB entry and the second TLB entry into a third TLB entry, and replace the second TLB entry with the third TLB entry; if the second TLB entry does not exist, insert the first TLB entry into the TLB, specifically including:

[0125] Obtaining a virtual address range of a TLB entry stored in the TLB according to a start identifier field and a granularity size field of the TLB entry stored in the TLB;

[0126] Obtaining a virtual address range of the first TLB table entry according to the start identifier field and the granularity size field of the first TLB table entry;

[0127] determining, based on a virtual address range of a TLB entry stored in the TLB, the virtual address range of the first TLB entry, a physical page frame number of a TLB entry stored in the TLB, and the physical page frame number of the first TLB entry, whether there is a second TLB entry continuous with the first TLB entry in the TLB entry stored in the TLB;

[0128] If the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry;

[0129] If the second TLB entry does not exist, insert the first TLB entry into the TLB.

[0130] As a preferred solution, the device further includes a new page allocation module, which is used to:

[0131] When a new page needs to be allocated to the dynamic random access memory, determining, based on virtual address fields of a plurality of page table entries in the processor cache and the virtual address field of the new page that needs to be allocated to the dynamic random access memory, whether there is a first page table entry in the plurality of page table entries that is continuous with the virtual address field of the new page that needs to be allocated to the dynamic random access memory;

[0132] When the first page table entry exists, obtaining the physical page frame number of the first page table entry, and determining whether consecutive physical page frame numbers adjacent to the physical page frame number of the first page table entry are in an unallocated state;

[0133] When the continuous physical page frame numbers are in an unallocated state, allocating the continuous physical page frame numbers to new pages that need to be allocated to the dynamic random access memory, so that the physical page frame numbers of the new pages that need to be allocated to the dynamic random access memory are the continuous physical page frame numbers;

[0134] When a new page needs to be allocated to a non-volatile memory, based on a continuous physical page frame number space preset in the non-volatile memory, according to the reserved physical page frame numbers of multiple page table entries in the dynamic random access memory and the virtual address field of the new page that needs to be allocated to the non-volatile memory, the reserved physical page frame number is allocated to the new page that needs to be allocated to the non-volatile memory, so that the physical page frame number of the new page that needs to be allocated to the non-volatile memory is the reserved physical page frame number; wherein, the continuous physical page frame number space includes multiple continuous physical page frame numbers, and the reserved physical page frame numbers of the multiple page table entries in the dynamic random access memory have a one-to-one correspondence with the multiple continuous physical page frame numbers.

[0135] As a preferred solution, the device further includes a TLB entry updating module, configured to:

[0136] When it is detected that the non-volatile memory migrates its pages to the dynamic random access memory, a new TLB entry is generated according to the migrated page, and the new TLB entry is inserted into the TLB.

[0137] As a preferred solution, the TLB includes a first-level TLB and a second-level TLB, and the first-level TLB is used to store a portion of TLB entries in the second-level TLB;

[0138] Then, the TLB entry merging module 704 is configured to determine whether a second TLB entry continuous with the first TLB entry exists in the TLB entries stored in the TLB; if the second TLB entry exists, merge the first TLB entry and the second TLB entry into a third TLB entry, and replace the second TLB entry with the third TLB entry; if the second TLB entry does not exist, insert the first TLB entry into the TLB, specifically including:

[0139] Obtaining a virtual address range of a TLB entry stored in the secondary TLB according to a start identifier field and a granularity size field of the TLB entry stored in the secondary TLB;

[0140] Obtaining a virtual address range of the first TLB table entry according to the start identifier field and the granularity size field of the first TLB table entry;

[0141] Determining, based on the virtual address range of the TLB entry stored in the secondary TLB, the virtual address range of the first TLB entry, the physical page frame number of the TLB entry stored in the secondary TLB, and the physical page frame number of the first TLB entry, whether there is a second TLB entry continuous with the first TLB entry in the TLB entry stored in the secondary TLB;

[0142] If the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry;

[0143] If the second TLB entry does not exist, inserting the first TLB entry into the second-level TLB.

[0144] It should be noted that the TLB management device provided in an embodiment of the present invention can implement all the processes of the TLB management method described in any of the above embodiments. The functions of each module in the device and the technical effects achieved are respectively the same as the functions and technical effects achieved by the TLB management method described in the above embodiments, and will not be repeated here.

[0145] A third aspect of an embodiment of the present invention provides a terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the TLB management method as described in any embodiment of the first aspect is implemented.

[0146] The terminal device may be a computing device such as a desktop computer, laptop, PDA, or cloud server. The terminal device may include, but is not limited to, a processor and memory. The terminal device may also include input and output devices, network access devices, buses, etc.

[0147] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor, etc. The processor is the control center of the terminal device, and connects various parts of the entire terminal device using various interfaces and lines.

[0148] The memory can be used to store the computer programs and / or modules, and the processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function (such as a sound playback function, an image playback function, etc.); the data storage area can store data created based on the use of the mobile phone (such as audio data, a phone book, etc.). In addition, the memory can include a high-speed random access memory and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (Small Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (Flash Card), at least one disk storage device, a flash memory device, or other volatile solid-state storage device.

[0149] A fourth aspect of an embodiment of the present invention provides a computer-readable storage medium, which includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the TLB management method as described in any embodiment of the first aspect.

[0150] Through the description of the above embodiments, those skilled in the art can clearly understand that the present invention can be implemented by means of software plus the necessary hardware platform, and of course, it can also be implemented entirely by hardware. Based on this understanding, all or part of the contribution of the technical solution of the present invention to the background art can be embodied in the form of a software product. This computer software product can be stored in a storage medium such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in various embodiments of the present invention or certain parts of the embodiments.

[0151] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A TLB management method, characterized in that: include: When receiving a virtual address sent by the processor, compare the identification field of the virtual address with the identification field of a TLB table entry stored in the TLB to determine whether there is a TLB table entry containing the virtual address; wherein the TLB table entry includes at least one page, and the identification field of the TLB table entry includes a start identification field for recording a start virtual address of the page and a granularity size field for recording a page granularity of the page; When there is a TLB table entry containing the virtual address, obtaining a physical address having a mapping relationship with the virtual address according to the TLB table entry containing the virtual address, and returning the physical address to the processor; When no TLB entry contains the virtual address, after the processor obtains the physical address from the memory, based on a plurality of page table entries pre-stored in the processor cache, merge consecutive page table entries from the plurality of page table entries into consecutive page table entries; and generate a first TLB entry based on the consecutive page table entries; Determine whether there is a second TLB table entry continuous with the first TLB table entry in the TLB table entries stored in the TLB; if the second TLB table entry exists, merge the first TLB table entry and the second TLB table entry into a third TLB table entry, and replace the second TLB table entry with the third TLB table entry; if the second TLB table entry does not exist, insert the first TLB table entry into the TLB.

2. The TLB management method according to claim 1, wherein: The identification field of the virtual address includes an index field, a high-bit identification field and a virtual address field; The identification field of the TLB table entry also includes a high-bit identification field; Then, comparing the identification field of the virtual address with the identification field of the TLB entry stored in the TLB specifically includes: Determining a TLB group in the TLB according to an index field of the virtual address; Comparing the high-order flag field of the virtual address with the high-order flag field of the TLB table entry stored in the TLB group, and determining whether there is a matching TLB table entry in the TLB group whose high-order flag field is the same as the high-order flag field of the virtual address; When there is at least one matching TLB table entry in the TLB group, the virtual address range of each matching TLB table entry is obtained according to the start identification field and the granularity size field of each matching TLB table entry; and the virtual address field of the virtual address is compared with the virtual address range of each matching TLB table entry.

3. The TLB management method according to claim 2, wherein: The step of merging consecutive page table entries from the plurality of page table entries pre-stored in the processor cache into consecutive page table entries specifically includes: Determining whether there are consecutive page table entries in the plurality of page table entries according to physical page frame numbers of the plurality of page table entries pre-stored in the processor cache; When there are continuous page table entries in the plurality of page table entries, the continuous page table entries in the plurality of page table entries are merged into continuous page table entries.

4. The TLB management method according to claim 3, wherein: The determining whether there is a second TLB entry continuous with the first TLB entry among the TLB entries stored in the TLB; if the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry; and if the second TLB entry does not exist, inserting the first TLB entry into the TLB, specifically includes: Obtaining a virtual address range of a TLB entry stored in the TLB according to a start identifier field and a granularity size field of the TLB entry stored in the TLB; Obtaining a virtual address range of the first TLB table entry according to the start identifier field and the granularity size field of the first TLB table entry; determining, based on a virtual address range of a TLB entry stored in the TLB, the virtual address range of the first TLB entry, a physical page frame number of a TLB entry stored in the TLB, and the physical page frame number of the first TLB entry, whether there is a second TLB entry continuous with the first TLB entry in the TLB entry stored in the TLB; If the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry; If the second TLB entry does not exist, insert the first TLB entry into the TLB.

5. The TLB management method according to claim 4, wherein: The method further comprises: When a new page needs to be allocated to the dynamic random access memory, determining, based on virtual address fields of a plurality of page table entries in the processor cache and the virtual address field of the new page that needs to be allocated to the dynamic random access memory, whether there is a first page table entry in the plurality of page table entries that is continuous with the virtual address field of the new page that needs to be allocated to the dynamic random access memory; When the first page table entry exists, obtaining the physical page frame number of the first page table entry, and determining whether consecutive physical page frame numbers adjacent to the physical page frame number of the first page table entry are in an unallocated state; When the continuous physical page frame numbers are in an unallocated state, allocating the continuous physical page frame numbers to new pages that need to be allocated to the dynamic random access memory, so that the physical page frame numbers of the new pages that need to be allocated to the dynamic random access memory are the continuous physical page frame numbers; When a new page needs to be allocated to a non-volatile memory, based on a continuous physical page frame number space preset in the non-volatile memory, according to the reserved physical page frame numbers of multiple page table entries in the dynamic random access memory and the virtual address field of the new page that needs to be allocated to the non-volatile memory, the reserved physical page frame number is allocated to the new page that needs to be allocated to the non-volatile memory, so that the physical page frame number of the new page that needs to be allocated to the non-volatile memory is the reserved physical page frame number; wherein, the continuous physical page frame number space includes multiple continuous physical page frame numbers, and the reserved physical page frame numbers of the multiple page table entries in the dynamic random access memory have a one-to-one correspondence with the multiple continuous physical page frame numbers.

6. The TLB management method according to claim 5, wherein: The method further comprises: When it is detected that the non-volatile memory migrates its pages to the dynamic random access memory, a new TLB entry is generated according to the migrated page, and the new TLB entry is inserted into the TLB.

7. The TLB management method according to claim 6, wherein: The TLB includes a first-level TLB and a second-level TLB, wherein the first-level TLB is used to store a portion of TLB entries in the second-level TLB; Then, determining whether there is a second TLB entry continuous with the first TLB entry in the TLB table entries stored in the TLB; if the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB table entry, and replacing the second TLB entry with the third TLB entry; if the second TLB entry does not exist, inserting the first TLB entry into the TLB, specifically includes: Obtaining a virtual address range of a TLB entry stored in the secondary TLB according to a start identifier field and a granularity size field of the TLB entry stored in the secondary TLB; Obtaining a virtual address range of the first TLB table entry according to the start identifier field and the granularity size field of the first TLB table entry; Determining, based on the virtual address range of the TLB entry stored in the secondary TLB, the virtual address range of the first TLB entry, the physical page frame number of the TLB entry stored in the secondary TLB, and the physical page frame number of the first TLB entry, whether there is a second TLB entry continuous with the first TLB entry in the TLB entry stored in the secondary TLB; If the second TLB entry exists, merging the first TLB entry and the second TLB entry into a third TLB entry, and replacing the second TLB entry with the third TLB entry; If the second TLB entry does not exist, inserting the first TLB entry into the second-level TLB.

8. A TLB management device, characterized in that: include: a TLB table entry lookup module configured to, upon receiving a virtual address sent by the processor, compare an identification field of the virtual address with an identification field of a TLB table entry stored in the TLB to determine whether there is a TLB table entry containing the virtual address; wherein the TLB table entry includes at least one page, and the identification field of the TLB table entry includes a start identification field for recording a start virtual address of the page and a granularity size field for recording a page granularity of the page; a physical address returning module, configured to, when there is a TLB table entry containing the virtual address, obtain a physical address having a mapping relationship with the virtual address according to the TLB table entry corresponding to the virtual address, and return the physical address to the processor; a page table entry merging module configured to, when no TLB entry contains the virtual address, merge consecutive page table entries from a plurality of page table entries pre-stored in a processor cache into consecutive page table entries after the processor obtains the physical address from the memory; and generate a first TLB entry based on the consecutive page table entries; A TLB table entry merging module is used to determine whether there is a second TLB table entry continuous with the first TLB table entry in the TLB table entries stored in the TLB; if the second TLB table entry exists, merge the first TLB table entry and the second TLB table entry into a third TLB table entry, and replace the second TLB table entry with the third TLB table entry; if the second TLB table entry does not exist, insert the first TLB table entry into the TLB.

9. A terminal device, characterized in that: The method comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the TLB management method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a stored computer program, wherein when the computer program is executed, the device where the computer-readable storage medium is located is controlled to execute the TLB management method according to any one of claims 1 to 7.

Images