Design method and device for DDR5 motherboard stacking

Abstract

The present application discloses a design method and device for a DDR5 motherboard stack, wherein the method includes selecting a power network that meets a preset noise voltage condition as a power reference layer; constructing a corresponding PCB stack model according to the power reference layer and a preset spacing distance, wherein the spacing distance represents the distance from the power reference layer to the DDR5 signal layer; simulating and verifying the PCB stack model to obtain the coupling degree between the power reference layer and the DDR5 signal layer; and determining whether to adjust the spacing distance according to the relationship between the coupling degree and the preset coupling condition. The present application reduces the development cost of the DDR5 motherboard by optimizing the PCB stack design and simulation method and finding a method for the remote reference power plane of the DDR5 signal.

Description

Technical Field

[0001] The present application relates to the field of PCB design technology, and in particular to a design method and device for a DDR5 motherboard stack. Background Art

[0002] DDR5 is a DDR interface technology in the server and storage fields. Compared with DDR4, DDR5 has a higher data rate, up to 6.4Gbps. For parallel buses, using high signal frequencies such as DDR5, SSN (synchronous switching noise) will face huge challenges, such as the need to pay attention to the impact of noise on the signal transmission quality of DDR5. Due to the influence of noise, the industry is currently studying the PCB stackup design of DDR5 signals using reference power planes (including main reference and remote reference). Today, in terms of PCB stackup design, DDR5 motherboards have at least 2 more GND layers than DDR4 motherboards, and the cost is more than 20% higher. Summary of the invention

[0003] The purpose of this application is to provide a DDR5 motherboard stack design method, device, electronic device and computer-readable storage medium to solve at least some of the above-mentioned technical problems, which can not only optimize the PCB stack design and simulation methods, but also find a method for the remote reference power plane of the DDR5 signal, thereby reducing the development cost of the DDR5 motherboard.

[0004] In order to achieve the above objectives, the present application provides a design method for a DDR5 motherboard stack, which includes:

[0005] Select a power network that meets the preset noise voltage condition as the power reference layer;

[0006] According to the power reference layer and the preset spacing distance, a corresponding PCB stacking model is constructed, wherein the spacing distance represents the distance from the power reference layer to the DDR5 signal layer;

[0007] The PCB stacking model is simulated and verified to obtain the coupling degree between the power reference layer and the DDR5 signal layer;

[0008] Whether to adjust the spacing distance is determined according to the relationship between the coupling degree and the preset coupling condition.

[0009] Optionally, the preset noise voltage condition includes that the preset noise voltage is less than a preset voltage value, and the preset voltage value has a corresponding relationship with the interface voltage of DDR5;

[0010] The “screening a power network that meets a preset noise voltage condition as a power reference layer” includes:

[0011] The power network with a voltage value less than the preset voltage is selected as the power reference layer.

[0012] Optionally, the preset coupling condition includes a preset coupling degree;

[0013] The “determining whether to adjust the spacing distance according to the relationship between the coupling degree and the preset coupling condition” includes:

[0014] Comparing the coupling degree corresponding to the PCB stacking model with the preset coupling degree;

[0015] If the coupling degree is greater than the preset coupling degree, increasing the interval distance;

[0016] If the coupling degree is less than or equal to the preset coupling degree, the spacing distance remains unchanged.

[0017] Optionally, after the spacing distance is increased, a corresponding PCB stacking model is constructed according to the increased spacing distance and a simulation verification is performed to obtain a corresponding coupling degree;

[0018] According to the relationship between the currently obtained coupling degree and the preset coupling condition, it is determined whether to adjust the increased interval distance.

[0019] Optionally, the method further comprises:

[0020] When the coupling degree satisfies a value less than or equal to the preset coupling degree, a signal and power supply joint simulation is performed on the PCB stacking model corresponding to the spacing distance to obtain a corresponding signal eye diagram;

[0021] Comparing the signal eye diagram with a preset reference signal eye diagram;

[0022] If the difference between the signal eye diagram and the preset reference signal eye diagram exceeds a preset range, increasing the distance ratio;

[0023] If the difference between the signal eye diagram and the preset reference signal eye diagram is within the preset range, determining the distance ratio;

[0024] The distance ratio refers to the ratio of the spacing distance to the distance from the GND reference layer to the DDR5 signal layer.

[0025] Optionally, the signal eye diagram includes an eye height and an eye width, wherein the eye height and the eye width represent a corresponding voltage axis and a time axis respectively;

[0026] The “comparing the signal eye diagram with a preset reference signal eye diagram” includes:

[0027] Respectively comparing the eye height and the eye width of the signal eye diagram and the preset reference signal eye diagram;

[0028] If the differences between the eye height and the eye width both meet a reference condition, then the output distance ratio is determined.

[0029] Optionally, the preset reference signal eye diagram is obtained based on DDR5 data in the CRB.

[0030] In order to achieve the above-mentioned purpose, the present application also provides a DDR5 motherboard stacking design device, which includes:

[0031] A screening module, the screening module is used to screen a power supply network that meets a preset noise voltage condition as a power supply reference layer;

[0032] A construction module, wherein the construction module is used to construct a corresponding PCB stacking model according to the power reference layer and a preset spacing distance, wherein the spacing distance represents a distance from the power reference layer to the DDR5 signal layer;

[0033] A simulation module, wherein the simulation module is used to simulate and verify the PCB stacking model to obtain the coupling degree between the power reference layer and the DDR5 signal layer;

[0034] A calculation module is used to determine whether to adjust the interval distance according to the relationship between the coupling degree and a preset coupling condition.

[0035] In order to achieve the above object, the present application also provides an electronic device, which includes:

[0036] processor;

[0037] a memory storing executable instructions of the processor;

[0038] Wherein, the processor is configured to execute the design method of DDR5 motherboard stack as described above by executing the executable instructions.

[0039] In order to achieve the above-mentioned objectives, the present application also provides a computer-readable storage medium having a computer program stored thereon, which includes a design method for implementing the DDR5 motherboard stack as described above when the computer program is executed by a processor.

[0040] The present application also provides a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of an electronic device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the electronic device executes the design method of the DDR5 motherboard stack as described above.

[0041] The present application first selects a power supply network that meets the preset noise voltage condition as a power supply reference layer, and constructs a corresponding PCB stacking model in combination with a preset spacing distance. The spacing distance is used to represent the distance from the power supply reference layer to the DDR5 signal layer. Then, the PCB stacking model is simulated and verified to obtain the coupling degree between the power supply reference layer and the DDR5 signal layer. Finally, according to the relationship between the coupling degree and the preset coupling condition, it is determined whether to adjust the spacing distance. The present application can use the screened power supply reference layer and the preset spacing distance to construct a corresponding PCB stacking model and perform simulation verification to obtain the corresponding coupling degree. Since the magnitude of the coupling degree will affect the power supply noise, and the magnitude of the coupling degree is related to the distance from the power supply reference layer to the DDR5 signal layer, in order to minimize the power supply noise, it is determined whether the spacing distance needs to be adjusted according to the relationship between the coupling degree and the preset coupling condition. The present application optimizes the PCB stacking design and simulation method, finds a method for the remote reference power plane of the DDR5 signal, and reduces the development cost of the DDR5 motherboard. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 This is a flow chart of the design method of the DDR5 motherboard stack according to an embodiment of the present application.

[0043] Figure 2 A schematic block diagram of a design device for a DDR5 motherboard stack according to an embodiment of the present application.

[0044] Figure 3 A schematic block diagram of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to explain in detail the technical content, structural features, implementation principles, and achieved purposes and effects of the present application, the following is a detailed description in conjunction with the implementation methods and the accompanying drawings.

[0046] See also Figure 1 , the present application discloses a design method for a DDR5 motherboard stack, which includes:

[0047] 101. Select a power network that meets a preset noise voltage condition as a power reference layer.

[0048] Generally speaking, the power network selected as the power reference layer needs to meet certain conditions. For example, the noise voltage of the power network needs to meet certain conditions (preset noise voltage conditions). The preset noise voltage conditions are related to the DDR5 interface.

[0049] Specifically, a power network that meets the preset noise voltage conditions can be selected from the CRB test data as the power reference layer. CRB is the abbreviation of the reference design board provided by Intel, that is, Customer Reference Board. CRB provides users with design reference data (test verification has been completed, and the quality can be guaranteed).

[0050] In some embodiments, the preset noise voltage condition includes that the preset noise voltage is less than a preset voltage value, and the preset voltage value has a corresponding relationship with the interface voltage of DDR5;

[0051] The above-mentioned “screening a power network that meets the preset noise voltage condition as a power reference layer” includes:

[0052] Select the power network with a voltage value less than the preset value as the power reference layer.

[0053] By selecting power networks with voltage values ​​lower than the preset voltage as the power reference layer, more power networks can be filtered, so that the power networks used as the power reference layer can be suitable for the interface voltage of DDR5, thereby ensuring reliability.

[0054] Specifically, the peak noise of the power network is compared with the preset voltage value, and the power network with a voltage value less than the preset voltage value is selected as the power reference layer. The preset voltage value is usually set to 10% of the interface voltage of DDR5 (such as 110mV), of course, it can also be other specific values, which are not limited here.

[0055] 102. Construct a corresponding PCB stacking model based on the screened power reference layer and the preset spacing distance, wherein the spacing distance represents the distance from the power reference layer to the DDR5 signal layer.

[0056] Specifically, the preset spacing distance can be set by itself, such as 3, and of course other values, which are not limited here. When constructing the corresponding PCB stacking model, the distance from the GND reference layer to the DDR5 signal layer is usually pre-set, and the corresponding PCB stacking model is constructed according to the screened power reference layer, the distance from the GND reference layer to the DDR5 signal layer, and the preset distance from the power reference layer to the DDR5 signal layer (spacing distance). Among them, there are many specific forms of constructing the corresponding PCB stacking model, and 3D modeling tools (such as HFSS, etc.) can be used to model the DDR5 interface wiring design and reference plane of the screened power reference layer, which includes the model of the PCB stacking (the thickness of each layer, such as the distance from the GND reference layer to the DDR5 signal layer and the distance from the power reference layer to the DDR5 signal layer, material assignment, etc.), the actual wiring of the DDR5 signal, the power copper plating of the power reference layer, etc. It should be noted that the specific modeling principles and execution processes are conventional means for those skilled in the art, and are not elaborated here one by one.

[0057] 103. The PCB stacking model is simulated and verified to obtain the coupling degree between the power reference layer and the DDR5 signal layer.

[0058] Specifically, the PCB stacking model is subjected to electromagnetic field simulation verification. Of course, other simulation verifications can also be adopted, as long as the coupling degree between the power reference layer and the DDR5 signal layer can be obtained, which is not limited here. For example, on the power reference layer, select a position closest to the DDR5 signal layer, and set a parameter port S1. At the same time, set a parameter port S2 on the DDR5 signal layer, and then terminate and excite the two parameter ports. Use HFSS to solve the electromagnetic field to obtain the coupling coefficient of the power reference layer to the DDR5 signal, which is the coupling degree. It should be noted that the specific simulation verification principles and execution processes are conventional means for those skilled in the art, and are not elaborated here one by one.

[0059] 104. Determine whether to adjust the interval distance based on the relationship between the coupling degree and the preset coupling condition.

[0060] Generally speaking, the power noise of the power reference layer will affect the DDR5 signal through spatial radiation (such as crosstalk). The closer the distance between the power reference layer and the DDR5 signal layer, the greater the coupling degree and the greater the crosstalk. Therefore, the coupling degree between the power reference layer and the DDR5 signal layer should be considered.

[0061] In some embodiments, the preset coupling condition includes a preset coupling degree;

[0062] The above-mentioned “determining whether to adjust the spacing distance according to the relationship between the coupling degree and the preset coupling condition” includes:

[0063] Comparing the coupling degree corresponding to the PCB stacking model with the preset coupling degree;

[0064] If the coupling degree is greater than the preset coupling degree, the interval distance is increased;

[0065] If the coupling degree is less than or equal to the preset coupling degree, the spacing distance remains unchanged.

[0066] By comparing the coupling degree corresponding to the PCB stacking model with the preset coupling degree, it is easy to determine whether the coupling degree meets the preset coupling degree, ensure that the power noise of the corresponding power reference layer has an appropriate impact on the DDR5 signal, and at the same time minimize the impact of the coupling degree, and determine the minimum value of the spacing distance that meets the preset coupling degree conditions. In addition, if the coupling degree is less than the preset coupling degree, it means that the closer the distance between the power reference layer and the DDR5 signal layer is, the more necessary it is to further adjust the distance (spacing distance) between the power reference layer and the DDR5 signal layer, so that the corresponding coupling degree is further reduced to meet the preset coupling degree.

[0067] Generally speaking, the preset coupling degree can be set by oneself, such as -20dB, and of course it can also be other specific values, which are not limited here. In addition, the interval distance can be increased by 1 each time, which is of course not limited to this.

[0068] Furthermore, when the spacing distance is increased, a corresponding PCB stacking model is constructed according to the increased spacing distance and a simulation verification is performed to obtain a corresponding coupling degree;

[0069] According to the relationship between the currently obtained coupling degree and the preset coupling condition, it is determined whether to adjust the increased interval distance.

[0070] By using the increased spacing distance to re-establish the PCB stacking model and simulate and verify the corresponding coupling degree, and then compare it with the preset coupling conditions again, it is convenient to determine whether the current coupling degree meets the preset coupling degree, ensure that the power supply noise of the corresponding power reference layer has an appropriate impact on the DDR5 signal, and at the same time, it can minimize the impact of the coupling degree and determine the minimum spacing distance that meets the preset coupling degree conditions. It should be noted that if the current coupling degree does not meet the preset coupling degree, continue to increase the current spacing distance and perform modeling, simulation verification and analysis, and compare the corresponding coupling degree with the preset coupling degree again to determine whether to continue to adjust the corresponding spacing distance (if it meets, keep it, if it does not meet, continue to increase and repeat the above steps), to ensure that the coupling degree of the PCB stacking model corresponding to the adjusted spacing distance meets the preset coupling conditions.

[0071] Furthermore, the above method also includes:

[0072] When the coupling degree satisfies the requirement of being less than or equal to the preset coupling degree, a signal and power supply joint simulation is performed on the PCB stacking model corresponding to the spacing distance to obtain a corresponding signal eye diagram;

[0073] comparing a signal eye diagram with a preset reference signal eye diagram;

[0074] If the difference between the signal eye diagram and the preset reference signal eye diagram exceeds the preset range, the distance ratio is increased;

[0075] If the difference between the signal eye diagram and the preset reference signal eye diagram is within a preset range, determining a distance ratio;

[0076] The distance ratio refers to the ratio of the spacing distance to the distance from the GND reference layer to the DDR5 signal layer.

[0077] It should be noted that after the spacing distance is increased, the increased spacing distance should continue to be used for modeling, simulation verification and analysis, and the current coupling degree should be compared with the preset coupling degree to determine whether to continue to adjust the spacing distance (if it is consistent, maintain it; if it is not consistent, continue to increase it and repeat the above steps) until the coupling degree of the PCB stacking model corresponding to the adjusted spacing distance meets the preset coupling conditions.

[0078] Generally speaking, the power noise of the power reference layer will also affect the DDR5 signal in another way (through the signal return path of DDR5). The signal return path will return from both the GND reference layer and the power reference layer (the return components of the two reference layers are inversely proportional to their respective distances to the DDR5 signal layer). Therefore, the distances from the GND reference layer and the power reference layer to the DDR5 signal layer (distance ratio) must also be considered.

[0079] When the spacing distance remains unchanged, that is, the corresponding coupling degree meets the preset coupling conditions, the PCB stacking model corresponding to the spacing distance is used and the signal and power supply joint simulation is performed to obtain the corresponding signal eye diagram, and then the signal eye diagram and the preset reference signal eye diagram are used to analyze the difference. If the difference is within the preset range, the distance ratio can be determined. If the difference exceeds the preset range, the corresponding distance ratio is increased, and the increased distance ratio is modeled and the signal and power supply are jointly simulated again to compare the corresponding signal eye diagram with the preset reference signal eye diagram again to ensure that the difference between the two exceeds the preset range. Generally speaking, the initial distance ratio can be set by itself, such as 3, and of course it can be other values, which are not limited here. It should be noted that the increase in the distance ratio can be increased by 1 each time, of course, it is not limited to this. The specific method can be to increase the distance from the power reference layer to the DDR5 signal layer (spacing distance), or to reduce the distance from the GND reference layer to the DDR5 signal layer, which is not limited here.

[0080] Specifically, a DDR signal simulation tool (such as ADS, etc.) can be used to add a DDR driver model on the CPU side and a DDR particle model on the receiving side, and perform a signal-power joint simulation on the PCB stacking model to obtain the corresponding signal eye diagram. It should be noted that the specific simulation verification principle and execution process are conventional means for technicians in this field, and will not be elaborated here one by one. Of course, other signal simulation tools can also be used, which are not limited here.

[0081] Generally speaking, the CQC (channel quality comparison) method is used to compare the signal eye diagram, and compare the difference between the corresponding signal eye diagram of the corresponding PCB stacking model and the preset reference signal eye diagram. When the difference is within the reference condition (within the controllable range, which can be set by yourself), the PCB stacking model is a low-risk design and is technically feasible.

[0082] Specifically, the preset reference signal eye diagram is obtained based on the DDR5 data in the CRB. Since the CRB provides users with design reference data (which has been tested and verified, and the quality can be guaranteed), it is helpful to ensure the reliability of the preset reference signal eye diagram.

[0083] Specifically, the preset reference signal eye diagram can be pre-generated based on the DDR5 data in the CRB, or it can be modeled based on the DDR5 data in the CRB, such as using the DDR5 interface wiring design and reference plane in the CRB for modeling, and then performing signal-power co-simulation on the model to obtain the corresponding signal eye diagram, which is regarded as the preset reference signal eye diagram. Of course, it can also be in other forms, as long as the design method of DDR5 motherboard stacking can be executed according to the preset reference signal eye diagram, which is not limited here.

[0084] Furthermore, the signal eye diagram includes an eye height and an eye width, wherein the eye height and the eye width represent the corresponding voltage axis and time axis respectively;

[0085] The above-mentioned “comparing the signal eye diagram with a preset reference signal eye diagram” includes:

[0086] Compare the eye height and eye width of the signal eye diagram with the preset reference signal eye diagram respectively;

[0087] If the differences in eye height and eye width meet the reference conditions, the output distance ratio is determined.

[0088] By comparing the eye height and eye width of the signal eye diagram with the preset reference signal eye diagram, the accuracy of the test can be improved.

[0089] Specifically, the reference condition may be set to a difference of less than 5%, but is certainly not limited thereto.

[0090] The present application first selects a power supply network that meets the preset noise voltage condition as a power supply reference layer, and constructs a corresponding PCB stacking model in combination with a preset spacing distance. The spacing distance is used to represent the distance from the power supply reference layer to the DDR5 signal layer. Then, the PCB stacking model is simulated and verified to obtain the coupling degree between the power supply reference layer and the DDR5 signal layer. Finally, according to the relationship between the coupling degree and the preset coupling condition, it is determined whether to adjust the spacing distance. The present application can use the screened power supply reference layer and the preset spacing distance to construct a corresponding PCB stacking model and perform simulation verification to obtain the corresponding coupling degree. Since the magnitude of the coupling degree will affect the power supply noise, and the magnitude of the coupling degree is related to the distance from the power supply reference layer to the DDR5 signal layer, in order to minimize the power supply noise, it is determined whether the spacing distance needs to be adjusted according to the relationship between the coupling degree and the preset coupling condition. The present application optimizes the PCB stacking design and simulation method, finds a method for the remote reference power plane of the DDR5 signal, and reduces the development cost of the DDR5 motherboard.

[0091] See also Figure 2 The present application also discloses a design device for a DDR5 motherboard stack, which includes:

[0092] A screening module 10, the screening module 10 is used to screen a power supply network that meets a preset noise voltage condition as a power supply reference layer;

[0093] A construction module 11 is used to construct a corresponding PCB stacking model according to a power reference layer and a preset spacing distance, wherein the spacing distance represents a distance from the power reference layer to the DDR5 signal layer;

[0094] A simulation module 12, which is used to simulate and verify the PCB stacking model to obtain the coupling degree between the power reference layer and the DDR5 signal layer;

[0095] The calculation module 13 is used to determine whether to adjust the interval distance according to the relationship between the coupling degree and the preset coupling condition.

[0096] For a detailed description of the design device of the DDR5 motherboard stack, please refer to the above-mentioned design method of the DDR5 motherboard stack, which will not be repeated here.

[0097] See also Figure 3 , the embodiment of the present application further discloses an electronic device, which includes:

[0098] Processor 21;

[0099] A memory 20 storing executable instructions of a processor 21;

[0100] Among them, the processor 21 is configured to execute the above-mentioned DDR5 motherboard stacking design method by executing executable instructions.

[0101] An embodiment of the present application also discloses a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the above-mentioned DDR5 motherboard stacking design method is implemented.

[0102] The present application also discloses a computer program product or a computer program, which includes a computer instruction stored in a computer-readable storage medium. A processor of an electronic device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the electronic device executes the above-mentioned DDR5 motherboard stacking design method.

[0103] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by hardware related to computer program instructions, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0104] The above disclosure is only a preferred example of the present application and cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are all within the scope covered by the present application.

Claims

1. A design method for a DDR5 motherboard stack, characterized in that: include: Select a power network that meets the preset noise voltage condition as the power reference layer; According to the power reference layer and the preset spacing distance, a corresponding PCB stacking model is constructed, wherein the spacing distance represents the distance from the power reference layer to the DDR5 signal layer; The PCB stacking model is simulated and verified to obtain the coupling degree between the power reference layer and the DDR5 signal layer; Determining whether to adjust the spacing distance according to a relationship between the coupling degree and a preset coupling condition; The preset coupling condition includes a preset coupling degree; The “determining whether to adjust the spacing distance according to the relationship between the coupling degree and the preset coupling condition” includes: Comparing the coupling degree corresponding to the PCB stacking model with the preset coupling degree; If the coupling degree is greater than the preset coupling degree, increasing the interval distance; If the coupling degree is less than or equal to the preset coupling degree, the spacing distance remains unchanged; When the coupling degree satisfies a value less than or equal to the preset coupling degree, a signal and power supply joint simulation is performed on the PCB stacking model corresponding to the spacing distance to obtain a corresponding signal eye diagram; Comparing the signal eye diagram with a preset reference signal eye diagram; If the difference between the signal eye diagram and the preset reference signal eye diagram exceeds a preset range, increasing the distance ratio; If the difference between the signal eye diagram and the preset reference signal eye diagram is within the preset range, determining the distance ratio; The distance ratio refers to the ratio of the spacing distance to the distance from the GND reference layer to the DDR5 signal layer; The signal eye diagram includes an eye height and an eye width, wherein the eye height and the eye width represent the corresponding voltage axis and time axis respectively; The “comparing the signal eye diagram with a preset reference signal eye diagram” includes: Respectively comparing the eye height and the eye width of the signal eye diagram and the preset reference signal eye diagram; If the differences between the eye height and the eye width both meet the reference condition, the distance ratio is determined.

2. The design method of DDR5 motherboard stack as claimed in claim 1, characterized in that: The preset noise voltage condition includes that the preset noise voltage is less than a preset voltage value, and the preset voltage value has a corresponding relationship with the interface voltage of DDR5; The "selecting a power network that meets a preset noise voltage condition as a power reference layer" includes: The power network with a voltage value less than the preset voltage is selected as the power reference layer.

3. The design method of DDR5 motherboard stack as claimed in claim 1, characterized in that: When the spacing distance is increased, a corresponding PCB stacking model is constructed according to the increased spacing distance and a simulation verification is performed to obtain a corresponding coupling degree; According to the relationship between the currently obtained coupling degree and the preset coupling condition, it is determined whether to adjust the increased interval distance.

4. The design method of DDR5 motherboard stack as claimed in claim 1, characterized in that: The preset reference signal eye diagram is obtained based on the DDR5 data in the CRB.

5. A design device for DDR5 motherboard stacking, characterized in that: include: A screening module, the screening module is used to screen a power supply network that meets a preset noise voltage condition as a power supply reference layer; A construction module, wherein the construction module is used to construct a corresponding PCB stacking model according to the power reference layer and a preset spacing distance, wherein the spacing distance represents a distance from the power reference layer to the DDR5 signal layer; A simulation module, wherein the simulation module is used to simulate and verify the PCB stacking model to obtain the coupling degree between the power reference layer and the DDR5 signal layer; A calculation module, the calculation module is used to determine whether to adjust the interval distance according to the relationship between the coupling degree and a preset coupling condition; The preset coupling condition includes a preset coupling degree; The “determining whether to adjust the spacing distance according to the relationship between the coupling degree and the preset coupling condition” includes: Comparing the coupling degree corresponding to the PCB stacking model with the preset coupling degree; If the coupling degree is greater than the preset coupling degree, increasing the interval distance; If the coupling degree is less than or equal to the preset coupling degree, the spacing distance remains unchanged; When the coupling degree satisfies a value less than or equal to the preset coupling degree, a signal and power supply joint simulation is performed on the PCB stacking model corresponding to the spacing distance to obtain a corresponding signal eye diagram; Comparing the signal eye diagram with a preset reference signal eye diagram; If the difference between the signal eye diagram and the preset reference signal eye diagram exceeds a preset range, increasing the distance ratio; If the difference between the signal eye diagram and the preset reference signal eye diagram is within the preset range, determining the distance ratio; The distance ratio refers to the ratio of the spacing distance to the distance from the GND reference layer to the DDR5 signal layer; The signal eye diagram includes an eye height and an eye width, wherein the eye height and the eye width represent the corresponding voltage axis and time axis respectively; The “comparing the signal eye diagram with a preset reference signal eye diagram” includes: Respectively comparing the eye height and the eye width of the signal eye diagram and the preset reference signal eye diagram; If the differences between the eye height and the eye width both meet the reference condition, the distance ratio is determined.

6. An electronic device, characterized in that: include: processor; a memory storing executable instructions of the processor; Wherein, the processor is configured to execute the DDR5 motherboard stack design method described in any one of claims 1-4 by executing the executable instructions.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the method for designing a DDR5 motherboard stack as described in any one of claims 1 to 4 is implemented.

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