Display device and method of driving a display device

Abstract

A display device and a method for driving the display device are provided. The display device includes: a display panel including gate lines and data lines; a gate driver for outputting gate signals to the gate lines; a data driver for outputting data voltages to the data lines; and a power voltage generator. The power voltage generator generates a gate on-state voltage, a gate off-state voltage, and a gate clock signal switching between the gate on-state voltage and the gate off-state voltage, detects the current level of the gate clock current, and cuts off power to the display device when the count of the gate clock current higher than or equal to a first current level is greater than or equal to a reference count, and cuts off power to the display device when the gate clock current is higher than or equal to a second current level higher than the first current level in the initial frame after the display device is turned on.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for driving the display device. More specifically, embodiments of the present invention relate to a display device and a method for driving the display device that improves safety and reliability by detecting short circuits between gate lines or short circuits between a gate line and a common electrode. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driver. The display panel displays an image based on an input image and includes multiple gate lines, multiple data lines, and multiple pixels. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, a drive controller for controlling the gate driver and the data driver, and a power voltage generator that provides drive voltages to the display panel, the gate driver, and the data driver.

[0003] When a short circuit occurs between signal transmission lines in a part of a display device, the user may suffer physical injury or property damage due to heat and / or fire. Therefore, when a short circuit occurs between signal transmission lines in a part of a display device, the power supply must be disconnected. Summary of the Invention

[0004] Embodiments of the present invention provide a display device with improved safety and reliability by sensitively detecting short circuits between gate lines or short circuits between a gate line and a common electrode.

[0005] Embodiments of the present invention also provide a method for driving a display device to improve safety and reliability by sensitively detecting short circuits between gate lines or short circuits between a gate line and a common electrode.

[0006] In an embodiment of a display device according to the present invention, the display device may include a display panel, a gate driver, a data driver, and a power voltage generator. The display panel includes gate lines, data lines, and pixels electrically connected to the gate lines and data lines. The display panel is configured to display an image based on input image data. The gate driver is configured to output a gate signal to the gate lines. The data driver is configured to output a data voltage to the data lines. The power voltage generator is configured to generate a gate on-state voltage, a gate off-state voltage, and a gate clock signal switching between the gate on-state voltage and the gate off-state voltage. The power voltage generator is also configured to detect the current level of the gate clock current based on the gate clock signal. The power voltage generator is further configured to cut off power to the display device when a count of the gate clock current at or above a first current level is greater than or equal to a reference count. The power voltage generator is also configured to cut off power to the display device when the gate clock current in an initial frame after the display device is turned on is higher than or equal to a second current level higher than the first current level.

[0007] In an embodiment, the power voltage generator can simultaneously activate a first cutoff mode and a second cutoff mode. The first cutoff mode cuts off the power to the display device when the count of the gate clock current, which is higher than or equal to a first current level, is greater than or equal to a reference count. The second cutoff mode cuts off the power to the display device when the gate clock current is higher than or equal to a second current level in the initial frame after the display device is turned on.

[0008] In an embodiment, the power voltage generator may include a voltage generator and an overcurrent detector. The voltage generator receives a power voltage and a clock control signal, and converts the clock control signal into a gate clock signal. The overcurrent detector detects the gate clock current flowing through the voltage terminal to output an overcurrent detection signal.

[0009] In an embodiment, the overcurrent detector may include: a current sensor for sensing the gate clock current output through a voltage terminal; an overcurrent detection circuit for determining whether the gate clock current is higher than or equal to a reference current level; an overcurrent counter for counting the gate clock current that is higher than or equal to the reference current level; and an overcurrent determination circuit for determining that the gate clock current is in an overcurrent state when the count counted by the overcurrent counter is greater than or equal to the reference count.

[0010] In an embodiment, when the gate clock current is determined to be in an overcurrent state, the overcurrent determination circuit can activate the overcurrent detection signal.

[0011] In one embodiment, when the overcurrent detection signal is activated, the voltage generator can cut off the power to the display device.

[0012] In one embodiment, after the gate clock signal is switched, the power voltage generator can detect the current level of the gate clock current after the rising edge of the gate clock signal or after the falling edge of the gate clock signal.

[0013] In one embodiment, after the gate clock signal is switched, the power voltage generator can detect the current level of the gate clock current immediately before the rising edge of the gate clock signal or before the falling edge of the gate clock signal.

[0014] In this embodiment, the first current level and the second current level can be settable.

[0015] In this embodiment, the reference count may be configurable.

[0016] In an embodiment of a method for driving a display device according to the present invention, the method may include: generating a gate on-state voltage and a gate off-state voltage; generating a gate clock signal that switches between the gate on-state voltage and the gate off-state voltage; detecting a current level of a gate clock current based on the gate clock signal; and cutting off power to the display device when a count of the gate clock current that is higher than or equal to a first current level is greater than or equal to a reference count. The method may further include: cutting off power to the display device when the gate clock current is higher than or equal to a second current level higher than the first current level in an initial frame after the display device is turned on.

[0017] In this embodiment, a first cutoff mode and a second cutoff mode are activated simultaneously. The first cutoff mode cuts off the power to the display device when the count of the gate clock current, which is higher than or equal to a first current level, is greater than or equal to a reference count. The second cutoff mode cuts off the power to the display device when the gate clock current is higher than or equal to a second current level in the initial frame after the display device is turned on.

[0018] In an embodiment, cutting off the power to the display device may further include: receiving a power voltage and a clock control signal, and converting and outputting the clock control signal as a gate clock signal; and detecting the gate clock current flowing through the voltage terminal and outputting an overcurrent detection signal.

[0019] In an embodiment, outputting an overcurrent detection signal may include: sensing a gate clock current output through a voltage terminal; determining whether the gate clock current is higher than or equal to a reference current level; counting the gate clock currents that are higher than or equal to the reference current level; and determining that the gate clock current is in an overcurrent state when the count of the gate clock currents that are higher than or equal to the reference current level is greater than or equal to the reference count.

[0020] In this embodiment, the output overcurrent detection signal may further include: activating the overcurrent detection signal when it is determined that the gate clock current is in an overcurrent state.

[0021] In one embodiment, converting and outputting the clock control signal as a gate clock signal may include cutting off the power to the display device when an overcurrent detection signal is activated.

[0022] In an embodiment, detecting the current level of the gate clock current may include: detecting the current level of the gate clock current after the gate clock signal is switched, after the rising edge of the gate clock signal, or after the falling edge of the gate clock signal.

[0023] In an embodiment, detecting the current level of the gate clock current may further include: detecting the current level of the gate clock current immediately after the gate clock signal is switched, immediately before the rising edge of the gate clock signal or before the falling edge of the gate clock signal.

[0024] In this embodiment, the first current level and the second current level can be settable.

[0025] In this embodiment, the reference count may be configurable.

[0026] According to the aforementioned display device and method for driving the display device, the display device detects abnormal current levels of the gate clock current after the display device is turned on, and cuts off the power to the display device when an overcurrent occurs, thereby preventing display panel malfunctions. Furthermore, the display device can prevent overheating due to high heat and reduce risks such as fire. As a result, the display device of this invention improves the safety and reliability of display devices. Attached Figure Description

[0027] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the concept of the present invention.

[0028] Figure 2 It is shown Figure 1 A plan view of the display device.

[0029] Figure 3 This is a block diagram of an electric voltage generator according to an embodiment of the present invention.

[0030] Figure 4 Is included Figure 3 Block diagram of the overcurrent detector in the power voltage generator.

[0031] Figure 5 It is shown Figure 1 Timing diagram of the gate clock control signal, gate clock signal and gate clock current of the gate driver.

[0032] Figure 6 This is a timing diagram illustrating the cut-off process of the power voltage generator of a display device according to an embodiment of the present invention.

[0033] Figure 7 This is a timing diagram illustrating the cut-off process of the power voltage generator of a display device according to an embodiment of the present invention.

[0034] Figure 8 This is a flowchart illustrating the operation of a display device according to an embodiment of the concept of the present invention.

[0035] Figure 9 This is a block diagram illustrating an electronic device according to an embodiment of the concept of the present invention.

[0036] Figure 10 It is shown that Figure 9 The diagram shows an example of an electronic device implemented as a smartphone. Detailed Implementation

[0037] The inventive concept will be described in more detail below with reference to the accompanying drawings.

[0038] Figure 1 This is a block diagram illustrating a display device 10 according to an embodiment of the concept of the present invention.

[0039] Reference Figure 1 The display device 10 includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500. The display panel driver may also include a power voltage generator 600.

[0040] For example, the drive controller 200 and the data driver 500 can be integrally formed. For example, the drive controller 200, the gamma reference voltage generator 400, and the data driver 500 can be integrally formed. The drive module in which at least the drive controller 200 and the data driver 500 are integrally formed can be referred to as a timing controller embedded data driver (TED).

[0041] The display panel 100 may include a display area for displaying images and a peripheral area adjacent to the display area.

[0042] The display panel 100 may include multiple gate lines GL, multiple data lines DL, and multiple pixels P electrically connected to each of the gate lines GL and data lines DL. The gate lines GL may extend in a first direction D1, and the data lines DL may extend in a second direction D2 intersecting the first direction D1.

[0043] The drive controller 200 can receive input image data IMG and input control signals CONT from an external device (not shown). For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may also include white image data. The input image data IMG may also include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0044] The drive controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0045] The drive controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal.

[0046] The drive controller 200 can generate a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0047] The drive controller 200 can generate a data signal DATA based on the input image data IMG. The drive controller 200 can output the data signal DATA to the data driver 500.

[0048] The drive controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400, and output the third control signal CONT3 to the gamma reference voltage generator 400.

[0049] The gate driver 300 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the drive controller 200. The gate driver 300 can output the gate signal to the gate line GL. For example, the gate driver 300 can sequentially output the gate signal to the gate line GL. In one embodiment, the gate driver 300 can be implemented using an amorphous silicon gate (ASG) circuit of an amorphous silicon thin-film transistor (a-Si TFT) and can be mounted in the peripheral region of the display panel 100. In another embodiment, the gate driver 300 can be implemented using oxide semiconductors, crystalline semiconductors, polycrystalline semiconductors, etc., and can be mounted in the peripheral region of the display panel 100.

[0050] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the drive controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF can have a value corresponding to each data signal DATA.

[0051] In one embodiment, the gamma reference voltage generator 400 may be located in the drive controller 200 or in the data driver 500.

[0052] The data driver 500 can receive a second control signal CONT2 and a data signal DATA from the drive controller 200, and a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can use the gamma reference voltage VGREF to convert the data signal DATA into a data voltage in analog format. The data driver 500 can output the data voltage to the data line DL. For example, the data driver 500 can be mounted in the peripheral area of ​​the display panel 100. Alternatively, the data driver 500 can be integrated into the peripheral area of ​​the display panel 100.

[0053] The power voltage generator 600 can provide power voltage to at least one of the display panel 100, drive controller 200, gate driver 300, gamma reference voltage generator 400, and data driver 500. In this case, the power voltage generator 600 may include a DC-DC converter. The power voltage generator 600 can generate a common voltage VCOM and output the common voltage VCOM to the display panel 100. In an embodiment, the display device 10 may be a liquid crystal display device including a liquid crystal layer. However, in an embodiment, the display device 10 may be another type of display device besides a liquid crystal display device.

[0054] In one embodiment, the power voltage generator 600 can generate a gate clock signal CKV for generating a gate signal, and a gate on-state voltage VON and a gate off-state voltage VOFF for controlling the operation of the gate driver 300. The power voltage generator 600 can output the gate clock signal CKV, the gate on-state voltage VON, and the gate off-state voltage VOFF to the gate driver 300. The power voltage generator 600 can receive a gate clock control signal CPV and a vertical start signal STV from the drive controller 200. The vertical start signal STV can be a signal indicating the start of a frame. The power voltage generator 600 can generate the gate clock signal CKV based on the gate clock control signal CPV and the vertical start signal STV. Simultaneously, the power voltage generator 600 can generate an analog high voltage AVDD for determining the level of the data voltage and output the analog high voltage AVDD to the data driver 500.

[0055] Figure 2 It is shown Figure 1 A plan view of the display device 10.

[0056] Reference Figure 1 and Figure 2 The drive controller 200 and the power voltage generator 600 can be housed in the printed circuit board assembly PBA. The printed circuit board assembly PBA can be connected to the first printed circuit P1 and the second printed circuit P2.

[0057] For example, the data driver 500 may include a plurality of data driver chips (DICs) connected between the first printed circuit P1 and the display panel 100, and a plurality of data driver chips (DICs) connected between the second printed circuit P2 and the display panel 100.

[0058] In this embodiment, the gate driver 300 may be disposed in the display panel 100. The power voltage generator 600 may output gate clock signals CKV1 and CKV2 to the gate driver 300 disposed in the display panel 100. The gate clock signal lines from which the gate clock signals CKV1 and CKV2 are applied may be disposed in the display panel 100.

[0059] Meanwhile, according to the display device 10, due to manufacturing problems or damage during use, adjacent gate lines GL may short-circuit, or gate line GL and the common electrode may short-circuit. When adjacent gate lines GL are short-circuited or gate line GL and the common electrode are short-circuited, the display device 10 may overheat or ignite, causing injury to the user. Furthermore, even when gate line GL and the common electrode are not short-circuited, the level of the gate clock signal CKV may change significantly due to coupling phenomena. Therefore, after the gate clock signal CKV, data voltage, etc., begin to switch, the display device 10 may need to detect a short circuit in adjacent gate line GL or a short circuit between gate line GL and the common electrode, and cut off the power to the display device 10.

[0060] As described below, the display device 10 according to the present invention can detect the current level of the gate clock current based on the gate clock signal CKV, and above a first current level OCP LEVEL (see below). Figure 6 The power to the display device 10 is cut off when the gate clock current count exceeds the reference count. Additionally, as described below, when the gate clock current is higher than the second current level ICPLEVEL (which is higher than the first current level OCP LEVEL) in the initial frame after the display device 10 is turned on, the power is cut off. Figure 7 When an abnormal current level of the gate clock current (OCP LEVEL) is detected, the display device 10 can be powered off. Specifically, the display device 10 can simultaneously activate a first cutoff mode and a second cutoff mode. The first cutoff mode cuts off the power to the display device 10 when the count of the gate clock current (OCP LEVEL) is greater than or equal to a reference count. The second cutoff mode cuts off the power to the display device 10 when the gate clock current (ICP LEVEL) is greater than or equal to a second current level (ICP LEVEL) in the initial frame after the display device 10 is powered on. Therefore, according to the display device 10, the safety and reliability of the display device 10 can be improved by more sensitively detecting abnormal current levels of the gate clock current.

[0061] Figure 3 This is a block diagram of a power voltage generator 600 according to an embodiment of the present invention. Figure 4 Is included Figure 3 Block diagram of the overcurrent detector 620 in the power voltage generator 600.

[0062] Reference Figure 3 and Figure 4 The power voltage generator 600 may include a voltage generator 610 and an overcurrent detector 620.

[0063] Voltage generator 610 can receive power voltage VIN and clock control signal CPV (sometimes called gate clock control signal CPV), and can convert the clock control signal CPV and output it as gate clock signal CKV. Overcurrent detector 620 can detect the output current of gate clock signal CKV flowing through voltage terminal OP, and output overcurrent detection signal OVER_C.

[0064] The overcurrent detector 620 may include a current sensor 621, an overcurrent detection circuit 622, an overcurrent counter 623, and an overcurrent determination circuit 624. The current sensor 621 can sense the output current of the gate clock signal CKV output through the voltage terminal OP. The overcurrent detection circuit 622 can determine whether the output current level of the gate clock signal CKV is higher than an overcurrent reference current level. Whenever the overcurrent detection circuit 622 sends a signal indicating that the output current level of the gate clock signal CKV is higher than the overcurrent reference current level, the overcurrent counter 623 can count the signals sent from the overcurrent detection circuit 622. The overcurrent counter 623 can be initialized at predetermined time intervals. When the overcurrent count by the overcurrent counter 623 exceeds the reference count, the overcurrent determination circuit 624 can determine the output current of the gate clock signal CKV as an overcurrent state and activate the overcurrent detection signal OVER_C. The voltage generator 610 can receive the overcurrent detection signal OVER_C. When the overcurrent detection signal OVER_C is activated, for example, when the overcurrent detection signal OVER_C is at a high level, the voltage generator 610 can stop generating the internal drive voltage. In other words, the generation of the drive voltage output to the voltage terminal OP is blocked, thereby preventing... Figure 1 The malfunction of the display panel 100 shown can be prevented. Additionally, product defects caused by high heat can be prevented, and risks such as fire can be reduced.

[0065] Figure 5 It is shown Figure 1 Timing diagram of the gate clock control signals CPV1 and CPV2, the gate clock signals CKV1 and CKV2, and the gate clock currents CKV1_C and CKV2_C of the gate driver 300.

[0066] Reference Figures 1 to 5 Gate clock control signals CPV1 and CPV2 can be output from the drive controller 200 to the power voltage generator 600 or the gate driver 300. Gate clock signals CKV1 and CKV2 can be synchronized with gate clock control signals CPV1 and CPV2.

[0067] When the gate clock signals CKV1 and CKV2 switch between the gate on voltage VON and the gate off voltage VOFF (when switching between the gate on voltage VON and the gate off voltage VOFF in the scan (SCAN) segment), the power voltage generator 600 can determine whether the gate clock signals CKV1 and CKV2 are normal.

[0068] After the gate clock signals CKV1 and CKV2 are switched (switched in the scan (SCAN) segment), the power voltage generator 600 according to the present invention can first detect the level of the gate clock signals CKV1 and CKV2 after the rising edge of the gate clock signals CKV1 and CKV2 or after the falling edge of the gate clock signals CKV1 and CKV2.

[0069] For example, Figure 5 The diagram shows the detection levels of the first gate clock signal CKV1 at the first detection point DP1, the second detection point DP2, the third detection point DP3, and the fourth detection point DP4 after the rising edge of the first gate clock signal CKV1.

[0070] The power voltage generator 600 can detect the levels of the gate clock signals CKV1 and CKV2 by determining whether the gate clock currents CKV1_C and CKV2_C are within the normal range after the rising edge of the gate clock signals CKV1 and CKV2 and after the falling edge of the gate clock signals CKV1 and CKV2.

[0071] When the measured gate clock currents CKV1_C and CKV2_C are outside the normal range (sometimes referred to as the preset range), the display device 10 can determine that the gate clock signals CKV1 and CKV2 are at abnormal levels. In this case, the display device 10 can determine that the gate line from which the gate clock signals CKV1 and CKV2 are applied is short-circuited to another wiring. Conversely, when the measured gate clock currents CKV1_C and CKV2_C are within the preset range, the display device 10 can determine that the gate clock signals CKV1 and CKV2 are at normal levels.

[0072] After the switching of gate clock signals CKV1 and CKV2 (switching in the scan (SCAN) segment), the power voltage generator 600 according to the present invention can detect the level of gate clock signals CKV1 and CKV2 a second time immediately before the rising edge of gate clock signals CKV1 and CKV2 or exactly before the falling edge of gate clock signals CKV1 and CKV2.

[0073] According to an embodiment, the power voltage generator 600 can determine whether the gate clock currents CKV1_C and CKV2_C are below the normal cutoff level immediately before the rising edges of the gate clock signals CKV1 and CKV2. For example, Figure 5 The illustration shows the case where the second gate clock current CKV2_C is sensed immediately before the rising edge of the second gate clock signal CKV2 (during time period DT1). Since the second gate clock current CKV2_C sensed immediately before the rising edge of the second gate clock signal CKV2 (during time period DT1) is below the normal cutoff level, the display device 10 can determine that the gate line from which the second gate clock signal CKV2 is applied is short-circuited to another wiring.

[0074] According to an embodiment, the power voltage generator 600 can determine whether the gate clock currents CKV1_C and CKV2_C are higher than the normal cutoff level immediately before the falling edges of the gate clock signals CKV1 and CKV2. For example, Figure 5 The illustration shows the case where the second gate clock current CKV2_C is sensed immediately before the falling edge of the second gate clock signal CKV2 (during time period DT2). Since the second gate clock current CKV2_C sensed immediately before the falling edge of the second gate clock signal CKV2 (during time period DT2) is higher than the normal cutoff level, the display device 10 can determine that the gate line from which the second gate clock signal CKV2 is applied is short-circuited to another wiring.

[0075] Therefore, the display device 10 according to the present invention can sense the abnormal levels of the gate clock signals CKV1 and CKV2 for the first and second time after the switching of the gate clock signals CKV1 and CKV2, and detect the abnormal current levels of the gate clock currents CKV1_C and CKV2_C, so as to solve the problem of overheating and ignition of the display device 10. As a result, the display device 10 according to the present invention can have improved safety and reliability.

[0076] Figure 6 This is a timing diagram illustrating the cut-off process of the power voltage generator 600 of the display device 10 according to an embodiment of the present invention. Figure 7 This is a timing diagram illustrating the cut-off process of the power voltage generator 600 of the display device 10 according to an embodiment of the present invention.

[0077] Reference Figures 1 to 6 The power voltage generator 600 can generate a gate on-state voltage VON, a gate off-state voltage VOFF, and a gate clock signal CKV that switches between the gate on-state voltage VON and the gate off-state voltage VOFF. It can also detect the current level of the gate clock current CKV_C based on the gate clock signal CKV. When the count of the gate clock current CKV_C, which is higher than a first current level OCPLEVEL, exceeds a reference count, the power voltage generator 600 can cut off the power to the display device 10.

[0078] In one embodiment, the power voltage generator 600 can provide power voltage to at least one of the display panel 100, drive controller 200, gate driver 300, gamma reference voltage generator 400, and data driver 500. Specifically, the power voltage generator 600 can generate a gate clock signal CKV for generating a gate signal, as well as a gate on-state voltage VON and a gate off-state voltage VOFF for controlling the operation of the gate driver 300, and output the gate clock signal CKV, the gate on-state voltage VON, and the gate off-state voltage VOFF to the gate driver 300. The power voltage generator 600 can receive a gate clock control signal CPV and a vertical start signal STV from the drive controller 200. The power voltage generator 600 can generate the gate clock signal CKV based on the gate clock control signal CPV and the vertical start signal STV.

[0079] In one embodiment, the power voltage generator 600 may include a voltage generator 610 and an overcurrent detector 620. The voltage generator 610 can receive a power voltage VIN and a clock control signal CPV, and convert the clock control signal CPV into a gate clock signal CKV. The overcurrent detector 620 can detect the output current of the gate clock signal CKV flowing through the voltage terminal OP, and output an overcurrent detection signal OVER_C. Specifically, the overcurrent detector 620 may include a current sensor 621, an overcurrent detection circuit 622, an overcurrent counter 623, and an overcurrent determination circuit 624. The current sensor 621 can sense the gate clock current CKV_C output through the voltage terminal OP. The overcurrent detection circuit 622 can determine whether the gate clock current CKV_C is higher than an overcurrent reference current level. For example, the overcurrent detection circuit 622 can determine whether the gate clock current CKV_C is higher than a first current level OCP LEVEL, and can determine that the gate clock signal CKV is at an abnormal level when the gate clock current CKV_C is greater than the first current level OCP LEVEL. Whenever the overcurrent detection circuit 622 sends a signal indicating that the gate clock current CKV_C is higher than the overcurrent reference current level, the overcurrent counter 623 can count the signals sent from the overcurrent detection circuit 622. For example, whenever the overcurrent detection circuit 622 sends a signal indicating that the output current level of the gate clock current CKV_C is higher than the first current level OCP LEVEL, the overcurrent counter 623 can count the signals sent from the overcurrent detection circuit 622. The overcurrent counter 623 can be initialized at predetermined time intervals. When the count of overcurrent occurrences counted by the overcurrent counter 623 exceeds the reference count, the overcurrent determination circuit 624 can determine the output current of the gate clock signal CKV as an overcurrent state and activate the overcurrent detection signal OVER_C. The reference count can be settable. For example, Figure 6 The example shown has the reference count set to 4; however, the reference count of this invention can be set to a value other than 4. The voltage generator 610 can receive an overcurrent detection signal OVER_C. When the overcurrent detection signal OVER_C is activated, for example, when the overcurrent detection signal OVER_C is at a high level, the voltage generator 610 can stop the generation of the internal drive voltage. In other words, the voltage generator 610 blocks the generation of the drive voltage output to the voltage terminal OP, thus preventing malfunctions of the display panel 100. The voltage generator 610 can prevent the display device 10 from overheating due to high heat and reduces the risk of hazards such as fire.

[0080] In one embodiment, when the display device 10 is turned on, and when the gate clock current CKV_C in the initial frame is greater than or equal to a second current level ICP LEVEL that is greater than a first current level OCP LEVEL, the power voltage generator 600 may cut off the power to the display device 10. (Refer to...) Figures 1 to 7 When the display device 10 is turned on, the overcurrent detector 620 can detect the output current of the gate clock signal CKV flowing through the voltage terminal OP and output an overcurrent detection signal OVER_C. Specifically, when the display device 10 is turned on, the current sensor 621 can sense the gate clock current CKV_C output through the voltage terminal OP. The overcurrent detection circuit 622 can determine whether the gate clock current CKV_C is higher than the second current level ICP LEVEL in the initial frame, and can determine that the gate clock signal CKV is at an abnormal level when the gate clock current CKV_C is higher than the second current level ICP LEVEL. The second current level ICP LEVEL can be higher than the first current level OCP LEVEL. When the overcurrent detection circuit 622 sends a signal indicating that the gate clock current CKV_C is higher than the second current level ICP LEVEL in the initial frame, the overcurrent counter 623 can count the signals from the overcurrent detection circuit 622. When the overcurrent counter 623 counts the occurrence of overcurrents higher than or equal to the second current level ICP LEVEL in the initial frame, the overcurrent determination circuit 624 can determine the output current of the gate clock signal CKV as an overcurrent state and activate the overcurrent detection signal OVER_C. Figure 7As shown, when the gate clock current CKV_C is higher than or equal to the second current level ICP LEVEL in the initial frame after the display device 10 is turned on, the power voltage generator 600 can cut off the power to the display device 10. According to the present invention, the power voltage generator 600 can simultaneously activate a first cutoff mode and a second cutoff mode. The first cutoff mode cuts off the power to the display device 10 when the count of the gate clock current CKV_C, which is higher than or equal to the first current level OCP LEVEL, is greater than or equal to a reference count. The second cutoff mode cuts off the power to the display device 10 when the gate clock current CKV_C is higher than or equal to the second current level ICP LEVEL in the initial frame after the display device 10 is turned on. Therefore, the power voltage generator 600 can improve the safety and reliability of the display device 10 by more sensitively detecting abnormal current levels of the gate clock current CKV_C.

[0081] Figure 8 This is a flowchart illustrating the operation of a display device 10 according to an embodiment of the present invention.

[0082] Reference Figures 3 to 8 The display device 10 can generate a gate on-state voltage VON and a gate off-state voltage VOFF in operation S100, generate a gate clock signal CKV that switches between the gate on-state voltage VON and the gate off-state voltage VOFF in operation S200, and detect the current level of the gate clock current CKV_C based on the gate clock signal CKV in operation S300. In operations S400, S500, and S700, when the count of the gate clock current CKV_C, which is higher than or equal to the first current level OCP LEVEL, is greater than or equal to the reference count, the display device 10 can cut off the power to the display device 10. In operations S600 and S700, when the gate clock current CKV_C, in the initial frame after the display device 10 is turned on, is greater than or equal to the second current level ICP LEVEL, which is greater than the first current level OCP LEVEL, the display device 10 can cut off the power to the display device 10.

[0083] In one embodiment, the display device 10 can generate a gate on-state voltage VON and a gate off-state voltage VOFF in operation S100, generate a gate clock signal CKV that switches between the gate on-state voltage VON and the gate off-state voltage VOFF in operation S200, and detect the current level of the gate clock current CKV_C based on the gate clock signal CKV in operation S300. Specifically, the power voltage generator 600 can provide power voltage to at least one of the display panel 100, the drive controller 200, the gate driver 300, the gamma reference voltage generator 400, and the data driver 500. The power voltage generator 600 can generate the gate clock signal CKV for generating the gate signal and the gate on-state voltage VON and the gate off-state voltage VOFF for controlling the operation of the gate driver 300, and output the gate clock signal CKV, the gate on-state voltage VON, and the gate off-state voltage VOFF to the gate driver 300. The power voltage generator 600 can determine whether the gate clock signal CKV is normal when the gate clock signal CKV switches between the gate on-state voltage VON and the gate off-state voltage VOFF. For example, after the gate clock signals CKV1 and CKV2 are switched, the power voltage generator 600 can first detect the level of the gate clock signals CKV1 and CKV2 after the rising edge of the gate clock signals CKV1 and CKV2 or after the falling edge of the gate clock signals CKV1 and CKV2. Figure 5The diagram illustrates the detection of the level of the first gate clock signal CKV1 at first detection points DP1, second detection point DP2, third detection point DP3, and fourth detection point DP4, following the rising edge of the first gate clock signal CKV1. The power voltage generator 600 can detect the levels of the gate clock signals CKV1 and CKV2 by utilizing whether the gate clock currents CKV1_C and CKV2_C are within normal ranges after the rising and falling edges of the gate clock signals CKV1 and CKV2. When the measured gate clock currents CKV1_C and CKV2_C are outside a preset range, the display device 10 can determine that the gate clock signals CKV1 and CKV2 are at abnormal levels. In this case, the display device 10 can determine that the gate line from which the gate clock signals CKV1 and CKV2 are applied is short-circuited to another wiring. Conversely, when the measured gate clock currents CKV1_C and CKV2_C are within the preset range, the display device 10 can determine that the gate clock signals CKV1 and CKV2 are at normal levels. In another example, after the gate clock signals CKV1 and CKV2 switch, the power voltage generator 600 can perform a secondary detection of the levels of the gate clock signals CKV1 and CKV2 immediately before the rising edge of CKV1 and CKV2 or exactly before the falling edge of CKV1 and CKV2. According to an embodiment, the power voltage generator 600 can determine whether the gate clock currents CKV1_C and CKV2_C are below the normal cutoff level immediately before the rising edge of the gate clock signals CKV1 and CKV2. Figure 5 The illustration shows the case where the second gate clock current CKV2_C is sensed immediately before the rising edge of the second gate clock signal CKV2 (during time period DT1). Since the second gate clock current CKV2_C sensed immediately before the rising edge of the second gate clock signal CKV2 (during time period DT1) is below the normal cutoff level, the display device 10 can determine that the gate line from which the second gate clock signal CKV2 is applied is short-circuited to another wiring. According to an embodiment, the power voltage generator 600 can determine whether the gate clock currents CKV1_C and CKV2_C are above the normal cutoff level immediately before the falling edges of the gate clock signals CKV1 and CKV2. Additionally, Figure 5 The illustration shows the case where the second gate clock current CKV2_C is sensed immediately before the falling edge of the second gate clock signal CKV2 (during time period DT2). Since the second gate clock current CKV2_C sensed immediately before the falling edge of the second gate clock signal CKV2 (during time period DT2) is higher than the normal cutoff level, the display device 10 can determine that the gate line from which the second gate clock signal CKV2 is applied is short-circuited with another wiring.

[0084] Therefore, the display device 10 according to the present invention can sense abnormal levels of gate clock signals CKV1 and CKV2 on both the first and second tests, so as to detect abnormal current levels of gate clock currents CKV1_C and CKV2_C after the gate clock signal CKV switches after the display device 10 is turned on, thereby solving the problems of overheating and ignition of the display device 10. As a result, the display device 10 according to the present invention can have improved safety and reliability.

[0085] In one embodiment, during operations S400, S500, and S700, when the count of the gate clock current CKV_C, which is higher than the first current level OCP LEVEL, exceeds the reference count, the display device 10 can cut off the power to the display device 10. Specifically, the power voltage generator 600 can generate a gate on-state voltage VON, a gate off-state voltage VOFF, and a gate clock signal CKV that switches between the gate on-state voltage VON and the gate off-state voltage VOFF, and can detect the current level of the gate clock current CKV_C based on the gate clock signal CKV. When the count of the gate clock current CKV_C, which is higher than the first current level OCP LEVEL, exceeds the reference count, the power voltage generator 600 can cut off the power to the display device 10. For example, the power voltage generator 600 may include a voltage generator 610 and an overcurrent detector 620. The voltage generator 610 can receive the power voltage VIN and the clock control signal CPV, and can convert the clock control signal CPV and output it as the gate clock signal CKV. The overcurrent detector 620 can detect the output current of the gate clock signal CKV flowing through the voltage terminal OP and output an overcurrent detection signal OVER_C. The overcurrent detector 620 may include a current sensor 621, an overcurrent detection circuit 622, an overcurrent counter 623, and an overcurrent determination circuit 624. The current sensor 621 can sense the gate clock current CKV_C output through the voltage terminal OP. The overcurrent detection circuit 622 can determine whether the gate clock current CKV_C is higher than an overcurrent reference current level. The overcurrent detection circuit 622 can determine whether the gate clock current CKV_C is higher than a first current level OCP LEVEL, and can determine that the gate clock signal CKV is at an abnormal level when the gate clock current CKV_C is greater than the first current level OCP LEVEL. According to an embodiment, the first current level OCP LEVEL can be settable. For example, the first current level OCP LEVEL can be set to a level between 40mA and 60mA. Whenever the overcurrent detection circuit 622 sends a signal indicating that the gate clock current CKV_C is higher than the overcurrent reference current level, the overcurrent counter 623 can count the signals sent from the overcurrent detection circuit 622. Whenever the overcurrent detection circuit 622 sends a signal indicating that the gate clock current CKV_C is higher than the first current level OCP LEVEL, the overcurrent counter 623 can count the signals sent from the overcurrent detection circuit 622. The overcurrent counter 623 can be initialized at predetermined time intervals. When the overcurrent count by the overcurrent counter 623 exceeds the reference count, the overcurrent determination circuit 624 can determine the output current of the gate clock signal CKV as an overcurrent state and activate the overcurrent detection signal OVER_C. The reference count can be settable. For example, the reference count can be set to 4.The voltage generator 610 can receive an overcurrent detection signal OVER_C. When the overcurrent detection signal OVER_C is activated, for example, when the overcurrent detection signal OVER_C is at a high level, the voltage generator 610 can stop the generation of the internal drive voltage. In other words, the voltage generator 610 blocks the generation of the drive voltage output to the voltage terminal OP, thereby preventing malfunctions of the display panel 100. In addition, the voltage generator 610 can prevent the display device 10 from overheating due to high heat and reduce the risk of fire.

[0086] In one embodiment, during operations S600 and S700, when the gate clock current CKV_C is greater than or equal to a second current level ICP LEVEL (which is greater than the first current level OCP LEVEL) in the initial frame after the display device 10 is turned on, the display device 10 can cut off its power. Specifically, the power voltage generator 600 can generate a gate on-state voltage VON, a gate off-state voltage VOFF, and a gate clock signal CKV that switches between the gate on-state voltage VON and the gate off-state voltage VOFF, and can detect the current level of the gate clock current CKV_C based on the gate clock signal CKV. When the display device 10 is turned on, and when the gate clock current CKV_C is greater than or equal to a second current level ICP LEVEL (which is greater than the first current level OCP LEVEL) in the initial frame, the power voltage generator 600 can cut off the power to the display device 10. For example, when the display device 10 is turned on, the current sensor 621 can sense the gate clock current CKV_C output through the voltage terminal OP. The overcurrent detection circuit 622 can determine whether the gate clock current CKV_C is higher than the second current level ICP LEVEL in the initial frame, and can determine that the gate clock signal CKV is at an abnormal level when the gate clock current CKV_C is higher than the second current level ICP LEVEL. The second current level ICP LEVEL can be higher than the first current level OCP LEVEL. According to an embodiment, the second current level ICP LEVEL can be settable. For example, the second current level ICP LEVEL can be set to a level of 150mA. When the overcurrent detection circuit 622 sends a signal indicating that the gate clock current CKV_C is higher than the second current level ICP LEVEL in the initial frame, the overcurrent counter 623 can count the signal from the overcurrent detection circuit 622. When the overcurrent counter 623 counts the occurrence of overcurrents higher than or equal to the second current level ICP LEVEL in the initial frame, the overcurrent determination circuit 624 can determine the output current of the gate clock signal CKV as an overcurrent state and activate the overcurrent detection signal OVER_C. Figure 7As shown, when the gate clock current CKV_C is higher than or equal to the second current level ICP LEVEL in the initial frame after the display device 10 is turned on, the power voltage generator 600 can cut off the power to the display device 10. According to the present invention, the power voltage generator 600 can simultaneously activate a first cutoff mode and a second cutoff mode. The first cutoff mode cuts off the power to the display device 10 when the count of the gate clock current CKV_C, which is higher than or equal to the first current level OCP LEVEL, is greater than or equal to a reference count. The second cutoff mode cuts off the power to the display device 10 when the gate clock current CKV_C is higher than or equal to the second current level ICP LEVEL in the initial frame after the display device 10 is turned on. Therefore, the power voltage generator 600 can improve the safety and reliability of the display device 10 by more sensitively detecting abnormal current levels of the gate clock current CKV_C.

[0087] Figure 9 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the concept of the present invention. Figure 10 It is shown that Figure 9 The diagram shows an example of an electronic device 1000 implemented as a smartphone.

[0088] Reference Figure 9 and Figure 10 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. Additionally, the electronic device 1000 may include multiple ports for communicating with video cards, sound cards, memory cards, Universal Serial Bus (USB) devices, and other electronic devices. In embodiments, such as... Figure 10 As shown, the electronic device 1000 can be implemented as a smartphone. However, in this embodiment, the electronic device 1000 can be implemented as a cellular phone, video phone, smartboard, smartwatch, tablet PC, car navigation system, computer monitor, laptop computer, head-mounted display (HMD) device, etc.

[0089] Processor 1010 can perform various computing functions. Processor 1010 can be a microprocessor, central processing unit (CPU), application processor (AP), etc. Processor 1010 can be integrated with other components via address bus, control bus, data bus, etc. In addition, processor 1010 can be integrated with an expansion bus such as the peripheral component interconnect (PCI) bus. Memory device 1020 can store data for the operation of electronic device 1000. For example, memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase-change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile DRAM device, etc.). Storage device 1030 may include a solid-state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. I / O device 1040 may include input devices such as a keyboard, keypad, mouse device, touchpad, touchscreen, etc., and output devices such as a printer, speaker, etc. In some embodiments, I / O device 1040 may include a display device 1060. Power supply 1050 can provide power for the operation of electronic device 1000.

[0090] Display device 1060 can display an image corresponding to the visual information of electronic device 1000. Display device 1060 may include a display panel, a gate driver, a data driver, and a power voltage generator. The display panel includes gate lines, data lines, and pixels electrically connected to the gate lines and data lines, and is configured to display an image based on input image data. The gate driver is configured to output a gate signal to the gate lines. The data driver is configured to output a data voltage to the data lines. The power voltage generator is configured to generate a gate on-state voltage, a gate off-state voltage, and a gate clock signal switching between the gate on-state voltage and the gate off-state voltage, detect the current level of the gate clock current based on the gate clock signal, and cut off power to the display device when the count of the gate clock current higher than or equal to a first current level is greater than or equal to a reference count. When the gate clock current is higher than or equal to a second current level higher than the first current level in the initial frame after the display device is turned on, the power voltage generator can cut off power to the display device. The display device detects abnormal current levels of the gate clock current after the display device is turned on and cuts off power to the display device when an overcurrent occurs, thereby preventing display panel malfunctions. Furthermore, the display device can be prevented from overheating due to high heat, and the risk of fire is reduced. As a result, the display device of the present invention can improve the safety and reliability of display devices.

[0091] The foregoing is illustrative of the inventive concept and is not to be construed as limiting it. Although some embodiments of the inventive concept have been described, it will be readily understood by those skilled in the art that many modifications can be made to the embodiments without substantially departing from the novel teachings and advantages of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. In the claims, any means plus function clause is intended to cover structures described herein that perform the functions, and not only structural equivalents but also equivalent structures. Therefore, it will be understood that the foregoing is illustrative of the inventive concept and is not to be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The inventive concept is defined by the claims and their equivalents included in the inventive concept.

Claims

1. A display device, the display device comprising: A display panel includes gate lines, data lines, and pixels electrically connected to the gate lines and the data lines, the display panel being configured to display an image based on input image data; A gate driver is configured to output a gate signal to the gate line; A data driver is configured to output a data voltage to the data line; as well as The power voltage generator is configured as follows: Generate a gate on-state voltage, a gate off-state voltage, and a gate clock signal that switches between the gate on-state voltage and the gate off-state voltage; The current level of the gate clock current is detected based on the gate clock signal; When the count of the gate clock current, which is higher than or equal to the first current level, is greater than or equal to the reference count, the power to the display device is cut off. and When the gate clock current is higher than or equal to a second current level higher than the first current level in the initial frame after the display device is turned on, the power to the display device is cut off. Wherein, after the gate clock signal is switched, the power voltage generator detects the current level of the gate clock current immediately before the rising edge of the gate clock signal or immediately before the falling edge of the gate clock signal.

2. The display device according to claim 1, wherein, The power voltage generator simultaneously activates a first cutoff mode and a second cutoff mode. The first cutoff mode cuts off the power to the display device when the count of the gate clock current, which is higher than or equal to the first current level, is greater than or equal to the reference count. The second cutoff mode cuts off the power to the display device when the gate clock current is higher than or equal to the second current level in the initial frame after the display device is turned on.

3. The display device according to claim 2, wherein, The power voltage generator includes: A voltage generator receives a power voltage and a clock control signal, and converts the clock control signal into the gate clock signal; and An overcurrent detector detects the gate clock current flowing through the voltage terminal to output an overcurrent detection signal.

4. The display device according to claim 3, wherein, The overcurrent detector includes: A current sensor for sensing the gate clock current output through the voltage terminal; An overcurrent detection circuit is used to determine whether the gate clock current is higher than or equal to the reference current level; An overcurrent counter for counting the gate clock current that is higher than or equal to the reference current level; and An overcurrent determination circuit is used to determine that the gate clock current is in an overcurrent state when the count counted by the overcurrent counter is greater than or equal to the reference count.

5. The display device according to claim 4, wherein, When the gate clock current is determined to be in the overcurrent state, the overcurrent determination circuit activates the overcurrent detection signal.

6. The display device according to claim 5, wherein, When the overcurrent detection signal is activated, the voltage generator cuts off the power to the display device.

7. A method for driving a display device, the method comprising: Generate gate on-state voltage and gate off-state voltage; Generate a gate clock signal that switches between the gate on voltage and the gate off voltage; The current level of the gate clock current is detected based on the gate clock signal; When the count of the gate clock current, which is higher than or equal to the first current level, is greater than or equal to the reference count, the power to the display device is cut off. and When the gate clock current is higher than or equal to a second current level higher than the first current level in the initial frame after the display device is turned on, the power to the display device is cut off. The detection of the current level of the gate clock current includes: detecting the current level of the gate clock current immediately after the gate clock signal is switched, immediately before the rising edge of the gate clock signal, or immediately before the falling edge of the gate clock signal.

8. The method according to claim 7, wherein, Simultaneously, a first cutoff mode and a second cutoff mode are activated. The first cutoff mode cuts off the power to the display device when the count of the gate clock current, which is higher than or equal to the first current level, is greater than or equal to the reference count. The second cutoff mode cuts off the power to the display device when the gate clock current is higher than or equal to the second current level in the initial frame after the display device is turned on.

9. The method according to claim 8, wherein, Cutting off the power to the display device also includes: Receives power voltage and clock control signals, and converts and outputs the clock control signals as the gate clock signal; and The gate clock current flowing through the voltage terminal is detected, and an overcurrent detection signal is output.

10. The method according to claim 9, wherein, The output of the overcurrent detection signal includes: Sensing the gate clock current output through the voltage terminal; Determine whether the gate clock current is higher than or equal to the reference current level; The gate clock currents that are higher than or equal to the reference current level are counted; and When the count of the gate clock current that is higher than or equal to the reference current level is greater than or equal to the reference count, the gate clock current is determined to be in an overcurrent state.

11. The method according to claim 10, wherein, The output of the overcurrent detection signal also includes: When it is determined that the gate clock current is in the overcurrent state, the overcurrent detection signal is activated.

12. The method according to claim 11, wherein, Converting the clock control signal and outputting it as the gate clock signal includes: When the overcurrent detection signal is activated, the power to the display device is cut off.

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