A semiconductor device and a method of manufacturing the same

Abstract

Embodiments of the present application provide a semiconductor device and a manufacturing method thereof. The method includes: forming columnar channels of a transistor array on the surface of a wafer; wherein, the extending direction of the columnar channels is perpendicular to the surface of the wafer; the columnar channels are arranged in an array in a first direction parallel to the surface of the wafer and a second direction parallel to the surface of the wafer; forming gates on one side wall of each columnar channel of the transistor array, wherein the gates are parallel to the first direction and arranged along the second direction; forming a metal layer between adjacent columnar channels, wherein the metal layer extends along the first direction; forming a source electrode and a drain electrode of the transistor at both ends of each columnar channel in the extending direction of the transistor array respectively. In the embodiments of the present application, the source electrode and the drain electrode are respectively located at both ends of the extending direction of the columnar channel, and the gate is located on one side wall of the columnar channel, reducing the area of the transistor array. Moreover, a metal layer is formed between adjacent columnar channels, which can shield the interference generated by the word line to adjacent columnar channels.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and relates to, but is not limited to, a semiconductor device and a manufacturing method thereof. Background Art

[0002] Transistors are widely used as switching devices or driving devices in electronic devices. For example, transistors can be used in a Dynamic Random Access Memory (DRAM) to control the capacitors in each memory cell, and a transistor array composed of multiple transistors can be used in a semiconductor memory device.

[0003] The transistor array mainly includes a planar transistor array and a buried-channel transistor array. However, whether it is a planar transistor array or a buried-channel transistor array, both will occupy a relatively large area. Summary of the Invention

[0004] In view of this, the main purpose of this application is to provide a semiconductor device and a manufacturing method thereof.

[0005] To achieve the above object, the technical solution of this application is implemented as follows:

[0006] An embodiment of this application provides a manufacturing method of a semiconductor device, where the semiconductor device includes a transistor array; the method includes:

[0007] Forming columnar channels of a transistor array on the surface of a wafer; wherein, the extending direction of the columnar channels is perpendicular to the surface of the wafer; the columnar channels are distributed in an array along a first direction parallel to the surface of the wafer and a second direction parallel to the surface of the wafer;

[0008] Forming a gate on one side wall of each columnar channel of the transistor array, where the gate is parallel to the first direction and arranged along the second direction;

[0009] Forming a metal layer between adjacent columnar channels, where the metal layer extends along the first direction;

[0010] Forming a source electrode and a drain electrode of the transistor at both ends of each columnar channel of the transistor array in the extending direction.

[0011] In the above solution, the gate and the metal layer are formed synchronously.

[0012] In the above solution, forming the columnar channels of the transistor array on the surface of the wafer includes:

[0013] Etching from the surface of the wafer to form the columnar channels distributed in an array and the first grooves between the columnar channels.

[0014] In the above solution, the gates on the sidewalls of adjacent columnar channels are located on different sides.

[0015] In the above solution, the synchronous formation of the gate and the metal layer includes:

[0016] Depositing an insulating material in the first groove to form an insulating layer surrounding each columnar channel;

[0017] Etching the insulating layer to form a second groove exposing one sidewall of each columnar channel and a third groove located between adjacent columnar channels; wherein, the second grooves of adjacent columnar channels are located on different sides, and the second groove and the third groove are located on different sides of the columnar channel;

[0018] Filling the second groove and the third groove with a metal material to form the gate and the metal layer.

[0019] In the above solution, the gates on the sidewalls of adjacent columnar channels are located on the same side.

[0020] In the above solution, the synchronous formation of the gate and the metal layer includes:

[0021] Depositing an insulating material in the first groove to form an insulating layer surrounding each columnar channel;

[0022] Etching the insulating layer to form a second groove exposing one sidewall of each columnar channel and a third groove located between adjacent columnar channels; wherein, the second grooves of adjacent columnar channels are located on the same side, and there is a second groove and a third groove between each adjacent columnar channel;

[0023] Filling the second groove and the third groove with a metal material to form the gate and the metal layer.

[0024] In the above solution, before filling the second groove and the third groove with a metal material, the method further includes:

[0025] Oxidizing the exposed sidewall of the columnar channel through the second groove to form a gate oxide layer on the sidewall of the columnar channel.

[0026] In the above solution, the second groove exposes the columnar channels in the same column in the array distribution of the columnar channels; the gates of the columnar channels in the same column are connected to each other, and the connected gates are the word lines of the columnar channels in the same column.

[0027] In the above solution, a bit line is formed, and the bit line is connected to the source or drain of each transistor in the transistor array;

[0028] A storage capacitor is formed. A first electrode of the storage capacitor is connected to a drain or a source of each transistor in the transistor array, and a second electrode of the storage capacitor is connected to a common terminal. The storage capacitor is used for storing data written into the semiconductor device.

[0029] In the above solution, the metal layer is connected to the common terminal.

[0030] In the above solution, an etching depth of the second groove is greater than an etching depth of the third groove.

[0031] In the above solution, an included angle exists between the first direction and the second direction, and the range of the included angle is: less than or equal to 90 degrees.

[0032] An embodiment of the present application further provides a semiconductor device, including:

[0033] A transistor array having columnar channels; wherein, the columnar channels of the transistor array are arranged in an array along a first direction and a second direction, and an extending direction of the columnar channels is perpendicular to a plane formed by the first direction and the second direction;

[0034] A gate is provided on one side wall of each columnar channel of the transistor array, wherein the gate extends along the first direction;

[0035] A metal layer is provided between adjacent columnar channels, wherein the metal layer extends along the first direction;

[0036] A source and a drain of the transistor are respectively provided at two ends of each columnar channel of the transistor array in the extending direction of the columnar channel.

[0037] In the above solution, a length of the metal layer along the extending direction of the columnar channel is less than a length of the gate along the extending direction of the columnar channel.

[0038] In the above solution, the gates on side walls of adjacent columnar channels are located on different sides; the gate and the metal layer are located on different sides of the columnar channel.

[0039] In the above solution, the gates on side walls of adjacent columnar channels are located on the same side; a gate and a metal layer are provided between each adjacent columnar channels.

[0040] In the above solution, it includes:

[0041] Bit lines, which are connected to sources or drains of the transistors in the transistor array;

[0042] A storage capacitor, wherein a first electrode of the storage capacitor is connected to a drain or a source of each transistor in the transistor array, a second electrode of the storage capacitor is connected to a common terminal, and the storage capacitor is configured to store data written into the semiconductor device.

[0043] In the above solution, the metal layer is connected to the common terminal.

[0044] In the above solution, there is an included angle between the first direction and the second direction, and the range of the included angle is: less than or equal to 90 degrees.

[0045] A method for manufacturing a semiconductor device provided by an embodiment of the present application, the semiconductor device including a transistor array; the method includes: forming columnar channels of the transistor array on the surface of a wafer; wherein, an extending direction of the columnar channels is perpendicular to the surface of the wafer; the columnar channels are arranged in an array along a first direction parallel to the surface of the wafer and a second direction parallel to the surface of the wafer; forming gates on one side wall of each columnar channel of the transistor array, wherein the gates are parallel to the first direction and arranged along the second direction; forming a metal layer between adjacent columnar channels, wherein the metal layer extends along the first direction; forming a source and a drain of a transistor at two ends of each columnar channel of the transistor array in the extending direction respectively. The embodiment of the present application provides a semiconductor device and a method for manufacturing the same. The source and the drain of the transistor array formed by this manufacturing method are respectively located at two ends in the extending direction of the columnar channels, and the extending direction is perpendicular to the surface of the wafer, and the gates are located on one side wall of the columnar channels. In this way, the area of the transistor array is greatly reduced, and the storage density of the device is improved. Further, a metal layer is further formed between adjacent columnar channels, and this metal layer can shield the interference generated by the word line to adjacent columnar channels. Description of the Drawings

[0046] Figure 1A Is a schematic structural diagram of a planar transistor in the related art;

[0047] Figure 1B Is a schematic structural diagram of a buried-channel transistor in the related art;

[0048] Figure 2 Is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

[0049] Figure 3 Is a cross-sectional view of a semiconductor device provided by an embodiment of the present application;

[0050] Figure 4A Is a schematic implementation flow diagram of the manufacturing of a semiconductor device provided by an embodiment of the present application;

[0051] Figure 4BTop view of forming a columnar channel provided by an embodiment of the present application;

[0052] Figure 4C Three-dimensional view of forming a columnar channel provided by an embodiment of the present application;

[0053] Figure 4D Top view of an optional formation of an insulating layer provided by an embodiment of the present application;

[0054] Figure 4E Top view of an optional formation of a second groove and a third groove provided by an embodiment of the present application;

[0055] Figure 4F Top view of an optional formation of a gate oxide layer provided by an embodiment of the present application;

[0056] Figure 4G Top view of an optional formation of a metal layer and a gate provided by an embodiment of the present application;

[0057] Figure 5 Schematic cross-sectional structure diagram of an optional semiconductor device provided by an embodiment of the present application;

[0058] Figure 6A Top view of forming a columnar channel provided by an embodiment of the present application;

[0059] Figure 6B Top view of an optional formation of an insulating layer provided by an embodiment of the present application;

[0060] Figure 6C Top view of an optional formation of a second groove and a third groove provided by an embodiment of the present application;

[0061] Figure 6D Top view of an optional formation of a gate oxide layer provided by an embodiment of the present application;

[0062] Figure 6E Top view of an optional formation of a metal layer and a gate provided by an embodiment of the present application;

[0063] Figure 7 Schematic cross-sectional structure diagram of an optional semiconductor device provided by an embodiment of the present application;

[0064] Figure 8 Top view of an optional formation of an extraction pad provided by an embodiment of the present application;

[0065] Figure 9 Another top view of an optional formation of an extraction pad provided by an embodiment of the present application. Detailed implementation manners

[0066] The technical solution of the present application will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present application and to be able to convey the scope of the present application completely to those skilled in the art.

[0067] In the following paragraphs, the present application will be described more specifically by way of example with reference to the accompanying drawings. The advantages and features of the present application will be more clear according to the following description and the claims. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present application.

[0068] In the embodiments of the present application, terms such as "first" and "second" are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0069] In the embodiments of the present application, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer can extend over the entire underlying or overlying structure, or can have a range smaller than the range of the underlying or overlying structure. In addition, the layer can be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer can be located between the top surface and the bottom surface of the continuous structure, or the layer can be at any horizontal plane between the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically, and / or along an inclined surface.

[0070] It should be noted that the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0071] In the related art, the transistor arrays of mainstream memories include planar transistor arrays and buried channel array transistors (BCAT). However, whether it is a planar transistor array or a buried channel transistor array, the source and drain are both located on the horizontal sides of the gate in terms of structure. Figure 1A FIG. [FIGURE NUMBER] is a schematic structural diagram of a planar transistor array in the related art. Figure 1B FIG. [FIGURE NUMBER] is a schematic structural diagram of a buried channel transistor array in the related art, as Figure 1A and 1B shown. In the related art, the source S and drain D of the transistor are respectively located on the horizontal sides of the gate G. In this structure, the source and drain respectively occupy different positions, resulting in a relatively large area for both the planar transistor array and the buried channel transistor array.

[0072] In addition, since the source and drain of the planar transistor array and the buried-channel transistor array are respectively located on both sides of the gate level, the bit line (BL) and the capacitor in the memory cell of the memory will also be on the same side of the gate. Moreover, in subsequent processes, connections between the bit line, the transistor, and the capacitor, as well as the connection between the word line (WL) and the transistor, etc., need to be implemented. As a result, in the memory array region of the memory, the circuit wiring is relatively complex and the manufacturing process is difficult.

[0073] It should be noted that the number of transistors in the transistor array shown in the following embodiments is only an exemplary illustration and not a limitation on the number of transistors in the transistor array of the present application.

[0074] Based on this, in an embodiment of the present application, a semiconductor device is provided. Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of the semiconductor device provided by the embodiment of the present application. As Figure 2 shown, the semiconductor device 200 includes a transistor array having columnar channels 211. Among them, the columnar channels 211 of the transistor array are arranged in an array in the first direction and the second direction. The extending direction of the columnar channels is perpendicular to the plane formed by the first direction and the second direction. On one side wall of each columnar channel of the transistor array, there is a gate oxide layer 215 and a gate 214, where the gate extends along the first direction. At both ends of the extending direction of each columnar channel of the transistor array, there are a source 212 and a drain 213 of the transistor respectively. The transistor array includes transistors 210 arranged in an array. In the embodiment of the present application, the positions of the source 212 and the drain 213 can be interchanged. Here, the X direction is the first direction, and the Y direction is the second direction. The above semiconductor device enables the source and the drain to be respectively formed at both ends of the columnar channel, avoiding the problem of a relatively large area of the transistor array caused by being formed on both sides of the gate, and can provide a transistor array structure with a smaller area, improving the storage density of the device. However, after further research and analysis of the above semiconductor device, the inventor found that when a single-sided gate structure is adopted, the columnar channels CH2 of the unselected word lines adjacent to the selected word line are easily affected. The main manifestation is that the activities on the adjacent word lines can cause the charge change in the units of the unselected word lines, which poses a risk to the information stored therein. Specifically, please refer to Figure 3 , Figure 3 which is a cross-sectional view of the semiconductor device structure shown in Figure 2 along the AA' direction. When the selected word line connected to the columnar channel CH1 is active, it will interfere with the adjacent columnar channel CH2, affecting the performance of the device. Therefore, further improvement is needed.

[0075] Based on this, an embodiment of the present application provides a manufacturing method of a semiconductor device. Figure 4A It is a schematic flowchart of the implementation of the manufacturing method of the semiconductor device provided by the embodiment of the present application. The specific steps of the manufacturing method of the semiconductor device include:

[0076] Step S401: Form columnar channels of a transistor array on the surface of the wafer; wherein, the extending direction of the columnar channels is perpendicular to the surface of the wafer; the columnar channels are distributed in an array along a first direction parallel to the surface of the wafer and a second direction parallel to the surface of the wafer.

[0077] Step S402: Form gates on one side wall of each columnar channel of the transistor array, wherein the gates are parallel to the first direction and arranged along the second direction.

[0078] Step S403: Form a metal layer between adjacent columnar channels, wherein the metal layer extends along the first direction.

[0079] Step S404: Form a source electrode and a drain electrode of the transistor at both ends of each columnar channel of the transistor array in the extending direction.

[0080] In the embodiment of the present application, the wafer is a single-crystalline silicon material for manufacturing semiconductor devices, which is a silicon wafer formed by steps such as grinding, polishing, and slicing a cylindrical single-crystalline silicon, that is, the wafer. The wafer has two opposite circular surfaces, one of the circular surfaces is the above-mentioned wafer surface, and the other circular surface can be called the back surface of the wafer in the embodiment of the present application.

[0081] Figure 4B - Figure 4G It is a schematic diagram of the technological process of a manufacturing method of a semiconductor device provided by the embodiment of the present application. It should be noted that Figure 4B - Figure 4G Taking the example that the gates on the side walls of adjacent columnar channels are located on different sides for illustration.

[0082] Figure 4B It is a top view of forming columnar channels provided by the embodiment of the present application. As Figure 4B shown, in the embodiment of the present application, columnar channels 401 distributed in an array are formed on the surface of the wafer. The channels are used to transfer charges or stop the transfer of charges under the action of an external electric field, so that the transistor is turned on or off. And the extending direction of each columnar channel is perpendicular to the surface of the wafer. Here, the extending direction of the columnar channel is the current direction when the transistor is turned on. The columnar channels 401 are distributed in an array along a first direction parallel to the surface of the wafer and a second direction parallel to the surface of the wafer. Here, the X direction is the first direction, and the Y direction is the second direction.

[0083] In some embodiments, the forming columnar channels of a transistor array on the surface of the wafer includes:

[0084] Etch from the surface of the wafer to form the columnar channels distributed in an array and the first grooves 402 between the columnar channels.

[0085] Here, processes such as photolithography (PH) or dry etching (ET) can be used to etch the surface of the wafer. For example, electron beam lithography process, plasma etching process, or reactive ion etching process, etc. The embodiments of the present application are not limited.

[0086] Figure 4C It is a perspective view of forming columnar conductive channels provided by the embodiments of the present application. As Figure 4B and 4C shown, during the process of etching the surface of the wafer, a part of the surface of the wafer can be covered by a mask (not shown in the figure), that is, each area where the columnar channels 401 need to be formed. Then, the surface of the wafer is etched. Outside the area covered by the mask, a part of the semiconductor material on the wafer is etched away to form a groove with a certain depth, that is, the above-mentioned first groove 402.

[0087] The etching depth is less than the initial thickness of the wafer, that is, the wafer will not be etched through during the etching process. In this way, the area covered by the mask is not etched away, and columnar channels 401 arranged in an array will be formed on the remaining part of the wafer after etching. The side walls of the columnar channels 401 are exposed in the above-mentioned first grooves 402.

[0088] In addition, the cross-section of the columnar channel 401 can be circular, rectangular, diamond-shaped, or polygonal, etc. The embodiments of the present application are not limited.

[0089] In the embodiments of the present application, by etching the entire surface of the wafer, an array of columnar channels 401 and first grooves 402 with the same depth are synchronously formed, which can simplify the manufacturing process and improve the efficiency.

[0090] In some embodiments, Figure 4D to 4G It is a top view of synchronously forming gates and metal layers for each columnar channel of a transistor array. As Figure 4D to 4G shown, the synchronous formation of the gates and metal layers includes:

[0091] Deposit an insulating material 403 in the first groove 402 to form an insulating layer surrounding each columnar channel;

[0092] Etch the insulating layer to form a second groove 404 exposing one side wall of each columnar channel and a third groove 405 located between adjacent columnar channels; wherein, the second grooves 404 of adjacent columnar channels are located on different sides, and the second groove 404 and the third groove 405 are located on different sides of the columnar channel 401. For details, please refer to Figure 4E ;

[0093] As Figure 4F shown, oxidize the exposed side wall of the columnar channel 401 through the second groove 404 to form a gate oxide layer 406 on the side wall of the columnar channel 401. The process of oxidizing the side wall of the columnar channel exposed in the second groove includes but is not limited to: direct oxidation, alkaline oxidation or acidic oxidation. In the embodiment of the present application, direct oxidation is performed by heating, so that the silicon on the side wall of the columnar channel chemically reacts with the gas containing oxidation substances at high temperature, thereby generating a dense silicon dioxide film on the silicon surface to form the gate oxide layer 406 on the side wall of the columnar channel. The gate oxide layer 406 is an insulating material, for example, silicon dioxide (SiO2), and the gate oxide layer 406 is located between the columnar channel 401 and the gate 407 for electrical isolation to prevent charge leakage caused by direct contact between the gate and the columnar channel.

[0094] As Figure 4G shown, fill the second groove 404 and the third groove 405 with a metal material to form the gate 407 and the metal layer 408. Among them, the filled metal material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al) or other metal materials. In a preferred embodiment, the metal material is tungsten.

[0095] In the embodiment of the present application, the insulating material may be silicon dioxide or other insulating materials. Figure 4D This is a top view of depositing an insulating material in the first groove provided by the embodiment of the present application. As Figure 4D shown, the insulating material SiO2 is filled around each columnar channel 401.

[0096] It should be noted that during the actual deposition of the insulating material, the insulating material SiO2 will cover the surface of the columnar channel 401. Usually, after the deposition is completed, a chemical mechanical polishing (CMP) process is used to polish and remove the excess insulating material SiO2 to expose the surface of the columnar channel 401.

[0097] In the embodiments of the present application, a metal layer is formed synchronously by using the gate formation process, so that the metal layer can be formed without adding extra process steps to shield the interference of the word line on the adjacent columnar channels. Thus, without increasing the process steps, the interference of the word line on the adjacent columnar channels is reduced by the metal layer. That is, the coupling effect between the word line and the adjacent columnar channels is improved.

[0098] In the embodiments of the present application, please refer to Figure 4G , the gates on the side walls of the adjacent columnar channels are located on different sides.

[0099] In the embodiments of the present application, as Figure 4E shown, the second groove 404 exposes the columnar channels 401 in the same column among the columnar channels distributed in an array; the gates of the columnar channels in the same column are connected to each other, and the connected gates are the word lines of the columnar channels in the same column. Among them, the word line can provide a word line voltage, and control the on or off of each transistor through the word line voltage.

[0100] In some embodiments, bit lines connected to the source or drain of each transistor in the transistor array are formed; a storage capacitor is formed, the first electrode of the storage capacitor is connected to the drain or source of each transistor in the transistor array, and the second electrode of the storage capacitor is connected to a common terminal, and the storage capacitor is used to store the data written into the semiconductor device. Here, the above common terminal can be connected to a low voltage terminal, and the low voltage can be -0.5V. In some embodiments, the above common terminal can also be a grounded terminal.

[0101] In some embodiments, the metal layer is connected to the common terminal. In actual applications, the metal layer can be set to be independently powered without being connected to the common terminal according to requirements. In the embodiments of the present application, a low voltage is applied to the metal layer or the metal layer is grounded, so that the metal layer can shield the interference of the word line on the adjacent columnar channels.

[0102] In the embodiments of the present application, the etching depth of the second groove 404 is greater than the etching depth of the third groove 405. The etching depth can be controlled by the process parameters of etching (for example: etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, when the etching rate is constant, the longer the etching time, the deeper the groove formed in the third direction. In an embodiment of the present application, the etching depth of the second groove 404 can be controlled to be greater than the etching depth of the third groove 405 by adjusting the process parameters of etching. The etching method can be dry etching, and the dry etching can be, for example, plasma etching.

[0103] In some embodiments, an included angle exists between the first direction and the second direction, and the range of the included angle is: less than or equal to 90 degrees.

[0104] Figure 5 shows a schematic cross-sectional structure of a semiconductor device formed by the manufacturing method shown Figure 4A . As shown Figure 5 , the semiconductor device includes: a transistor array having columnar channels 501; wherein, the columnar channels of the transistor array are arranged in an array in a first direction and a second direction, and the extending direction of the columnar channels is perpendicular to the plane formed by the first direction and the second direction; on one side wall of each columnar channel of the transistor array, there is a gate 507, wherein, the gate extends along the first direction; there is a metal layer 508 between adjacent columnar channels, wherein, the metal layer 508 extends along the first direction; at both ends of the extending direction of each columnar channel 501 of the transistor array, there are a source electrode 504 and a drain electrode 503 of the transistor respectively. Here, the metal layer 508 and the gate 507 are parallel.

[0105] In some embodiments, referring to Figure 5 , the length of the metal layer 508 along the extending direction of the columnar channel is less than the length of the gate along the extending direction of the columnar channel 501. The above lengths can be controlled by adjusting the etching depths of the third groove and the second groove, and the process parameters of the etching include but are not limited to etching time, etching agent gas flow rate, ratio, pressure, temperature, etc. In a preferred embodiment, by adjusting the process parameters, the length of the formed metal layer 508 along the extending direction of the columnar channel 501 is greater than or equal to one-third of the length of the gate 507 along the extending direction of the columnar channel 501.

[0106] In some embodiments, referring to Figure 5 , the gates on the side walls of adjacent columnar channels 501 are on different sides; the gate and the metal layer 508 are on different sides of the columnar channel, wherein, a gate oxide layer 506 is located between the columnar channel 501 and the gate 507 for electrical isolation to prevent charge leakage caused by direct contact between the gate and the columnar channel.

[0107] In some embodiments, the semiconductor device includes: bit lines connected to the source electrodes or drain electrodes of the transistors in the transistor array; a storage capacitor, the first electrode of the storage capacitor is connected to the drain electrode or source electrode of the transistors in the transistor array through a storage capacitor contact, and the second electrode of the storage capacitor is connected to a common terminal, and the storage capacitor is used to store data written into the semiconductor device.

[0108] Referring to Figure 5, in a specific embodiment, the bit line 510 is connected to the source electrodes of the transistors in the transistor array; the first electrode of the storage capacitor 509 is connected to the drain electrodes 503 of the transistors in the transistor array through the storage capacitor contact 505, and the second electrode of the storage capacitor 509 is connected to a common terminal (not shown in the figure). The storage capacitor 509 is used to store the data written into the semiconductor device.

[0109] In some embodiments, the metal layer 508 is connected to the common terminal, and a voltage is applied to the metal layer through the common terminal. In actual applications, the metal layer can also be set to be independently powered without being connected to the common terminal according to actual requirements.

[0110] In some embodiments, there is an included angle between the first direction and the second direction, and the range of the included angle is: less than or equal to 90 degrees.

[0111] Figure 6A - Figure 6E It is a process schematic diagram of another manufacturing method of the semiconductor device provided by the embodiments of the present application. It should be noted that, Figure 6A - Figure 6E Taking the example that the gates on the side walls of adjacent columnar channels are on the same side for illustration.

[0112] Figure 6A It is a top view of forming columnar channels provided by the embodiments of the present application. As Figure 6A shown, in the embodiments of the present application, columnar channels 601 distributed in an array are formed on the wafer surface. The channels are used to transfer charges or stop the transfer of charges under the action of an external electric field, so that the transistors are turned on or off. And the extending direction of each columnar channel is perpendicular to the wafer surface. Here, the extending direction of the columnar channel is the current direction when the transistor is turned on. The columnar channels 601 are distributed in an array along a first direction parallel to the wafer surface and a second direction parallel to the wafer surface. Here, the X direction is the first direction, and the Y direction is the second direction. In some embodiments, forming the columnar channels of the transistor array on the wafer surface includes:

[0113] Etching from the wafer surface to form the columnar channels 601 distributed in an array and the first grooves 602 between the columnar channels.

[0114] Here, processes such as photolithography (PH) or dry etching (ET) can be used to etch the wafer surface. For example, electron beam lithography process, plasma etching process or reactive ion etching process, etc. The embodiments of the present application do not make limitations.

[0115] In the embodiments of the present application, a metal layer is formed synchronously with the formation process of the gate, so that a metal layer can be formed without adding extra process steps to shield the interference of the word line on the adjacent columnar channels. In this way, without increasing the process steps, the interference of the word line on the adjacent columnar channels is reduced by the metal layer. That is, the coupling effect between the word line and the adjacent columnar channels is improved.

[0116] As Figure 6A shown, during the etching process of the wafer surface, part of the wafer surface can be covered by a mask (not shown in the figure), that is, each area where the columnar channel 601 needs to be formed. Then, the wafer surface is etched. Outside the area covered by the mask, part of the semiconductor material on the wafer is etched away to form a groove with a certain depth, that is, the above-mentioned first groove 602.

[0117] In addition, the cross-section of the columnar channel 601 can be circular, rectangular, diamond-shaped or polygonal, etc., which is not limited in the embodiments of the present application.

[0118] In the embodiments of the present application, by etching the entire wafer surface, an array of columnar channels 601 and first grooves 602 with the same depth are formed synchronously, which can simplify the manufacturing process and improve the efficiency.

[0119] In some embodiments, Figure 6B to 6E is a top view of synchronously forming a gate and a metal layer for each columnar channel of a transistor array. As Figure 6B to 6E shown, the synchronous formation of the gate and the metal layer includes:

[0120] Depositing an insulating material 603 in the first groove 602 to form an insulating layer surrounding each columnar channel;

[0121] Etching the insulating layer to form a second groove 604 exposing one side wall of each columnar channel and a third groove 605 located between adjacent columnar channels; wherein, the second grooves 604 of adjacent columnar channels are located on the same side, and there is a second groove 604 and a third groove 605 between each adjacent columnar channel. For details, please refer to Figure 6C ;

[0122] As Figure 6DAs shown, the side wall of the columnar channel 601 exposed through the second groove 604 is oxidized to form a gate oxide layer 606 on the side wall of the columnar channel 601. The process of oxidizing the side wall of the columnar channel exposed in the second groove includes but is not limited to: direct oxidation, alkaline oxidation or acidic oxidation. In the embodiment of the present application, direct oxidation is carried out by heating, so that the silicon on the side wall of the columnar channel undergoes a chemical reaction with the gas containing the oxidizing substance at a high temperature, thereby generating a dense silicon dioxide film on the silicon surface to form the gate oxide layer 606 on the side wall of the columnar channel. The gate oxide layer 606 is an insulating material, for example, silicon dioxide (SiO2), and the gate oxide layer 606 is located between the columnar channel 601 and the gate 607 for electrical isolation to prevent charge leakage caused by direct contact between the gate and the columnar channel.

[0123] As Figure 6E shown, a metal material is filled in the second groove 604 and the third groove 605 to form the gate 607 and the metal layer 608. Among them, the filled metal material includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al) or other metal materials. In a preferred embodiment, the metal material is tungsten. In the embodiment of the present application, the insulating material may be silicon dioxide or other insulating materials. Figure 6B is a top view structural schematic diagram of depositing an insulating material in the first groove provided by the embodiment of the present application. As Figure 6B shown, the insulating material SiO2 is filled around each columnar channel 601.

[0124] It should be noted that during the actual deposition of the insulating material, the insulating material SiO2 will cover the surface of the columnar channel 601. Usually, after the deposition is completed, a chemical mechanical polishing (CMP) process is used to polish and remove the excess insulating material SiO2 to expose the surface of the columnar channel 601.

[0125] In the embodiment of the present application, please refer to Figure 6E , the gates on the side walls of adjacent columnar channels are located on the same side.

[0126] In the embodiment of the present application, as Figure 6C shown, the second groove 604 exposes the columnar channels 601 in the same column among the columnar channels distributed in an array; the gates of the columnar channels in the same column are connected to each other, and the connected gates are the word lines of the columnar channels in the same column. Among them, the word line can provide a word line voltage and control the on or off of each transistor through the word line voltage.

[0127] In some embodiments, bit lines are formed and connected to the source or drain of each transistor in the transistor array; a storage capacitor is formed, a first electrode of the storage capacitor is connected to the drain or source of each transistor in the transistor array, and a second electrode of the storage capacitor is connected to a common terminal, and the storage capacitor is used to store data written into the semiconductor device. Here, the above-mentioned common terminal may be connected to a low-voltage terminal, and the low voltage may be -0.5V. In some embodiments, the above-mentioned common terminal may also be a grounded terminal.

[0128] In some embodiments, the metal layer is connected to the common terminal. In actual applications, the metal layer can be set to be independently powered and not connected to the common terminal according to requirements.

[0129] In the embodiments of the present application, the etching depth of the second groove 604 is greater than the etching depth of the third groove 605. The etching depth can be controlled by etching process parameters (such as: etching time, gas flow rate, ratio, pressure, temperature, etc.). For example, when the etching rate is constant, the longer the etching time, the deeper the groove formed in the third direction. In an embodiment of the present application, the etching depth of the second groove 604 can be controlled to be greater than the etching depth of the third groove 605 by adjusting the etching process parameters. The etching method can be dry etching, and the dry etching can be, for example, plasma etching.

[0130] In some embodiments, an included angle exists between the first direction and the second direction, and the range of the included angle is: less than or equal to 90 degrees.

[0131] Figure 7 Shows through Figure 4A A cross-sectional structural schematic diagram of another semiconductor device formed by the manufacturing method shown. As Figure 7 shown, the semiconductor device includes: a transistor array having columnar channels 701; wherein, the columnar channels of the transistor array are arranged in an array along a first direction and a second direction, and the extending direction of the columnar channels is perpendicular to the plane formed by the first direction and the second direction; a gate 707 is provided on one side wall of each columnar channel of the transistor array, wherein the gate extends along the first direction; a metal layer 708 is provided between adjacent columnar channels, wherein the metal layer 708 extends along the first direction; the two ends of each columnar channel 701 of the transistor array in the extending direction thereof respectively have a source 704 and a drain 703 of the transistor. Here, the metal layer 708 and the gate 707 are parallel.

[0132] In some embodiments, please refer to Figure 7, the length of the metal layer 708 along the extending direction of the columnar channel is less than the length of the gate along the extending direction of the columnar channel 701. The above lengths can be controlled by adjusting the etching depths of the third groove and the second groove. The process parameters of etching include but are not limited to etching time, etching agent gas flow rate, ratio, pressure, temperature, etc. In a preferred embodiment, by adjusting the process parameters, the length of the formed metal layer 708 along the extending direction of the columnar channel 701 is greater than or equal to one-third of the length of the gate 707 along the extending direction of the columnar channel 701.

[0133] In some embodiments, refer to Figure 7 , the gates 707 on the sidewalls of adjacent columnar channels 701 are located on the same side; there is a gate 707 and a metal layer 708 between each adjacent columnar channel 701. Among them, the gate oxide layer 506 is located between the columnar channel 501 and the gate 507 for electrical isolation to avoid charge leakage caused by direct contact between the gate and the columnar channel.

[0134] In some embodiments, the semiconductor device further includes: bit lines connected to the source or drain of each transistor in the transistor array; a storage capacitor, the first electrode of the storage capacitor is connected to the drain or source of each transistor in the transistor array through a storage capacitor contact, and the second electrode of the storage capacitor is connected to a common terminal. The storage capacitor is used to store data written into the semiconductor device.

[0135] In some embodiments, there is an included angle between the first direction and the second direction, and the range of the included angle is: less than or equal to 90 degrees.

[0136] Refer to Figure 7 , in a specific embodiment, the bit line 710 is connected to the source of each transistor in the transistor array; the first electrode of the storage capacitor 709 is connected to the drain 703 of each transistor in the transistor array through a storage capacitor contact 705, and the second electrode of the storage capacitor 709 is connected to a common terminal (not shown in the figure). The storage capacitor 709 is used to store data written into the semiconductor device.

[0137] In some embodiments, the metal layer 708 is connected to the common terminal. The metal layer can be led out and connected to the common terminal at a suitable position in a buried manner, and a voltage is applied to the metal layer through the common terminal. In actual applications, the metal layer can also be set to be independently powered and not connected to the common terminal according to actual requirements.

[0138] Figure 8 This is a top view of an optional way to form an extraction pad provided by an embodiment of the present application. The bit line 810 is connected to the source or drain of each transistor in the transistor array, as Figure 8As shown, when the distance between the word line and the metal layer is small, the lead pads 802 of the metal layer and the lead pads 801 of the word line need to be staggered (arranged on different sides) to avoid short - circuiting between the word line and the metal layer. At the same time, the device size can be reduced and the space utilization rate can be improved.

[0139] Figure 9 Another optional top - view diagram of forming lead pads provided by an embodiment of the present application. The bit line 910 is connected to the source or drain of each transistor in the transistor array, as Figure 9 shown, when the distance between the word line and the metal layer permits, the lead pads 902 of the metal layer and the lead pads 901 of the word line can be arranged on the same side, which is convenient for actual control.

[0140] The present application provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a transistor array. The method includes: forming columnar channels of the transistor array on the surface of the wafer; wherein, the extending direction of the columnar channels is perpendicular to the surface of the wafer; the columnar channels are arranged in an array along a first direction parallel to the surface of the wafer and a second direction parallel to the surface of the wafer; forming a gate on one side wall of each columnar channel of the transistor array, wherein, the gate is parallel to the first direction and arranged along the second direction; forming a metal layer between adjacent columnar channels, wherein, the metal layer extends along the first direction; forming a source and a drain of the transistor at both ends of each columnar channel of the transistor array in the extending direction respectively. Through the embodiment of the present application, a semiconductor device and a manufacturing method thereof are provided. The source and the drain of the transistor array formed by this manufacturing method are respectively located at both ends of the extending direction of the columnar channels, and the extending direction is perpendicular to the surface of the wafer, and the gate is located on one side wall of the columnar channel. Thus, the area of the transistor array is greatly reduced and the storage density of the device is improved. Further, a metal layer is also formed between adjacent columnar channels, and this metal layer can shield the interference generated by the word line to adjacent columnar channels.

[0141] It should be understood that the "one embodiment" or "some embodiments" mentioned throughout the specification means that specific features, structures, or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, the "in one embodiment" or "in some embodiments" that appear throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the magnitudes of the serial numbers of the above - mentioned processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The serial numbers of the embodiments of the present application above are only for description and do not represent the advantages and disadvantages of the embodiments.

[0142] As described above, it is only the specific implementation manner of the present application. However, the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claimed rights.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes a transistor array; the method includes: Forming columnar channels of the transistor array on the wafer surface; wherein, the extending direction of the columnar channels is perpendicular to the wafer surface; the columnar channels are arrayed in a first direction parallel to the wafer surface and a second direction parallel to the wafer surface; Forming gates on one side wall of each columnar channel of the transistor array, wherein the gates are parallel to the first direction and arranged along the second direction; Forming a metal layer between adjacent columnar channels, wherein the metal layer extends along the first direction; Forming a source electrode and a drain electrode of the transistor at both ends of each columnar channel in the extending direction of the transistor array; Forming a storage capacitor, the first electrode of the storage capacitor is connected to the drain electrode or the source electrode of each transistor in the transistor array, the second electrode of the storage capacitor is connected to a common terminal, and the storage capacitor is used to store data written into the semiconductor device.

2. The method according to claim 1, wherein Forming the gates and the metal layer synchronously.

3. The method according to claim 2, wherein The forming of the columnar channels of the transistor array on the wafer surface includes: Etching from the wafer surface to form the arrayed columnar channels and the first grooves between the columnar channels.

4. The method according to claim 3, characterized in that, The gates on the side walls of adjacent columnar channels are located on different sides.

5. The method according to claim 4, wherein The synchronously forming the gates and the metal layer includes: Depositing an insulating material in the first grooves to form an insulating layer surrounding each columnar channel; Etching the insulating layer to form second grooves exposing one side wall of each columnar channel and third grooves located between adjacent columnar channels; wherein, the second grooves of adjacent columnar channels are located on different sides, and the second grooves and the third grooves are located on different sides of the columnar channels; Filling the second grooves and the third grooves with a metal material to form the gates and the metal layer.

6. The method according to claim 3, wherein The gates on the side walls of adjacent columnar channels are located on the same side.

7. The method according to claim 6, characterized in that, The synchronously forming the gates and the metal layer includes: Depositing an insulating material in the first grooves to form an insulating layer surrounding each columnar channel; Etching the insulating layer to form second grooves exposing one side wall of each columnar channel and third grooves located between adjacent columnar channels; wherein, the second grooves of adjacent columnar channels are located on the same side, and there is a second groove and a third groove between each adjacent columnar channel; Filling the second grooves and the third grooves with a metal material to form the gates and the metal layer.

8. The method according to claim 5 or 7, characterized in that, Before filling the second grooves and the third grooves with a metal material, the method further includes: Performing an oxidation treatment on the exposed side wall of the columnar channel through the second groove to form a gate oxide layer on the side wall of the columnar channel.

9. The method according to claim 5 or 7, characterized in that, The second grooves expose the columnar channels in the same column of the arrayed columnar channels; the gates of the columnar channels in the same column are connected to each other, and the connected gates are the word lines of the columnar channels in the same column.

10. The method according to claim 1, wherein The method further includes: Forming bit lines, the bit lines are connected to the source electrode or the drain electrode of each transistor in the transistor array.

11. The method according to claim 10, wherein the metal layer is connected to the common terminal.

12. The method according to claim 5 or 7, characterized in that the etching depth of the second groove is greater than that of the third groove.

13. The method according to claim 1, wherein an angle exists between the first direction and the second direction, and the range of the angle is less than or equal to 90 degrees.

14. A semiconductor device, characterized in that, comprising: a transistor array having columnar channels; wherein, the columnar channels of the transistor array are arranged in an array along a first direction and a second direction, and the extending direction of the columnar channels is perpendicular to the plane formed by the first direction and the second direction; a gate is provided on one side wall of each columnar channel of the transistor array, wherein the gate extends along the first direction; a metal layer exists between adjacent columnar channels, wherein the metal layer extends along the first direction; the two ends of the extending direction of each columnar channel of the transistor array are respectively provided with a source electrode and a drain electrode of the transistor; a storage capacitor, a first electrode of the storage capacitor is connected to the drain electrode or the source electrode of each transistor in the transistor array, a second electrode of the storage capacitor is connected to the common terminal, and the storage capacitor is used for storing data written into the semiconductor device.

15. The semiconductor device according to claim 14, characterized in that, the length of the metal layer along the extending direction of the columnar channel is less than the length of the gate along the extending direction of the columnar channel.

16. The semiconductor device according to claim 14, wherein the gates on the side walls of adjacent columnar channels are located on different sides; the gate and the metal layer are located on different sides of the columnar channel.

17. The semiconductor device according to claim 14, wherein, the gates on the side walls of adjacent columnar channels are located on the same side; a gate and a metal layer exist between each adjacent columnar channels.

18. The semiconductor device according to claim 14, wherein, comprising: bit lines, which are connected to the source electrodes or the drain electrodes of the transistors in the transistor array.

19. The semiconductor device according to claim 18, wherein the metal layer is connected to the common terminal.

20. The semiconductor device according to claim 14, characterized in that, an angle exists between the first direction and the second direction, and the range of the angle is less than or equal to 90 degrees.

Images