Flash memory device and method for manufacturing the same

Abstract

The present invention provides a flash memory device and a manufacturing method thereof. Among them, the manufacturing method of the flash memory device includes: providing a substrate, on which a floating gate material layer, a control gate material layer, and a hard mask layer are sequentially formed, and a first opening exposing the substrate is formed on the floating gate material layer, the control gate material layer, and the hard mask layer; forming a first sidewall on the sidewall and bottom of the first opening; etching the first sidewall at the bottom of the first opening and a part of the substrate downward along the first opening to form a second opening, so that the bottom of the second opening is lower than the surface of the substrate by a set distance; and forming a second sidewall on the sidewall and bottom of the second opening, and forming a word line in the second opening. By etching a part of the substrate, the present invention makes the bottom of the subsequently formed word line lower than the substrate surface, thereby increasing the effective length of the word line, reducing the short-channel effect of the flash memory device, and improving the writing efficiency of the flash memory device.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit manufacturing technology, and in particular to a flash memory device and a manufacturing method thereof. Background Art

[0002] As a non-volatile memory, flash memory devices have the characteristics of convenience, high storage density, strong reliability, etc., and are widely used. The structures of existing flash memory devices usually include split-gate structures, stacked-gate structures or combinations thereof. Among them, split-gate flash memory devices have the characteristic of high programming efficiency.

[0003] With the development of advanced semiconductor manufacturing processes, the capacity requirements of NOR flash memories are gradually increasing. In order to increase the capacity while reducing the area, it is usually necessary to further reduce the minimum size of flash memory devices. However, as the area of the flash memory device is reduced, the short-channel effect of the flash memory device becomes more prominent, which becomes a key factor restricting the write efficiency of the flash memory device. At the same time, the increase in the capacity of the flash memory device also makes the read disturb problem of the flash memory device more serious.

[0004] In view of this, a method is needed to improve the short-channel effect and read disturb problem of flash memory devices during the process of reducing the area and increasing the capacity of flash memory devices. Summary of the Invention

[0005] The purpose of the present invention is to provide a flash memory device and a manufacturing method thereof, which increase the effective length of the word line, reduce the short-channel effect of the flash memory device, and improve the write efficiency.

[0006] To achieve the above object, the present invention provides a manufacturing method of a flash memory device, including:

[0007] Providing a substrate, on which a floating gate material layer, a control gate material layer and a hard mask layer are sequentially formed, and a first opening exposing the substrate is formed on the floating gate material layer, the control gate material layer and the hard mask layer;

[0008] Forming a first sidewall on the sidewall and bottom of the first opening;

[0009] Etching the first sidewall at the bottom of the first opening and part of the substrate downward along the first opening to form a second opening, so that the bottom of the second opening is lower than the surface of the substrate by a set distance; and,

[0010] Forming a second sidewall on the sidewall and bottom of the second opening, and forming a word line in the second opening.

[0011] Optionally, the set distance is

[0012] Optionally, the thickness of the second sidewall formed between the word line and the substrate ranges from

[0013] Optionally, the thickness of the second sidewall is less than that of the first sidewall.

[0014] Optionally, the process of forming the first opening includes:

[0015] Etching the hard mask layer to form a third opening exposing the control gate material layer, and forming a third sidewall on the sidewalls of the third opening;

[0016] Etching the control gate material layer downward along the third opening to form a fourth opening exposing the floating gate material layer, and forming a fourth sidewall on the sidewalls of the fourth opening; and,

[0017] Etching the floating gate material layer downward along the fourth opening to form the first opening.

[0018] Optionally, the fourth sidewall covers the sidewalls of the third sidewall, the first sidewall covers the sidewalls of the fourth sidewall, and the second sidewall covers the sidewalls of the first sidewall.

[0019] Optionally, after forming the word line, it further includes: removing part of the control gate material layer and the floating gate material layer, and retaining the control gate material layer and the floating gate material layer below the third sidewall to form the control gate and the floating gate.

[0020] Correspondingly, the present invention further provides a flash memory device, including:

[0021] A substrate;

[0022] A word line disposed on the substrate, and the bottom of the word line penetrates into the substrate by a set distance;

[0023] A floating gate disposed on the surfaces of the substrate on both sides of the word line;

[0024] A control gate disposed on the surface of the floating gate;

[0025] Wherein, a first sidewall is further disposed on the sidewall of the floating gate close to the word line, and a second sidewall is further disposed between the word line and the substrate, the floating gate and the control gate, and the second sidewall covers the sidewall of the first sidewall.

[0026] Optionally, the set distance is

[0027] Optionally, a third sidewall is further disposed on the surface of the control gate, and a fourth sidewall is further disposed on the sidewall of the control gate close to the word line side. The fourth sidewall covers the sidewall of the third sidewall, and the first sidewall covers the sidewall of the fourth sidewall.

[0028] Optionally, the thickness of the second sidewall is less than the thickness of the first sidewall.

[0029] Optionally, the thickness range of the second sidewall located between the word line and the substrate is

[0030] In summary, the present invention provides a flash memory device and a manufacturing method thereof. Wherein, the manufacturing method of the flash memory device includes: providing a substrate, on which a floating gate material layer, a control gate material layer and a hard mask layer are sequentially formed, and a first opening exposing the substrate is formed on the floating gate material layer, the control gate material layer and the hard mask layer; forming a first sidewall on the sidewall and the bottom of the first opening; etching the first sidewall at the bottom of the first opening and part of the substrate downward along the first opening to form a second opening, so that the bottom of the second opening is lower than the surface of the substrate by a set distance; and forming a second sidewall on the sidewall and the bottom of the second opening, and forming a word line in the second opening. By etching part of the substrate in the present invention, the bottom of the subsequently formed word line is lower than the substrate surface, thereby increasing the effective length of the word line, reducing the short-channel effect of the flash memory device, and improving the writing efficiency of the flash memory device.

[0031] Further, the thickness range of the second sidewall between the word line and the substrate is reduced to The read voltage applied to the word line during the read operation of the flash memory device is reduced, effectively improving the read interference problem of the flash memory device and extending the service life of the flash memory device. Description of the Drawings

[0032] Figure 1 is a flowchart of a manufacturing method of a flash memory device provided by an embodiment of the present invention;

[0033] Figures 2 - 7 are schematic structural diagrams corresponding to each step in the manufacturing method of a flash memory device provided by an embodiment of the present invention;

[0034] Figure 8 is a schematic structural diagram of an existing flash memory device;

[0035] Wherein, the reference numerals are as follows:

[0036] 100 - Substrate; 110 - Floating gate material layer; 111 - Floating gate; 120 - Control gate material layer; 121 - Control gate; 130 - Hard mask layer; 131 - Third opening; 132 - Third sidewall; 133 - Fourth opening; 134 - Fourth sidewall; 140 - First opening; 141 - First sidewall; 142 - Second opening; 143 - Second sidewall; 150 - Word line;

[0037] 200 - Substrate; 201 - Tunneling oxide layer; 211 - Floating gate; 250 - Word line. Detailed implementation manners

[0038] The following will describe the detailed implementation manners of the present invention in more detail with reference to the schematic diagrams. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non - precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0039] Figure 1 It is a flowchart of a manufacturing method of a flash memory device provided in an embodiment of the present invention. Refer to Figure 1 In this embodiment, the manufacturing method of the flash memory device described includes:

[0040] Step S01: Provide a substrate, on which a floating gate material layer, a control gate material layer, and a hard mask layer are sequentially formed, and a first opening exposing the substrate is formed on the floating gate material layer, the control gate material layer, and the hard mask layer;

[0041] Step S02: Form a first sidewall on the sidewall and bottom of the first opening;

[0042] Step S03: Etch the first sidewall at the bottom of the first opening and part of the substrate downward along the first opening to form a second opening, so that the bottom of the second opening is lower than the surface of the substrate by a set distance; and,

[0043] Step S04: Form a second sidewall on the sidewall and bottom of the second opening, and form a word line in the second opening.

[0044] Figures 2 - 7 It is a schematic diagram of the structure corresponding to each step in the manufacturing method of the flash memory device provided in an embodiment of the present invention. The following will describe in detail the manufacturing method of the flash memory device described in this embodiment with reference to Figures 2 - 7 in detail.

[0045] First, refer to Figures 2 - 4, perform step S01, provide a substrate 100, on which a floating gate material layer 110, a control gate material layer 120, and a hard mask layer 130 are sequentially formed, and a first opening 140 exposing the substrate 100 is formed on the floating gate material layer 110, the control gate material layer 120, and the hard mask layer 130. Exemplarily, the process of forming the first opening 140 includes: Refer to Figure 2 , etch the hard mask layer 130 to form a third opening 131 exposing the control gate material layer 120, and form a third sidewall 132 on the sidewall of the third opening 131; Refer to Figure 3 , etch the control gate material layer 120 downward along the third opening 131 to form a fourth opening 133 exposing the floating gate material layer 110, and form a fourth sidewall 134 on the sidewall of the fourth opening 133; and, Refer to Figure 4 , etch the floating gate material layer 110 downward along the fourth opening 133 to form the first opening 140.

[0046] In this embodiment, the substrate 100 is a silicon substrate, the floating gate material layer 110 and the control gate material layer 120 are both polysilicon layers, and the hard mask layer 130 is a silicon nitride layer. In other embodiments of the present invention, the material selected for the substrate 100 may be at least one of the materials mentioned below: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors. The substrate 100 may also be a multi-layer structure composed of these semiconductor materials or be silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeO), etc. The present invention does not limit this.

[0047] Next, continue to refer to Figure 4 , perform step S02, form a first sidewall 141 on the sidewall and bottom of the first opening 140. In this embodiment, the first sidewall 141 covers the sidewall of the fourth sidewall 134, and the fourth sidewall 134 covers the sidewall of the third sidewall 132.

[0048] Next, refer to Figure 5 , perform step S03, etch the first sidewall 141 at the bottom of the first opening 140 and a part of the substrate 100 downward along the first opening 140 to form a second opening 142, so that the bottom of the second opening 142 is lower than the surface of the substrate 100 by a set distance. In this embodiment, the set distance is

[0049] Subsequently, refer to Figure 6, perform step S04 to form a second sidewall 143 on the sidewall and bottom of the second opening 142, and form a word line 150 in the second opening 142. Optionally, the second sidewall 143 covers the sidewall of the first sidewall 141, the thickness of the second sidewall 143 is less than the thickness of the first sidewall 141, and the thickness range of the second sidewall formed between the word line 150 and the substrate 100 is

[0050] In addition, referring to Figure 7 , after forming the word line 150, it further includes: removing part of the control gate material layer 120 and the floating gate material layer 110, and retaining the control gate material layer 120 and the floating gate material layer 110 below the third sidewall 132 to form the control gate 121 and the floating gate 111. Optionally, a gate oxide layer (not labeled in the figure) is further formed between the substrate 100 and the floating gate 111, and an inter-gate dielectric layer (not labeled in the figure) is further formed between the floating gate 111 and the control gate 121.

[0051] It should be noted that in the manufacturing method of existing flash memory devices, the word line is usually formed after step S02, that is, the word line is formed in the first opening after forming the first sidewall. At this time, part of the first sidewall located between the word line and the substrate is the tunneling oxide layer of the flash memory device. At this time, the thickness of the tunneling oxide layer (i.e., the thickness of the first sidewall) is usually In this embodiment, part of the second sidewall between the word line and the substrate is the tunneling oxide layer of the flash memory device. At this time, the thickness of the tunneling oxide layer (the thickness of the second sidewall) is It can be seen that the manufacturing method of the flash memory device in this embodiment thins the thickness of the tunneling oxide layer in the flash memory device, thereby reducing the read voltage required to be applied to the word line during the read operation of the flash memory device, and further effectively improving the read interference problem of the flash memory device.

[0052] In this embodiment, a self-alignment process is used to form the basic structure of the flash memory device (i.e., the word line 150, the floating gate 111, and the control gate 121). In other embodiments of the present invention, the method of forming the word line 150, the floating gate 111, and the control gate 121 can be adjusted according to actual needs, and the present invention does not limit this. In other embodiments of the present invention, the manufacturing method of the flash memory device can also be used to manufacture other semiconductor devices with the same structure, and the present invention does not limit this.

[0053] Correspondingly, referring to Figure 7 , this embodiment further provides a flash memory device, including:

[0054] Substrate 100;

[0055] Word line 150, disposed on the substrate 100, and the bottom of the word line 150 penetrates into the substrate 100 by a set distance;

[0056] Floating gate 111, disposed on the surfaces of the substrate 100 on both sides of the word line 150;

[0057] Control gate 121, disposed on the surface of the floating gate 111;

[0058] Wherein, a first sidewall 141 is further disposed on the sidewall of the floating gate 111 close to the word line 150, and a second sidewall 143 is further disposed between the word line 150, the substrate 100, the floating gate 111 and the control gate 121, and the second sidewall 143 covers the sidewall of the first sidewall 141.

[0059] In this embodiment, the set distance is Optionally, a gate oxide layer (not labeled in the figure) is further disposed between the substrate 100 and the floating gate 111, and an inter-gate dielectric layer (not labeled in the figure) is further disposed between the floating gate 111 and the control gate 121.

[0060] In this embodiment, a third sidewall 132 is further disposed on the surface of the control gate 121, and a fourth sidewall 134 is further disposed on the sidewall of the control gate 121 close to the word line 150. The fourth sidewall 134 covers the sidewall of the third sidewall 132, and the first sidewall 141 covers the sidewall of the fourth sidewall 134. Optionally, the thickness of the second sidewall 143 is less than the thickness of the first sidewall 141, and the thickness range of the second sidewall 143 between the word line 150 and the substrate 100 is

[0061] Optionally, when performing a write operation, the two control gates 121 of the flash memory device are respectively connected to a first programming voltage (for example, 6V) and a second programming voltage (for example, 9V), the word line 150 is connected to a third programming voltage (for example, 1.3V), and when a bit line (not shown in the figure) of the flash memory device is connected to a fourth programming voltage (for example, 4.9V), at this time, the programming current of the flash memory device is 4 μA. When performing a read operation, the two control gates 121 of the flash memory device are respectively connected to a first read voltage (for example, 0V) and a second read voltage (for example, 5.4V), the word line 150 is connected to a third read voltage (for example, 3V), and the two bit lines (not shown in the figure) on both sides of the word line 150 are respectively connected to a fourth read voltage (for example, 0V) and a fifth read voltage (for example, 0.8V).

[0062] Figure 8It is a schematic structural diagram of an existing flash memory device. In comparison Figure 7 and Figure 8 it can be seen that the bottom of the word line 250 in the existing flash memory device is higher than the surface of the substrate 200, while the bottom of the word line in the flash memory device described in this embodiment penetrates into the substrate. Therefore, with the same device size and area, the effective length (i.e., the length in the vertical direction) of the word line in the flash memory device described in this embodiment is longer, thereby reducing the short-channel effect of the flash memory device. When performing a write operation, electrons (the movement path of the electrons is shown by the dotted line) in the existing flash memory device move horizontally and finally enter the floating gate 211; while in the flash memory device described in this embodiment, electrons (the movement path of the electrons is shown by the dotted line) move around the bottom of the word line 150 and finally enter the floating gate 111. Since the movement direction of the electrons after bypassing the word line 150 is perpendicular to the surface of the floating gate 111, the electrons are more likely to be injected into the floating gate 111 under the action of the vertical electric field, thereby improving the write efficiency.

[0063] In addition, continuing to refer to Figure 7 and Figure 8 , the thickness of the tunneling oxide layer 201 between the word line 250 and the substrate 200 in the existing flash memory device (for example, ) is significantly greater than the thickness of the second sidewall 143 between the word line 150 and the substrate 100 in the flash memory device described in this embodiment (for example, ). Therefore, when performing a read operation, the read voltage (for example, 3V) required to be applied to the word line of the flash memory device described in this embodiment is lower than the read voltage (for example, 4.2V) required to be applied to the word line of the existing flash memory device, thereby effectively improving the read interference problem of the flash memory device and extending the service life of the flash memory device.

[0064] In summary, the present invention provides a flash memory device and a manufacturing method thereof. The manufacturing method of the flash memory device includes: providing a substrate, on which a floating gate material layer, a control gate material layer, and a hard mask layer are sequentially formed, and a first opening exposing the substrate is formed on the floating gate material layer, the control gate material layer, and the hard mask layer; forming a first sidewall on the sidewall and bottom of the first opening; etching the first sidewall at the bottom of the first opening and part of the substrate downward along the first opening to form a second opening, so that the bottom of the second opening is lower than the surface of the substrate by a set distance; and forming a second sidewall on the sidewall and bottom of the second opening, and forming a word line in the second opening. The present invention etches part of the substrate to make the bottom of the subsequently formed word line lower than the substrate surface, thereby increasing the effective length of the word line, reducing the short-channel effect of the flash memory device, and improving the write efficiency of the flash memory device.

[0065] Further, the thickness range of the second sidewall between the word line and the substrate is reduced to The read voltage applied to the word line during the read operation of the flash memory device is reduced, effectively improving the read interference problem of the flash memory device and extending the service life of the flash memory device.

[0066] The above are only the preferred embodiments of the present invention and do not impose any limitation on the present invention. Any person skilled in the art, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, all of which belong to the content of the technical solution of the present invention and are still within the protection scope of the present invention.

Claims

1. A manufacturing method of a flash memory device, characterized in that, Comprising: Providing a substrate, on which a floating gate material layer, a control gate material layer, and a hard mask layer are sequentially formed, and a first opening exposing the substrate is formed on the floating gate material layer, the control gate material layer, and the hard mask layer; Forming a first sidewall on the sidewall and bottom of the first opening; Etching the first sidewall at the bottom of the first opening and part of the substrate downward along the first opening to form a second opening, such that the bottom of the second opening is lower than the surface of the substrate by a set distance; And, Forming a second sidewall on the sidewall and bottom of the second opening, and forming a word line in the second opening; wherein, the thickness range of the second sidewall formed between the word line and the substrate is 2. The manufacturing method of the flash memory device according to claim 1, characterized in that, The set distance is 3. The manufacturing method of the flash memory device according to claim 1 or 2, characterized in that, The thickness of the second sidewall is less than the thickness of the first sidewall.

4. The manufacturing method of the flash memory device according to claim 1, characterized in that, The process of forming the first opening includes: Etching the hard mask layer to form a third opening exposing the control gate material layer, and forming a third sidewall on the sidewall of the third opening; Etching the control gate material layer downward along the third opening to form a fourth opening exposing the floating gate material layer, and forming a fourth sidewall on the sidewall of the fourth opening; and, Etching the floating gate material layer downward along the fourth opening to form the first opening.

5. The manufacturing method of the flash memory device according to claim 4, characterized in that, The fourth sidewall covers the sidewall of the third sidewall, the first sidewall covers the sidewall of the fourth sidewall, and the second sidewall covers the sidewall of the first sidewall.

6. The manufacturing method of the flash memory device according to claim 5, characterized in that, After forming the word line, it further includes: removing part of the control gate material layer and the floating gate material layer, and retaining the control gate material layer and the floating gate material layer under the third sidewall to form the control gate and the floating gate.

7. A flash memory device, characterized in that, Comprising: A substrate; A word line, disposed on the substrate, and the bottom of the word line penetrates into the substrate by a set distance; A floating gate, disposed on the surface of the substrate on both sides of the word line; A control gate, disposed on the surface of the floating gate; Wherein, a first sidewall is further provided on a sidewall of the floating gate close to the word line, and a second sidewall is further provided between the word line, the substrate, the floating gate, and the control gate. The second sidewall covers the sidewall of the first sidewall, and the thickness range of the second sidewall located between the word line and the substrate is 8. The flash memory device according to claim 7, wherein, The set distance is 9. The flash memory device according to claim 7, wherein, A third sidewall is further disposed on the surface of the control gate, and a fourth sidewall is further disposed on the sidewall of the control gate close to the word line, the fourth sidewall covers the sidewall of the third sidewall, and the first sidewall covers the sidewall of the fourth sidewall.

10. The flash memory device according to claim 7 or 9, characterized in that, The thickness of the second sidewall is less than the thickness of the first sidewall.

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