Third-generation semiconductor contact window structure and manufacturing method thereof

Abstract

The present invention relates to the field of semiconductor manufacturing technology, and discloses a third-generation semiconductor contact window structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, depositing a compound epitaxial layer on the substrate; depositing a first metal layer on the compound epitaxial layer through an evaporation metal process; depositing an isolation layer on the compound epitaxial layer and the first metal layer; correspondingly arranging through holes on the isolation layer located above the first metal layer and penetrating through the isolation layer, wherein the inner wall of the through hole is an inclined arc surface; depositing a second metal layer on the isolation layer and the through holes through an evaporation metal process. It effectively prevents the damage to the lattice structure on the surface of the compound epitaxial layer and the contamination of impurity ions during the metal sputtering process, and reduces the contact impedance of the third-generation semiconductor contact window structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to a third-generation semiconductor contact window structure and a manufacturing method thereof. Background Art

[0002] In the traditional compound semiconductor manufacturing industry, an insulating layer is usually deposited on the surface of the compound first, then vias are opened in a fixed area through photolithography and etching processes, and then metal is deposited in the vias to form via metal and metal lines. There are several disadvantages: First, directly performing the etching process on the surface of the compound will directly damage the lattice of the compound surface; Second, when sputtering metal, metal atoms will sputter and bombard the compound surface, thereby damaging the lattice of the compound surface; Third, the sputtered metal material is an aluminum-nickel alloy, but the aluminum-nickel alloy has a large impedance and cannot meet the low-impedance metal conduction of the new generation of high-voltage and high-energy devices. Summary of the Invention

[0003] The main object of the present invention is to provide a third-generation semiconductor contact window structure and a manufacturing method thereof, aiming to solve the technical problems of lattice structure damage and impurity ion pollution on the surface of the compound epitaxial layer caused by the metal sputtering process of the third-generation semiconductor device, and the high contact window resistance.

[0004] To achieve the above object, the present invention provides a manufacturing method of a third-generation semiconductor contact window structure, and the manufacturing method includes:

[0005] Providing a substrate, and depositing a compound epitaxial layer on the substrate;

[0006] Depositing a first metal layer on the compound epitaxial layer through an evaporation metal process;

[0007] Depositing an isolation layer on the compound epitaxial layer and the first metal layer;

[0008] Correspondingly providing vias on the isolation layer located above the first metal layer and penetrating through the isolation layer, wherein the inner wall of the vias is an inclined arc surface;

[0009] Depositing a second metal layer on the isolation layer and the vias through an evaporation metal process.

[0010] Further, in an embodiment, depositing a first metal layer on the compound epitaxial layer through an evaporation metal process includes: forming a barrier layer on the compound epitaxial layer, wherein a plurality of development regions and a plurality of barrier regions are arranged at intervals in the barrier layer; sequentially depositing gold, germanium, and nickel on the barrier layer through an evaporation metal process to form a first metal layer in the development regions.

[0011] Further, in one embodiment, the included angle between the side wall of the barrier layer located in the barrier region and the compound epitaxial layer is less than 90°.

[0012] Further, in one embodiment, forming a barrier layer on the compound epitaxial layer includes: coating a photoresist on the compound epitaxial layer to form a photoresist layer; disposing a preset photomask above the photoresist layer, and exposing the photoresist layer through the preset photomask to form a plurality of mask regions and a plurality of first exposure regions arranged at intervals in the photoresist layer, wherein the included angle between the side wall of the photoresist layer located in the first exposure region and the compound epitaxial layer is greater than 90°; baking and exposing the mask regions and the first exposure regions with ammonia gas to make the mask regions form second exposure regions and make the first exposure regions form non-exposure regions; developing the photoresist layer to dissolve the photoresist layer located in the second exposure regions to form a barrier layer.

[0013] Further, in one embodiment, after sequentially depositing gold, germanium, and nickel on the barrier layer by a metal evaporation process to form a first metal layer in the developed region, it further includes: injecting an organic solvent into the developed region to dissolve the barrier layer; removing the barrier layer and the first metal layer located on the barrier layer, and retaining the first metal layer located on the compound epitaxial layer.

[0014] Further, in one embodiment, depositing a second metal layer on the isolation layer and the through hole by a metal evaporation process includes: depositing a second metal layer on the isolation layer and the through hole by the method of manufacturing the first metal layer.

[0015] Further, in one embodiment, depositing an isolation layer on the compound epitaxial layer and the first metal layer includes: depositing silicon nitride on the compound epitaxial layer and the first metal layer to form a first isolation layer; depositing silicon oxide on the first isolation layer to form a second isolation layer.

[0016] Further, in one embodiment, after depositing silicon nitride on the compound epitaxial layer and the first metal layer to form a first isolation layer, it further includes: performing high-temperature tempering on the substrate, the chemical epitaxial layer, the first metal layer, and the first isolation layer to make the surface lattice of the first metal layer fuse with that of the compound epitaxial layer.

[0017] The present invention also provides a third-generation semiconductor contact window structure, which is made by using the manufacturing method described above. The third-generation semiconductor contact window structure includes:

[0018] A substrate; a compound epitaxial layer disposed on the substrate; a first metal layer disposed on the compound epitaxial layer; an isolation layer covering the compound epitaxial layer and the first metal layer; a through hole passing through the isolation layer and disposed on the first metal layer, wherein the inner wall of the through hole is an inclined arc surface; a second metal layer covering the through hole and disposed on the isolation layer.

[0019] Further, in an embodiment, the isolation layer includes a first isolation layer and a second isolation layer. The first isolation layer covers the compound epitaxial layer and the first metal layer, and the second isolation layer is stacked on the first isolation layer.

[0020] In this embodiment, a barrier layer is formed on the compound epitaxial layer through a photoresist process to determine the position and size of the deposition of the first metal on the compound epitaxial layer. Then, the first metal layer is deposited on the compound epitaxial layer at the place covered by the barrier layer through an evaporation metal process. Then, the barrier layer is removed, which can effectively prevent the damage to the lattice structure and the impurity ion pollution on the surface of the compound epitaxial layer by the metal sputtering process, and stably maintain the electronic physical properties of the compound. By depositing an isolation layer on the compound epitaxial layer and the first metal layer, the compound epitaxial layer is protected from being damaged in subsequent processes. At the same time, the first metal and the second metal are sufficiently isolated, effectively preventing the leakage of electricity. A through hole is opened at the position of the isolation layer on the first metal layer, and the second metal layer is evaporated in the through hole, thereby completing the metal conduction between the compound epitaxial layer and the device. The first metal and the second metal are made of gold-germanium-nickel, and gold-germanium-nickel has low impedance characteristics, thereby reducing the contact impedance of the third-generation semiconductor contact window structure and improving acid corrosion resistance, radiation resistance and high temperature resistance. At the same time, the process steps are reduced, thereby shortening the production time and reducing the cost. Description of the Drawings

[0021] One or more embodiments are exemplarily illustrated by corresponding drawings. These exemplary illustrations do not limit the embodiments. Elements with the same reference numerals in the drawings represent similar elements. Unless otherwise stated, the figures in the drawings do not constitute a proportional limitation.

[0022] Figure 1 Schematic diagram of the manufacturing process of the third-generation semiconductor contact window structure according to the first embodiment of the present invention;

[0023] Figure 2 Schematic diagram of the manufacturing process of the third-generation semiconductor contact window structure according to the second embodiment of the present invention;

[0024] Figure 3 、 Figure 4 and Figure 5Schematic structural diagram of forming a barrier layer for the first embodiment of the present invention;

[0025] Figure 6 Schematic structural diagram of depositing a first metal layer for an embodiment of the present invention;

[0026] Figure 7 Schematic structural diagram of removing a barrier layer for an embodiment of the present invention;

[0027] Figure 8 Schematic structural diagram of a third-generation semiconductor contact window structure for an embodiment of the present invention.

[0028] Among them, 100, third-generation semiconductor contact window structure; 101, substrate; 102, compound epitaxial layer; 103, first metal layer; the included angle between the side wall of the photoresist layer located in the first exposure area and the compound epitaxial layer, 2a; the included angle between the side wall of the barrier layer located in the barrier area and the compound epitaxial layer, 2b; 201, isolation layer; 202, arc surface; 301, through hole; 401, second metal layer; 501, barrier layer; 502, development area; 503, barrier area; 601, photolithography mask; 701, photoresist layer; 702, mask area; 703, first exposure area; 704, non-exposure area; 705, second exposure area. Detailed implementation manners

[0029] For the convenience of understanding the present invention, the present invention will be described in more detail below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is expressed as "fixed to" another element, it can be directly on the other element, or there can be one or more intermediate elements therebetween. When an element is expressed as "connected to" another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween. The terms "vertical", "horizontal", "left", "right", "inner", "outer" and similar expressions used in this specification are only for the purpose of illustration. In the description of the present invention, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating relative importance or implicitly indicating the quantity of the indicated technical features. Thus, unless otherwise stated, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features; the meaning of "a plurality" is two or more. The term "comprising" and any deformation thereof mean non-exclusive inclusion, and there may be or add one or more other features, integers, steps, operations, units, components and / or their combinations.

[0030] In addition, unless otherwise clearly defined and limited, the terms "installed", "connected", and "joined" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, or the internal communication of two components. All technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the technical field to which the present invention belongs. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not used to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0031] In addition, the technical features involved in different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0032] To facilitate the understanding of the present invention, the specific processes of the embodiments of the present invention are described below. Please refer to Figure 1 , an embodiment of the manufacturing method of the third-generation semiconductor contact window structure in the embodiment of the present invention includes:

[0033] S1. Provide a substrate 101, and deposit a compound epitaxial layer 102 on the substrate 101;

[0034] Specifically, the substrate 101 is a silicon-based or silicon carbide-based substrate 101, and a layer of compound epitaxial layer 102 is deposited on the substrate 101 by chemical vapor deposition. The material of the compound epitaxial layer 102 is silicon carbide or gallium nitride.

[0035] S2. Deposit a first metal layer 103 on the compound epitaxial layer 102 by evaporation of metal;

[0036] Specifically, the compound epitaxial layer 102 is placed in a vacuum evaporation machine. Through vacuum pumping and heating, the metal is melted and evaporated into a gaseous state, and the gaseous metal is deposited on the surface of the compound epitaxial layer 102. After cooling, the first metal layer 103 is formed. Since the first metal layer 103 is deposited on the surface of the compound epitaxial layer 102 after gasification, the lattice on the surface of the compound epitaxial layer 102 is not damaged; and the material of the first metal layer 103 is gold-germanium-nickel, and the gold-germanium-nickel material has a lower contact resistance, thereby reducing the contact impedance of the third-generation semiconductor contact window structure 100 and improving acid corrosion resistance, radiation resistance, and high temperature resistance.

[0037] S3. Deposit an isolation layer 201 on the compound epitaxial layer 102 and the first metal layer 103;

[0038] Specifically, an isolation layer 201 is deposited on the compound epitaxial layer 102 and the first metal layer 103 by chemical vapor deposition to protect the compound epitaxial layer 102 and the first metal layer 103 from being damaged or corroded in subsequent processes.

[0039] S4. A through hole 301 is correspondingly arranged on the isolation layer 201 above the first metal layer 103 and penetrates through the isolation layer 201, wherein the inner wall of the through hole 301 is an inclined arc surface.

[0040] Specifically, the isolation layer 201 above the first metal layer 103 is etched by a through hole lithography process, and the inner wall of the through hole 301 is etched into an inclined arc surface, which is beneficial for the subsequently evaporated metal to continuously adhere to the inner wall of the through hole 301 without metal discontinuity.

[0041] S5. A second metal layer 401 is deposited on the isolation layer 201 and the through hole 301 by an evaporation metal process.

[0042] Optionally, the above step S5 is specifically: depositing the second metal layer 401 on the isolation layer 201 and the through hole 301 by the method of manufacturing the first metal layer 103.

[0043] Specifically, a photoresist is coated on the isolation layer 201 and the through hole 301 to form a second photoresist layer; a preset photomask 601 is disposed above the second photoresist layer, and the second photoresist layer is exposed through the preset photomask 601 to form a plurality of second mask regions and a plurality of third exposure regions arranged at intervals in the second photoresist layer. By controlling the light energy and focus of the lithography machine, the included angle between the side wall of the photoresist layer in the third exposure region and the isolation layer is greater than 90°, which is beneficial to avoiding the generation of metal filaments when depositing metal in the subsequent development region, where the barrier layer and the metal are located on the same vertical axis, thus avoiding the leakage phenomenon; the second mask region and the third exposure region are baked with ammonia and exposed, so that the second mask region forms a fourth exposure region, and the third exposure region forms a second non-exposure region; the second photoresist layer is developed to dissolve the second photoresist layer located in the fourth exposure region, forming a second barrier layer with a plurality of second development regions and a plurality of second barrier regions arranged at intervals; gold, germanium, and nickel are sequentially deposited on the second barrier layer through a metal evaporation process to form a second metal layer in the second development region; an organic solvent is injected into the second development region to dissolve the second barrier layer; the second barrier layer and the second metal layer 401 located on the second barrier layer are removed, and the second metal layer 401 located on the isolation layer 201 and the through hole 301 is retained. At the same time, the material of the first metal layer 103 is the same as that of the first metal layer 103, both being gold-germanium-nickel, which not only improves the conduction ability of the same material but also reduces the contact impedance of the third-generation semiconductor contact window structure 100.

[0044] In this embodiment, the first metal layer 103 is directly deposited on the compound epitaxial layer 102 through a metal evaporation process, effectively preventing the damage to the lattice structure and the contamination of impurity ions on the surface of the compound epitaxial layer 102 by the metal sputtering process. An isolation layer 201 is deposited on the compound epitaxial layer 102 and the first metal layer 103 to protect the compound epitaxial layer 102 from being damaged in the subsequent process. At the same time, sufficient isolation is provided between the first metal and the second metal to effectively prevent leakage. A through hole is opened at the position of the isolation layer 201 on the first metal layer 103, and a second metal layer 401 is deposited in the through hole, thereby completing the metal conduction between the compound epitaxial layer 102 and the device.

[0045] Please refer to Figures 2 - 7 , Figures 2 - 7 Another embodiment of the manufacturing method of the third-generation semiconductor contact window structure 100 of the present invention includes:

[0046] S21. Provide a substrate 101, and deposit a compound epitaxial layer 102 on the substrate 101;

[0047] Specifically, the description of step S21 above refers to the first embodiment and will not be elaborated in this embodiment. Hereinafter, the implementation process of the third-generation semiconductor contact window structure 100 will be specifically described.

[0048] S22. Form a barrier layer 501 on the compound epitaxial layer 102. Among them, a plurality of development regions 502 and a plurality of barrier regions 503 are arranged at intervals in the barrier layer 501. Among them, the included angle 2b between the side wall of the barrier layer 501 located in the barrier region 503 and the compound epitaxial layer 201 is less than 90°.

[0049] Optionally, as Figures 3 - 5 shown, the above step S22 is formed in four steps:

[0050] Coat a photoresist on the compound epitaxial layer 102 to form a photoresist layer 701.

[0051] Set a preset photomask 601 above the photoresist layer 701, and expose the photoresist layer 701 through the preset photomask 601 to form a plurality of mask regions 702 and a plurality of first exposure regions 703 arranged at intervals in the photoresist layer 701. Among them, the included angle 2a between the side wall of the photoresist layer 701 located in the first exposure region 703 and the compound epitaxial layer 102 is greater than 90°.

[0052] Bake and expose the mask region 702 and the first exposure region 703 with ammonia gas to make the mask region 301 form a second exposure region 705 and make the first exposure region 703 form a non-exposure region 704.

[0053] Develop the photoresist layer 701 to dissolve the photoresist layer 701 located in the second exposure region 705 to form the barrier layer 501.

[0054] In this embodiment, the material of the photoresist is preferably polymethyl methacrylate. The photoresist will be dissolved when exposed to the developer in the exposed area, and will not be dissolved but retained when exposed to the developer in the non-exposed area. A layer of photoresist is uniformly coated on the compound epitaxial layer 102 by spin coating, and the photoresist is baked and cured to form a photoresist layer 701. A preset photomask 601 is arranged above the photoresist layer 701, and the photoresist layer 701 is exposed through the preset mask by controlling the accurate light quantity, parallelism and uniformity of the light source of the lithography machine. At the same time, by controlling the light energy and focus of the lithography machine, the angle 2a between the side wall of the photoresist layer 701 in the first exposure area 703 and the compound epitaxial layer 102 is controlled to be greater than 90°, which is beneficial to avoiding the generation of metal residue filaments when the metal is evaporated in the subsequent development area 502, where the barrier layer 501 and the metal are located on the same vertical axis, thus avoiding the leakage phenomenon. The photoresist layer with the mask area 702 and the first exposure area 703 formed is baked with high-temperature ammonia gas, so that the photoresist layer 701 in the mask area 702 and the photoresist layer 701 in the first exposure area 703 have different chemical reactions with ammonia gas, causing different reactions in their internal structures, and correspondingly forming the second exposure area 705 and the non-exposed area 704. Then, the photoresist layer 701 is exposed to ultraviolet light comprehensively by a lamp, curing the photoresist layer 701 in the non-exposed area 704, and at the same time, decomposing the photoresist layer 701 in the second exposure area 705. When the photoresist layer 701 with the non-exposed area 704 and the second exposure area 705 formed is put into the developer, the photoresist layer 701 in the second exposure area 705 will be dissolved by the developer, and the photoresist layer 701 in the non-exposed area 704 will not be dissolved by the developer because it is in the non-exposed area and does not undergo a chemical reaction, and is retained to form the barrier layer 501. This barrier layer 501 provides a clear position and the size of the evaporated first metal for evaporating the first metal layer 103 on the compound epitaxial layer 102. Moreover, the spin coating, deposition and removal of the photoresist belong to the standard semiconductor process mode. Therefore, when performing the spin coating, deposition and removal steps of the photoresist on the compound epitaxial layer 102, the lattice on the surface of the compound epitaxial layer 102 will not be damaged.

[0055] S23. Deposit gold, germanium and nickel in sequence on the barrier layer 501 through an evaporation metal process to form a first metal layer 103 in the development area;

[0056] Specifically, place the substrate with the formed barrier layer 501 into a vacuum evaporation machine. Through vacuum pumping and heating, the gold melts and evaporates into a gaseous state. The gaseous gold deposits on the barrier layer 501 and within the development region 502 to form a gold layer. Then, through vacuum pumping and heating again, the germanium melts and evaporates into a gaseous state. The gaseous germanium deposits germanium on the gold layer to form a germanium layer. Finally, through vacuum pumping and heating, the nickel melts and evaporates into a gaseous state. The gaseous nickel deposits nickel-germanium on the germanium layer to form a nickel layer. After the gold layer, germanium layer, and nickel layer cool down, a first metal layer is formed.

[0057] S24. Inject an organic solvent into the development region 502 to dissolve the barrier layer 501.

[0058] Specifically, remove the barrier layer 501 and the first metal on the barrier layer 501. By injecting an organic solvent into the development region 502, the organic solvent flows into the bottom of the barrier layer 501 through the gap between the first metal layer 103 and the barrier layer 501 and dissolves the bottom of the barrier layer 501. Since it directly dissolves the bottom of the barrier layer 501, the dissolution time can be reduced and the amount of organic solvent used can be decreased, improving production efficiency and environmental protection.

[0059] S25. Remove the barrier layer 501 and the first metal layer 103 on the barrier layer 501, and retain the first metal layer 103 on the compound epitaxial layer.

[0060] Specifically, remove the dissolved barrier layer 501 and the first metal layer 103 on the barrier layer 501 through a cleaning method, and retain the first metal layer 103 on the compound epitaxial layer 102.

[0061] S26. Deposit silicon nitride on the compound epitaxial layer 102 and the first metal layer 103 to form a first isolation layer 201.

[0062] Specifically, deposit silicon nitride on the compound epitaxial layer 102 and the first metal layer 103 through chemical vapor deposition to protect the compound and the first metal layer 103 from being damaged or impaired in subsequent processes.

[0063] S27. Perform high-temperature tempering on the substrate 101, the chemical epitaxial layer 102, the first metal layer 103, and the first isolation layer 201 to enable the surface lattice of the first metal layer 103 to fuse with that of the compound epitaxial layer 102.

[0064] Specifically, a first isolation layer 201 is deposited on the chemical epitaxial layer 102 and the first metal layer 103. When performing high-temperature tempering on the substrate 101, the chemical epitaxial layer 102, the first metal layer 103, and the first isolation layer 201, the first isolation layer 201 protects the first metal layer 103 from being damaged by high temperature, and at the same time, enables the lattice on the surfaces of the first metal layer 103 and the compound epitaxial layer 102 to fuse, so as to reduce the impedance of the third-generation semiconductor contact window structure 100.

[0065] S28. Deposit silicon oxide on the first isolation layer 201 to form a second isolation layer 201;

[0066] Specifically, silicon oxide is deposited on the first isolation layer 201 by chemical vapor deposition to form a second isolation layer 201, so that the first metal layer 103 and the second metal layer 401 are sufficiently isolated to avoid current leakage. And the second isolation layer 201 located on the first metal layer 103 is convex, and the opposite sides of the convex are provided with arc surfaces 202; effectively preventing the second metal deposited here from experiencing metal cracking or tip discharge phenomena.

[0067] S29. Corresponding vias 301 are provided on the isolation layer 201 located above the first metal layer 103 and penetrate through the isolation layer 201, wherein the inner wall of the via 301 is an inclined arc surface;

[0068] S30. Deposit a second metal layer 401 on the isolation layer 201 and the vias 301 by evaporation of metal process.

[0069] Specifically, the descriptions of the above steps S29 and S30 refer to the first embodiment, and will not be elaborated in this embodiment.

[0070] In this embodiment, a barrier layer 501 is formed on the compound epitaxial layer 102 through a photoresist process to determine the position and size of the deposition of the first metal on the compound epitaxial layer 102. Then, a first metal layer 103 is deposited on the compound epitaxial layer 102 at the place not covered by the barrier layer 501 through an evaporation metal process. Then, the barrier layer 501 is removed, which can effectively prevent the lattice structure damage and impurity ion contamination on the surface of the compound epitaxial layer 102 by the metal sputtering process, and stably maintain the electronic physical properties of the compound. By depositing an isolation layer 201 on the compound epitaxial layer 102 and the first metal layer 103, the compound epitaxial layer 102 is protected from being damaged in subsequent processes. At the same time, there is sufficient isolation between the first metal and the second metal, effectively preventing the leakage of electricity. A through hole is opened at the position of the isolation layer 201 on the first metal layer 103, and a second metal layer 401 is evaporated in the through hole, thereby completing the metal conduction between the compound epitaxial layer 102 and the device. The materials of the first metal layer 103 and the second metal layer 401 are gold-germanium-nickel, and gold-germanium-nickel has low impedance characteristics, thereby reducing the contact impedance of the third-generation semiconductor contact window structure 100.

[0071] As Figure 8 shown, an embodiment of the present invention discloses a third-generation semiconductor contact window structure 100, and the third-generation semiconductor contact window structure 100 is made by using the manufacturing method described above. The third-generation semiconductor contact window structure 100 includes: a substrate 101, a compound epitaxial layer 102, a first metal layer 103, an isolation layer 201, a through hole 301, and a second metal layer 401. The compound epitaxial layer 102 is disposed on the substrate 101; the first metal layer 103 is disposed on the compound epitaxial layer 102; the isolation layer 201 covers the compound epitaxial layer 102 and the first metal layer 103; the through hole 301 is disposed on the first metal layer 103 through the isolation layer, and the inner wall of the through hole 301 is an inclined arc surface; the second metal layer 401 covers the through hole 301 and is disposed on the isolation layer 201.

[0072] Specifically, the compound epitaxial layer 102 is disposed on the substrate 101, and a first metal is disposed on the compound epitaxial layer 102 by vapor deposition of metal. The vapor deposition of metal can effectively reduce the lattice damage to the surface of the compound epitaxial layer 102 and is used for the electrical conduction between the compound epitaxial layer 102 and the outside world. The material of the first metal layer 103 is gold-germanium-nickel, and the gold-germanium-nickel material has low impedance characteristics. Therefore, the impedance of the third-generation semiconductor contact window structure 100 is effectively reduced. An isolation layer 201 is disposed on the compound epitaxial layer 102 and the first metal layer 103. On the one hand, it is beneficial to protect the compound from being damaged in subsequent processes; on the other hand, in order to provide sufficient isolation between the first metal layer 103 and the second metal layer 401 to prevent leakage. The through hole 301 is disposed on the first metal layer 103 through the isolation layer and is used for the conduction between the second metal and the first metal, so that the compound epitaxial layer 102 can be electrically connected to the device. The inner wall of the through hole 301 is an inclined arc surface, which is beneficial to prevent the second metal layer 401 deposited on the inner wall of the through hole from breaking or being too thin; the second metal layer 401 covers the through hole 301 and is disposed on the isolation layer 201. The second metal layer 401 is used for conducting with the first metal layer 103.

[0073] Further, the isolation layer 201 includes a first isolation layer 201 and a second isolation layer 201. The first isolation layer 201 covers the compound epitaxial layer 102 and the first metal layer 103, and the second isolation layer 201 is stacked on the first isolation layer 201. Specifically, the material of the first isolation layer 201 is silicon nitride, and the material of the second isolation layer 201 is silicon oxide. The first isolation layer 201 is deposited on the compound epitaxial layer 102 and the first metal layer 103 by chemical vapor deposition, and the second isolation layer 201 is deposited on the first isolation layer 201 by chemical vapor deposition, so as to provide sufficient isolation between the first metal layer 103 and the second metal layer 401 and effectively prevent leakage.

[0074] In this embodiment, by directly disposing a first metal layer 103 on the compound epitaxial layer 102, the lattice structure damage and impurity ion contamination on the surface of the compound epitaxial layer 102 caused by the metal sputtering process are effectively prevented. And an isolation layer 201 is disposed on the compound epitaxial layer 102 and the first metal layer 103 to protect the compound epitaxial layer 102 from being damaged in subsequent processes and to provide sufficient isolation between the first metal and the second metal, effectively preventing the occurrence of leakage. A through hole is opened at the position of the isolation layer 201 located on the first metal layer 103, and a second metal layer 401 is disposed in the through hole, thereby completing the metal conduction between the compound epitaxial layer 102 and the device. The first metal layer 103 and the second metal layer 401 are made of gold-germanium-nickel, and gold-germanium-nickel has low impedance characteristics, thereby reducing the contact impedance of the third-generation semiconductor contact window structure 100 and improving acid erosion resistance, radiation resistance and high temperature resistance.

[0075] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; under the idea of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order, and there are many other variations in different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A manufacturing method of a third-generation semiconductor contact window structure, characterized in that, the manufacturing method includes: providing a substrate and depositing a compound epitaxial layer on the substrate; depositing a first metal layer on the compound epitaxial layer by evaporation plating metal process; depositing an isolation layer on the compound epitaxial layer and the first metal layer; correspondingly providing through holes on the isolation layer located above the first metal layer and penetrating through the isolation layer, wherein the inner wall of the through holes is an inclined arc surface; depositing a second metal layer on the isolation layer and the through holes by evaporation plating metal process; wherein, the depositing a first metal layer on the compound epitaxial layer by evaporation plating metal process includes: forming a barrier layer on the compound epitaxial layer, wherein a plurality of development regions and a plurality of barrier regions are arranged at intervals in the barrier layer, and the included angle between the side wall of the barrier layer located in the barrier region and the compound epitaxial layer is less than 90°; sequentially depositing gold, germanium and nickel on the barrier layer by evaporation plating metal process to form a first metal layer in the development region; the forming a barrier layer on the compound epitaxial layer includes: coating a photoresist on the compound epitaxial layer to form a photoresist layer; providing a preset photomask above the photoresist layer and exposing the photoresist layer through the preset photomask to form a plurality of mask regions and a plurality of first exposure regions arranged at intervals in the photoresist layer, wherein the included angle between the side wall of the photoresist layer located in the first exposure region and the compound epitaxial layer is greater than 90°; performing ammonia baking and exposure on the mask region and the first exposure region to make the mask region form a second exposure region and make the first exposure region form a non-exposure region; developing the photoresist layer to dissolve the photoresist layer located in the second exposure region to form a barrier layer.

2. The manufacturing method according to claim 1, characterized in that, after sequentially depositing gold, germanium and nickel on the barrier layer by evaporation plating metal process to form a first metal layer in the development region, it further includes: injecting an organic solvent into the development region to dissolve the barrier layer; removing the barrier layer and the first metal layer located on the barrier layer, and retaining the first metal layer located on the compound epitaxial layer.

3. The manufacturing method according to claim 1, characterized in that, the depositing a second metal layer on the isolation layer and the through holes by evaporation plating metal process includes: depositing a second metal layer on the isolation layer and the through holes by the method of manufacturing the first metal layer.

4. The manufacturing method according to claim 1, characterized in that, the depositing an isolation layer on the compound epitaxial layer and the first metal layer includes: depositing silicon nitride on the compound epitaxial layer and the first metal layer to form a first isolation layer; depositing silicon oxide on the first isolation layer to form a second isolation layer.

5. The manufacturing method according to claim 4, characterized in that, after depositing silicon nitride on the compound epitaxial layer and the first metal layer to form a first isolation layer, it further includes: Perform high-temperature tempering on the substrate, the compound epitaxial layer, the first metal layer, and the first isolation layer so that the surface lattice of the first metal layer fuses with that of the compound epitaxial layer.

6. A third-generation semiconductor contact window structure, characterized in that the third-generation semiconductor contact window structure is fabricated by using the manufacturing method according to any one of claims 1 to 5, and the third-generation semiconductor contact window structure comprises: a substrate; a compound epitaxial layer, which is disposed on the substrate; a first metal layer, which is disposed on the compound epitaxial layer; an isolation layer, which covers the compound epitaxial layer and the first metal layer; a through hole, which is disposed on the first metal layer through the isolation layer, and the inner wall of the through hole is an inclined arc surface; a second metal layer, which covers the through hole and is disposed on the isolation layer.

7. The third-generation semiconductor contact window structure according to claim 6, characterized in that the isolation layer comprises a first isolation layer and a second isolation layer, the first isolation layer covers the compound epitaxial layer and the first metal layer, and the second isolation layer is stacked on the first isolation layer.

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