Semiconductor packaging structure and manufacturing method thereof

Abstract

The present invention provides a semiconductor packaging structure and a manufacturing method thereof, wherein the semiconductor packaging structure includes a first stacking structure and a second stacking structure stacked together; the first stacking structure includes a first dielectric layer, a first power chip, a first conductive connection element, a first conductive column and a first patterned conductive layer; the second stacking structure includes a second dielectric layer, a second power chip, a second conductive connection element, a second conductive column, a second patterned conductive layer and a third patterned conductive layer; by arranging the first power chip and the second power chip in an upper and lower stacking manner, a semiconductor packaging structure is provided in which the first power chip and the second power chip can be directly electrically connected through a circuit structure and the disadvantages associated with the lead frame are eliminated; in addition, the present invention also provides a manufacturing method for the semiconductor packaging structure.

Description

Technical Field

[0001] The present invention relates to a packaging structure and a manufacturing method thereof, and in particular to a semiconductor packaging structure and a manufacturing method thereof. Background Art

[0002] With the significant growth in demand for information and automotive electronics, the Quad Flat No-Lead (QFN) package structure has become an important semiconductor packaging technology due to its better heat dissipation, lower impedance, and better resistance to electromagnetic interference.

[0003] In the QFN structure, copper clip technology was developed to meet high-power demands. The copper clip is designed into a high-rise arch shape with a height difference. Solder paste is dispensed to bond the clip to the chip. This design offers low impedance, allowing it to carry high currents and withstand deformation caused by thermal stress, making it suitable for high-power components such as transistors.

[0004] Please refer to the following Figures 1A to 1D , to briefly explain the portion of the prior art packaging structure that utilizes copper sheet bridge technology to connect transistors.

[0005] like Figure 1A As shown in FIG, a solder paste layer 102 is formed on a lead frame 101 by screen printing. Figure 1B , a transistor chip 103 is placed on the solder paste layer 102. Then, as Figure 1C , forming solder 104 on the transistor chip 103. Finally, Figure 1D A bridging copper sheet 105 is placed on the corresponding solder paste layer 102 and solder 104, and after a high-temperature reflow process at 380 degrees Celsius, the lead frame 101, the transistor chip 103 and the bridging copper sheet 105 are bonded to each other.

[0006] The above process and finished product have at least the following problems:

[0007] (1) The package structure uses a lead frame and a bridging copper sheet, so the height (thickness) of the package cannot be reduced, which limits its application areas.

[0008] (2) Solder or solder paste contains a relatively high proportion of lead, which can cause environmental pollution and have a considerable impact on human health.

[0009] (3) Before all components are fixed in the high-temperature reflow process at 380 degrees Celsius, individual components may shift, resulting in a decrease in accuracy.

[0010] Therefore, how to improve the above-mentioned shortcomings and provide a semiconductor package structure capable of integrating high-power devices and a manufacturing method thereof is one of the important issues at present. Summary of the Invention

[0011] In view of the foregoing, one object of the present invention is to provide a semiconductor package structure and a method for manufacturing the same that replaces the use of lead frames and can reduce the height of semiconductor packages containing high-power components while increasing electrical performance. Another object of the present invention is to provide a semiconductor package structure and a method for manufacturing the same that avoids the use of lead-containing processes and thus meets environmental requirements.

[0012] To achieve the above objectives, the present invention provides a semiconductor package structure comprising a first stacked structure and a second stacked structure. The first stacked structure comprises a first dielectric layer, a first patterned conductive layer, a first power chip, at least one first conductive connection element, and at least one first conductive pillar. The second stacked structure comprises a second dielectric layer, a second patterned conductive layer, a second power chip, at least one second conductive connection element, at least one second conductive pillar, and a third patterned conductive layer.

[0013] The first dielectric layer has a first surface and a second surface arranged opposite to each other. The first patterned conductive layer is embedded in the first dielectric layer, and one side of the first patterned conductive layer is exposed to the first surface of the first dielectric layer. The first power chip is embedded in the first dielectric layer and has a first electrode layout and a second electrode layout arranged opposite to each other. The first power chip is bonded to the first patterned conductive layer in the first dielectric layer with the second electrode layout end through a first conductive adhesive layer. In addition, the electrode pad on the first electrode layout of the first power chip is provided with at least one first conductive connecting element, and one end of the first conductive connecting element is exposed to the second surface of the first dielectric layer. The first conductive column is embedded in the first dielectric layer, and one end of the first conductive column is connected to the first patterned conductive layer in the first dielectric layer, and the other end is exposed to the second surface of the first dielectric layer.

[0014] The second dielectric layer has a third surface and a fourth surface disposed opposite each other, with the third surface adjacent to the second surface of the first dielectric layer. A second patterned conductive layer is embedded within the second dielectric layer, with one side exposed on the third surface of the second dielectric layer to connect to the first conductive pillar and the first conductive connection element. A second power chip is embedded within the second dielectric layer and has a third electrode layout and a fourth electrode layout disposed opposite each other. The second power chip is bonded to the second patterned conductive layer within the second dielectric layer via a second conductive adhesive layer at the end of the fourth electrode layout. Furthermore, the electrode pads on the third electrode layout of the second power chip are provided with at least one second conductive connection element, one end of which is exposed on the fourth surface of the second dielectric layer, wherein the projections of the second power chip and the first power chip along the stacking direction overlap. A second conductive pillar is embedded within the second dielectric layer, with one end connected to the second patterned conductive layer within the second dielectric layer and the other end exposed on the fourth surface of the second dielectric layer. A third patterned conductive layer is disposed on the fourth surface of the second dielectric layer to connect to the second conductive pillar and the second conductive connection element.

[0015] In one embodiment, the first electrode layout and the third electrode layout include a drain and a gate, and the second electrode layout and the fourth electrode layout include a source.

[0016] In one embodiment, the first electrode layout and the third electrode layout include a source, and the second electrode layout and the fourth electrode layout include a drain and a gate.

[0017] In one embodiment, the geometric profiles of the contact surfaces of the first conductive connection element and the electrode pad on the first electrode layout of the first power chip are similar.

[0018] In one embodiment, the second conductive connection element and the contact surface of the electrode pad on the third electrode layout of the second power chip have similar geometric profiles.

[0019] In one embodiment, the first patterned conductive layer includes a patterned conductive layer and an external conductive pillar layer stacked on top of each other and electrically connected, wherein the external conductive pillar layer is pillar-shaped with one end exposed to the first surface of the first dielectric layer.

[0020] In one embodiment, the semiconductor package structure further includes a control chip having an active surface and a back surface disposed opposite each other, and the control chip is embedded in the first dielectric layer. The back surface of the control chip is bonded to the first patterned conductive layer via a first conductive adhesive layer, and the active surface of the control chip is connected to the second patterned conductive layer via a plurality of first conductive connecting elements.

[0021] In one embodiment, the geometric profiles of the first conductive connection element and the contact surface of the electrode pad on the active surface of the control power chip are similar.

[0022] In one embodiment, the semiconductor package structure further includes a control chip having an active surface and a back surface disposed opposite each other. The control chip is embedded in the second dielectric layer. The back surface of the control chip is bonded to the second patterned conductive layer via a second conductive adhesive layer. The active surface of the control chip is connected to the third patterned conductive layer via a plurality of second conductive connecting elements.

[0023] In one embodiment, the second conductive connection element and the contact surface of the electrode pad on the active surface of the control power chip have similar geometric profiles.

[0024] In one embodiment, the geometric profiles of the contact surfaces of the first conductive connection element and the electrode pads of the second electrode layout of the first power chip and / or the electrode pads of the active surface of the control chip are similar.

[0025] In one embodiment, the geometric profiles of the contact surfaces of the second conductive connection element and the electrode pads of the fourth electrode layout of the second power chip and / or the electrode pads of the active surface of the control chip are similar.

[0026] In addition, to achieve the above-mentioned purpose, the present invention provides a method for manufacturing a semiconductor packaging structure, which includes the following steps. Provide a carrier board; form a first stacking structure; and form a second stacking structure. It is further explained that the step of forming the first stacking structure includes forming a first patterned conductive layer on the carrier board; providing a first power chip, which has a first electrode layout and a second electrode layout arranged opposite to each other, and the first power chip is bonded to the first patterned conductive layer with the second electrode layout end through a first conductive adhesive layer; forming at least a first conductive connection element on the electrode pad of the first electrode layout; forming at least a first conductive column on the first patterned conductive layer; and forming a first dielectric layer to cover the first patterned conductive layer, the first power chip and the first conductive column, and exposing one end of the first conductive column and one end of the first conductive connection element.

[0027] The steps of forming a second stacking structure include forming a second patterned conductive layer on the first dielectric layer of the first stacking structure to connect the first conductive column and the first conductive connection element; providing a second power chip having a third electrode layout and a fourth electrode layout arranged opposite to each other, and bonding the second power chip to the second patterned conductive layer at the end of the fourth electrode layout through a second conductive adhesive layer, wherein the projections of the second power chip and the first power chip along the stacking direction overlap; forming at least one second conductive connection element on the electrode pad of the third electrode layout; forming at least one second conductive column on the second patterned conductive layer; forming a second dielectric layer to cover the second patterned conductive layer, the second power chip, the second power chip and the second conductive column, and exposing one end of the second conductive column and one end of the second conductive connection element; and forming a third patterned conductive layer on the second dielectric layer to connect the second conductive column and the second conductive connection element.

[0028] In one embodiment, the method for manufacturing a semiconductor package structure further includes: the first electrode layout and the third electrode layout include a drain and a gate, and the second electrode layout and the fourth electrode layout include a source.

[0029] In one embodiment, the method for manufacturing a semiconductor package structure further includes wherein the first electrode layout and the third electrode layout include a source, and the second electrode layout and the fourth electrode layout include a drain and a gate.

[0030] In one embodiment, the method for manufacturing a semiconductor package structure further includes the following steps: before forming the first dielectric layer, providing a control chip having an active surface and a back surface oppositely disposed, and bonding the control chip to the first patterned conductive layer via a first adhesive layer via the back surface, and forming at least one first conductive connection element on the electrode pad on the active surface of the control chip; after forming the first dielectric layer, exposing one end of the first conductive column and one end of these first conductive connection elements on the first power chip and the control chip.

[0031] In one embodiment, the method for manufacturing a semiconductor package structure further includes the following steps: before forming the second dielectric layer, providing a control chip having an active surface and a back surface oppositely disposed, bonding the control chip to the second patterned conductive layer via a second adhesive layer via the back surface, and forming at least one second conductive connection element on the electrode pad on the active surface of the control chip; and after forming the second dielectric layer, exposing one end of the second conductive pillar and one end of the second conductive connection elements on the second power chip and the control chip.

[0032] Furthermore, to achieve the above-mentioned object, the present invention also provides a method for manufacturing a semiconductor package structure, which includes the following steps: providing a carrier board; forming a first stacking structure; and forming a second stacking structure.

[0033] Further explanation, the steps of forming the first stacking structure include forming a first patterned conductive layer on the carrier plate; providing a first power chip having a first electrode layout and a second electrode layout arranged opposite to each other, and combining the first power chip with the second electrode layout end on the first patterned conductive layer through a first conductive adhesive layer; forming at least one first conductive column on the first patterned conductive layer; forming a first dielectric layer to cover the first patterned conductive layer, the first power chip and the first conductive column, and exposing an end portion of the first conductive column; forming at least one first opening in the first dielectric layer to expose the first electrode layout of the first power chip; and forming a first conductive connection element in the first opening to connect the first electrode layout.

[0034] The step of forming the second stack structure also includes forming a second patterned conductive layer on the first dielectric layer of the first stack structure to connect the first conductive column and the first conductive connection element; providing a second power chip having a third electrode layout and a fourth electrode layout arranged opposite to each other, and bonding the second power chip to the second patterned conductive layer at the fourth electrode layout end through a second conductive adhesive layer, wherein the projections of the second power chip and the first power chip along the stacking direction overlap; forming at least one second conductive column on the second patterned conductive layer; forming a second dielectric layer to cover the second patterned conductive layer, the second power chip and the second conductive column, and exposing an end portion of the second conductive column; forming at least one second opening in the second dielectric layer to expose the third electrode layout of the second power chip; forming a second conductive connection element in the second opening to connect the third electrode layout; and forming a third patterned conductive layer on the second dielectric layer to connect the second conductive column and the second conductive connection element.

[0035] In one embodiment, the method for manufacturing a semiconductor package structure further includes: the first electrode layout and the third electrode layout include a drain and a gate, and the second electrode layout and the fourth electrode layout include a source.

[0036] In one embodiment, the method for manufacturing a semiconductor package structure further includes wherein the first electrode layout and the third electrode layout include a source, and the second electrode layout and the fourth electrode layout include a drain and a gate.

[0037] In one embodiment, the step of forming the first stacking structure also includes the following steps: forming a columnar external conductive column layer on a surface of a carrier board; forming a first sub-dielectric layer covering the external conductive column layer and the surface of the carrier board; forming a patterned conductive layer on the external conductive column layer and the first sub-dielectric layer, wherein the external conductive column layer and the patterned conductive layer together form a first patterned conductive layer; and after completing the process of the first power chip and the first conductive column, forming a second sub-dielectric layer on the first sub-dielectric layer, and covering the first sub-dielectric layer, the first patterned conductive layer, the first conductive adhesive layer, the first power chip and the first conductive column, and exposing an end of the first conductive column, wherein the first sub-dielectric layer and the second sub-dielectric layer together form the first dielectric layer.

[0038] In one embodiment, the method for manufacturing a semiconductor package structure further includes, before forming a first dielectric layer, providing a control chip having an active surface and a back surface disposed opposite each other, and first bonding the control chip to the first patterned conductive layer via the back surface via a first adhesive layer; after forming the first dielectric layer, forming a plurality of first openings in the first dielectric layer to expose a first electrode layout of a first power chip and the active surface of the control chip; and forming a plurality of first conductive connection elements in these first openings to respectively connect the first electrode layout of the first power chip and the active surface of the control chip.

[0039] In one embodiment, the method for manufacturing a semiconductor package structure further includes, before forming the second dielectric layer, providing a control chip having an active surface and a back surface disposed opposite each other, and first bonding the control chip to the second patterned conductive layer via the back surface via a second adhesive layer; after forming the second dielectric layer, forming a plurality of second openings in the second dielectric layer to expose the third electrode layout of the second power chip and the active surface of the control chip; and forming a plurality of second conductive connection elements in these second openings to respectively connect the third electrode layout of the second power chip and the active surface of the control chip.

[0040] In one embodiment, the first opening is formed by laser, plasma, machine drilling, exposure, development, and etching processes, and the first conductive connection element is formed by electroplating, filling, deposition, or patterning processes.

[0041] In one embodiment, the second opening is formed by laser, plasma, drilling, exposure, development, and etching processes, and the second conductive connection element is formed by electroplating, filling, deposition, or patterning processes.

[0042] As described above, the semiconductor package structure and manufacturing method of the present invention stacks a first power chip and a second power chip, such as transistor chips, in an upper-lower stack, with the chips oriented in the same direction. This shortens the distance between the chips for electrical connection (i.e., the first electrode layout of the first power chip can be directly electrically connected to the fourth electrode layout of the second power chip), thereby increasing electrical performance. Furthermore, by directly electrically connecting the first and second power chips through a wiring structure, replacing the existing lead frame and reflow process, the package structure can be significantly improved in precision, reduced in height, and environmentally friendly. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0044] Figures 1A to 1D This is a schematic diagram of a conventional method for manufacturing a transistor using copper bridge technology in a packaging structure;

[0045] Figure 2 is a schematic diagram of a first state of a semiconductor package structure according to a preferred embodiment of the present invention;

[0046] Figures 3A to 3M is a schematic diagram of a first method for manufacturing a semiconductor package structure according to a preferred embodiment of the present invention;

[0047] Figures 4A to 4C is a schematic diagram of a portion of a second method for manufacturing a semiconductor package structure according to a preferred embodiment of the present invention;

[0048] Figure 5 is a schematic diagram of a second state of a semiconductor package structure according to a preferred embodiment of the present invention;

[0049] Figure 6A and Figure 6B is a schematic diagram of a third state of a semiconductor package structure according to a preferred embodiment of the present invention;

[0050] Figure 7 FIG. 4 is a schematic diagram of a semiconductor package structure in a fourth state according to a preferred embodiment of the present invention.

[0051] Description of Reference Numerals

[0052] 101: Lead frame; 102: Solder paste layer; 103: Transistor chip; 104: Solder; 105: Bridging copper sheet; 2, 2a, 2b: Semiconductor package structure; 20: First stack structure; 21: Carrier board; 211: Surface; 22: First patterned conductive layer; 2211: Surface; 221: External conductive pillar layer; 222: Patterned conductive layer; 23: First dielectric layer; 231: First sub-dielectric layer; 232: Second sub-dielectric layer; 2311: First surface; 2312: Second surface; 24-1, 24-1′, 24-2: First conductive adhesive layer; 25: First power chip; 251: First electrode layout; 252: Second electrode layout; 26: Control chip; 261: Active surface; 262: Back surface; 27-1, 27-2, 27-3, 27-4, 27- 1′: first conductive connection element; 28-1, 28-2: first conductive pillar; 30: second stacked structure; 31: second patterned conductive layer; 32, 32′: second conductive adhesive layer; 33: second power chip; 331: third electrode layout; 332: fourth electrode layout; 34-1, 34-2, 34-3, 34-4, 34-1′: second conductive connection element; 35-1, 35-2: second conductive pillar; 36: second dielectric layer; 361: third surface; 362: fourth surface; 37: third patterned conductive layer; 38: protective layer; 39: solder mask; 391: opening; D1, D2: drain; G1, G2: gate; S1, S2: source; O1-1, O1-2, O1-3, O1-4: first opening; O2-1, O2-2: second opening. DETAILED DESCRIPTION

[0053] The following is a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0054] Please refer to Figure 2As shown, a first embodiment of a semiconductor package structure 2 according to a preferred embodiment of the present invention includes a first stack structure 20 and a second stack structure 30. The second stack structure 30 is stacked on the first stack structure 20. The first stack structure 20 includes a first patterned conductive layer 22, a first dielectric layer 23, two first conductive adhesive layers 24-1 and 24-2, a first power chip 25, a control chip 26, four first conductive connecting elements 27-1, 27-2, 27-3, and 27-4, and two first conductive pillars 28-1 and 28-2. The second stack structure 30 includes a second patterned conductive layer 31, a second conductive adhesive layer 32, a second power chip 33, two second conductive connecting elements 34-1 and 34-2, two second conductive pillars 35-1 and 35-2, a second dielectric layer 36, a third patterned conductive layer 37, and a protective layer 38.

[0055] The first dielectric layer 23 has a first surface 2311 and a second surface 2312 disposed opposite each other. The first patterned conductive layer 22 is located on the first surface 2311 of the first dielectric layer 23. Specifically, the first patterned conductive layer 22 is embedded in the first dielectric layer 23, with a surface 2211 of the first patterned conductive layer 22 exposed on the first surface 2311 of the first dielectric layer 23.

[0056] In this embodiment, the first patterned conductive layer 22 includes an external conductive pillar layer 221 and a patterned conductive layer 222 stacked on each other. A surface 2211 of the external conductive pillar layer 221 is exposed to the first surface 2311 of the first dielectric layer 23 and can serve as an electrode pad for electrical connection to other devices or structures (such as a PCB, not shown). The first patterned conductive layer 22 can be made of copper, and the exposed surface can be further treated with a surface treatment layer such as immersion tin (IT), electroplated nickel-palladium-gold (ENEPIG), electroplated nickel-palladium (ENEP), and organic solderability preservatives (OSP).

[0057] The first power chip 25 has a first electrode layout 251 and a second electrode layout 252. The first electrode layout 251 and the second electrode layout 252 are arranged opposite each other. The first power chip 25 is embedded in the first dielectric layer 23 and bonded to the patterned conductive layer 222 within the first dielectric layer 23 at the end of the second electrode layout 252 via the first conductive adhesive layer 24-1.

[0058] The control chip 26 has an active surface 261 and a back surface 262 disposed opposite each other. Similar to the first power chip 25, the control chip 26 is embedded in the first dielectric layer 23, and the back surface 262 of the control chip 26 is bonded to the patterned conductive layer 222 via the first conductive adhesive layer 24-2. However, in other embodiments, since the back surface 262 of the control chip 26 may not have connection pads, a conductive function is not required, and a less expensive adhesive layer may be used. Of course, in other embodiments, if the back surface of the control chip also has input / output connection pads (I / O pads), a conductive adhesive layer must be used to electrically connect to the first patterned conductive layer 22.

[0059] The first conductive adhesive layer 24-1 is disposed between the second electrode layout 252 of the first power chip 25 and the patterned conductive layer 222, thereby forming an electrical connection. The first conductive adhesive layer 24-2 is disposed between the back surface 262 of the control chip 26 and the patterned conductive layer 222, thereby forming an electrical connection.

[0060] The first conductive connection elements 27-1 and 27-2 are arranged on the electrode pads of the first electrode layout 251 of the first power chip 25, and the first conductive connection elements 27-3 and 27-4 are arranged on the electrode pads of the active surface 261 of the control chip 26, and one end of these first conductive connection elements 27-1, 27-2, 27-3, and 27-4 are exposed to the second surface 2312 of the first dielectric layer 23.

[0061] The first conductive pillars 28 - 1 and 28 - 2 are embedded in the first dielectric layer 23 , and one end of the first conductive pillars 28 - 1 and 28 - 2 is electrically connected to the patterned conductive layer 222 , while the other end thereof is exposed to the second surface 2312 of the first dielectric layer 23 .

[0062] In one embodiment, the geometric contours of the contact surfaces of the electrode pads of the first electrode layout 251 of the first power chips 25 are similar to each other; and the geometric contours of the contact surfaces of the electrode pads of the active surface 261 of the control chips 26 of the first conductive connection elements 27-1 and 27-2 are similar to each other; therefore, the electrical performance of the connection between each other can be effectively improved.

[0063] The second dielectric layer 36 has a third surface 361 and a fourth surface 362 opposite to each other, wherein the third surface 361 is bonded to the second surface 2312 of the first dielectric layer 23. Specifically, the third surface 361 of the second dielectric layer 36 and the second surface 2312 of the first dielectric layer 23 are substantially coplanar.

[0064] The second patterned conductive layer 31 is located on the third surface 361 of the second dielectric layer 36 and is electrically connected to the first electrode layout 251 of the first power chip 25 and the active surface 261 of the control chip 26 through the first conductive connection elements 27 - 1 , 27 - 2 , 27 - 3 , 27 - 4 of the first stacked structure 20 .

[0065] The second power chip 33 has a third electrode layout 331 and a fourth electrode layout 332. The second power chip 33 is embedded in the second dielectric layer 36 and bonded to the second patterned conductive layer 31 in the second dielectric layer 36 via the second conductive adhesive layer 32 at the fourth electrode layout 332.

[0066] The second conductive connection elements 34 - 1 and 34 - 2 are disposed on the third electrode layout 331 of the second power chip 33 , and one end portion of the second conductive connection elements 34 - 1 and 34 - 2 is exposed to the fourth surface 362 of the second dielectric layer 36 .

[0067] The second conductive pillars 35 - 1 and 35 - 2 are embedded in the second dielectric layer 36 , with one end connected to the second patterned conductive layer 31 in the second dielectric layer 36 and the other end exposed to the fourth surface 362 of the second dielectric layer 36 .

[0068] The third patterned conductive layer 37 is disposed on the fourth surface 362 of the second dielectric layer 36 to connect the second conductive pillars 35 - 1 and 35 - 2 and the second conductive connection elements 34 - 1 and 34 - 2 .

[0069] In one embodiment, the second conductive connection elements 34 - 1 , 34 - 2 have similar geometrical profiles to the contact surfaces of the electrode pads of the third electrode layout 331 of the second power chips 33 ; thus, the electrical performance of the connection can be effectively enhanced.

[0070] In this embodiment, the first power chip 25 and the second power chip 33 are identical power chips, each of which is a transistor chip, such as a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) chip. Therefore, the second electrode layout 252 and the fourth electrode layout 332 include a source S1 and S2, respectively. On the other hand, the first electrode layout 251 and the third electrode layout 331 include a gate G1 and G2 and a drain D1 and D2, respectively. In other words, the third electrode layout 331 is the same as the first electrode layout 251, and the fourth electrode layout 332 is the same as the second electrode layout 252. In addition, in other embodiments, the transistor chip can also be a bipolar junction transistor (BJT) chip or an insulated gate bipolar transistor (IGBT) chip, etc.

[0071] In addition, in this embodiment, the first dielectric layer 23 and the second dielectric layer 36 can be made of a high-filler content dielectric material, such as a molding compound. The molding compound is primarily composed of a novolac-based resin, an epoxy-based resin, or a silicone-based resin, which accounts for approximately 8 wt.% to 12 wt.% of the total molding compound, and is doped with a filler that accounts for approximately 70 wt.% to 90 wt.%. The filler can include silicon dioxide and aluminum oxide to increase mechanical strength, reduce linear thermal expansion coefficient, enhance thermal conductivity, improve water resistance, and reduce adhesive overflow.

[0072] Next, please match Figure 2 and Figures 3A to 3M As shown, the first method for manufacturing the semiconductor package structure 2 includes steps S01 to S17 .

[0073] like Figure 3AAs shown, step S01 involves providing a carrier plate 21, which can be a metal plate or an insulating plate. It is important to note that the present invention utilizes a panel-level packaging process; the area of ​​the carrier plate 21 is a multiple of the area of ​​a single wafer. Therefore, the large-scale carrier plate 21 of the present invention enables simultaneous packaging of all chips (or dies) cut from multiple wafers, effectively reducing manufacturing time.

[0074] Then, step S02 is to form an external conductive column layer 221 on a surface 211 of the carrier 21 . Next, step S03 is to form a first sub-dielectric layer 231 on the surface 211 of the carrier 21 and cover the external conductive column layer 221 .

[0075] like Figure 3B As shown, step S04 is to form a patterned conductive layer 222 on the external conductive pillar layer 221 and the first sub-dielectric layer 231. The external conductive pillar layer 221 and the patterned conductive layer 222 together constitute the first patterned conductive layer 22. In this embodiment, the external conductive pillar layer 221 and the patterned conductive layer 222 can be completed by photolithography and metal electroplating technology, and the material thereof is, for example, copper.

[0076] like Figure 3C As shown, step S05 involves disposing the first power chip 25 on the first patterned conductive layer 22 via the first conductive adhesive layer 24-1, and disposing the control chip 26 on the first patterned conductive layer 22 via the first conductive adhesive layer 24-2. Specifically, the first power chip 25 and the control chip 26 are disposed on the patterned conductive layer 222. In this embodiment, the first power chip 25 is bonded and electrically connected to the patterned conductive layer 222 via the first conductive adhesive layer 24-1 via the second electrode layout 252, while the control chip 26 is bonded and electrically connected to the patterned conductive layer 222 via the first conductive adhesive layer 24-2 via the back surface 262.

[0077] like Figure 3D As shown, step S06 is to form first conductive pillars 28-1 and 28-2 on the patterned conductive layer 222. In this embodiment, the first conductive pillars 28-1 and 28-2 can be formed by photolithography and metal electroplating techniques, and their material is, for example, copper. In other embodiments, the first conductive pillars 28-1 and 28-2 can also be pre-formed by electroless plating techniques and then disposed on the patterned conductive layer 222 via a conductive adhesive layer.

[0078] like Figure 3EAs shown, step S07 forms a second sub-dielectric layer 232 on the first sub-dielectric layer 231, covering the first patterned conductive layer 22, the first conductive adhesive layers 24-1 and 24-2, the first power chip 25, the control chip 26, and the first conductive pillars 28-1 and 28-2. In the present invention, the first sub-dielectric layer 231 and the second sub-dielectric layer 232 constitute the first dielectric layer 23. It should be noted that after forming the second sub-dielectric layer 232, a polishing process may be performed to expose one end surface of the first conductive pillars 28-1 and 28-2 to the second surface 2312 of the first dielectric layer 23.

[0079] like Figure 3F As shown, step S08 is to form first openings O1-1, O1-2, O1-3, and O1-4 in the first dielectric layer 23 to expose the first electrode layout 251 of the first power chip 25 and the active surface 261 of the control chip 26. The first openings O1-1, O1-2, O1-3, and O1-4 can be formed by laser drilling technology, or alternatively by plasma, mechanical drilling, or exposure, development, and etching processes.

[0080] like Figure 3G As shown, step S09 is to form first conductive connection elements 27-1, 27-2, 27-3, and 27-4 in the first openings O1-1, O1-2, O1-3, and O1-4, and to form a second patterned conductive layer 31 on the first dielectric layer 23 to electrically connect the first conductive pillars 28-1 and 28-2 and the first conductive connection elements 27-1, 27-2, 27-3, and 27-4. The second patterned conductive layer 31 and the first conductive connection elements 27-1, 27-2, 27-3, and 27-4 can be simultaneously formed by photolithography and metal electroplating techniques, and the material thereof is, for example, copper.

[0081] In other embodiments, the first conductive connection elements 27-1, 27-2, 27-3, 27-4 and the second patterned conductive layer 31 may also be formed by electroplating in stages. In addition, in other embodiments, the second patterned conductive layer 31 and the first conductive connection elements 27-1, 27-2, 27-3, 27-4 may also be formed by a filler, deposition, or patterning process.

[0082] like Figure 3H As shown, step S10 is to dispose the second power chip 33 on the second patterned conductive layer 31 through the second conductive adhesive layer 32. Further, the second power chip 33 is bonded and electrically connected to the second patterned conductive layer 31 through the second conductive adhesive layer 32 at the fourth electrode layout 332 end.

[0083] like Figure 3IAs shown, step S11 forms second conductive pillars 35-1 and 35-2 on the second patterned conductive layer 31. Similar to the first conductive pillars 28-1 and 28-2, the second conductive pillars 35-1 and 35-2 can be formed by photolithography and metal electroplating techniques, and their material is, for example, copper. In other embodiments, the second conductive pillars 35-1 and 35-2 can also be pre-formed by electroless plating techniques and then disposed on the second patterned conductive layer 31 via a conductive adhesive layer.

[0084] like Figure 3J As shown, step S12 is to form a second dielectric layer 36 to cover the second patterned conductive layer 31, the second power chip 33, and the second conductive pillars 35-1 and 35-2. It should be noted that after forming the second dielectric layer 36, a polishing process can be performed to expose one end surface of the second conductive pillars 35-1 and 35-2 to the fourth surface 362 of the second dielectric layer 36.

[0085] like Figure 3K As shown, step S13 forms second openings O2-1 and O2-2 in the second dielectric layer 36 to expose the third electrode layout 331 of the second power chip 33. Similar to the first openings O1-1, O1-2, O1-3, and O1-4, the second openings O2-1 and O2-2 can be formed by laser drilling technology, or alternatively, by plasma drilling, mechanical drilling, or exposure, development, and etching processes.

[0086] like Figure 3L As shown, step S14 is to form second conductive connection elements 34-1 and 34-2 in these second openings O2-1 and O2-2, and form a third patterned conductive layer 37 on the second dielectric layer 36 to electrically connect the second conductive pillars 35-1 and 35-2 and the second conductive connection elements 34-1 and 34-2. The second conductive connection elements 34-1 and 34-2 and the third patterned conductive layer 37 can also be completed by lithography and metal electroplating technology, and the material thereof is, for example, copper, which is not limited here. In other embodiments, the second conductive connection elements 34-1 and 34-2 and the second patterned conductive layer 31 can also be formed by electroplating in batches. In addition, the second conductive connection elements and the third patterned conductive layer can also be formed by filler, deposition, or patterning processes.

[0087] Finally, Figure 3M As shown, step S15 is to form a protective layer 38 and remove the carrier plate 21 to form Figure 2 The semiconductor package structure 2 is shown. A protective layer 38 is formed on the second dielectric layer 36 and covers the third patterned conductive layer 37. Meanwhile, at this step, the second stacked structure 30 is formed on the first stacked structure 20. In this embodiment, the protective layer 38 can be made of an insulating and anti-oxidation material.

[0088] Next, the second method for manufacturing the semiconductor package structure 2 is briefly described below, which includes steps S21 to S36 , wherein steps S21 to S25 are the same as steps S01 to S05 , and thus their description is omitted.

[0089] Please refer to Figure 4A As shown, step S26 is to form first conductive connection elements 27-1 and 27-2 on the first electrode layout 251 of the first power chip 25, and first conductive connection elements 27-3 and 27-4 on the active surface 261 of the control chip 26. Similar to the previous embodiment, the first conductive connection elements 27-1, 27-2, 27-3, and 27-4 can be completed by photolithography and metal plating technology, and their material is, for example, copper.

[0090] In one embodiment, the geometric profiles of the contact surfaces of the first conductive connection elements and the electrode pads on the first electrode layout 251 are similar. Furthermore, the geometric profiles of the contact surfaces of the first conductive connection elements and the electrode pads on the active surface 261 of the control chip 26 are also similar, which effectively improves electrical performance. The similar geometric profiles of the contact surfaces can include being completely identical or slightly different due to process tolerances.

[0091] Then as Figure 4B As shown, step S27 is the same as step S07 , forming first conductive pillars 28 - 1 and 28 - 2 on the patterned conductive layer 222 , and other details are omitted for brevity.

[0092] Then as Figure 4C As shown, step S28 forms a second sub-dielectric layer 232 on the first sub-dielectric layer 231, and covers the first patterned conductive layer 22, the first conductive adhesive layers 24-1 and 24-2, the first power chip 25, the control chip 26, the first conductive connection elements 27-1, 27-2, 27-3, and 27-4, and the first conductive pillars 28-1 and 28-2. It should be noted that after forming the second sub-dielectric layer 232, a polishing process may be performed to expose one end surface of the first conductive pillars 28-1 and 28-2 and one end surface of the first conductive connection elements 27-1, 27-2, 27-3, and 27-4 to the second surface 2312 of the first dielectric layer 23.

[0093] The subsequent steps S29 to S36 are the same as the aforementioned steps S10 to S17, and finally form the following Figure 2The semiconductor package structure shown is not described in detail here. Prior to forming the second conductive pillars 35-1 and 35-2, second conductive connecting elements 34-1 and 34-2 are formed on the third electrode layout 331 of the second power chip 33. Similar to the previous embodiment, the second conductive connecting elements 34-1 and 34-2 can be formed using photolithography and metal plating techniques, and their material, for example, is copper.

[0094] In one embodiment, the second conductive connection elements 34 - 1 and 34 - 2 have similar geometric profiles to the contact surfaces of the electrode pads on the third electrode layout 331 , so as to effectively improve the electrical performance.

[0095] The semiconductor package structure of the present invention has at least the following two changing states in addition to the first state mentioned above. Figure 5 and related instructions; and the third change state of the semiconductor package structure please refer to Figure 6A and Figure 6B And related instructions.

[0096] like Figure 5 As shown, the second state of the semiconductor package structure of the preferred embodiment of the present invention differs from the first state of the semiconductor package structure 2 described above in that the first power chip 25 and the second power chip 33 of the second state semiconductor package structure 2a are arranged in the reverse orientation of the first power chip 25 and the second power chip 33 of the previous embodiment. In other words, the first power chip 25 is bonded to the first patterned conductive layer 22 via the first conductive adhesive layer 24-1' at the end of the first electrode layout 251, while the second power chip 33 is bonded to the second patterned conductive layer 31 via the second conductive adhesive layer 32' at the end of the third electrode layout 331. The remaining components are identical to those of the previous embodiment and are not further described here.

[0097] In one embodiment, the geometric profiles of the contact surfaces of the first conductive connection elements 27 - 1 ′ and the electrode pads on the second electrode layout 252 are similar, so as to effectively improve the electrical performance.

[0098] In one embodiment, the second conductive connection elements 34 - 1 ′ have similar geometric profiles to the contact surfaces of the electrode pads on the fourth electrode layout 332 , so as to effectively improve the electrical performance.

[0099] like Figure 6A and Figure 6BAs shown, the third state of the semiconductor package structure of the preferred embodiment of the present invention differs from the semiconductor package structures of the first and second states described above in that the first patterned conductive layer 22 is composed solely of the patterned conductive layer 222, and therefore the first dielectric layer 23 is also composed solely of the second sub-dielectric layer 232. In other words, the first patterned conductive layer 22 and the first dielectric layer 23 are each a single-layer structure, which can be formed in the same step. Furthermore, a solder mask layer 39 can be further coated on the bottom side of the first patterned conductive layer 22, and the solder mask layer 39 is formed with a plurality of openings 391 to expose portions of the first patterned conductive layer 22 for use as solder pads.

[0100] In addition, in the above three semiconductor packaging states, the control chip 26 is not only embedded in the first dielectric layer 23, but also can be embedded in the second dielectric layer 36 and electrically connected to the third patterned conductive layer (such as Figure 7 ), making the overall design more flexible. Further, the control chip 26 of the semiconductor package structure 2b is bonded to the second patterned conductive layer 31 via the second adhesive layer 32 via the back surface 262, and is electrically connected to the third patterned conductive layer 37 via the active surface 261 via the second conductive connection elements 34-3 and 34-4.

[0101] Furthermore, the first conductive connecting element and the second conductive connecting element may also be conductive pillars, which may be copper pillars, copper alloy pillars or other conductive metal pillars formed by an electroplating process or an electroless plating process.

[0102] In summary, a semiconductor package structure and a manufacturing method thereof of the present invention is to arrange a first power chip and a second power chip, such as a transistor chip, in an inverted manner, which has the following characteristics:

[0103] (1) The first power chip and the second power chip are arranged in an upper and lower layer manner, and are arranged in the same direction (for example, the first electrode layout and the third electrode layout are both facing upward or downward), thereby shortening the distance of electrical connection between the power chips, and directly electrically connecting through, for example, electroplated copper conductors, rather than electrically connecting through solder balls as in traditional lead frames, thereby effectively increasing electrical performance and reducing the height of the package structure because a traditional lead frame is not required.

[0104] (2) Using semiconductor technology to replace the existing lead frame reflow process to significantly improve the accuracy of the packaging structure.

[0105] (3) The lead-containing lead frame reflow process is abandoned in the process, thus complying with the trend of environmental protection.

[0106] (4) One side of the power chip is fixed to the first patterned conductive layer or the second patterned conductive layer using a conductive adhesive layer (or adhesive layer), which can simplify the process.

[0107] The above description is only a preferred embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: A first stacking structure comprising: a first dielectric layer having a first surface and a second surface opposite to each other; a first patterned conductive layer embedded in the first dielectric layer, with one side exposed to the first surface of the first dielectric layer; a first power chip embedded in the first dielectric layer and having a first electrode layout and a second electrode layout disposed opposite each other, wherein the first power chip is bonded to the first patterned conductive layer within the first dielectric layer via a first conductive adhesive layer at an end of the second electrode layout, and at least one first conductive connecting element is disposed on the first electrode layout of the first power chip, with one end of the first conductive connecting element exposed at the second surface of the first dielectric layer; a control chip having an active surface and a back surface disposed opposite to each other, the control chip being embedded in the first dielectric layer, wherein the back surface of the control chip is bonded to the first patterned conductive layer via the first conductive adhesive layer, and the active surface of the control chip is connected to the second patterned conductive layer via a plurality of first conductive connection elements; and At least one first conductive pillar is embedded in the first dielectric layer, one end of the first conductive pillar is connected to the first patterned conductive layer in the first dielectric layer, and the other end is exposed to the second surface of the first dielectric layer; and a second stacking structure, stacked on the first stacking structure, comprising: a second dielectric layer having a third surface and a fourth surface opposite to each other, wherein the third surface is adjacent to the second surface of the first dielectric layer; a second patterned conductive layer embedded in the second dielectric layer, with one side exposed to the third surface of the second dielectric layer to connect the first conductive pillar and the first conductive connecting element; a second power chip embedded in the second dielectric layer and having a third electrode layout and a fourth electrode layout disposed opposite each other, the second power chip being bonded to the second patterned conductive layer within the second dielectric layer via a second conductive adhesive layer at an end of the fourth electrode layout, at least one second conductive connecting element being disposed on the third electrode layout of the second power chip, and one end of the second conductive connecting element being exposed to the fourth surface of the second dielectric layer, wherein projections of the second power chip and the first power chip along the stacking direction overlap; at least one second conductive pillar embedded in the second dielectric layer, one end of which is connected to the second patterned conductive layer in the second dielectric layer, and the other end of which is exposed to the fourth surface of the second dielectric layer; and A third patterned conductive layer is disposed on the fourth surface of the second dielectric layer and connects the second conductive pillar and the second conductive connecting element.

2. The semiconductor package structure according to claim 1, wherein: The first electrode layout and the third electrode layout include a drain and a gate, and the second electrode layout and the fourth electrode layout include a source.

3. The semiconductor package structure according to claim 1, wherein: The first electrode layout and the third electrode layout include a source, and the second electrode layout and the fourth electrode layout include a drain and a gate.

4. A semiconductor packaging structure, characterized in that: include: A first stacking structure comprising: a first dielectric layer having a first surface and a second surface opposite to each other; a first patterned conductive layer embedded in the first dielectric layer, with one side exposed to the first surface of the first dielectric layer; a first power chip embedded in the first dielectric layer and having a first electrode layout and a second electrode layout disposed opposite each other, wherein the first power chip is bonded to the first patterned conductive layer within the first dielectric layer via a first conductive adhesive layer at an end of the second electrode layout, and at least one first conductive connecting element is disposed on the first electrode layout of the first power chip, with one end of the first conductive connecting element exposed to the second surface of the first dielectric layer; and At least one first conductive pillar is embedded in the first dielectric layer, one end of the first conductive pillar is connected to the first patterned conductive layer in the first dielectric layer, and the other end is exposed to the second surface of the first dielectric layer; and a second stacking structure, stacked on the first stacking structure, comprising: a second dielectric layer having a third surface and a fourth surface opposite to each other, wherein the third surface is adjacent to the second surface of the first dielectric layer; a second patterned conductive layer embedded in the second dielectric layer, with one side exposed to the third surface of the second dielectric layer to connect the first conductive pillar and the first conductive connecting element; a second power chip embedded in the second dielectric layer and having a third electrode layout and a fourth electrode layout disposed opposite each other, the second power chip being bonded to the second patterned conductive layer within the second dielectric layer via a second conductive adhesive layer at an end of the fourth electrode layout, at least one second conductive connecting element being disposed on the third electrode layout of the second power chip, and one end of the second conductive connecting element being exposed to the fourth surface of the second dielectric layer, wherein projections of the second power chip and the first power chip along the stacking direction overlap; a control chip having an active surface and a back surface opposite to each other, the control chip being embedded in the second dielectric layer, wherein the back surface of the control chip is bonded to the second patterned conductive layer via the second conductive adhesive layer, and the active surface of the control chip is connected to the third patterned conductive layer via a plurality of second conductive connection elements; at least one second conductive pillar embedded in the second dielectric layer, one end of which is connected to the second patterned conductive layer in the second dielectric layer, and the other end of which is exposed to the fourth surface of the second dielectric layer; and A third patterned conductive layer is disposed on the fourth surface of the second dielectric layer and connects the second conductive pillar and the second conductive connecting element.

5. The semiconductor package structure according to claim 1 or 4, wherein: The first patterned conductive layer includes a patterned conductive layer and an external conductive column layer stacked on top of each other and electrically connected. The external conductive column layer is column-shaped, and one end portion is exposed to the first surface of the first dielectric layer.

6. A method for manufacturing a semiconductor packaging structure, characterized in that: include: providing a carrier plate; A first stacking structure is formed, comprising: forming a first patterned conductive layer on the carrier; Providing a first power chip having a first electrode layout and a second electrode layout disposed opposite to each other, and bonding the first power chip to the first patterned conductive layer at the second electrode layout end through a first conductive adhesive layer; Providing a control chip having an active surface and a back surface disposed opposite to each other, and bonding the control chip to the first patterned conductive layer via a first adhesive layer at the back surface; forming a plurality of first conductive connection elements on the first electrode layout of the first power chip and the active surface of the control chip; forming at least one first conductive pillar on the first patterned conductive layer; and forming a first dielectric layer to cover the first patterned conductive layer, the first power chip, the control chip, and the first conductive pillar, and exposing an end portion of the first conductive pillar and an end portion of the first conductive connection elements on the first power chip and the control chip; and A second stacking structure is formed, comprising: forming a second patterned conductive layer on the first dielectric layer of the first stacked structure to connect the first conductive pillar and the first conductive connecting element; A second power chip is provided, having a third electrode layout and a fourth electrode layout disposed opposite each other. The second power chip is bonded to the second patterned conductive layer via a second conductive adhesive layer at an end of the fourth electrode layout. At least one second conductive connection element is provided on the third electrode layout. The second power chip and the first power chip overlap in projection along the stacking direction. forming at least one second conductive connection element on the third electrode layout of the second power chip; forming at least one second conductive pillar on the second patterned conductive layer; forming a second dielectric layer to cover the second patterned conductive layer, the second power chip, and the second conductive pillar, and exposing an end portion of the second conductive pillar and an end portion of the second conductive connecting element; forming a third patterned conductive layer on the second dielectric layer to connect the second conductive pillar and the second conductive connection element; and Remove the carrier plate.

7. The method for manufacturing a semiconductor package structure according to claim 6, wherein: Also included: The first electrode layout and the third electrode layout include a drain and a gate, and the second electrode layout and the fourth electrode layout include a source.

8. The method for manufacturing a semiconductor package structure according to claim 6, wherein: Also included: The first electrode layout and the third electrode layout include a source, and the second electrode layout and the fourth electrode layout include a drain and a gate.

9. A method for manufacturing a semiconductor packaging structure, characterized in that: include: providing a carrier plate; A first stacking structure is formed, comprising: forming a first patterned conductive layer on the carrier; Providing a first power chip having a first electrode layout and a second electrode layout disposed opposite to each other, and bonding the first power chip to the first patterned conductive layer at the second electrode layout end through a first conductive adhesive layer; forming at least one first conductive connection element on the first electrode layout of the first power chip; forming at least one first conductive pillar on the first patterned conductive layer; and forming a first dielectric layer to cover the first patterned conductive layer, the first power chip, and the first conductive pillar, and exposing an end portion of the first conductive pillar and an end portion of the first conductive connecting element; and A second stacking structure is formed, comprising: forming a second patterned conductive layer on the first dielectric layer of the first stacked structure to connect the first conductive pillar and the first conductive connecting element; A second power chip is provided, having a third electrode layout and a fourth electrode layout disposed opposite each other. The second power chip is bonded to the second patterned conductive layer via a second conductive adhesive layer at an end of the fourth electrode layout. At least one second conductive connection element is provided on the third electrode layout. The second power chip and the first power chip overlap in projection along the stacking direction. Providing a control chip having an active surface and a back surface disposed opposite to each other, and connecting the control chip to the second patterned conductive layer via a second adhesive layer at the back surface; forming a plurality of second conductive connection elements on the third electrode layout of the second power chip and the active surface of the control chip; forming at least one second conductive pillar on the second patterned conductive layer; forming a second dielectric layer to cover the second patterned conductive layer, the second power chip, the control chip, and the second conductive pillar, and exposing one end of the second conductive pillar and one end of the second conductive connection elements on the second power chip and the control chip; forming a third patterned conductive layer on the second dielectric layer to connect the second conductive pillar and the second conductive connection element; and Remove the carrier plate.

10. A method for manufacturing a semiconductor packaging structure, characterized in that: include: providing a carrier plate; A first stacking structure is formed, comprising: forming a first patterned conductive layer on the carrier; Providing a first power chip having a first electrode layout and a second electrode layout disposed opposite to each other, and bonding the first power chip to the first patterned conductive layer at the second electrode layout end through a first conductive adhesive layer; forming at least one first conductive pillar on the first patterned conductive layer; Providing a control chip having an active surface and a back surface disposed opposite to each other, and bonding the control chip to the first patterned conductive layer via a first adhesive layer at the back surface; forming a first dielectric layer to cover the first patterned conductive layer, the first power chip, the control chip and the first conductive pillar, and exposing an end portion of the first conductive pillar; forming a plurality of first openings in the first dielectric layer to expose the first electrode layout of the first power chip and the active surface of the control chip; and forming a plurality of first conductive connection elements in the first opening to respectively connect the first electrode layout and the active surface of the control chip; and A second stacking structure is formed, comprising: forming a second patterned conductive layer on the first dielectric layer of the first stacked structure to connect the first conductive pillar and the first conductive connecting element; Providing a second power chip having a third electrode layout and a fourth electrode layout disposed opposite to each other, and bonding the second power chip to the second patterned conductive layer at the fourth electrode layout end via a second conductive adhesive layer, wherein the second power chip and the first power chip overlap in projection along the stacking direction; forming at least one second conductive pillar on the second patterned conductive layer; forming a second dielectric layer to cover the second patterned conductive layer, the second power chip and the second conductive pillar, and exposing an end portion of the second conductive pillar; forming at least one second opening in the second dielectric layer to expose the third electrode layout of the second power chip; forming a second conductive connecting element in the second opening to connect to the third electrode layout; forming a third patterned conductive layer on the second dielectric layer to connect the second conductive pillar and the second conductive connection element; and Remove the carrier plate.

11. The method for manufacturing a semiconductor package structure according to claim 10, wherein: Also included: The first electrode layout and the third electrode layout include a drain and a gate, and the second electrode layout and the fourth electrode layout include a source.

12. The method for manufacturing a semiconductor package structure according to claim 10, wherein: Also included: The first electrode layout and the third electrode layout include a source, and the second electrode layout and the fourth electrode layout include a drain and a gate.

13. The method for manufacturing a semiconductor package structure according to claim 6 or 10, wherein: The step of forming the first stacking structure further includes: forming a columnar external conductive column layer on a surface of the carrier plate; forming a first sub-dielectric layer covering the external conductive column layer and the surface of the carrier plate; forming a patterned conductive layer on the external conductive column layer and the first sub-dielectric layer, wherein the external conductive column layer and the patterned conductive layer together form the first patterned conductive layer; and After completing the processes of the first power chip, the control chip, and the first conductive pillar, a second sub-dielectric layer is formed on the first sub-dielectric layer to cover the first sub-dielectric layer, the first patterned conductive layer, the first conductive adhesive layer, the first power chip, the control chip, and the first conductive pillar, and to expose an end portion of the first conductive pillar, wherein the first sub-dielectric layer and the second sub-dielectric layer together form the first dielectric layer.

14. A method for manufacturing a semiconductor packaging structure, characterized in that: include: providing a carrier plate; A first stacking structure is formed, comprising: forming a first patterned conductive layer on the carrier; Providing a first power chip having a first electrode layout and a second electrode layout disposed opposite to each other, and bonding the first power chip to the first patterned conductive layer at the second electrode layout end through a first conductive adhesive layer; forming at least one first conductive pillar on the first patterned conductive layer; forming a first dielectric layer to cover the first patterned conductive layer, the first power chip, and the first conductive pillar, and exposing an end portion of the first conductive pillar; forming at least one first opening in the first dielectric layer to expose the first electrode layout of the first power chip; and forming a first conductive connection element in the first opening to connect the first electrode layout; and A second stacking structure is formed, comprising: forming a second patterned conductive layer on the first dielectric layer of the first stacked structure to connect the first conductive pillar and the first conductive connecting element; Providing a second power chip having a third electrode layout and a fourth electrode layout disposed opposite to each other, and bonding the second power chip to the second patterned conductive layer at the fourth electrode layout end via a second conductive adhesive layer, wherein the second power chip and the first power chip overlap in projection along the stacking direction; Providing a control chip having an active surface and a back surface disposed opposite to each other, and bonding the control chip to the second patterned conductive layer via a second adhesive layer at the back surface; forming at least one second conductive pillar on the second patterned conductive layer; forming a second dielectric layer to cover the second patterned conductive layer, the second power chip, the control chip and the second conductive pillar, and exposing an end portion of the second conductive pillar; forming a plurality of second openings in the second dielectric layer to expose the third electrode layout of the second power chip and the active surface of the control chip; forming a plurality of second conductive connection elements in the second opening to respectively connect the third electrode layout of the second power chip and the active surface of the control chip; forming a third patterned conductive layer on the second dielectric layer to connect the second conductive pillar and the second conductive connection element; and Remove the carrier plate.

15. The method for manufacturing a semiconductor package structure according to claim 10 or 14, wherein: The first opening is formed by laser, plasma, machine drilling, or exposure, development, and etching processes; and The first conductive connection element is formed by electroplating, filling, deposition or patterning.

16. The method for manufacturing a semiconductor package structure according to claim 10 or 14, wherein: The second opening is formed by laser, plasma, machine drilling, exposure, development and etching; and The second conductive connection element is formed by one of electroplating, filling, deposition and patterning processes.

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