A silicon carbide intelligent power module

Abstract

The embodiment of the present application belongs to the field of semiconductors and relates to a silicon carbide intelligent power module. It includes a substrate, a lead frame, a silicon carbide power module and a driving chipset; the lead frame is partially arranged on the substrate, and the silicon carbide power module is arranged on the substrate or the lead frame; the driving chipset includes an input-level chip, an isolation transformer chip and an output-level chip; the input-level chip, the isolation transformer chip and the output-level chip are separately arranged on the substrate or the lead frame; the input-level chip is used to process and protect the received input signal; the isolation transformer chip is connected between the input-level chip and the output-level chip, and is used to isolate the processed signal at high voltage, and transmit the signal after high-voltage isolation to the output-level chip; the output port of the output-level chip is electrically connected to the silicon carbide power module, and is used to drive the silicon carbide power module. The technical solution provided by the present application can improve reliability and ease of use.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a silicon carbide intelligent power module. Background Art

[0002] Intelligent power module, or IPM (Intelligent Power Module), is a power semiconductor system product that combines power electronics and integrated circuit technology. Intelligent power modules integrate power switching devices and high-voltage drive circuits, and have built-in fault detection circuits such as undervoltage, overcurrent and overheating. The voltage is generally 600V, and the current is generally 1A to 50A. The integrated power devices are silicon IGBT and silicon MOSFET. On the one hand, the intelligent power module receives the control signal of MCU and ASIC, performs voltage and current amplification, high and low voltage isolation, and drives the subsequent circuit to work. On the other hand, it performs abnormal detection and self-protection, and sends abnormal state detection signals back to MCU. Compared with traditional discrete solutions, intelligent power modules have won an increasingly large market with their advantages such as high integration and high reliability. They are especially suitable for inverters and various inverter systems for driving motors. They are an ideal power electronic device for industrial machinery motor drives, servo motor drives, variable frequency home appliances, electric vehicles, and new energy.

[0003] The HVIC inside the current IPM uses PN junction and HVJT isolation, and the isolation voltage cannot reach 1200V. Therefore, there is no 1200V IPM, let alone 1200V silicon carbide IPM, which makes the IPM reliability relatively poor. Silicon carbide MOS and SBD are currently mainly single-tube packages, and their driving circuits are mainly board-level circuits or single-tube package HVICs, which are inconvenient to use, making the IPM less convenient to use. Summary of the invention

[0004] The technical problem to be solved by the embodiments of the present application is how to improve the reliability and ease of use of the silicon carbide intelligent power module.

[0005] In order to solve the above technical problems, the embodiment of the present application provides a silicon carbide intelligent power module, which adopts the following technical solution:

[0006] A substrate, a lead frame, a silicon carbide power module, and a driving chipset for driving the silicon carbide power module; a portion of the lead frame is disposed on the substrate, and the silicon carbide power module is disposed on the substrate or the lead frame;

[0007] The driving chipset includes an input-stage chip, an isolation transformer chip and an output-stage chip;

[0008] The input-stage chip, the isolation transformer chip and the output-stage chip are separately arranged on the substrate or the lead frame;

[0009] The input-level chip is used to process and protect the received input signal;

[0010] The isolation transformer is connected between the input-level chip and the output-level chip, and is used to perform high-voltage isolation on the processed signal and transmit the high-voltage isolated signal to the output-level chip;

[0011] The output port of the output stage chip is electrically connected to the silicon carbide power module for driving the silicon carbide power module.

[0012] Further, the input stage chip includes an input port protection circuit, a Schmitt circuit, a first filtering circuit, a dead time and interlocking circuit, a first control circuit, a modulation circuit, an overcurrent detection and protection circuit, and a fault feedback circuit;

[0013] The input port protection circuit is used to provide electrostatic protection for the received input signal;

[0014] The Schmitt circuit is connected between the input port protection circuit and the first filter circuit and is used for signal shaping;

[0015] The output port of the first filtering circuit is electrically connected to the input port of the dead time and interlock circuit for signal filtering;

[0016] The output port of the dead time and interlock circuit is electrically connected to the input port of the first control circuit for dead time control;

[0017] The output port of the first control circuit is electrically connected to the output port of the modulation circuit for signal processing control;

[0018] The output port of the modulation circuit is electrically connected to the input port of the isolation transformer chip for signal modulation output;

[0019] The input port of the overcurrent detection and protection circuit is electrically connected to the output port of the input port protection circuit, and the output port of the overcurrent detection and protection circuit is electrically connected to the input port of the first filter circuit for overcurrent detection and protection;

[0020] The input port of the fault feedback circuit is electrically connected to the output port of the first filter circuit, and the output port of the fault feedback circuit is electrically connected to the first control circuit for fault detection.

[0021] Furthermore, the output stage chip includes a demodulation circuit, a second filtering circuit, an undervoltage protection circuit, a second control circuit, and a driving and dead zone circuit;

[0022] The input port of the demodulation circuit is electrically connected to the output port of the isolation transformer chip for signal demodulation;

[0023] The input port of the second filter circuit is electrically connected to the output port of the demodulation circuit, and the output port of the second filter circuit is electrically connected to the first input port of the second control circuit, for filtering the demodulated signal;

[0024] The input port of the undervoltage protection circuit is electrically connected to an external isolated power supply, and the output port of the undervoltage protection circuit is electrically connected to the second input port of the second control circuit for circuit undervoltage protection;

[0025] The output port of the second control circuit is electrically connected to the first input port of the drive and dead zone circuit for signal processing and control;

[0026] The second input port of the driving and dead zone circuit is electrically connected to the external isolated power supply, and the output port of the driving and dead zone circuit is electrically connected to the input port of the silicon carbide power module for driving the silicon carbide power module.

[0027] Furthermore, the output stage chip further includes: a first output NMOS transistor, a second output NMOS transistor, a first integrated driving resistor and a second integrated driving resistor;

[0028] The gate of the first output NMOS tube is electrically connected to the third input port of the driving and dead zone circuit, the drain of the first output NMOS tube is electrically connected to the external isolated power supply, the source of the first output NMOS tube is electrically connected to one end of the first integrated driving resistor, and the other end of the first integrated driving resistor is electrically connected to the output port of the driving and dead zone circuit;

[0029] The gate of the second output NMOS tube is electrically connected to the fourth input port of the drive and dead zone circuit, the drain of the second output NMOS tube is electrically connected to the external isolation power supply, the source of the second output NMOS tube is electrically connected to one end of the second integrated drive resistor, and the other end of the second integrated drive resistor is electrically connected to the output port of the drive and dead zone circuit.

[0030] Furthermore, the silicon carbide power module includes a first silicon carbide MOS tube and a first silicon carbide special diode anti-parallel to the silicon carbide MOS tube, the drain of the first silicon carbide MOS tube is electrically connected to the cathode of the first silicon carbide special diode, the source of the first silicon carbide MOS tube is electrically connected to the anode of the first silicon carbide special diode, and the gate of the first silicon carbide MOS tube is electrically connected to the output port of the output stage chip.

[0031] Further, the silicon carbide power module is a half-bridge silicon carbide module, and the half-bridge silicon carbide module includes a second silicon carbide MOS tube, a third silicon carbide MOS tube, a second silicon carbide FET diode and a third silicon carbide FET diode;

[0032] The drain of the second silicon carbide MOS tube is electrically connected to the cathode of the second silicon carbide FET diode, the source of the second silicon carbide MOS tube is electrically connected to the anode of the second silicon carbide FET diode, and the gate of the second silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0033] The drain of the third silicon carbide MOS tube is electrically connected to the cathode of the third silicon carbide FET diode, the source of the third silicon carbide MOS tube is electrically connected to the anode of the third silicon carbide FET diode, and the gate of the third silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0034] The source of the second silicon carbide MOS tube is electrically connected to the drain of the third silicon carbide MOS tube.

[0035] Further, the silicon carbide power module is an H-bridge silicon carbide module, and the H-bridge silicon carbide module includes a fourth silicon carbide MOS tube, a fifth silicon carbide MOS tube, a sixth silicon carbide MOS tube, a seventh silicon carbide MOS tube, a fourth silicon carbide FET diode, a fifth silicon carbide FET diode, a sixth silicon carbide FET diode, and a seventh silicon carbide FET diode; the gate of each silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0036] The drain of the fourth silicon carbide MOS tube is electrically connected to the cathode of the fourth silicon carbide FET diode, the source of the fourth silicon carbide MOS tube is electrically connected to the anode of the fourth silicon carbide FET diode, and the gate of the fourth silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0037] The drain of the fifth silicon carbide MOS tube is electrically connected to the cathode of the fifth silicon carbide FET diode, the source of the fifth silicon carbide MOS tube is electrically connected to the anode of the fifth silicon carbide FET diode, and the gate of the fifth silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0038] The drain of the sixth silicon carbide MOS tube is electrically connected to the cathode of the sixth silicon carbide FET diode, the source of the sixth silicon carbide MOS tube is electrically connected to the anode of the sixth silicon carbide FET diode, and the gate of the sixth silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0039] The drain of the seventh silicon carbide MOS tube is electrically connected to the cathode of the third silicon carbide FET diode, the source of the seventh silicon carbide MOS tube is electrically connected to the anode of the third silicon carbide FET diode, and the gate of the seventh silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0040] The source electrode of the fourth silicon carbide MOS tube is electrically connected to the drain electrode of the fifth silicon carbide MOS tube;

[0041] The source electrode of the sixth silicon carbide MOS tube is electrically connected to the drain electrode of the seventh silicon carbide MOS tube;

[0042] The source of the fourth silicon carbide MOS tube is electrically connected to the source of the sixth silicon carbide MOS tube.

[0043] Further, the silicon carbide power module is a full-bridge silicon carbide module, and the full-bridge silicon carbide module includes an eighth silicon carbide MOS tube, a ninth silicon carbide MOS tube, a tenth silicon carbide MOS tube, an eleventh silicon carbide MOS tube, a twelfth silicon carbide MOS tube, a thirteenth silicon carbide MOS tube, an eighth silicon carbide FET diode, a ninth silicon carbide FET diode, a tenth silicon carbide FET diode, an eleventh silicon carbide FET diode, a twelfth silicon carbide FET diode and a thirteenth silicon carbide FET diode;

[0044] The drain of the eighth silicon carbide MOS tube is electrically connected to the cathode of the eighth silicon carbide FET diode, the source of the eighth silicon carbide MOS tube is electrically connected to the anode of the eighth silicon carbide FET diode, and the gate of the eighth silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0045] The drain of the ninth silicon carbide MOS tube is electrically connected to the cathode of the ninth silicon carbide FET diode, the source of the ninth silicon carbide MOS tube is electrically connected to the anode of the ninth silicon carbide FET diode, and the gate of the ninth silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0046] The drain of the tenth silicon carbide MOS tube is electrically connected to the cathode of the tenth silicon carbide FET diode, the source of the tenth silicon carbide MOS tube is electrically connected to the anode of the tenth silicon carbide FET diode, and the gate of the tenth silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0047] The drain of the eleventh silicon carbide MOS tube is electrically connected to the cathode of the eleventh silicon carbide FET diode, the source of the eleventh silicon carbide MOS tube is electrically connected to the anode of the eleventh silicon carbide FET diode, and the gate of the eleventh silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0048] The drain of the twelfth silicon carbide MOS tube is electrically connected to the cathode of the twelfth silicon carbide FET diode, the source of the twelfth silicon carbide MOS tube is electrically connected to the anode of the twelfth silicon carbide FET diode, and the gate of the twelfth silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0049] The drain of the thirteenth silicon carbide MOS tube is electrically connected to the cathode of the thirteenth silicon carbide FET diode, the source of the thirteenth silicon carbide MOS tube is electrically connected to the anode of the thirteenth silicon carbide FET diode, and the gate of the thirteenth silicon carbide MOS tube is electrically connected to the output port of the output stage chip;

[0050] The source electrode of the eighth silicon carbide MOS tube is electrically connected to the drain electrode of the ninth silicon carbide MOS tube;

[0051] The source electrode of the tenth silicon carbide MOS tube is electrically connected to the drain electrode of the eleventh silicon carbide MOS tube;

[0052] The source electrode of the twelfth silicon carbide MOS tube is electrically connected to the drain electrode of the thirteenth silicon carbide MOS tube;

[0053] The source of the eighth silicon carbide MOS tube, the source of the tenth silicon carbide MOS tube and the source of the twelfth silicon carbide MOS tube are electrically connected.

[0054] Furthermore, the substrate is an IMS substrate, and the lead frame is partially fixed on both side edges of the IMS substrate; the input-level chip, the isolation transformer chip and the output-level chip are separately arranged on one end plate of the IMS substrate, and the silicon carbide power module is arranged on the other end plate of the IMS substrate.

[0055] Further, the substrate is a DBC substrate, a portion of the lead frame is fixed to a side edge of the DBC substrate, and another portion of the lead frame is partially and separately arranged on one side of the DBC substrate and spaced apart from the DBC substrate;

[0056] Wherein, the silicon carbide power module is arranged on the DBC substrate;

[0057] The input-stage chip, the isolation transformer chip and the output-stage chip are separately arranged on a lead frame on one side of the DBC substrate.

[0058] Compared with the prior art, the embodiments of the present application have the following beneficial effects: the present application drives the silicon carbide power module by providing a driving chipset including an input-level chip, an isolation transformer chip, and an output-level chip. Specifically, the input signal processing and protection are realized by the input-level chip, and the signal transmission and high-voltage isolation are realized by the isolation transformer chip. Finally, the silicon carbide power module is driven by the output-level chip. Thus, a silicon carbide intelligent power module with a voltage of 600V, 1200V or even higher can be realized; at the same time, the driving chipset and the silicon carbide power module are both integrated, which makes the traditional SiC power system miniaturized and integrated, and further improves reliability and ease of use. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the scheme of the present application, a brief introduction is given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0060] Figure 1 This is a schematic diagram of a framework of a silicon carbide intelligent power module provided in an embodiment of the present application;

[0061] Figure 2 It is a schematic diagram of the framework of another silicon carbide intelligent power module provided in an embodiment of the present application;

[0062] Figure 3 This is a schematic diagram of a framework of another silicon carbide intelligent power module provided in an embodiment of the present application;

[0063] Figure 4 is a circuit diagram of an isolation transformer chip provided in an embodiment of the present application;

[0064] Figure 5 is a circuit diagram of a single silicon carbide module provided in an embodiment of the present application;

[0065] Figure 6 This is a circuit diagram of a double-bridge silicon carbide module provided in an embodiment of the present application;

[0066] Figure 7 This is a circuit diagram of an H-bridge silicon carbide module provided in an embodiment of the present application;

[0067] Figure 8 This is a circuit diagram of a full-bridge silicon carbide module provided in an embodiment of the present application;

[0068] Fig. 9 is a circuit diagram of an input-level chip provided in an embodiment of the present application;

[0069] Fig.10 is a circuit diagram of an output-stage chip provided in an embodiment of the present application;

[0070] Fig.11 It is a plan schematic diagram of a full-bridge silicon carbide intelligent power module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0071] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of this application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" and any variations thereof in the specification and claims of this application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0072] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0073] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0074] like Figure 1-Figure 3 As shown, the silicon carbide intelligent power module of the present application includes: a substrate 1, a lead frame 2, a silicon carbide power module, and a driving chipset for driving the silicon carbide power module. The lead frame is partially arranged on the substrate, and the silicon carbide power module is arranged on the substrate or the lead frame 2. The driving chipset includes an input-stage chip 3, an isolation transformer chip 4, and an output-stage chip 5. The input-stage chip 3, the isolation transformer chip 4, and the output-stage chip 5 are separately arranged on the substrate 1 or the lead frame 2.

[0075] The input chip 3 is used to process and protect the received input signal. The input chip 3 also includes power ports VDD and VSS for connecting an external power supply; function ports, etc.

[0076] The isolation transformer chip 4 is connected between the input stage chip 3 and the output stage chip 5, and is used to isolate the processed signal at high voltage and transmit the high voltage isolated signal to the output stage chip 5. The output port of the output transformer is electrically connected to the input port of the output stage chip 5 for signal transmission and high voltage isolation. Figure 4 As shown, the isolation transformer chip 4 is an integrated isolation transformer chip, specifically an integrated circuit chip process isolation transformer, which uses integrated circuit technology to manufacture input coils, output coils, magnetic cores and other structures on the chip, and has an isolation capability of more than 2000V between the input coil and the output coil. The isolation transformer chip 4 includes a primary input terminal IN1, a primary input terminal IN2, a secondary output terminal OUT1 and a secondary output terminal OUT2.

[0077] The output port of the output stage chip 5 is electrically connected to the silicon carbide power module for driving the silicon carbide power module. At the same time, the output stage chip 5 also has a built-in undervoltage protection circuit 25. The output stage chip 5 also includes a power port, which is connected to an external independent isolated power supply.

[0078] It should be noted that the substrate 1 , the lead frame 2 , the silicon carbide power module and the driving chipset may be connected via bonding wires and bonding pads.

[0079] The silicon carbide power module can be one of a single silicon carbide module, a half-bridge silicon carbide module, an H-bridge silicon carbide module, and a full-bridge silicon carbide module; the silicon carbide power module includes one or more integrated silicon carbide MOS tubes 6 (SiC MOSFET) and silicon carbide special diodes 7 (SiC SBD).

[0080] Specifically, Figure 5 As shown, when the silicon carbide power module is a single silicon carbide module, the single silicon carbide module includes a first silicon carbide MOS tube Q1 and a first silicon carbide FET diode D1 anti-parallel to the silicon carbide MOS tube, the drain of the first silicon carbide MOS tube Q1 is electrically connected to the cathode of the first silicon carbide FET diode D1, the source of the first silicon carbide MOS tube Q1 is electrically connected to the anode of the first silicon carbide FET diode D1, and the gate of the first silicon carbide MOS tube Q1 is electrically connected to the output port of the output stage chip. In the embodiment of the present application, the silicon carbide MOS tube 6 and the silicon carbide FET diode 7 are used to distinguish between silicon carbide MOS tubes and silicon carbide FET diodes, and the silicon carbide MOS tubes and silicon carbide FET diodes are not limited.

[0081] like Figure 6As shown, when the silicon carbide power module is a half-bridge (dual-path) silicon carbide module (SiC MOSFET module), the half-bridge silicon carbide module includes a second silicon carbide MOS tube Q2, a third silicon carbide MOS tube Q3, a second silicon carbide FET diode D2, and a third silicon carbide FET diode D3. The drain of the second silicon carbide MOS tube Q2 is electrically connected to the cathode of the second silicon carbide FET diode D2, the source of the second silicon carbide MOS tube Q2 is electrically connected to the anode of the second silicon carbide FET diode D2, and the gate of the second silicon carbide MOS tube Q2 is electrically connected to the output port of the output stage chip. The drain of the third silicon carbide MOS tube Q3 is electrically connected to the cathode of the third silicon carbide FET diode D3, the source of the third silicon carbide MOS tube Q3 is electrically connected to the anode of the third silicon carbide FET diode D3, and the gate of the third silicon carbide MOS tube Q3 is electrically connected to the output port of the output stage chip. The source of the second silicon carbide MOS tube Q2 is electrically connected to the drain of the third silicon carbide MOS tube Q3. The source of the second silicon carbide MOS transistor Q2 and the drain of the third silicon carbide MOS transistor Q3 form a power output port A. The drain of the second silicon carbide MOS transistor Q2 is a power output port P, and the source of the third silicon carbide MOS transistor Q3 is a power output port N.

[0082] It should be noted that when the silicon carbide power module is a half-bridge silicon carbide module, the corresponding input-stage chip 3 can be a dual-channel input or two separate single-channel input-stage chips. The isolation transformer chip 4 can also be a dual-channel or two separate chips. The number of output-stage chips corresponds to the number of silicon carbide MOS tubes, which is two, and the output port of each output-stage chip is electrically connected to the gate of a silicon carbide MOS tube. In this way, the circuit connection of the half-bridge silicon carbide module can be satisfied, and the corresponding half-bridge silicon carbide module can be driven to realize the function of the dual-bridge silicon carbide intelligent power module.

[0083] like Figure 7 As shown, when the silicon carbide power module is an H-bridge (4-way) silicon carbide module (SiC MOSFET module), the H-bridge silicon carbide module includes a fourth silicon carbide MOS tube Q4, a fifth silicon carbide MOS tube Q5, a sixth silicon carbide MOS tube Q6, a seventh silicon carbide MOS tube Q7, a fourth silicon carbide FET diode D4, a fifth silicon carbide FET diode D5, a sixth silicon carbide FET diode D6 and a seventh silicon carbide FET diode D7; the gate of each silicon carbide MOS tube is electrically connected to the output port of the output stage chip.

[0084] The drain of the fourth silicon carbide MOS tube Q4 is electrically connected to the cathode of the fourth silicon carbide FET diode D4, the source of the fourth silicon carbide MOS tube Q4 is electrically connected to the anode of the fourth silicon carbide FET diode D4, and the gate of the fourth silicon carbide MOS tube Q4 is electrically connected to the output port of the output stage chip.

[0085] The drain of the fifth silicon carbide MOS tube Q5 is electrically connected to the cathode of the fifth silicon carbide FET diode D5, the source of the fifth silicon carbide MOS tube Q5 is electrically connected to the anode of the fifth silicon carbide FET diode D5, and the gate of the fifth silicon carbide MOS tube Q5 is electrically connected to the output port of the output stage chip.

[0086] The drain of the sixth silicon carbide MOS tube Q6 is electrically connected to the cathode of the sixth silicon carbide FET diode D6, the source of the sixth silicon carbide MOS tube Q6 is electrically connected to the anode of the sixth silicon carbide FET diode D6, and the gate of the sixth silicon carbide MOS tube Q6 is electrically connected to the output port of the output stage chip.

[0087] The drain of the seventh silicon carbide MOS tube Q7 is electrically connected to the cathode of the seventh silicon carbide FET diode D7, the source of the seventh silicon carbide MOS tube Q7 is electrically connected to the anode of the seventh silicon carbide FET diode D7, and the gate of the seventh silicon carbide MOS tube Q7 is electrically connected to the output port of the output stage chip.

[0088] The source of the fourth silicon carbide MOS transistor Q4 is electrically connected to the drain of the fifth silicon carbide MOS transistor Q5 to form a power output port A. The source of the sixth silicon carbide MOS transistor Q6 is electrically connected to the drain of the seventh silicon carbide MOS transistor Q7 to form a power output port B. The source of the fourth silicon carbide MOS transistor Q4 is electrically connected to the source of the sixth silicon carbide MOS transistor Q6 to form a power output port P. The source of the fifth silicon carbide MOS transistor Q5 forms a power output port NA, and the source of the seventh silicon carbide MOS transistor Q7 forms a power output port NB.

[0089] It should be noted that when the silicon carbide power module is an H-bridge silicon carbide module, the corresponding input-stage chip 3 can be a 4-way input, or it can be 2 dual-way input chips, or it can be 4 separate single-way input-stage chips 3. Similarly, the isolation transformer chip 4 can be a 4-way integration, or it can be two separate dual-way isolation transformer chips, or it can be 4 single-way isolation transformer chips. The number of output-stage chips corresponds to the number of silicon carbide MOS tubes, which is four, and the output port of each output-stage chip corresponds to the gate of a silicon carbide MOS tube. In this way, the circuit connection of the H-bridge silicon carbide module can be met, and then the corresponding H-bridge silicon carbide module can be driven to realize the function of the H-bridge silicon carbide intelligent power module.

[0090] like Figure 8As shown, when the silicon carbide power module is a full-bridge (6-way) silicon carbide module (SiC MOSFET module), the full-bridge silicon carbide module includes an eighth silicon carbide MOS tube Q8, a ninth silicon carbide MOS tube Q9, a tenth silicon carbide MOS tube Q10, an eleventh silicon carbide MOS tube Q11, a twelfth silicon carbide MOS tube Q12, a thirteenth silicon carbide MOS tube Q13, an eighth silicon carbide FET diode D8, a ninth silicon carbide FET diode D9, a tenth silicon carbide FET diode D10, an eleventh silicon carbide FET diode D11, a twelfth silicon carbide FET diode D12 and a thirteenth silicon carbide FET diode D13.

[0091] The drain of the eighth silicon carbide MOS tube Q8 is electrically connected to the cathode of the eighth silicon carbide FET diode D8, the source of the eighth silicon carbide MOS tube Q8 is electrically connected to the anode of the eighth silicon carbide FET diode D8, and the gate of the eighth silicon carbide MOS tube Q8 is electrically connected to the output port of the output stage chip.

[0092] The drain of the ninth silicon carbide MOS tube Q9 is electrically connected to the cathode of the ninth silicon carbide FET diode D9, the source of the ninth silicon carbide MOS tube Q9 is electrically connected to the anode of the ninth silicon carbide FET diode D9, and the gate of the ninth silicon carbide MOS tube Q9 is electrically connected to the output port of the output stage chip.

[0093] The drain of the tenth silicon carbide MOS tube Q10 is electrically connected to the cathode of the tenth silicon carbide FET diode D10, the source of the tenth silicon carbide MOS tube Q10 is electrically connected to the anode of the tenth silicon carbide FET diode D10, and the gate of the tenth silicon carbide MOS tube Q10 is electrically connected to the output port of the output stage chip.

[0094] The drain of the eleventh silicon carbide MOS tube Q11 is electrically connected to the cathode of the eleventh silicon carbide FET diode D11, the source of the eleventh silicon carbide MOS tube Q11 is electrically connected to the anode of the eleventh silicon carbide FET diode D11, and the gate of the eleventh silicon carbide MOS tube Q11 is electrically connected to the output port of the output stage chip.

[0095] The drain of the twelfth silicon carbide MOS tube Q12 is electrically connected to the cathode of the twelfth silicon carbide FET diode D12, the source of the twelfth silicon carbide MOS tube Q12 is electrically connected to the anode of the twelfth silicon carbide FET diode D12, and the gate of the twelfth silicon carbide MOS tube Q12 is electrically connected to the output port of the output stage chip.

[0096] The drain of the thirteenth silicon carbide MOS tube Q13 is electrically connected to the cathode of the thirteenth silicon carbide FET diode D13, the source of the thirteenth silicon carbide MOS tube Q13 is electrically connected to the anode of the thirteenth silicon carbide FET diode D13, and the gate of the thirteenth silicon carbide MOS tube Q13 is electrically connected to the output port of the output stage chip.

[0097] The source of the eighth silicon carbide MOS transistor Q8 is electrically connected to the drain of the ninth silicon carbide MOS transistor Q9 to form a power output port A. The source of the tenth silicon carbide MOS transistor Q10 is electrically connected to the drain of the eleventh silicon carbide MOS transistor Q11 to form a power output port B. The source of the twelfth silicon carbide MOS transistor Q12 is electrically connected to the drain of the thirteenth silicon carbide MOS transistor Q13 to form a power output port C. The source of the eighth silicon carbide MOS transistor Q8, the source of the tenth silicon carbide MOS transistor Q10, and the source of the twelfth silicon carbide MOS transistor Q12 are electrically connected to form a power output port P. The source of the ninth silicon carbide MOS transistor Q9 forms a power output port NA, the source of the eleventh silicon carbide MOS transistor Q11 forms a power output port NB, and the source of the thirteenth silicon carbide MOS transistor Q13 forms a power output port NC.

[0098] It should be noted that when the silicon carbide power module is a full-bridge silicon carbide module, the corresponding input-stage chip 3 can be 6-way input, 3 dual-way input chips, 2 triple-way input chips, or 6 single-way input-stage chips. Similarly, the isolation transformer chip 4 can be 6-way integrated, 3 dual-way isolation transformer chips, 2 triple-way isolation transformer chips 4, or 6 single-way isolation transformer chips 4. The number of output-stage chips corresponds to the number of silicon carbide MOS tubes, which is six, and the output port of each output-stage chip corresponds to the gate of a silicon carbide MOS tube. In this way, the circuit connection of the full-bridge silicon carbide module can be met, and then the corresponding full-bridge silicon carbide module can be driven to realize the function of the full-bridge silicon carbide intelligent power module.

[0099] The present application drives the silicon carbide power module by providing a driving chipset including an input chip 3, an isolation transformer chip 4 and an output chip 5. Specifically, the input signal processing and protection are realized by the input chip 3, the signal transmission and high-voltage isolation are realized by the isolation transformer chip 4, and finally the driving of the silicon carbide power module is realized by the output chip 5. Thus, a silicon carbide (SiC) intelligent power module with a voltage of 600V, 1200V or even higher can be realized; at the same time, the driving chipset and the silicon carbide power module are integrated, which makes the traditional SiC power system miniaturized and integrated, and further improves the reliability and convenience of use.

[0100] In the embodiments of the present application, Fig. 9As shown, the input stage chip 3 includes an input port protection circuit, a Schmitt circuit, a first filtering circuit, a dead time and interlocking circuit 17, a first control circuit 18, a modulation circuit, an overcurrent detection and protection circuit 16, and a fault feedback circuit 21. The input port protection circuit is used to provide electrostatic protection for the received input signal. The Schmitt circuit is connected between the input port protection circuit and the first filtering circuit for signal shaping. The output port of the first filtering circuit is electrically connected to the input port of the dead time and interlocking circuit 17 for signal filtering and filtering out interference signals. The output port of the dead time and interlocking circuit 17 is electrically connected to the input port of the first control circuit 18 for dead time control. The output port of the first control circuit 18 is electrically connected to the output port of the modulation circuit for signal processing control. The output port of the modulation circuit is electrically connected to the input port of the isolation transformer chip 4 for signal modulation output. The input port of the overcurrent detection and protection circuit 16 is electrically connected to the output port of the input port protection circuit, and the output port of the overcurrent detection and protection circuit 16 is electrically connected to the input port of the first filtering circuit for overcurrent detection and protection. The input port of the fault feedback circuit 21 is electrically connected to the output port of the first filter circuit, and the output port of the fault feedback circuit 21 is electrically connected to the first control circuit 18 for fault detection.

[0101] Specifically, the input port protection circuit is an input port ESD (Electro-Static discharge) protection circuit, and the input port ESD protection circuit includes a first input port ESD protection unit 8 , a second input port ESD protection unit 9 , and a third input port ESD protection unit 10 .

[0102] The Schmitt circuit includes a first Schmitt cell 11 and a second Schmitt cell 12. The first filter circuit includes a first filter unit 13, a second filter unit 14 and a third filter unit 15.

[0103] The modulation circuit includes a first modulation unit 19 and a second modulation unit 20 .

[0104] The input port of the first input port ESD protection unit 8 is electrically connected to the input power supply INA, and the output port of the first input port ESD protection unit 8 is electrically connected to the input port of the first Schmitt unit 11. The output port of the first Schmitt unit 11 is electrically connected to the input port of the first filter unit 13. The output port of the first filter unit 13 is electrically connected to the first input port of the dead time and interlock circuit 17. The first output port of the dead time and interlock circuit 17 is electrically connected to the first input port of the first control circuit 18. The second output port of the dead time and interlock circuit 17 is electrically connected to the second input port of the first control circuit 18. The first output port of the first control circuit 18 is electrically connected to the input port of the first modulation unit 19, and the output port of the first modulation unit 19 includes output ports OUTA1 and OUTA2, which are electrically connected to the input port of the isolation transformer chip 4 respectively. The second output port of the output first control circuit 18 is electrically connected to the input port of the second modulation unit 20. The output port of the second modulation unit 20 includes output ports OUTB1 and OUTB2, which are electrically connected to the input port of the isolation transformer chip 4 respectively.

[0105] The input port of the second input port ESD protection unit 9 is electrically connected to the input power supply I NB, and the output port of the second input port ESD protection unit 9 is electrically connected to the input port of the second Schmitt cell 12. The output port of the second Schmitt cell 12 is electrically connected to the input port of the second filtering unit 14. The output port of the second filtering unit 14 is electrically connected to the second input port of the dead time and interlock circuit 17.

[0106] The input port of the third input port ESD protection unit 10 is electrically connected to the fuse current (ITRIP) input port, and the output port of the third input port ESD protection unit 10 is electrically connected to the input port of the overcurrent detection and protection circuit 16 (specifically, the ITRIP overcurrent detection and protection circuit). The output port of the output port of the overcurrent detection and protection circuit 16 is electrically connected to the input port of the third filter unit 15, the output port of the third filter unit 15 is electrically connected to the first input port of the fault feedback circuit 21, and the output port of the fault feedback circuit 21 is electrically connected to the third input port of the first control circuit 18. Among them, the second input port of the fault feedback circuit 21 is electrically connected to the gate of the MOS tube, the source of the MOS tube is grounded, and the drain of the MOS tube is electrically connected to the pin FO (fast port). The MOS tube is used to control the switch of the pin FO.

[0107] The input stage chip 3 further includes a temperature detection circuit 22 , which is electrically connected to the first control circuit 18 and is used to detect the temperature of the entire circuit and output the temperature to the first control circuit 18 .

[0108] In the embodiment of the present application, the input stage chip 3 can perform Schmitt and filtering processing on the input signal through the input port protection circuit, Schmitt circuit, first filtering circuit, dead time and interlock circuit 17, first control circuit 18, modulation circuit, overcurrent detection and protection circuit 16 and fault feedback circuit 21, and detect and control the input signal, fault, current and temperature in the input stage chip 3 through the dead time and interlock circuit 17 and the first control circuit 18, and modulate it into an analog signal through the modulation circuit and output it to the isolation transformer chip 4 for voltage isolation processing. Then the input signal processing and protection are realized.

[0109] In the embodiments of the present application, Fig.10 As shown, the output stage chip 5 includes a demodulation circuit 23, a second filter circuit 24, an undervoltage protection circuit 25, a second control circuit 26, and a drive and dead zone circuit 27. The input port of the demodulation circuit 23 is electrically connected to the output port of the isolation transformer chip 4 for signal demodulation. The input port of the second filter circuit 24 is electrically connected to the output port of the demodulation circuit 23, and the output port of the second filter circuit 24 is electrically connected to the first input port of the second control circuit 26 for filtering the demodulated signal. The input port of the undervoltage protection circuit 25 is electrically connected to an external isolated power supply, and the output port of the undervoltage protection circuit 25 is electrically connected to the second input port of the second control circuit 26 for circuit undervoltage protection. The output port of the second control circuit 26 is electrically connected to the first input port of the drive and dead zone circuit 27 for signal processing and control. The second input port of the drive and dead zone circuit 27 is electrically connected to the external isolated power supply, and the output port of the drive and dead zone circuit 27 is electrically connected to the input port of the silicon carbide power module for driving the silicon carbide power module.

[0110] Specifically, the input port of the demodulation circuit 23 (input port one IN1 is electrically connected to IN1 of the isolation transformer chip 4 , and input port two is electrically connected to IN2 of the isolation transformer chip 4 ) and the output port of the demodulation circuit 23 are electrically connected to the input port of the second filter circuit 24 .

[0111] The output stage chip 5 further includes: a first output NMOS transistor 28, a second output NMOS transistor 31, a first integrated driving resistor 29 and a second integrated driving resistor 30. The gate of the first output NMOS transistor 28 is electrically connected to the third input port of the driving and dead zone circuit 27, the drain of the first output NMOS transistor 28 is electrically connected to the external isolated power supply, the source of the first output NMOS transistor 28 is electrically connected to one end of the first integrated driving resistor 29, and the other end of the first integrated driving resistor 29 is electrically connected to the output port of the driving and dead zone circuit 27. The gate of the second output NMOS transistor 31 is electrically connected to the fourth input port of the driving and dead zone circuit 27, the drain of the second output NMOS transistor 31 is electrically connected to the external isolated power supply, the source of the second output NMOS transistor 31 is electrically connected to one end of the second integrated driving resistor 30, and the other end of the second integrated driving resistor 30 is electrically connected to the output port of the driving and dead zone circuit 27. The first output NMOS transistor 28 , the second output NMOS transistor 31 , the first integrated driving resistor 29 and the second integrated driving resistor 30 are used to control the on or off of the external power supply, thereby driving the silicon carbide power module to be on or off.

[0112] In the embodiment of the present application, the demodulation circuit 23, the second filtering circuit 24, the undervoltage protection circuit 25, the second control circuit 26, and the driving and dead zone circuit 27 are combined and controlled to realize the function of driving the silicon carbide power module to work. At the same time, the undervoltage protection function is also realized to improve the stability of the output stage chip 5.

[0113] In the embodiments of the present application, Figure 1 As shown, the substrate 1 is an IMS (Insulated Metal Substrate) substrate, and the lead frame 2 is partially fixed on the two side edges of the IMS substrate; the input stage chip 3, the isolation transformer chip 4 and the output stage chip 5 are separately arranged on one end plate of the IMS substrate, and the silicon carbide power module is arranged on the other end plate of the IMS substrate.

[0114] Specifically, the SiC MOSFET chip (silicon carbide MOS tube 6), SiC SBD chip (silicon carbide special diode 7), and driver chipset (input chip 3, isolation transformer chip 4, and output chip 5) in the silicon carbide module are all assembled on the IMS substrate. The IMS substrate plays the role of heat dissipation, voltage isolation, logic circuit connection, and power circuit connection. The lead frame 2 is connected to the IMS substrate to transmit signals and power to the external circuit.

[0115] In the embodiments of the present application, Figure 2As shown, the substrate 1 is a DBC (Direct Bonded Copper) substrate, a portion of the lead frame 2 is fixed to one side edge of the DBC substrate, and another portion of the lead frame 2 is partially and separately arranged on one side of the DBC substrate and spaced from the DBC substrate. The silicon carbide power module is arranged on the DBC substrate. The input stage chip 3, the isolation transformer chip 4 and the output stage chip 5 are separately arranged on the lead frame 2 on one side of the DBC substrate.

[0116] Specifically, the SiC MOSFET chip (silicon carbide MOS tube 6) and SiC SBD chip (silicon carbide special diode 7) in the silicon carbide module are assembled on the DBC substrate. The driver chipset (input-level chip 3, isolation transformer chip 4 and output-level chip 5) are all assembled on the lead frame 2, and the DBC substrate plays the role of heat dissipation, voltage isolation, and power circuit connection. The lead frame 2 plays the role of voltage isolation and logic circuit connection. The lead frame 2 is connected to the DBC substrate and performs signal transmission and power transmission with the external circuit. The lead frame 2 on the driver chipset side is mainly for signal transmission, and the lead frame 2 on the DBC substrate side is mainly for power transmission.

[0117] In the embodiments of the present application, Figure 3 As shown, the substrate 1 is a Hiset (High Set) substrate, the power side of the lead frame 2 is arranged on the Hiset substrate, and the signal side of the lead frame 2 is partially and separately arranged on one side of the Hiset substrate and is spaced apart from the Hiset substrate. Among them, the silicon carbide power module is arranged on part of the lead frame 2 on the Hiset substrate. The input stage chip 3, the isolation transformer chip 4 and the output stage chip 5 are separately arranged on the lead frame 2 on one side of the Hiset substrate.

[0118] Specifically, the SiC MOSFET chip (silicon carbide MOS tube 6) and SiC SBD chip (silicon carbide special diode 7) in the silicon carbide module are assembled on the power side of the lead frame 2, and the back of the lead frame 2 on the power side is bonded to the Hiset substrate. The driver chipset (input-level chip 3, isolation transformer chip 4 and output-level chip 5) are all assembled on the signal side of the lead frame 2, and the signal side is not bonded to the Hiset substrate. The Hiset substrate serves for heat dissipation and voltage isolation, and the lead frame 2 on the power side serves as a power circuit connection. The lead frame 2 on the signal side serves for voltage isolation and logic circuit connection. The lead frame 2 performs signal transmission and power transmission with the external circuit. The lead frame 2 on the signal side is mainly for signal transmission, and the lead frame 2 on the power side is mainly for power transmission.

[0119] In the embodiments of the present application, Fig.11 As shown, a planar schematic diagram of a full-bridge (6-way) silicon carbide intelligent power module is provided.

[0120] Fig.11 Figure a shows a silicon carbide module with an IMS substrate structure. The IMS substrate is used as a circuit board, on which SiC MOSFET chips (silicon carbide MOS tubes 6), SiC SBD chips (silicon carbide special diodes 7), driver chipsets, signal lines, power lines, and passive components are laid, and the lead frame is only used as an external connection.

[0121] Fig.11 Figure b shows a silicon carbide module with a DBC substrate structure. The DBC substrate is used as a power circuit board, on which SiCMOSFET chips (silicon carbide MOS tubes 6) and SiC SBD chips (silicon carbide special diodes 7) are arranged; the lead frame 2 is used as a signal circuit and external connection, on which the drive chipset and signal lines are designed and arranged, wherein the base island bonded with the drive chipset can be flexibly designed according to the pins of the module, and a single 6-way input-level chip, or 3 dual-way chips, or 2 three-way chips, or 6 single-way chips can be used. The isolation transformer chip 4 is also the same, and a single 6-way input-level chip, or 3 dual-way chips, or 2 three-way chips, or 6 single-way chips can be used.

[0122] Fig.11 Figure c shows a silicon carbide module with a Hiset substrate structure. The Hiset substrate serves as a power circuit board, and the power side of the lead frame 2 is arranged on the Hiset substrate. SiC MOSFET chips and SiC SBD chips are arranged on the power side of the lead frame 2. The drive chipset and signal lines are arranged on the signal side of the lead frame 2. The lead frame 2 transmits signals and power to the external circuit. The lead frame 2 on the signal side is mainly used for signal transmission, and the lead frame 2 on the power side is mainly used for power transmission. The base island to which the drive chipset is bonded can be flexibly designed according to the pins of the module, and a single 6-way input-level chip, or 3 dual-way chips, or 2 three-way chips, or 6 single-way chips can be used. The isolation transformer chip 4 is also the same, and a single 6-way input-level chip, or 3 dual-way chips, or 2 three-way chips, or 6 single-way chips can be used.

[0123] Of course, single-channel, half-bridge (dual-channel), and H-bridge (4-channel) silicon carbide intelligent power modules are also designed similarly, thereby obtaining different silicon carbide intelligent power modules to meet different needs.

[0124] In the embodiment of the present application, the silicon carbide intelligent power module is mainly composed of a substrate (IMS substrate, DBC substrate, Hiset substrate), SiC MOSFET, SIC SBD, a driving chipset, a lead frame, bonding wires, plastic packaging materials, etc. Solder the lead frame to the substrate (IMS substrate, DBC substrate, Hiset substrate) by soft soldering; solder the power chips such as SiC MOSFET, SiCSBD to the IMS substrate, DBC substrate or lead frame by soft soldering; bond the driver chipset to the substrate (IMS substrate, DBC substrate, Hiset substrate) or the base island of the lead frame by epoxy bonding process; directly bond the bonding pad of the output chip and the MOSFET gate bonding pad by bonding wire; connect the driver chipset by bonding wire, and bond the other bonding pads of the driver chipset to the lead frame and substrate (IMS substrate, DBC substrate, Hiset substrate); wrap the substrate (IMS substrate, DBC substrate, Hiset substrate) or the substrate (IMS substrate, DBC substrate, Hiset substrate) part (exposing the heat dissipation surface), the lead frame part (leaving the pins), all the chips and bonding wires by epoxy resin injection molding process. Then, the corresponding silicon carbide intelligent power module is obtained to meet different needs. Improve the reliability and ease of use of silicon carbide intelligent power modules.

[0125] Obviously, the embodiments described above are only some embodiments of the present application, rather than all embodiments. The preferred embodiments of the present application are given in the accompanying drawings, but they do not limit the patent scope of the present application. The present application can be implemented in many different forms. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive. Although the present application is described in detail with reference to the aforementioned embodiments, for those skilled in the art, it is still possible to modify the technical solutions recorded in the aforementioned specific implementation methods, or to perform equivalent replacement of some of the technical features therein. Any equivalent structure made using the contents of the specification and drawings of this application, directly or indirectly used in other related technical fields, is similarly within the scope of patent protection of this application.

Claims

1. A silicon carbide intelligent power module, characterized in that: include: A substrate, a lead frame, a silicon carbide power module, and a driving chipset for driving the silicon carbide power module; The lead frame is partially disposed on the substrate, and the silicon carbide power module is disposed on the substrate; The driving chipset comprises an input-level chip, an isolation transformer chip and an output-level chip; the input-level chip, the isolation transformer chip and the output-level chip are separately arranged on the lead frame; The input-level chip is used to process and protect the received input signal; the input-level chip includes an input port protection circuit, a Schmitt circuit, a first filtering circuit, a dead time and interlocking circuit, a first control circuit, a modulation circuit, an overcurrent detection and protection circuit, and a fault feedback circuit; The isolation transformer chip is connected between the input-level chip and the output-level chip, and is used to perform high-voltage isolation on the processed signal and transmit the high-voltage isolated signal to the output-level chip; The output port of the output stage chip is electrically connected to the silicon carbide power module for driving the silicon carbide power module; the output stage chip comprises a demodulation circuit, a second filtering circuit, an undervoltage protection circuit, a second control circuit, and a driving and dead zone circuit; The substrate is a DBC substrate, a portion of the lead frame is fixed to one side edge of the DBC substrate, and another portion of the lead frame is partially and separately arranged on one side of the DBC substrate and is spaced apart from the DBC substrate; Wherein, the silicon carbide power module is arranged on the DBC substrate; The input-stage chip, the isolation transformer chip and the output-stage chip are separately arranged on a lead frame on one side of the DBC substrate.

2. The silicon carbide intelligent power module according to claim 1, characterized in that: The input port protection circuit is used to provide electrostatic protection for the received input signal; The Schmitt circuit is connected between the input port protection circuit and the first filter circuit and is used for signal shaping; The output port of the first filtering circuit is electrically connected to the input port of the dead time and interlock circuit for signal filtering; The output port of the dead time and interlock circuit is electrically connected to the input port of the first control circuit for dead time control; The output port of the first control circuit is electrically connected to the output port of the modulation circuit for signal processing control; The output port of the modulation circuit is electrically connected to the input port of the isolation transformer chip for signal modulation output; The input port of the overcurrent detection and protection circuit is electrically connected to the output port of the input port protection circuit, and the output port of the overcurrent detection and protection circuit is electrically connected to the input port of the first filter circuit for overcurrent detection and protection; The input port of the fault feedback circuit is electrically connected to the output port of the first filter circuit, and the output port of the fault feedback circuit is electrically connected to the first control circuit for fault detection.

3. The silicon carbide intelligent power module according to claim 1, characterized in that: The input port of the demodulation circuit is electrically connected to the output port of the isolation transformer chip for signal demodulation; The input port of the second filter circuit is electrically connected to the output port of the demodulation circuit, and the output port of the second filter circuit is electrically connected to the first input port of the second control circuit, for filtering the demodulated signal; The input port of the undervoltage protection circuit is electrically connected to an external isolated power supply, and the output port of the undervoltage protection circuit is electrically connected to the second input port of the second control circuit for circuit undervoltage protection; The output port of the second control circuit is electrically connected to the first input port of the drive and dead zone circuit for signal processing and control; The second input port of the driving and dead zone circuit is electrically connected to the external isolated power supply, and the output port of the driving and dead zone circuit is electrically connected to the input port of the silicon carbide power module for driving the silicon carbide power module.

4. The silicon carbide intelligent power module according to claim 3, characterized in that: The output stage chip further includes: a first output NMOS transistor, a second output NMOS transistor, a first integrated driving resistor and a second integrated driving resistor; The gate of the first output NMOS tube is electrically connected to the third input port of the drive and dead zone circuit, the drain of the first output NMOS tube is electrically connected to the external isolated power supply, the source of the first output NMOS tube is electrically connected to one end of the first integrated drive resistor, and the other end of the first integrated drive resistor is electrically connected to the output port of the drive and dead zone circuit; The gate of the second output NMOS tube is electrically connected to the fourth input port of the drive and dead zone circuit, the drain of the second output NMOS tube is electrically connected to the external isolation power supply, the source of the second output NMOS tube is electrically connected to one end of the second integrated drive resistor, and the other end of the second integrated drive resistor is electrically connected to the output port of the drive and dead zone circuit.

5. The silicon carbide intelligent power module according to claim 1, characterized in that: The silicon carbide power module includes a first silicon carbide MOS tube and a first silicon carbide FET diode anti-parallel to the silicon carbide MOS tube, the drain of the first silicon carbide MOS tube is electrically connected to the cathode of the first silicon carbide FET diode, the source of the first silicon carbide MOS tube is electrically connected to the anode of the first silicon carbide FET diode, and the gate of the first silicon carbide MOS tube is electrically connected to the output port of the output stage chip.

6. The silicon carbide intelligent power module according to claim 1, characterized in that: The silicon carbide power module is a half-bridge silicon carbide module, and the half-bridge silicon carbide module includes a second silicon carbide MOS tube, a third silicon carbide MOS tube, a second silicon carbide FET diode and a third silicon carbide FET diode; The drain of the second silicon carbide MOS tube is electrically connected to the cathode of the second silicon carbide FET diode, the source of the second silicon carbide MOS tube is electrically connected to the anode of the second silicon carbide FET diode, and the gate of the second silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The drain of the third silicon carbide MOS tube is electrically connected to the cathode of the third silicon carbide FET diode, the source of the third silicon carbide MOS tube is electrically connected to the anode of the third silicon carbide FET diode, and the gate of the third silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The source of the second silicon carbide MOS tube is electrically connected to the drain of the third silicon carbide MOS tube.

7. The silicon carbide intelligent power module according to claim 1, characterized in that: The silicon carbide power module is an H-bridge silicon carbide module, and the H-bridge silicon carbide module includes a fourth silicon carbide MOS tube, a fifth silicon carbide MOS tube, a sixth silicon carbide MOS tube, a seventh silicon carbide MOS tube, a fourth silicon carbide FET diode, a fifth silicon carbide FET diode, a sixth silicon carbide FET diode, and a seventh silicon carbide FET diode; the gate of each silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The drain of the fourth silicon carbide MOS tube is electrically connected to the cathode of the fourth silicon carbide FET diode, the source of the fourth silicon carbide MOS tube is electrically connected to the anode of the fourth silicon carbide FET diode, and the gate of the fourth silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The drain of the fifth silicon carbide MOS tube is electrically connected to the cathode of the fifth silicon carbide FET diode, the source of the fifth silicon carbide MOS tube is electrically connected to the anode of the fifth silicon carbide FET diode, and the gate of the fifth silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The drain of the sixth silicon carbide MOS tube is electrically connected to the cathode of the sixth silicon carbide FET diode, the source of the sixth silicon carbide MOS tube is electrically connected to the anode of the sixth silicon carbide FET diode, and the gate of the sixth silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The drain of the seventh silicon carbide MOS tube is electrically connected to the cathode of the seventh silicon carbide FET diode, the source of the seventh silicon carbide MOS tube is electrically connected to the anode of the seventh silicon carbide FET diode, and the gate of the seventh silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The source electrode of the fourth silicon carbide MOS tube is electrically connected to the drain electrode of the fifth silicon carbide MOS tube; The source electrode of the sixth silicon carbide MOS tube is electrically connected to the drain electrode of the seventh silicon carbide MOS tube; The source of the fourth silicon carbide MOS tube is electrically connected to the source of the sixth silicon carbide MOS tube.

8. The silicon carbide intelligent power module according to claim 1, characterized in that: The silicon carbide power module is a full-bridge silicon carbide module, and the full-bridge silicon carbide module includes an eighth silicon carbide MOS tube, a ninth silicon carbide MOS tube, a tenth silicon carbide MOS tube, an eleventh silicon carbide MOS tube, a twelfth silicon carbide MOS tube, a thirteenth silicon carbide MOS tube, an eighth silicon carbide FET diode, a ninth silicon carbide FET diode, a tenth silicon carbide FET diode, an eleventh silicon carbide FET diode, a twelfth silicon carbide FET diode, and a thirteenth silicon carbide FET diode; The drain of the eighth silicon carbide MOS tube is electrically connected to the cathode of the eighth silicon carbide FET diode, the source of the eighth silicon carbide MOS tube is electrically connected to the anode of the eighth silicon carbide FET diode, and the gate of the eighth silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The drain of the ninth silicon carbide MOS tube is electrically connected to the cathode of the ninth silicon carbide FET diode, the source of the ninth silicon carbide MOS tube is electrically connected to the anode of the ninth silicon carbide FET diode, and the gate of the ninth silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The drain of the tenth silicon carbide MOS tube is electrically connected to the cathode of the tenth silicon carbide FET diode, the source of the tenth silicon carbide MOS tube is electrically connected to the anode of the tenth silicon carbide FET diode, and the gate of the tenth silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The drain of the eleventh silicon carbide MOS tube is electrically connected to the cathode of the eleventh silicon carbide FET diode, the source of the eleventh silicon carbide MOS tube is electrically connected to the anode of the eleventh silicon carbide FET diode, and the gate of the eleventh silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The drain of the twelfth silicon carbide MOS tube is electrically connected to the cathode of the twelfth silicon carbide FET diode, the source of the twelfth silicon carbide MOS tube is electrically connected to the anode of the twelfth silicon carbide FET diode, and the gate of the twelfth silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The drain of the thirteenth silicon carbide MOS tube is electrically connected to the cathode of the thirteenth silicon carbide FET diode, the source of the thirteenth silicon carbide MOS tube is electrically connected to the anode of the thirteenth silicon carbide FET diode, and the gate of the thirteenth silicon carbide MOS tube is electrically connected to the output port of the output stage chip; The source electrode of the eighth silicon carbide MOS tube is electrically connected to the drain electrode of the ninth silicon carbide MOS tube; The source electrode of the tenth silicon carbide MOS tube is electrically connected to the drain electrode of the eleventh silicon carbide MOS tube; The source electrode of the twelfth silicon carbide MOS tube is electrically connected to the drain electrode of the thirteenth silicon carbide MOS tube; The source of the eighth silicon carbide MOS tube, the source of the tenth silicon carbide MOS tube and the source of the twelfth silicon carbide MOS tube are electrically connected.

Images