Bidirectional electrostatic discharge protection device

Abstract

The present invention discloses a bidirectional electrostatic discharge protection device, comprising a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip comprises a first diode and a first bipolar junction transistor, wherein the first diode and the first bipolar junction transistor are electrically connected to a first pin. The second transient voltage suppressor chip comprises a second diode and a second bipolar junction transistor, wherein the second diode and the second bipolar junction transistor are electrically connected to a second pin. The first conductive wire is electrically connected between the first diode and the second bipolar junction transistor, and the second conductive wire is electrically connected between the second diode and the first bipolar junction transistor.

Description

Technical Field

[0001] The present invention relates to an electrostatic discharge technology, and in particular to a bidirectional electrostatic discharge protection device. Background Art

[0002] Electrostatic discharge (ESD) damage has become a major reliability issue for CMOS integrated circuits manufactured using nanometer-scale complementary metal oxide semiconductor (CMOS) processes. ESD protection components are typically designed to release ESD energy, thereby preventing ESD damage to the integrated circuit chips.

[0003] The working principle of electrostatic discharge protection device is as follows Figure 1 As shown, on an integrated circuit chip, an electrostatic discharge (ESD) protection device 1 is connected in parallel with the circuit to be protected 2. When an ESD event occurs, the ESD protection device 1 is instantly triggered. Simultaneously, the ESD protection device 1 also provides a low-resistance path for the instantaneous ESD current to discharge, allowing the energy of the ESD transient current to be released through the ESD protection device 1. To achieve bidirectional electrostatic discharge, a bidirectional transient voltage suppressor includes two ESD discharge paths. One ESD discharge path is the discharge path, and the other is the reverse breakdown path. In the prior art, only one diode withstands the reverse voltage in the reverse breakdown path, making the forward voltage applied to the discharge path easily exceed the diode's breakdown voltage. Three ESD elements are connected in series in the discharge path. Therefore, the clamping voltage of these three ESD elements is relatively high. Furthermore, U.S. Patent No. 7,361,942 B1 implements a bidirectional transient voltage suppressor. However, the buried layer of this bidirectional transient voltage suppressor is used to connect multiple diodes, which increases process complexity.

[0004] Therefore, the present invention aims to solve the above-mentioned problems and proposes a bidirectional electrostatic discharge protection device to address the problems of the prior art. Summary of the Invention

[0005] The present invention provides a bidirectional electrostatic discharge protection device, which has a lower clamping voltage on a discharge path, reduces process complexity, and increases the electrostatic discharge level.

[0006] In one embodiment of the present invention, a bidirectional electrostatic discharge protection device is provided, which includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first PNP bipolar junction transistor. The anode of the first diode is electrically connected to a first pin, and the collector of the first PNP bipolar junction transistor is electrically connected to the first pin. The second transient voltage suppressor chip includes a second diode and a second PNP bipolar junction transistor. The anode of the second diode is electrically connected to a second pin, and the collector of the second PNP bipolar junction transistor is electrically connected to the second pin. The first conductive wire is electrically connected between the cathode of the first diode and the emitter of the second PNP bipolar junction transistor, and the second conductive wire is electrically connected between the cathode of the second diode and the emitter of the first PNP bipolar junction transistor.

[0007] In one embodiment of the present invention, the bases of the first PNP bipolar junction transistor and the second PNP bipolar junction transistor are floating.

[0008] In one embodiment of the present invention, the parasitic capacitance of the first PNP bipolar junction transistor or the second PNP bipolar junction transistor is greater than the parasitic capacitance of the first diode or the second diode.

[0009] In one embodiment of the present invention, the bidirectional ESD protection device further includes a first lead frame and a first conductive material. The first lead frame serves as a first pin, the first conductive material is disposed on the first lead frame and electrically connected to the first lead frame, and the first transient voltage suppressor chip is disposed on the first conductive material.

[0010] In one embodiment of the present invention, the first diode and the first PNP bipolar junction transistor are implemented using a first P-type semiconductor substrate, a first N-type semiconductor epitaxial layer, a first N-type heavily doped region, and a first P-type heavily doped region. The first P-type semiconductor substrate is disposed on a first conductive material and electrically connected to the first conductive material. The first N-type semiconductor epitaxial layer is disposed on the first P-type semiconductor substrate, and the first N-type heavily doped region and the first P-type heavily doped region are disposed in the first N-type semiconductor epitaxial layer. The first N-type heavily doped region is electrically connected to a first conductive line, and the first P-type heavily doped region is electrically connected to a second conductive line. The first transient voltage suppressor chip also includes a first isolation structure disposed in the first N-type semiconductor epitaxial layer and located between the first N-type heavily doped region and the first P-type heavily doped region. The first isolation structure contacts the first P-type semiconductor substrate and separates the first N-type heavily doped region from the first P-type heavily doped region. The height of the first isolation structure is equal to or greater than the thickness of the first N-type semiconductor epitaxial layer.

[0011] In one embodiment of the present invention, the first isolation structure surrounds the first N-type heavily doped region and the first P-type heavily doped region.

[0012] In one embodiment of the present invention, the bidirectional ESD protection device further includes a second lead frame and a second conductive material. The second lead frame serves as a second pin, the second conductive material is disposed on the second lead frame and electrically connected to the second lead frame, and the second transient voltage suppressor chip is disposed on the second conductive material.

[0013] In one embodiment of the present invention, the second diode and the second PNP bipolar junction transistor are implemented using a second P-type semiconductor substrate, a second N-type semiconductor epitaxial layer, a second N-type heavily doped region, and a second P-type heavily doped region. The second P-type semiconductor substrate is disposed on a second conductive material and electrically connected to the second conductive material. The second N-type semiconductor epitaxial layer is disposed on the second P-type semiconductor substrate, and the second N-type heavily doped region and the second P-type heavily doped region are disposed in the second N-type semiconductor epitaxial layer. The second N-type heavily doped region is electrically connected to the second conductive line, and the second P-type heavily doped region is electrically connected to the first conductive line. The second transient voltage suppressor chip also includes a second isolation structure disposed in the second N-type semiconductor epitaxial layer and located between the second N-type heavily doped region and the second P-type heavily doped region. The second isolation structure contacts the second P-type semiconductor substrate and separates the second N-type heavily doped region from the second P-type heavily doped region. The height of the second isolation structure is equal to or greater than the thickness of the second N-type semiconductor epitaxial layer.

[0014] In one embodiment of the present invention, the second isolation structure surrounds the second N-type heavily doped region and the second P-type heavily doped region.

[0015] In one embodiment of the present invention, the bidirectional electrostatic discharge protection device further includes a packaging colloid that covers the first transient voltage suppressor chip, the second transient voltage suppressor chip, the first conductive line, and the second conductive line.

[0016] In one embodiment of the present invention, a bidirectional electrostatic discharge protection device includes a first transient voltage suppressor chip, a second transient voltage suppressor chip, a first conductive wire, and a second conductive wire. The first transient voltage suppressor chip includes a first diode and a first NPN bipolar junction transistor. The cathode of the first diode is electrically connected to a first pin, and the collector of the first NPN bipolar junction transistor is electrically connected to the first pin. The second transient voltage suppressor chip includes a second diode and a second NPN bipolar junction transistor. The cathode of the second diode is electrically connected to a second pin, and the collector of the second NPN bipolar junction transistor is electrically connected to the second pin. The first conductive wire is electrically connected between the anode of the first diode and the emitter of the second NPN bipolar junction transistor, and the second conductive wire is electrically connected between the anode of the second diode and the emitter of the first NPN bipolar junction transistor.

[0017] In one embodiment of the present invention, the bases of the first NPN bipolar junction transistor and the second NPN bipolar junction transistor are floating.

[0018] In one embodiment of the present invention, the parasitic capacitance of the first NPN bipolar junction transistor or the second NPN bipolar junction transistor is greater than the parasitic capacitance of the first diode or the second diode.

[0019] In one embodiment of the present invention, the bidirectional ESD protection device further includes a first lead frame and a first conductive material. The first lead frame serves as a first pin, the first conductive material is disposed on the first lead frame and electrically connected to the first lead frame, and the first transient voltage suppressor chip is disposed on the first conductive material.

[0020] In one embodiment of the present invention, the first diode and the first NPN bipolar junction transistor are implemented using a first N-type semiconductor substrate, a first P-type semiconductor epitaxial layer, a first P-type heavily doped region, and a first N-type heavily doped region. The first N-type semiconductor substrate is disposed on and electrically connected to a first conductive material. The first P-type semiconductor epitaxial layer is disposed on the first N-type semiconductor substrate, and the first P-type heavily doped region and the first N-type heavily doped region are disposed in the first P-type semiconductor epitaxial layer. The first P-type heavily doped region is electrically connected to a first conductive line, and the first N-type heavily doped region is electrically connected to a second conductive line. The first transient voltage suppressor chip also includes a first isolation structure disposed in the first P-type semiconductor epitaxial layer and located between the first P-type heavily doped region and the first N-type heavily doped region. The first isolation structure contacts the first N-type semiconductor substrate and separates the first P-type heavily doped region from the first N-type heavily doped region. The height of the first isolation structure is equal to or greater than the thickness of the first P-type semiconductor epitaxial layer.

[0021] In one embodiment of the present invention, the first isolation structure surrounds the first P-type heavily doped region and the first N-type heavily doped region.

[0022] In one embodiment of the present invention, the bidirectional ESD protection device further includes a second lead frame and a second conductive material. The second lead frame serves as a second pin, the second conductive material is disposed on the second lead frame and electrically connected to the second lead frame, and the second transient voltage suppressor chip is disposed on the second conductive material.

[0023] In one embodiment of the present invention, the second diode and the second NPN bipolar junction transistor are implemented using a second N-type semiconductor substrate, a second P-type semiconductor epitaxial layer, a second P-type heavily doped region, and a second N-type heavily doped region. The second N-type semiconductor substrate is disposed on a second conductive material and electrically connected to the second conductive material. The second P-type semiconductor epitaxial layer is disposed on the second N-type semiconductor substrate, and the second P-type heavily doped region and the second N-type heavily doped region are disposed in the second P-type semiconductor epitaxial layer. The second P-type heavily doped region is electrically connected to the second conductive line, and the second N-type heavily doped region is electrically connected to the first conductive line. The second transient voltage suppressor chip also includes a second isolation structure disposed in the second P-type semiconductor epitaxial layer and located between the second P-type heavily doped region and the second N-type heavily doped region. The second isolation structure contacts the second N-type semiconductor substrate and separates the second P-type heavily doped region from the second N-type heavily doped region. The height of the second isolation structure is equal to or greater than the thickness of the second P-type semiconductor epitaxial layer.

[0024] In one embodiment of the present invention, the second isolation structure surrounds the second P-type heavily doped region and the second N-type heavily doped region.

[0025] In one embodiment of the present invention, the bidirectional electrostatic discharge protection device further includes a packaging colloid that covers the first transient voltage suppressor chip, the second transient voltage suppressor chip, the first conductive line, and the second conductive line.

[0026] Based on the above, the bidirectional ESD protection device utilizes two ESD components in the reverse breakdown path to withstand the reverse voltage, making it easier for the ESD component breakdown voltage to exceed the total conduction voltage applied to the discharge path. Furthermore, the smaller number of ESD components connected in series results in a lower clamping voltage in the discharge path. Conductive lines replace high-concentration and low-impedance paths to reduce process complexity and form inductors to increase ESD ratings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 The present invention is a schematic diagram showing a conventional electrostatic discharge protection device on an integrated circuit chip connected to a circuit to be protected.

[0028] Figure 2 FIG. 1 is a schematic diagram of a first embodiment of a bidirectional electrostatic discharge protection device according to the present invention.

[0029] Figure 3 FIG. 4 is a schematic diagram of a second embodiment of a bidirectional electrostatic discharge protection device according to the present invention.

[0030] Figure 4 FIG. 4 is a cross-sectional view of the structure of a third embodiment of a bidirectional electrostatic discharge protection device according to the present invention.

[0031] Figure 5FIG. 4 is a schematic diagram of a bidirectional electrostatic discharge protection device according to a fourth embodiment of the present invention.

[0032] Figure 6 FIG. 4 is a schematic diagram of a fifth embodiment of a bidirectional electrostatic discharge protection device according to the present invention.

[0033] Figure 7 FIG. 4 is a cross-sectional view of the structure of a sixth embodiment of a bidirectional electrostatic discharge protection device according to the present invention.

[0034] Explanation of the accompanying figures: 1-electrostatic discharge protection device; 2-circuit to be protected; 3, 3'-bidirectional electrostatic discharge protection device; 30, 30'-first transient voltage suppressor chip; 300, 300'-first diode; 301-first PNP bipolar junction transistor; 301'-first NPN bipolar junction transistor; 302-first P-type semiconductor substrate; 302'-first N-type semiconductor substrate; 303-first N-type semiconductor epitaxial layer; 303'-first P-type semiconductor epitaxial layer; 304-first N-type heavily doped region; 304'-first P-type heavily doped region; 305-first P-type heavily doped region; 305'-first N-type heavily doped region; 306, 306'-first isolation structure; 31, 31'-second transient voltage suppressor chip; 310, 310'-second diode; 31 1-second PNP bipolar junction transistor; 311'-second NPN bipolar junction transistor; 312-second P-type semiconductor substrate; 312'-second N-type semiconductor substrate; 313-second N-type semiconductor epitaxial layer; 313'-second P-type semiconductor epitaxial layer; 314-second N-type heavily doped region; 314'-second P-type heavily doped region; 315-second P-type heavily doped region; 315'-second N-type heavily doped region; 316, 316'-second isolation structure; 32, 32'-first conductive line; 33, 33'-second conductive line; 34, 34'-first pin; 35, 35'-second pin; 36, 36'-first lead frame; 37, 37'-first conductive material; 38, 38'-second lead frame; 39, 39'-second conductive material; 41, 41'-packaging glue. DETAILED DESCRIPTION

[0035] The embodiments of the present invention are further explained below with reference to the accompanying drawings. Whenever possible, identical reference numerals will be used in the drawings and the specification to represent identical or similar components. In the drawings, shapes and thicknesses may be exaggerated for simplicity and convenience. It should be understood that components not specifically shown in the drawings or described in the specification are generally known to those skilled in the art. Those skilled in the art may make various changes and modifications based on the disclosure of the present invention.

[0036] Unless otherwise specified, conditional sentences or words such as "can," "could," "might," or "may" are generally intended to convey that an embodiment of the present invention has features, elements, or steps, but may also be interpreted as features, elements, or steps that may not be required. In other embodiments, these features, elements, or steps may not be required.

[0037] The following descriptions of "one embodiment" or "an embodiment" refer to a specific component, structure, or feature associated with at least one embodiment. Therefore, multiple references to "one embodiment" or "an embodiment" in various places below do not necessarily refer to the same embodiment. Furthermore, specific components, structures, and features in one or more embodiments may be combined in any suitable manner.

[0038] Certain words are used in the specification and claims to refer to specific components. However, a person with ordinary knowledge in the technical field should understand that the same component may be referred to by different nouns. The specification and claims do not use the difference in name as a way to distinguish components, but use the difference in function of the components as the basis for distinction. The "including" mentioned in the specification and claims is an open term, so it should be interpreted as "including but not limited to". In addition, "coupling" here includes any direct and indirect connection means. Therefore, if the text describes a first element coupled to a second element, it means that the first element can be directly connected to the second element through electrical connection or wireless transmission, optical transmission and other signal connection methods, or indirectly electrically or signal connected to the second element through other elements or connection means.

[0039] The present invention is particularly described with reference to the following examples, which are intended to be illustrative only. As various modifications and variations will readily occur to those skilled in the art without departing from the spirit and scope of the present disclosure, the scope of protection of the present disclosure is determined by the claims. Throughout the specification and claims, unless the context clearly dictates otherwise, the meanings of "a," "an," and "the" include references to "one or at least one" of the elements or components. Furthermore, as used herein, the singular article includes references to plural elements or components unless the context clearly dictates otherwise. Furthermore, as used in this description and throughout the following claims, the meaning of "in which" includes "in which" and "on which," unless the context clearly dictates otherwise. Terms used throughout the specification and claims generally have their ordinary meaning as used in the art, in the context of this invention, and in the particular context, unless otherwise noted. Certain terms used to describe the present invention will be discussed below or elsewhere in this specification to provide practitioners with additional guidance regarding the description of the present invention. The use of examples anywhere throughout the specification, including examples of any terms discussed herein, is intended to be illustrative only and does not limit the scope or meaning of the invention or any exemplified terms. Likewise, the present invention is not limited to the various embodiments set forth in this specification.

[0040] The following description provides a bidirectional ESD protection device that utilizes two ESD components in the reverse breakdown path to withstand reverse voltage, allowing the ESD component breakdown voltage to easily exceed the total on-state voltage applied to the discharge path. Furthermore, fewer ESD components connected in series result in a lower clamping voltage in the discharge path. Conductive lines replace high-concentration and low-impedance paths to reduce process complexity and form inductors to increase ESD ratings.

[0041] Figure 2 FIG1 is a schematic diagram of a first embodiment of a bidirectional electrostatic discharge protection device according to the present invention. Figure 2The bidirectional ESD protection device 3 includes a first transient voltage suppressor chip 30, a second transient voltage suppressor chip 31, a first conductive line 32, and a second conductive line 33. The first transient voltage suppressor chip 30 includes a first diode 300 and a first PNP bipolar junction transistor 301. The second transient voltage suppressor chip 31 includes a second diode 310 and a second PNP bipolar junction transistor 311. The anode of the first diode 300 is electrically connected to a first pin 34. The collector of the first PNP bipolar junction transistor 301 is electrically connected to the first pin 34. The base of the first PNP bipolar junction transistor 301 is floating. The anode of the second diode 310 is electrically connected to a second pin 35. The collector of the second PNP bipolar junction transistor 311 is electrically connected to the second pin 35. The base of the second PNP bipolar junction transistor 311 is floating. The first conductive line 32 is electrically connected between the cathode of the first diode 300 and the emitter of the second PNP BJT 311. The second conductive line 33 is electrically connected between the cathode of the second diode 310 and the emitter of the first PNP BJT 301. The bidirectional ESD protection device 3 has two ESD paths, including a discharge path and a reverse breakdown path. One ESD path includes the first diode 300, the first conductive line 32, and the second PNP BJT 311. The other ESD path includes the first PNP BJT 301, the second conductive line 33, and the second diode 310. To reduce the overall parasitic capacitance of the bidirectional ESD protection device 3, the parasitic capacitance of the first PNP BJT 301 or the second PNP BJT 311 is designed to be greater than the parasitic capacitance of the first diode 300 or the second diode 310.

[0042] The following describes the operation of the bidirectional ESD protection device 3 according to the first embodiment. When the first pin 34 and the second pin 35 receive a positive ESD voltage and a ground voltage, respectively, the ESD current flows sequentially through the first diode 300, the first conductive line 32, and the second PNP BJT 311. In this example, the discharge path includes the first diode 300, the first conductive line 32, and the second PNP BJT 311, while the reverse breakdown path includes the first PNP BJT 301, the second conductive line 33, and the second diode 310. Furthermore, the forward voltage applied to the discharge path is lower than the total breakdown voltage applied to the reverse breakdown path. In other words, the total forward voltage of the first diode 300 and the second PNP BJT 311 is lower than the total breakdown voltage of the first PNP BJT 301 and the second diode 310. Because the reverse breakdown path uses two ESD elements, the total breakdown voltage applied to the reverse breakdown path is increased. Because the discharge path uses only two ESD elements, the clamping voltage of the discharge path is lower. In addition, the first conductive line 32 and the second conductive line 33 replace the high-concentration and low-resistance paths in the prior art to reduce process complexity.

[0043] When the first pin 34 and the second pin 35 receive a ground voltage and a positive ESD voltage, respectively, the ESD current flows sequentially through the second diode 310, the second conductive line 33, and the first PNP BJT 301. In this example, the discharge path includes the first PNP BJT 301, the second conductive line 33, and the second diode 310, while the reverse breakdown path includes the first diode 300, the first conductive line 32, and the second PNP BJT 311. Furthermore, the forward voltage applied to the discharge path is lower than the total breakdown voltage applied to the reverse breakdown path. In other words, the total forward voltage of the first PNP BJT 301 and the second diode 310 is lower than the total breakdown voltage of the first diode 300 and the second PNP BJT 311. Because the reverse breakdown path uses two ESD elements, the total breakdown voltage applied to the reverse breakdown path is increased. Because the discharge path uses only two ESD elements, the clamping voltage of the discharge path is lower.

[0044] Figure 3 FIG2 is a schematic diagram of a second embodiment of a bidirectional electrostatic discharge protection device according to the present invention. Figure 3 When a high-frequency electrostatic discharge voltage is applied to the first pin 34 and the second pin 35 , the first conductive line 32 and the second conductive line 33 generate an inductive effect to have a high impedance and increase the rise time of the electrostatic discharge voltage, thereby improving the electrostatic discharge level of the bidirectional electrostatic discharge protection device 3 and preventing the bidirectional electrostatic discharge protection device 3 from being damaged.

[0045] Figure 4 This is a cross-sectional view of the structure of the third embodiment of the bidirectional electrostatic discharge protection device of the present invention. Figure 4 and Figure 3 The bidirectional electrostatic discharge protection device 3 of the third embodiment further includes a first lead frame 36, a first conductive material 37, a second lead frame 38, and a second conductive material 39. For example, the first conductive material 37 and the second conductive material 39 may be conductive glue, eutectic material, or other suitable conductive materials. The first lead frame 36 serves as the first pin 34, and the second lead frame 38 serves as the second pin 35. The first conductive material 37 is disposed on the first lead frame 36 and is electrically connected to the first lead frame 36. The first transient voltage suppressor chip 30 is disposed on the first conductive material 37. The second conductive material 39 is disposed on the second lead frame 38 and is electrically connected to the second lead frame 38. The second transient voltage suppressor chip 31 is disposed on the second conductive material 39.

[0046] The first diode 300 and the first PNP bipolar junction transistor 301 can be implemented with a first P-type semiconductor substrate 302, a first N-type semiconductor epitaxial layer 303, a first N-type heavily doped region 304, and a first P-type heavily doped region 305. The first diode 300 is implemented with the first P-type semiconductor substrate 302, the first N-type semiconductor epitaxial layer 303, and the first N-type heavily doped region 304. The first PNP bipolar junction transistor 301 is implemented with the first P-type semiconductor substrate 302, the first N-type semiconductor epitaxial layer 303, and the first P-type heavily doped region 305. The first P-type semiconductor substrate 302 is disposed on and electrically connected to the first conductive material 37. The first N-type semiconductor epitaxial layer 303 is disposed on the first P-type semiconductor substrate 302, and the first N-type heavily doped region 304 and the first P-type heavily doped region 305 are disposed in the first N-type semiconductor epitaxial layer 303. The first heavily N-type doped region 304 is electrically connected to the first conductive line 32, and the first heavily P-type doped region 305 is electrically connected to the second conductive line 33. Furthermore, the first transient voltage suppressor chip 30 may further include a first isolation structure 306 formed of an insulating material. The first isolation structure 306 is disposed in the first N-type semiconductor epitaxial layer 303 and is located between the first heavily N-type doped region 304 and the first heavily P-type doped region 305. The first isolation structure 306 contacts the first P-type semiconductor substrate 302 and separates the first heavily N-type doped region 304 from the first heavily P-type doped region 305. The height of the first isolation structure 306 is equal to or greater than the thickness of the first N-type semiconductor epitaxial layer 304. To reduce the parasitic capacitance of the first diode 300, the first isolation structure 306 may surround the first heavily N-type doped region 304 and the first heavily P-type doped region 305. Furthermore, the first diode 300 and the first PNP bipolar junction transistor 301 are not interconnected via metal, polysilicon, or a heavily doped semiconductor layer.

[0047] The second diode 310 and the second PNP bipolar junction transistor 311 can be implemented with a second P-type semiconductor substrate 312, a second N-type semiconductor epitaxial layer 313, a second N-type heavily doped region 314, and a second P-type heavily doped region 315. The second diode 310 is implemented with the second P-type semiconductor substrate 312, the second N-type semiconductor epitaxial layer 313, and the second N-type heavily doped region 314, while the second PNP bipolar junction transistor 311 is implemented with the second P-type semiconductor substrate 312, the second N-type semiconductor epitaxial layer 313, and the second P-type heavily doped region 315. The second P-type semiconductor substrate 312 is disposed on the second conductive material 39 and is electrically connected to the second conductive material 39. A second N-type semiconductor epitaxial layer 313 is disposed on a second P-type semiconductor substrate 312. A second N-type heavily doped region 314 and a second P-type heavily doped region 315 are disposed in the second N-type semiconductor epitaxial layer 313. The second N-type heavily doped region 314 is electrically connected to the second conductive line 33, and the second P-type heavily doped region 315 is electrically connected to the first conductive line 32. The second transient voltage suppressor chip 31 may also include a second isolation structure 316 formed of an insulating material. The second isolation structure 316 is disposed in the second N-type semiconductor epitaxial layer 313 and is located between the second N-type heavily doped region 314 and the second P-type heavily doped region 315. The second isolation structure 316 contacts the second P-type semiconductor substrate 312 and separates the second N-type heavily doped region 314 from the second P-type heavily doped region 315. The height of the second isolation structure 316 is equal to or greater than the thickness of the second N-type semiconductor epitaxial layer 313. To reduce the parasitic capacitance of the second diode 310, the second isolation structure 316 surrounds the second N-type heavily doped region 314 and the second P-type heavily doped region 315. In addition, the second diode 310 and the second PNP bipolar junction transistor 311 are not connected to each other through metal, polysilicon, or heavily doped semiconductor layers.

[0048] In some embodiments of the present invention, the bidirectional ESD protection device 3 may further include an encapsulant 41 . The encapsulant 41 is formed using a mold to cover the first transient voltage suppressor chip 30 , the second transient voltage suppressor chip 31 , the first conductive line 32 , and the second conductive line 33 .

[0049] Figure 5 FIG4 is a schematic diagram of a fourth embodiment of a bidirectional electrostatic discharge protection device according to the present invention. Figure 5The bidirectional ESD protection device 3' includes a first transient voltage suppressor chip 30', a second transient voltage suppressor chip 31', a first conductive line 32', and a second conductive line 33'. The first transient voltage suppressor chip 30' includes a first diode 300' and a first NPN bipolar junction transistor 301'. The second transient voltage suppressor chip 31' includes a second diode 310' and a second NPN bipolar junction transistor 311'. The cathode of the first diode 300' is electrically connected to a first pin 34'. The collector of the first NPN bipolar junction transistor 301' is electrically connected to the first pin 34'. The base of the first NPN bipolar junction transistor 301' is floating. The cathode of the second diode 310' is electrically connected to a second pin 35'. The collector of the second NPN bipolar junction transistor 311' is electrically connected to the second pin 35'. The base of the second NPN bipolar junction transistor 311' is floating. The first conductive line 32' is electrically connected between the anode of the first diode 300' and the emitter of the second NPN bipolar junction transistor 311'. The second conductive line 33' is electrically connected between the anode of the second diode 310' and the emitter of the first NPN bipolar junction transistor 301'. The bidirectional ESD protection device 3' has two ESD paths: a discharge path and a reverse breakdown path. One ESD path includes the first diode 300', the first conductive line 32', and the second NPN bipolar junction transistor 311'. The other ESD path includes the first NPN bipolar junction transistor 301', the second conductive line 33', and the second diode 310'. To reduce the overall parasitic capacitance of the bidirectional ESD protection device 3', the parasitic capacitance of the first NPN bipolar junction transistor 301' or the second NPN bipolar junction transistor 311' is designed to be greater than the parasitic capacitance of the first diode 300' or the second diode 310'.

[0050] The following describes the operation of the bidirectional ESD protection device 3' according to the fourth embodiment. When the first pin 34' and the second pin 35' receive a ground voltage and a positive ESD voltage, respectively, the ESD current flows sequentially through the second NPN BJT 311', the first conductive line 32', and the first diode 300'. In this example, the discharge path includes the second NPN BJT 311', the first conductive line 32', and the first diode 300', while the reverse breakdown path includes the first NPN BJT 301', the second conductive line 33', and the second diode 310'. Furthermore, the forward voltage applied to the discharge path is lower than the total breakdown voltage applied to the reverse breakdown path. In other words, the total forward voltage of the first diode 300' and the second NPN BJT 311' is lower than the total breakdown voltage of the first NPN BJT 301' and the second diode 310'. Because the reverse breakdown path uses two ESD components, the total breakdown voltage applied to the reverse breakdown path is increased. Because the discharge path uses only two ESD elements, the clamping voltage of the discharge path is lower. In addition, the first conductive line 32' and the second conductive line 33' replace the high-concentration and low-resistance paths of the prior art to reduce process complexity.

[0051] When the first pin 34' and the second pin 35' receive a positive ESD voltage and a ground voltage, respectively, an ESD current flows sequentially through the first NPN BJT 301', the second conductive line 33', and the second diode 310'. In this example, the discharge path includes the first NPN BJT 301', the second conductive line 33', and the second diode 310', while the reverse breakdown path includes the first diode 300', the first conductive line 32', and the second NPN BJT 311'. Furthermore, the forward voltage applied to the discharge path is lower than the total breakdown voltage applied to the reverse breakdown path. In other words, the total forward voltage of the first NPN BJT 301' and the second diode 310' is lower than the total breakdown voltage of the first diode 300' and the second NPN BJT 311'. Because the reverse breakdown path uses two ESD elements, the total breakdown voltage applied to the reverse breakdown path is increased. Because the discharge path uses only two ESD elements, the clamping voltage of the discharge path is lower.

[0052] Figure 6 FIG is a schematic diagram of a fifth embodiment of a bidirectional electrostatic discharge protection device according to the present invention. Figure 6When a high-frequency electrostatic discharge voltage is applied to the first pin 34' and the second pin 35', the first conductive line 32' and the second conductive line 33' generate an inductive effect to have a high impedance and increase the rise time of the electrostatic discharge voltage, thereby improving the electrostatic discharge level of the bidirectional electrostatic discharge protection device 3' and preventing the bidirectional electrostatic discharge protection device 3' from being damaged.

[0053] Figure 7 This is a cross-sectional view of the structure of the sixth embodiment of the bidirectional electrostatic discharge protection device of the present invention. Figure 7 and Figure 6 The bidirectional electrostatic discharge protection device 3' of the third embodiment also includes a first lead frame 36', a first conductive material 37', a second lead frame 38' and a second conductive material 39'. For example, the first conductive material 37' and the second conductive material 39' can be conductive glue, eutectic material or other suitable conductive materials. The first lead frame 36' serves as the first pin 34', and the second lead frame 38' serves as the second pin 35'. The first conductive material 37' is arranged on the first lead frame 36' and is electrically connected to the first lead frame 36'. The first transient voltage suppressor chip 30' is arranged on the first conductive material 37'. The second conductive material 39' is arranged on the second lead frame 38' and is electrically connected to the second lead frame 38'. The second transient voltage suppressor chip 31' is arranged on the second conductive material 39'.

[0054] The first diode 300' and the first NPN bipolar junction transistor 301' can be implemented with a first N-type semiconductor substrate 302', a first P-type semiconductor epitaxial layer 303', a first P-type heavily doped region 304', and a first N-type heavily doped region 305'. The first diode 300' is implemented with the first N-type semiconductor substrate 302', the first P-type semiconductor epitaxial layer 303', and the first P-type heavily doped region 304'. The first NPN bipolar junction transistor 301' is implemented with the first N-type semiconductor substrate 302', the first P-type semiconductor epitaxial layer 303', and the first N-type heavily doped region 305'. The first N-type semiconductor substrate 302' is disposed on the first conductive material 37' and is electrically connected to the first conductive material 37'. A first P-type semiconductor epitaxial layer 303' is disposed on a first N-type semiconductor substrate 302'. A first P-type heavily doped region 304' and a first N-type heavily doped region 305' are disposed in the first P-type semiconductor epitaxial layer 303'. The first P-type heavily doped region 304' is electrically connected to the first conductive line 32', and the first N-type heavily doped region 305' is electrically connected to the second conductive line 33'. Furthermore, the first transient voltage suppressor chip 30' may further include a first isolation structure 306' formed of an insulating material. The first isolation structure 306' is disposed in the first P-type semiconductor epitaxial layer 303' and is located between the first P-type heavily doped region 304' and the first N-type heavily doped region 305'. The first isolation structure 306' contacts the first N-type semiconductor substrate 302' and separates the first P-type heavily doped region 304' from the first N-type heavily doped region 305'. The height of the first isolation structure 306' is equal to or greater than the thickness of the first P-type semiconductor epitaxial layer 304'. To reduce the parasitic capacitance of the first diode 300', a first isolation structure 306' may surround the first P-type heavily doped region 304' and the first N-type heavily doped region 305'. Furthermore, the first diode 300' and the first NPN bipolar junction transistor 301' are not interconnected via metal, polysilicon, or heavily doped semiconductor layers.

[0055] The second diode 310' and the second NPN bipolar junction transistor 311' can be implemented with a second N-type semiconductor substrate 312', a second P-type semiconductor epitaxial layer 313', a second P-type heavily doped region 314', and a second N-type heavily doped region 315'. The second diode 310' is implemented with the second N-type semiconductor substrate 312', the second P-type semiconductor epitaxial layer 313', and the second P-type heavily doped region 314', while the second NPN bipolar junction transistor 311' is implemented with the second N-type semiconductor substrate 312', the second P-type semiconductor epitaxial layer 313', and the second N-type heavily doped region 315'. The second N-type semiconductor substrate 312' is disposed on the second conductive material 39' and is electrically connected to the second conductive material 39'. A second P-type semiconductor epitaxial layer 313' is disposed on a second N-type semiconductor substrate 312'. A second P-type heavily doped region 314' and a second N-type heavily doped region 315' are disposed in the second P-type semiconductor epitaxial layer 313'. The second P-type heavily doped region 314' is electrically connected to the second conductive line 33', and the second N-type heavily doped region 315' is electrically connected to the first conductive line 32'. The second transient voltage suppressor chip 31' may also include a second isolation structure 316' formed of an insulating material. The second isolation structure 316' is disposed in the second P-type semiconductor epitaxial layer 313' and is located between the second P-type heavily doped region 314' and the second N-type heavily doped region 315'. The second isolation structure 316' contacts the second N-type semiconductor substrate 312' and separates the second P-type heavily doped region 314' from the second N-type heavily doped region 315'. The height of the second isolation structure 316' is equal to or greater than the thickness of the second P-type semiconductor epitaxial layer 313'. To reduce the parasitic capacitance of the second diode 310', a second isolation structure 316' surrounds the second heavily P-type doped region 314' and the second heavily N-type doped region 315'. Furthermore, the second diode 310' and the second NPN bipolar junction transistor 311' are not interconnected via metal, polysilicon, or heavily doped semiconductor layers.

[0056] In some embodiments of the present invention, the bidirectional ESD protection device 3' may further include an encapsulant 41'. The encapsulant 41' is formed using a mold to encapsulate the first transient voltage suppressor chip 30', the second transient voltage suppressor chip 31', the first conductive line 32', and the second conductive line 33'.

[0057] According to the above-described embodiment, the bidirectional ESD protection device utilizes two ESD components in the reverse breakdown path to withstand reverse voltage, making it easier for the ESD component breakdown voltage to exceed the total on-state voltage applied to the discharge path. Furthermore, the smaller number of ESD components connected in series results in a lower clamping voltage in the discharge path. Conductive lines replace high-concentration and low-impedance paths to reduce process complexity and form inductors to increase ESD ratings.

[0058] The above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent changes and modifications based on the shape, structure, characteristics and spirit described in the claims of the present invention should be included in the scope of the present invention.

Claims

1. A bidirectional electrostatic discharge protection device, characterized in that: include: A first transient voltage suppressor chip, comprising: a first diode, an anode of which is electrically connected to a first pin; and a first PNP bipolar junction transistor, the collector of which is electrically connected to the first pin; A second transient voltage suppressor chip, comprising: a second diode, an anode of which is electrically connected to a second pin; and a second PNP bipolar junction transistor, the collector of which is electrically connected to the second pin; a first conductive line electrically connected between the cathode of the first diode and the emitter of the second PNP bipolar junction transistor; and A second conductive line is electrically connected between the cathode of the second diode and the emitter of the first PNP bipolar junction transistor.

2. The bidirectional electrostatic discharge protection device according to claim 1, wherein: Bases of the first PNP bipolar junction transistor and the second PNP bipolar junction transistor are floating.

3. The bidirectional electrostatic discharge protection device according to claim 1, wherein: The parasitic capacitance of the first PNP bipolar junction transistor or the second PNP bipolar junction transistor is greater than the parasitic capacitance of the first diode or the second diode.

4. The bidirectional electrostatic discharge protection device according to claim 1, wherein: Also includes: a first lead frame, serving as the first pin; as well as A first conductive material is disposed on the first lead frame and electrically connected to the first lead frame, wherein the first transient voltage suppressor chip is disposed on the first conductive material.

5. The bidirectional electrostatic discharge protection device according to claim 4, wherein: The first diode and the first PNP bipolar junction transistor are implemented using a first P-type semiconductor substrate, a first N-type semiconductor epitaxial layer, a first N-type heavily doped region, and a first P-type heavily doped region. The first P-type semiconductor substrate is disposed on the first conductive material and electrically connected to the first conductive material. The first N-type semiconductor epitaxial layer is disposed on the first P-type semiconductor substrate. The first N-type heavily doped region and the first P-type heavily doped region are disposed in the first N-type semiconductor epitaxial layer. The first N-type heavily doped region is electrically connected to the first conductive line, and the first P-type heavily doped region is electrically connected to the second conductive line. The first transient voltage suppressor chip further includes a first isolation structure disposed in the first N-type semiconductor epitaxial layer and located between the first N-type heavily doped region and the first P-type heavily doped region. The first isolation structure contacts the first P-type semiconductor substrate and separates the first N-type heavily doped region from the first P-type heavily doped region. The height of the first isolation structure is equal to or greater than the thickness of the first N-type semiconductor epitaxial layer.

6. The bidirectional electrostatic discharge protection device according to claim 5, wherein: The first isolation structure surrounds the first N-type heavily doped region and the first P-type heavily doped region.

7. The bidirectional electrostatic discharge protection device according to claim 5, wherein: Also includes: a second lead frame, serving as the second pin; as well as A second conductive material is disposed on the second lead frame and electrically connected to the second lead frame, wherein the second transient voltage suppressor chip is disposed on the second conductive material.

8. The bidirectional electrostatic discharge protection device according to claim 7, wherein: The second diode and the second PNP bipolar junction transistor are implemented using a second P-type semiconductor substrate, a second N-type semiconductor epitaxial layer, a second N-type heavily doped region, and a second P-type heavily doped region. The second P-type semiconductor substrate is disposed on the second conductive material and electrically connected to the second conductive material. The second N-type semiconductor epitaxial layer is disposed on the second P-type semiconductor substrate. The second N-type heavily doped region and the second P-type heavily doped region are disposed in the second N-type semiconductor epitaxial layer. The second N-type heavily doped region is electrically connected to the second conductive line, and the second P-type heavily doped region is electrically connected to the first conductive line. The second transient voltage suppressor chip further includes a second isolation structure disposed in the second N-type semiconductor epitaxial layer and located between the second N-type heavily doped region and the second P-type heavily doped region. The second isolation structure contacts the second P-type semiconductor substrate and separates the second N-type heavily doped region from the second P-type heavily doped region. The height of the second isolation structure is equal to or greater than the thickness of the second N-type semiconductor epitaxial layer.

9. The bidirectional electrostatic discharge protection device according to claim 8, wherein: The second isolation structure surrounds the second N-type heavily doped region and the second P-type heavily doped region.

10. The bidirectional electrostatic discharge protection device according to claim 1, wherein: The device also includes a packaging colloid, which covers the first transient voltage suppressor chip, the second transient voltage suppressor chip, the first conductive line and the second conductive line.

11. A bidirectional electrostatic discharge protection device, characterized in that: include: A first transient voltage suppressor chip, comprising: a first diode, a cathode of which is electrically connected to a first pin; and a first NPN bipolar junction transistor, whose collector is electrically connected to the first pin; A second transient voltage suppressor chip, comprising: a second diode, a cathode of which is electrically connected to a second pin; and a second NPN bipolar junction transistor, the collector of which is electrically connected to the second pin; a first conductive line electrically connected between the anode of the first diode and the emitter of the second NPN bipolar junction transistor; and A second conductive line is electrically connected between the anode of the second diode and the emitter of the first NPN bipolar junction transistor.

12. The bidirectional electrostatic discharge protection device according to claim 11, wherein: Bases of the first NPN bipolar junction transistor and the second NPN bipolar junction transistor are floating.

13. The bidirectional electrostatic discharge protection device according to claim 11, wherein: The parasitic capacitance of the first NPN bipolar junction transistor or the second NPN bipolar junction transistor is greater than the parasitic capacitance of the first diode or the second diode.

14. The bidirectional electrostatic discharge protection device according to claim 11, wherein: Also includes: a first lead frame, serving as the first pin; as well as A first conductive material is disposed on the first lead frame and electrically connected to the first lead frame, wherein the first transient voltage suppressor chip is disposed on the first conductive material.

15. The bidirectional electrostatic discharge protection device according to claim 14, wherein: The first diode and the first NPN bipolar junction transistor are implemented using a first N-type semiconductor substrate, a first P-type semiconductor epitaxial layer, a first P-type heavily doped region, and a first N-type heavily doped region. The first N-type semiconductor substrate is disposed on the first conductive material and electrically connected to the first conductive material. The first P-type semiconductor epitaxial layer is disposed on the first N-type semiconductor substrate. The first P-type heavily doped region and the first N-type heavily doped region are disposed in the first P-type semiconductor epitaxial layer. The first P-type heavily doped region is electrically connected to the first conductive line, and the first N-type heavily doped region is electrically connected to the second conductive line. The first transient voltage suppressor chip further includes a first isolation structure disposed in the first P-type semiconductor epitaxial layer and located between the first P-type heavily doped region and the first N-type heavily doped region. The first isolation structure contacts the first N-type semiconductor substrate and separates the first P-type heavily doped region from the first N-type heavily doped region. The height of the first isolation structure is equal to or greater than the thickness of the first P-type semiconductor epitaxial layer.

16. The bidirectional electrostatic discharge protection device according to claim 15, wherein: The first isolation structure surrounds the first P-type heavily doped region and the first N-type heavily doped region.

17. The bidirectional electrostatic discharge protection device according to claim 15, wherein: Also includes: a second lead frame, serving as the second pin; as well as A second conductive material is disposed on the second lead frame and electrically connected to the second lead frame, wherein the second transient voltage suppressor chip is disposed on the second conductive material.

18. The bidirectional electrostatic discharge protection device according to claim 17, wherein: The second diode and the second NPN bipolar junction transistor are implemented using a second N-type semiconductor substrate, a second P-type semiconductor epitaxial layer, a second P-type heavily doped region, and a second N-type heavily doped region. The second N-type semiconductor substrate is disposed on the second conductive material and electrically connected to the second conductive material. The second P-type semiconductor epitaxial layer is disposed on the second N-type semiconductor substrate. The second P-type heavily doped region and the second N-type heavily doped region are disposed in the second P-type semiconductor epitaxial layer. The second P-type heavily doped region is electrically connected to the second conductive line, and the second N-type heavily doped region is electrically connected to the first conductive line. The second transient voltage suppressor chip further includes a second isolation structure disposed in the second P-type semiconductor epitaxial layer and located between the second P-type heavily doped region and the second N-type heavily doped region. The second isolation structure contacts the second N-type semiconductor substrate and separates the second P-type heavily doped region from the second N-type heavily doped region. The height of the second isolation structure is equal to or greater than the thickness of the second P-type semiconductor epitaxial layer.

19. The bidirectional electrostatic discharge protection device according to claim 18, wherein: The second isolation structure surrounds the second P-type heavily doped region and the second N-type heavily doped region.

20. The bidirectional electrostatic discharge protection device according to claim 11, wherein: The device also includes a packaging colloid, which covers the first transient voltage suppressor chip, the second transient voltage suppressor chip, the first conductive line and the second conductive line.

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