Semiconductor structure and method of manufacturing the same

Abstract

The embodiment of the present disclosure provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises: a substrate; a first electrode, the first electrode is located on the substrate, and the first electrode surrounds a through hole extending away from the substrate; a second electrode, the second electrode is located at least in the through hole; a capacitor dielectric layer, the capacitor dielectric layer is located between the first electrode and the second electrode, and the second electrode, the capacitor dielectric layer and the first electrode constitute a capacitor structure; a transistor, the transistor is located on the capacitor structure, and the transistor comprises a first doped region and a second doped region arranged at intervals in a direction perpendicular to the surface of the substrate, the first doped region is electrically connected with the second electrode, the first doped region and the second doped region are one of N type or P type, and the first doped region and the second doped region are of the same type; and a bit line, the bit line is located on the transistor and is electrically connected with the second doped region. The embodiment of the present disclosure is at least beneficial to improve the performance of the semiconductor device and reduce the difficulty of the manufacturing process.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and its manufacturing method. Background Technology

[0002] With the development of semiconductor technology, manufacturing semiconductor devices with better performance and higher integration has become the main pursuit in semiconductor processing.

[0003] However, the manufacturing process for smaller semiconductor devices is complex, and the performance requirements for processing equipment are extremely high. Furthermore, it is difficult to improve the processing accuracy by improving the performance of processing equipment.

[0004] Therefore, improving the layout and formation of semiconductor device structures is an effective way to achieve better performance and smaller size while reducing the difficulty of semiconductor device processing. Summary of the Invention

[0005] This disclosure provides a semiconductor structure and a method for manufacturing the same, which at least helps to improve the performance of semiconductor devices and reduce the difficulty of manufacturing processes.

[0006] This disclosure provides a semiconductor structure, comprising: a substrate; a first electrode located on the substrate and forming a via extending away from the substrate; a second electrode located at least within the via; a capacitor dielectric layer located between the first electrode and the second electrode, the second electrode, the capacitor dielectric layer, and the first electrode constituting a capacitor structure; a transistor located on the capacitor structure, the transistor including a first doped region and a second doped region spaced apart along a direction perpendicular to the substrate surface, the first doped region being electrically connected to the second electrode, the first doped region and the second doped region being either N-type or P-type, and the first doped region and the second doped region having the same doping type; and a bit line located on the transistor and electrically connected to the second doped region.

[0007] In some embodiments, the device further includes: an insulating layer, wherein the capacitor structure is located within the insulating layer and the insulating layer exposes the top surface of the second electrode; the outer wall of the via away from the second electrode is in contact with the insulating layer; the via is filled by the second electrode and the capacitor dielectric layer, and the top surface of the second electrode is flush with the top surface of the capacitor dielectric layer.

[0008] In some embodiments, the capacitor dielectric layer is also located on the top surface of the first electrode and the top surface of the insulating layer, and the top surface of the second electrode is flush with the top surface of the capacitor dielectric layer.

[0009] In some embodiments, the second electrode is also located on the outer wall of the through hole and the top surface of the first electrode, and the second electrode includes: a first main body portion located inside the through hole; a second main body portion located on the outer wall of the through hole, the material of the second main body portion being the same as that of the first main body portion, and the thickness of the first main body portion being greater than the thickness of the second main body portion in the direction parallel to the substrate surface; and an electrical connection portion spanning the first main body portion and the second main body portion, and contacting the top surface of the first main body portion and the top surface of the second main body portion.

[0010] In some embodiments, for the same capacitor structure, the second electrode is an integrally formed structure.

[0011] In some embodiments, the first electrode includes: a side portion, which is a sidewall portion of a via; a bottom connection portion, which is a bottom surface portion of the via parallel to the substrate; the semiconductor structure further includes: an electrical connection layer, which is located on the substrate and electrically connects the adjacent bottom connection portions.

[0012] In some embodiments, the electrical connection layer and the bottom connection portion are integrally formed film layers, and the capacitor dielectric layer is also located on the surface of the electrical connection layer.

[0013] In some embodiments, the side portion and the bottom connection portion are integrally formed film layers, and the electrical connection layer is also located between the bottom connection portion and the substrate.

[0014] In some embodiments, the transistor further includes: a channel region located between a first doped region and a second doped region, wherein the materials of the channel region, the first doped region, and the second doped region include at least one or more of IGZO, IWO, or ITO; a gate dielectric layer disposed around the channel region and located on the sidewall surface of the channel region; and a gate conductive layer disposed around the channel region and located on the sidewall surface of the gate dielectric layer corresponding to the channel region.

[0015] Another aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a first electrode on the substrate, the first electrode forming a through-hole extending in a direction away from the substrate; forming a second electrode, the second electrode being at least located within the through-hole; forming a capacitor dielectric layer, the capacitor dielectric layer being located between the first electrode and the second electrode, the second electrode, the capacitor dielectric layer, and the first electrode constituting a capacitor structure; forming a transistor, the transistor being located on the capacitor structure, and the transistor including a first doped region and a second doped region spaced apart along a direction perpendicular to the substrate surface, the first doped region being electrically connected to the second electrode, the doping type of the first doped region and the second doped region being either N-type or P-type, and the first doped region and the second doped region having the same doping type; forming a bit line, the bit line being located on the transistor and electrically connected to the second doped region.

[0016] In some embodiments, the step of forming the first electrode includes: forming an insulating film on a substrate, wherein the insulating film has a groove extending through the thickness of the insulating film; and forming the first electrode, wherein the first electrode is located at the bottom and sidewall of the groove.

[0017] In some embodiments, the remaining insulating film serves as an insulating layer; the steps of forming a capacitor dielectric layer and a second electrode include: forming a capacitor dielectric layer located at the bottom and sidewalls of a via; and forming a second electrode layer located on the surface of the capacitor dielectric layer and filling the via.

[0018] In some embodiments, the steps of forming a capacitor dielectric layer and a second electrode include: removing the remaining insulating film to expose the outer wall of the via; forming a capacitor dielectric layer located at the bottom, inner wall, and outer wall of the via; and forming a second electrode located on the surface of the capacitor dielectric layer and also located inside the via and on the outer wall of the via.

[0019] In some embodiments, the method further includes: forming an insulating layer located on a substrate; the process steps of forming the insulating layer and the second electrode include: forming a first body portion and a second body portion, the first body portion being located within a through hole, the second body portion being located on the outer sidewall of the through hole, the material of the second body portion being the same as the material of the first body portion; forming an insulating layer on the substrate, the insulating layer being located on the sidewall of the second body portion; forming an electrical connection portion, the electrical connection portion spanning the first body portion and the second body portion, and contacting the top surface of the first body portion and the top surface of the second body portion, the electrical connection portion, the first body portion, and the second body portion together constituting the second electrode.

[0020] In some embodiments, prior to forming the first electrode, the method further includes forming an electrical connection layer on a substrate, the electrical connection layer being electrically connected to the first electrode.

[0021] The technical solution provided in this disclosure has at least the following advantages: the capacitor structure of the semiconductor structure is located below the transistor. This arrangement has two main advantages: First, after the transistor is formed, the bit line structure can be directly formed on the exposed second doped region, which is simpler than the traditional buried bit line formation process. Second, this arrangement of the capacitor structure overcomes the limitations of the manufacturing line on subsequent processes, thus enabling multi-layer stacking of the capacitor structure and the crystal structure, increasing the storage capacity. Furthermore, in the case of multi-layer stacking, the requirement for miniaturizing the single-layer structure is reduced, allowing for an appropriate increase in the size of the single-layer structure and reducing the process difficulty. In addition, the capacitor structure is a columnar capacitor, which increases the relative area of ​​the first electrode and the second electrode within a limited space, further increasing the storage capacity. Attached Figure Description

[0022] One or more embodiments are illustrated by way of example with corresponding pictures in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this disclosure or the conventional technology, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram of a vertical cross-sectional structure of a semiconductor structure provided in an embodiment of the present disclosure.

[0024] Figure 2 for Figure 1 A horizontal cross-sectional view of the capacitor structure in the illustrated embodiment;

[0025] Figure 3 A schematic diagram of the vertical cross-sectional structure of a semiconductor structure provided in another embodiment of this disclosure;

[0026] Figure 4 A schematic diagram of the vertical cross-sectional structure of a semiconductor structure provided in another embodiment of this disclosure;

[0027] Figure 5 A schematic diagram of the vertical cross-sectional structure of a semiconductor structure provided in another embodiment of this disclosure;

[0028] Figure 6 A schematic diagram of the vertical cross-sectional structure of a semiconductor structure provided in another embodiment of this disclosure;

[0029] Figure 7 A schematic diagram of the vertical cross-sectional structure of a semiconductor structure provided in another embodiment of this disclosure;

[0030] Figure 8 for Figure 7 A horizontal cross-sectional view of the transistor in the embodiment shown.

[0031] Figure 9 for Figure 7 The illustrated embodiment does not include a top view of the isolation layer;

[0032] Figures 10 to 25 The diagram shows the structural schematics corresponding to each step of the semiconductor structure fabrication method provided in the embodiments of this disclosure. Detailed Implementation

[0033] As can be seen from the background technology, it is difficult to improve the processing accuracy by improving the performance of processing equipment. Improving the layout and formation method of semiconductor device structure is an effective way to enable semiconductor devices to achieve better performance while reducing size integration.

[0034] To address the aforementioned problems, this disclosure provides a semiconductor structure and its manufacturing method. By adjusting the positional relationship between the capacitor structure and the transistor, the fabrication process of the bit lines in the semiconductor structure is simplified, and it facilitates 3D (3-Dimensional) stacking of the memory, increasing the integration density of the semiconductor structure. Furthermore, by increasing the relative area between the first electrode and the second electrode, the capacitance is increased, thereby increasing the storage capacity.

[0035] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this disclosure to facilitate a better understanding of the embodiments. However, the technical solutions claimed in the embodiments of this disclosure can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0036] Figure 1 This is a schematic diagram of a vertical cross-sectional structure of a semiconductor structure provided in an embodiment of the present disclosure. Figure 2 for Figure 1 A horizontal cross-sectional view of the capacitor structure in the illustrated embodiment; Figure 3 A schematic diagram of the vertical cross-sectional structure of a semiconductor structure provided in another embodiment of this disclosure; Figure 4 A schematic diagram of the vertical cross-sectional structure of a semiconductor structure provided in another embodiment of this disclosure; Figure 5 A schematic diagram of the vertical cross-sectional structure of a semiconductor structure provided in another embodiment of this disclosure; Figure 6 A schematic diagram of the vertical cross-sectional structure of a semiconductor structure provided in another embodiment of this disclosure; Figure 7 A schematic diagram of the vertical cross-sectional structure of a semiconductor structure provided in another embodiment of this disclosure; Figure 8 for Figure 7 A horizontal cross-sectional view of the transistor in the embodiment shown. Figure 9 for Figure 7 The illustrated embodiment does not include a top view of the isolation layer.

[0037] refer to Figures 1 to 9The semiconductor structure includes: a substrate 100; a first electrode 102 located on the substrate 100, the first electrode 102 forming a via extending in a direction away from the substrate 100; a second electrode 104 located at least within the via; a capacitor dielectric layer 103 located between the first electrode 102 and the second electrode 104, the second electrode 104, the capacitor dielectric layer 103, and the first electrode 102 constituting a capacitor structure 110; a transistor 111 located on the capacitor structure 110, and the transistor 111 includes a first doped region I and a second doped region III arranged at intervals along a direction perpendicular to the surface of the substrate 100, the first doped region I being electrically connected to the second electrode 104, the doping type of the first doped region I and the second doped region III being either N-type or P-type, and the doping type of the first doped region I and the second doped region III being the same; and a bit line 112 located on the transistor 111 and electrically connected to the second doped region III.

[0038] Since the semiconductor structure includes a vertical gate-all-around (GAA) transistor 111, and the manufacturing process temperature of the transistor 111 is compatible with the conductive materials in the capacitor structure 110 and the bit line 112, the transistor 111 can be stacked on the capacitor structure 110 or the bit line 112, thus forming a 3D stacked memory device, which is beneficial to improving the integration density of the semiconductor structure. Furthermore, by appropriately increasing the size of a single-layer memory device based on 3D stacking, the manufacturing difficulty can be reduced. The bit line 112 is located on the transistor 111; therefore, compared to a buried bit line 112, the formation method of the bit line 112 superimposed on the transistor 111 in this embodiment is simpler. Moreover, since the second electrode 104 is located within the via formed by the first electrode 102, compared to a planar capacitor, the relative area between the outer surface of the second electrode 104 facing the inner wall of the via and the inner sidewall of the via of the first electrode 102 is larger, resulting in a larger capacitance.

[0039] refer to Figure 1 In this embodiment, since the first electrode 102 located on the substrate 100 is in contact with the substrate 100, in order to improve the potential stability of the first electrode 102, the substrate 100 can be an insulating material, such as silicon dioxide, silicon oxynitride, etc., and the substrate 100 can have a conductive layer (not shown in the figure). The conductive layer is electrically connected to the first electrode 102 for leading out the first electrode 102, and multiple first electrodes 102 can be electrically connected to the same conductive layer, which is beneficial to save wiring space and reduce the size of the semiconductor structure.

[0040] In some embodiments, the substrate 100 may also be a stacked structure composed of a first substrate layer 114 and a second substrate layer 115. Taking the second substrate layer 115 as an example, the substrate 100 in contact with the first electrode 102 may be an insulating material, such as silicon oxide. The second substrate layer 115 may also have a conductive layer (not shown) for leading out the first electrode 102. The first substrate layer 114 may be a material that can be directly used in the manufacturing process to produce semiconductor devices. For example, the first substrate layer 114 may be silicon on an insulating substrate (SOI), silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or sapphire.

[0041] refer to Figure 1 and Figure 2 In some embodiments, the via formed by the first electrode 102 of the capacitor structure 110 on the substrate 100 is a cylindrical via, meaning the capacitor structure 110 is a cylindrical capacitor. This capacitor structure 110 has smooth sides, which helps to avoid tip discharge. The capacitor dielectric layer 103 is located on the inner surface and bottom of the via of the first electrode 102, meaning the capacitor dielectric layer 103 also forms a via extending away from the substrate 100. The second electrode 104 fills the via formed by the capacitor dielectric layer 103, and the second electrode 104 is in contact with the capacitor dielectric layer 103 near the lower surface of the substrate 100. In other embodiments, the via formed by the first electrode 102 can be a square via or a cylindrical hole of other shapes, which also has a larger relative area of ​​the plates compared to a planar capacitor, thus increasing the capacitance.

[0042] In some embodiments, the first electrode 102 and the second electrode 104 are conductive materials, such as titanium nitride. In other embodiments, the materials of the first electrode 102 and the second electrode 104 may also be at least one of conductive materials such as platinum nickel, titanium, tantalum, cobalt, copper, tungsten, and tantalum nitride. The capacitor dielectric layer 103 is an insulating dielectric material, for example, the material of the capacitor dielectric layer 103 is at least one of high dielectric constant materials such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate.

[0043] In addition, the semiconductor structure includes a plurality of capacitor structures 110 arranged at intervals along a direction parallel to the top surface of the substrate 100, and the different capacitor structures 110 are discrete from each other.

[0044] Continue to refer to Figure 1In some embodiments, the semiconductor structure may further include: an insulating layer 101, a capacitor structure 110 located within the insulating layer 101, and the insulating layer 101 exposing the top surface of the second electrode 104; the outer wall of the via away from the second electrode 104 is in contact with the insulating layer 101; the via is filled by the second electrode 104 and the capacitor dielectric layer 103, and the top surface of the second electrode 104 is flush with the top surface of the capacitor dielectric layer 103.

[0045] An insulating layer 101 is located between capacitor structures 110, serving to support the capacitor structures 110 and isolate the second electrodes 102 of adjacent capacitor structures 110. The insulating layer 101 is made of at least one of silicon nitride, silicon oxynitride, or silicon oxide. In some embodiments, the insulating layer 101 may also be a stacked film structure, as long as it can fulfill its supporting and isolating functions. This disclosure does not specifically limit the structure of the insulating layer 101.

[0046] In some embodiments, the capacitor dielectric layer 103 may also be located on the top surface of the first electrode 102, so that only the second electrode 104 is exposed on the top surface of the insulating layer 101. This helps to avoid the possibility of electrical connection between the first electrode 102 and the first doped region I of the transistor 111 due to subsequent processing errors. Furthermore, the top surface of the second electrode 104 is flush with the top surface of the capacitor dielectric layer 103, ensuring a larger relative area between the first electrode 102 and the second electrode 104, which is beneficial for increasing the capacitance. It is understood that in other embodiments, the top surface of the first electrode 102 may also be higher than the top surface of the capacitor dielectric layer 103.

[0047] refer to Figure 3 In some embodiments, the capacitor dielectric layer 103 is also located on the top surface of the first electrode 102 and the top surface of the insulating layer 101, and the top surface of the second electrode 104 is flush with the top surface of the capacitor dielectric layer 103.

[0048] Specifically, the capacitor dielectric layer 103 located on the top surface of the first electrode 102 and the top surface of the insulating layer 101 can serve as a planarization stop layer for the second electrode 104. The second electrode 104 is located only in the through hole of the capacitor dielectric layer 103 and is flush with the top surface of the capacitor dielectric layer 103. This not only simplifies the processing technology but also ensures that the capacitor structure 110 has a large capacitance.

[0049] refer to Figure 4In some embodiments, the second electrode 104 is also located on the outer wall of the through hole and the top surface of the first electrode 102, and the second electrode 104 includes: a first body portion 120 located inside the through hole; a second body portion 121 located on the outer wall of the through hole, the material of the second body portion 121 being the same as that of the first body portion 120, and the thickness of the first body portion 120 being greater than the thickness of the second body portion 121 in a direction parallel to the surface of the substrate 100; and an electrical connection portion 122 spanning the first body portion 120 and the second body portion 121, and contacting the top surface of the first body portion 120 and the top surface of the second body portion 121. The electrical connection portion 122 is used to electrically connect the first body portion 120 on the inner wall of the through hole and the second body portion 121 on the outer wall of the through hole, such that the second electrode 104 is shared in a single capacitor. In addition, both the outer and inner walls of the via have opposing second electrodes 104. Compared with planar capacitors, by providing the first main body 120 and the second main body 121, the capacitance can be greatly increased, effectively improving the performance of the semiconductor structure.

[0050] Specifically, the outer wall of the second electrode 104 also has an insulating layer 101, which serves to isolate the second electrode 104 from the supporting capacitor structure 110, making the capacitors independent of each other, with each capacitor corresponding to a transistor 111. The first main body portion 120 and the second main body portion 121 are structures formed simultaneously, meaning that the materials constituting the first main body portion 120 and the second main body portion 121 are the same conductive material. Furthermore, the thickness of the first main body portion 120 refers to its maximum thickness in the direction parallel to the surface of the substrate 100. In addition, the capacitor dielectric layer 103 is also located on the surface of the substrate 100. The capacitor dielectric layer 103 can be selectively removed or retained. For example, retaining the capacitor dielectric layer 103 can reduce the process time of the entire semiconductor manufacturing process and improve the manufacturing efficiency of the semiconductor structure. It is understood that in other embodiments, the capacitor dielectric layer 103 may also be located only on the surface of the first electrode 102, which can also achieve the effect of isolating the first electrode 102 from the second electrode 104.

[0051] Continue to refer to Figure 4 In some embodiments, for the same capacitor structure 110, the second electrode 104 is a one-piece molded structure. That is, the electrical connection portion 122, the first main body portion 120, and the second main body portion 121 are all formed simultaneously from the same material, and this one-piece molded structure simplifies the processing of the second electrode 104. It is understood that in other embodiments, the electrical connection portion 122 and the first main body portion 120 and the second main body portion 121 may be made of different materials.

[0052] refer to Figure 5 and Figure 6In some embodiments, the first electrode 102 may include: a side portion 123, which is a sidewall portion of a through hole; a bottom connection portion 124, which is a portion of the through hole parallel to the bottom surface of the substrate 100; the semiconductor structure may also include: an electrical connection layer 108, which is located on the substrate 100 and electrically connected to the adjacent bottom connection portion 124.

[0053] It should be noted that since the substrate 100 has an electrical connection layer 108, the substrate 100 may not contain a conductive layer. The electrical connection layer 108 electrically connects the first electrode 102 of each capacitor structure 110 to the electrical connection layer 108. The semiconductor structure with the electrical connection layer 108 ensures the independence of each capacitor structure 110, and also allows the first electrode 102 to be electrically connected to an external circuit via the electrical connection layer 108. This enables the capacitor structures 110 of the semiconductor structure to share a common first electrode 102, simplifies the process, and helps to reduce the space waste caused by adding a conductive layer.

[0054] In some embodiments, the material of the electrical connection layer 108 is the same as the material of the first electrode 102 layer, which helps to avoid interface state defects and improve conductivity. It is understood that in other embodiments, the material of the electrical connection layer 108 may be different from the material of the first electrode 102, as long as the electrical connection to the first electrode 102 is ensured.

[0055] refer to Figure 5 and Figure 6 In some embodiments, the electrical connection layer 108 and the bottom connection portion 124 can be an integrally formed film layer, and the capacitor dielectric layer 103 is also located on the surface of the electrical connection layer 108.

[0056] Specifically, the electrical connection layer 108 located at the bottom of the through hole directly serves as the bottom connection portion 124 of the first electrode 102, which simplifies the processing technology of the first electrode 102. Furthermore, the capacitor dielectric layer 103 located on the surface of the electrical connection layer 108 prevents the second electrode 104 from contacting the electrical connection layer 108.

[0057] refer to Figure 7 In some embodiments, the side portion 123 and the bottom connection portion 124 can be an integrally formed film layer, and the electrical connection layer 108 is also located between the bottom connection portion 124 and the substrate 100.

[0058] Specifically, the electrical connection layer 108 and the bottom connection portion 124 have different structures. The part of the electrical connection layer 108 away from the substrate 100 is in contact with the bottom connection portion 124 of the first electrode 102. The first electrode 102 is directly led out through the electrical connection layer 108, avoiding the need to add other electrical connection structures to lead out the first electrode 103, thereby avoiding the waste of space caused by adding other electrical connection structures.

[0059] refer to Figure 7 and Figure 8 In each capacitor structure 110 of the semiconductor structure, the top of the second electrode 104 is in contact with a first doped region I of a transistor 111. The first doped region I constitutes either the source or the drain of the transistor 111, and the second doped region III constitutes the other either the source or the drain of the transistor 111. The first doped region I and the second doped region III can be N-type doped regions or P-type doped regions. Ions in the N-type doped region include arsenic ions, phosphorus ions, antimony ions, etc., and ions in the P-type doped region include boron ions, aluminum ions, gallium ions, etc.

[0060] In some embodiments, transistor 111 may further include a channel region II, which is located between the first doped region I and the second doped region III, and the materials of the channel region II, the first doped region I and the second doped region III include at least one or more of IGZO (indium gallium zinc oxide), IWO (indium tungsten oxide) or ITO (indium tin oxide). The above materials have high carrier mobility, which is beneficial to reduce leakage current when the semiconductor structure is working and improve the performance of the semiconductor structure.

[0061] The channel region II and the first doped region I and the second doped region III of transistor 111 constitute the semiconductor channel 105 of transistor 111. In some embodiments, the material of semiconductor channel 105 is IGZO. The carrier mobility of IGZO is 20 to 50 times that of polycrystalline silicon, which is beneficial to improving the carrier mobility of channel region II, thereby reducing the power consumption of the semiconductor structure and improving the operating efficiency of the semiconductor structure. In addition, the IGZO semiconductor channel 105 has a lower formation temperature, which is convenient for forming on a metal structure, and is conducive to forming a 3D stacked memory structure, thereby increasing the integration density of the semiconductor structure and integrating more semiconductor structures in a limited space.

[0062] In some embodiments, the first doped region I, the channel region II, and the second doped region III constituting the semiconductor channel 105 are integrated into a single structure. This is beneficial for improving the interface state defects between the first doped region I and the channel region II, and for improving the interface state defects between the channel region II and the second doped region III, thereby improving the performance of the semiconductor structure. It is understood that in other embodiments, the semiconductor channel 105 may also be a three-layer structure, with each layer corresponding to the first doped region I, the channel region II, and the second doped region III.

[0063] In addition, refer to Figure 8In some embodiments, the semiconductor channel 105 is a cylindrical structure, making the sides of the semiconductor channel 105 a smooth transition surface. This helps to avoid tip discharge or leakage in the semiconductor channel 105, further improving the electrical performance of the semiconductor structure. It should be noted that in other embodiments, the semiconductor channel 105 can also be a square columnar structure or other irregular structures. It is understood that when the semiconductor channel 105 is a square columnar structure, the corners formed by adjacent sidewalls of the square columnar structure can be rounded corners, which can also avoid tip discharge problems. The square columnar structure can be a cubic columnar structure or a cuboid columnar structure.

[0064] Continue to refer to Figure 7 and Figure 8 The transistor 111 structure may further include: a gate dielectric layer 106, which is disposed around the channel region II and located on the sidewall surface of the channel region II; and a gate conductive layer 107, which is disposed around the channel region II and located on the sidewall surface of the gate dielectric layer 106 corresponding to the channel region II.

[0065] In some embodiments, the gate dielectric layer 106 is located on the sidewall surface of the semiconductor channel 105 in channel region II and the sidewall surface of the semiconductor channel 105 in the second doped region III, serving to isolate the gate conductive layer 107 from the semiconductor channel 105. Furthermore, the gate dielectric layer 106 located on the sidewall surface of the semiconductor channel 105 in the second doped region III can protect the surface of the second doped region III, preventing process damage to the surface of the second doped region III during the formation of the gate conductive layer 107, thereby facilitating further improvement of the semiconductor structure's performance. It is understood that in other embodiments, the gate dielectric layer 106 may also be located only on the sidewall surface of the semiconductor channel 105 in channel region II.

[0066] The gate dielectric layer 106 is made of at least one of silicon oxide, silicon nitride, silicon oxynitride, or other high dielectric constant dielectric materials. The gate conductive layer 107 is made of at least one of polysilicon, titanium nitride, tantalum nitride, copper, tungsten, or aluminum.

[0067] Continue to refer to Figure 7In some embodiments, transistor 111 may further include an interlayer dielectric layer 113, which is located between transistors 111, exposing the top surface of the second doped region III of transistor 111, and serves to isolate adjacent transistors 111 and provide support. The interlayer dielectric layer 113 includes a first interlayer dielectric 125, a second interlayer dielectric 126, and a third interlayer dielectric 127. The first interlayer dielectric 125 is located on the sidewall surface of the semiconductor channel 105 where the first doped region I is located, the bottom surface of the gate dielectric layer 106 facing the substrate 100, and the bottom surface of the gate conductive layer 107 facing the substrate 100. The second interlayer dielectric 126 is located on the sidewall surface of the gate dielectric layer 106 on the sidewall of the second doped region III and the top surface of the gate conductive layer 107 away from the substrate 100. The third interlayer dielectric 127 is located on the sidewall surface of the gate conductive layer 107, between different sidewalls of the first interlayer dielectric 125, and between different sidewalls of the second interlayer dielectric 126. In this embodiment, the first interlayer dielectric 125, the second interlayer dielectric 126, and the third interlayer dielectric 127 can be separately formed structures. The first interlayer dielectric 125, the second interlayer dielectric 126, and the third interlayer dielectric 127 can be made of the same insulating material, such as at least one of silicon oxide, silicon nitride, silicon carbonitride, or silicon carbonitride oxycarbonate. Using the same material facilitates the formation of a good contact interface and improves the reliability of the semiconductor structure. It is understood that in other embodiments, the first interlayer dielectric 125, the second interlayer dielectric 126, and the third interlayer dielectric 127 can also be made of different insulating materials.

[0068] refer to Figure 7 In some embodiments, the semiconductor structure may further include bit lines 112 and an isolation layer 109. Bit lines 112 are located on a portion of the surface of the interlayer dielectric layer 113 and are in contact with the second doped region III of the transistor 111 and the top surface of the gate dielectric layer 106 away from the substrate 100. The isolation layer 109 covers the surface of the bit lines 112 to isolate different bit lines 112 and support other semiconductor structures stacked on the bit lines 112. The material of the isolation layer 109 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. Furthermore, having the same material for the interlayer dielectric layer 113 and the isolation layer 109 is beneficial for improving interface state defects between the interlayer dielectric layer 113 and the isolation layer 109, improving the performance of the semiconductor structure, and reducing the number of processing steps, thus lowering the manufacturing cost and complexity of the semiconductor structure. It is understood that in other embodiments, the material of the interlayer dielectric layer 113 may be different from the material of the isolation layer 109.

[0069] Specifically, a portion of the surface of the interlayer dielectric layer 113 may have multiple spaced bit lines 112, each bit line 112 being electrically connected to at least one second doped region III. For example, reference Figure 9Each line 112 is in contact with two second doped regions III. The number of second doped regions III that are in contact with each line 112 can be reasonably set according to actual electrical requirements.

[0070] The semiconductor structure provided in the above embodiments, with the capacitor structure 110 being a columnar structure, has opposing second electrodes 104 both inside and outside the via formed by the first electrode 102, greatly increasing the relative plate area of ​​the capacitor structure 110 and thus increasing the capacitance. The electrical connection layer 108 not only enables the semiconductor structure to have independent capacitor structures 110, but also allows the first electrode 102 to be electrically connected to an external circuit via the electrical connection layer 108, achieving a shared first electrode 102 across the semiconductor structure. This simplifies the manufacturing process and avoids wasted space. By adjusting the positional relationship between the transistor 111 and the capacitor structure 110, the semiconductor structure meets the conditions for multi-layer stacking, increasing the integration density of the semiconductor structure within the same volume. Furthermore, the arrangement of the transistor 111 on the capacitor structure 110 not only simplifies the formation process of the bit line 112 but also appropriately increases the size of the single-layer semiconductor structure, thus reducing manufacturing complexity.

[0071] Accordingly, another aspect of this disclosure provides a method for manufacturing a semiconductor structure, used to form the aforementioned semiconductor structure. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments can be found in the detailed descriptions of the foregoing embodiments, and will not be repeated hereafter.

[0072] Figures 10 to 25 The diagram shows the structural schematics corresponding to each step of the semiconductor structure fabrication method provided in the embodiments of this disclosure.

[0073] refer to Figure 10 The method for manufacturing a semiconductor structure includes: providing a substrate 100.

[0074] In this case, the surface of the substrate 100 is formed with an insulating material or the substrate 100 itself is an insulating material. In this way, the semiconductor structure in contact with the substrate 100 can be prevented from being affected by unstable electrical signals, thus affecting the electrical performance of the semiconductor structure.

[0075] refer to Figure 11 In some embodiments, an electrical connection layer 108 may be formed on the substrate 100. The electrical connection layer 108 is a conductive film layer located on the top surface of the substrate 100 and is electrically connected to the subsequently formed first electrode 102. Furthermore, the electrical connection layer 108 may be formed by physical vapor deposition, evaporation, sputtering, or other methods. For details regarding the materials of the substrate 100 and the electrical connection layer 108, please refer to the corresponding descriptions in the foregoing embodiments; further details will not be repeated here.

[0076] refer to Figures 12 to 14A first electrode 102 is formed on the substrate 100, and the first electrode 102 forms a through hole extending in a direction away from the substrate 100.

[0077] For details, please refer to Figure 14 Independent first electrodes 102 can be formed on the electrical connection layer 108 of the substrate 100, with the first electrodes 102 contacting the electrical connection layer 108 on the bottom surface facing the substrate 100. In this way, no additional lead layers are needed; the first electrodes 102 can be directly led out through the electrical connection layer 108, saving space and facilitating the reduction of the semiconductor structure size. Furthermore, the shape of the vias can be referred to the corresponding description in the foregoing embodiments, and will not be repeated here.

[0078] Continue to refer to Figures 12 to 14 In some embodiments, the step of forming the first electrode 102 may further include: forming an insulating film on the substrate 100, wherein the insulating film has a groove extending through the thickness of the insulating film; forming the first electrode 102, wherein the first electrode 102 is located at the bottom and sidewalls of the groove. The groove within the insulating film defines the position of the first electrode 102. With the assistance and support of the insulating film, by forming conductive material on the sidewalls and bottom of the groove, a first electrode 102 with a larger capacitance is obtained. Furthermore, the material of the insulating film may be silicon oxide.

[0079] Specifically, an insulating film is first formed on the electrical connection layer 108 of the substrate 100 by deposition, and the thickness of the insulating film is determined according to the required height of the columnar capacitor. Then, a groove is formed on the insulating film using photolithography, etching, or other processes, with the bottom of the groove partially exposing the top surface of the electrical connection layer 108. Furthermore, the groove formed here can be a circular hole-shaped groove extending towards the substrate 100. It is understood that in other embodiments, the groove can also be a square hole-shaped groove or a groove of other shapes. Then, a conductive material is formed as a first electrode 102 on the surface of the electrical connection layer 108 exposed at the bottom of the groove, the sidewalls of the groove, and the top surface of the insulating film. The conductive material on the top surface of the insulating film is removed using maskless etching, thereby forming independent first electrodes 102. Furthermore, the first electrode 102 can be formed using atomic layer deposition (ALD).

[0080] In some embodiments, photoresist can be used to cover the via, and then the first electrode 102 on the top surface of the insulating film can be removed to obtain the first electrode 102. It should be noted that, in this case, the first electrode 102 located at the bottom of the via will not be etched away under the coverage of the photoresist, and is thus retained on the electrical connection layer 108 inside the via.

[0081] refer to Figures 15 to 20After forming the first electrode 102, the process further includes forming a second electrode 104 and a capacitor dielectric layer 103. The second electrode 104 is located at least within the via, and the capacitor dielectric layer 103 is located between the first electrode 102 and the second electrode 104. The second electrode 104, the capacitor dielectric layer 103, and the first electrode 102 constitute a capacitor structure 110. Furthermore, the second electrode 104 can be formed using an atomic layer deposition process.

[0082] The method for forming the capacitor dielectric layer 103 and the second electrode 104 is specifically described in the following embodiments.

[0083] refer to Figures 15 to 16 In some embodiments, the remaining insulating film can serve as insulating layer 101, followed by the formation of capacitor dielectric layer 103, which is located at the bottom and sidewalls of the via; a second electrode layer 104 is then formed, located on the surface of capacitor dielectric layer 103 and filling the via. Retaining the remaining insulating film as insulating layer 101 can provide support when forming the second electrode 104 with opposite sidewalls of the via.

[0084] Specifically, a capacitor dielectric layer 103 is formed on the top surface of the insulating layer 101 away from the substrate 100, the sidewall of the via formed by the first electrode 102, the top surface, and the bottom surface. Then, a second electrode 104 is formed on the capacitor dielectric layer 103, and the second electrode 104 fills the via formed by the capacitor dielectric layer 103. Using a planarization process, with the capacitor dielectric layer 103 as the planarization stop layer, the second electrode 104 located on the top surface of the insulating layer 101 and the top surface of the first electrode 102 on the capacitor dielectric layer 103 is removed, resulting in a second electrode 104 flush with the top surface of the capacitor dielectric layer 103. This simplifies the process flow and reduces manufacturing complexity. In other embodiments, the removal of the second electrode 104 located on the top surface of the insulating layer 101 and the top surface of the first electrode 102 on the capacitor dielectric layer 103 can also be achieved using a mask etching method, i.e., photoresist is used to cover the top surface of the second electrode 104 within the via, and then the remaining second electrode 104 is removed.

[0085] refer to Figure 17 and Figure 18 In some embodiments, the steps of forming the capacitor dielectric layer 103 and the second electrode 104 may further include: removing the remaining insulating film to expose the outer wall of the through hole; forming the capacitor dielectric layer 103, which is located at the bottom, inner sidewall, and outer sidewall of the through hole; and forming the second electrode 104, which is located on the surface of the capacitor dielectric layer 103 and also inside the through hole and on the outer sidewall of the through hole. In this way, the second electrode 104 can be formed on both the inner and outer sidewalls of the through hole of the first electrode 102, further increasing the relative area of ​​the electrodes and thus increasing the capacitance.

[0086] Specifically, the insulating film on the electrical connection layer 108 and the outer wall of the via on the substrate 100 is removed, and a capacitor dielectric layer 103 is formed on the electrical connection layer 108 and the first electrode 102 by a deposition process, and then a second electrode 104 is formed on the capacitor dielectric layer 103. The second electrode 104 is formed by an atomic layer deposition process.

[0087] refer to Figures 19 to 20 In some embodiments, the step of forming the second electrode 104 may further include: forming an insulating layer 101, the insulating layer 101 being located on the substrate 100; the process steps of forming the insulating layer 101 and the second electrode 104 include: forming a first main body portion 120 and a second main body portion 121, the first main body portion 120 being located inside a through hole, the second main body portion 121 being located on the outer sidewall of the through hole, the material of the second main body portion 121 being the same as the material of the first main body portion 120; forming an insulating layer 101 on the substrate 100, the insulating layer 101 being located on the sidewall of the second main body portion 121; forming an electrical connection portion 122, the electrical connection portion 122 spanning the first main body portion 120 and the second main body portion 121, and contacting the top surface of the first main body portion 120 and the top surface of the second main body portion 121, the electrical connection portion 122, the first main body portion 120 and the second main body portion 121 together constituting the second electrode 104.

[0088] Specifically, after the second electrode 104 is formed on the capacitor dielectric layer 103, a maskless etching method is used to remove the second electrode 104 from the top of the via in the capacitor dielectric layer 103 and the surface of the capacitor dielectric layer 103 on the electrical connection layer 108, resulting in a first main body portion 120 and a second main body portion 121 of the second electrode 104. An insulating layer 101 is formed on the outer wall of the second main body portion 121 to insulate and isolate the independent second electrodes 104 and to provide support for the subsequent semiconductor structure. The insulating layer 101 exposes the top surface of the first main body portion 120, the top surface of the second main body portion 121, and the top surface of the capacitor dielectric layer 103 away from the substrate 100. Electrical connection portion 122 material is formed on the top surface of insulating layer 101 away from substrate 100, the top surface of first main body portion 120, the top surface of second main body portion 121, and the top surface of capacitor dielectric layer 103 away from substrate 100. The electrical connection portion 122 on the top surface of insulating layer 101 away from substrate 100 is removed, so that the first main body portion 120 of second electrode 104 is electrically connected to the second main body portion 121, and an independent second electrode 104 is formed.

[0089] In some embodiments, the electrical connection portion 122 is formed as follows: a layer, such as a conductive material and a mask layer, is formed on the top surface of the insulating layer 101 away from the substrate 100, the top surface of the first main body portion 120, the top surface of the second main body portion 121, and the top surface of the capacitor dielectric layer 103 away from the substrate 100. Using SADP (Self-aligned Double Patterning) technology, multiple raised first mask patterns are formed in one direction, and multiple raised second mask patterns are formed in another direction using SADP technology. The areas where the first and second mask patterns intersect are selectively etched to remove the mask layer and the conductive material beneath it until the insulating layer 101 is exposed. The remaining mask layer is then removed, leaving the remaining material for the electrical connection portion 122, thus forming the electrical connection portion 122. The embodiments disclosed herein can precisely control the position and shape of the electrical connection portion 122 to form mutually independent electrical connection portions 122, thereby enabling the first main body portion 120 and the second main body portion 121 to be connected through the electrical connection portion 122 to form a mutually independent and integrally structured second electrode 104. In other embodiments, the electrical connection portion 122 can also be formed by using the SAQP (Self-aligned Quadruple Patterning) process.

[0090] In some embodiments, photoresist is used to cover the second electrode 104 on the outer sidewall, inner sidewall, bottom, and top of the via formed by the capacitor dielectric layer 103. The second electrode 104 on the surface of the capacitor dielectric layer 103 on the external electrical connection layer 108 of the via is etched away, thereby directly obtaining the independent second electrode 104 including the first body portion 120, the second body portion 121, and the electrical connection portion 122. Furthermore, after removing the photoresist, an insulating layer 101 is formed, and a planarization process is used to expose the top surface of the insulating layer 101 of the second electrode 104 so that the first doped region I of the subsequently formed transistor 111 comes into contact with the second electrode 104.

[0091] refer to Figures 21 to 23A transistor 111 is formed on a capacitor structure 110. The transistor 111 includes a first doped region I and a second doped region III arranged at intervals along a direction perpendicular to the surface of the substrate 100. The first doped region I is electrically connected to the second electrode 104. The doping type of the first doped region I and the second doped region III is either N-type or P-type, and the doping types of the first doped region I and the second doped region III are the same. It should be noted that forming the transistor 111 may further include: forming a channel region II, which is located between the first doped region I and the second doped region III, and the channel region II, the first doped region I, and the second doped region III constitute the semiconductor channel 105 of the transistor 111; forming a gate dielectric layer 106, which is disposed around the channel region II and located on the sidewall surface of the channel region II; and forming a gate conductive layer 107, which is disposed around the channel region II and located on the sidewall surface of the gate dielectric layer 106 corresponding to the channel region II.

[0092] Furthermore, before forming transistor 111, the process may include forming a first interlayer dielectric 125, as shown in the reference. Figure 21 The first interlayer dielectric 125 forms a portion of the surface of the second electrode 104 and the surface of the insulating layer 101, and a groove extending towards the top surface of the second electrode 104 is formed within the first interlayer dielectric 125, with the bottom of the groove exposing a portion of the top surface of the second electrode 104. The groove can be a circular hole-shaped groove. (Reference) Figure 22 A semiconductor channel 105 is formed within the groove, and then a portion of the first interlayer dielectric 125 is removed to form a gate dielectric layer 106, a gate conductive layer 107, and a second interlayer dielectric 126. Since the gate conductive layers 107 of different transistors 111 are interconnected at this point, therefore, refer to... Figure 23 By selectively etching away the gate conductive layer 107, gate conductive layers 107 that are independent of each other or have a specified connection method are formed. A third interlayer dielectric 127 is then formed between the independent gate conductive layers 107. The first interlayer dielectric 125, the second interlayer dielectric 126, and the third interlayer dielectric 127 constitute an interlayer dielectric layer 113. The interlayer dielectric layer 113 facilitates better insulation of the transistor and provides support for subsequent semiconductor structures.

[0093] refer to Figure 24 Bit line 112 is formed, located on transistor 111, and electrically connected to the second doped region III.

[0094] Specifically, bit lines 112 are formed and patterned on the surface of the interlayer dielectric layer 113, the second doped region III of the transistor 111, and the top surface of the gate dielectric layer 106 away from the substrate 100, forming independent bit lines 112 or bit lines 112 with a specified connection method. In addition, an isolation layer 109 is formed on the surface of the bit lines 112 to provide good insulation between the independent bit lines 112 and to provide support for the stacked semiconductor structure formed on the subsequent bit lines 112.

[0095] refer to Figure 25 The capacitor structure 110, transistor 111 and bit line 112 adjacent to the substrate 100 constitute a memory cell array 130. At least one memory cell array 130 is formed on the isolation layer 109, and multiple memory cell arrays 130 extend in a direction away from the top surface of the substrate 100.

[0096] The semiconductor structure manufacturing method provided in the above embodiments can form a columnar capacitor structure 110 with a common first electrode 102, a transistor structure 111 arranged on the capacitor structure 110, and a non-buried bit line 112. The common first electrode 102 saves space, and the transistor structure 111 arranged on the capacitor structure 110 enables multi-layer stacking of memory cell arrays. This facilitates further miniaturization while ensuring superior performance of the semiconductor structure. Furthermore, the non-buried bit line 112 reduces manufacturing complexity, and the columnar capacitor structure 110 has a larger relative electrode area, improving the performance of the semiconductor structure.

[0097] Those skilled in the art will understand that the above embodiments are specific examples of implementing this disclosure, and in practical applications, various changes in form and detail may be made without departing from the spirit and scope of this disclosure. Any person skilled in the art can make their own variations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A first electrode is located on the substrate and forms a through hole extending in a direction away from the substrate; A second electrode, wherein the second electrode is located at least within the through hole; A capacitor dielectric layer is located between the first electrode and the second electrode, and the second electrode, the capacitor dielectric layer, and the first electrode constitute a capacitor structure. A transistor located on the capacitor structure, the transistor including a first doped region and a second doped region spaced apart along a direction perpendicular to the surface of the substrate, the first doped region being electrically connected to the second electrode, the doping type of the first doped region and the second doped region being either N-type or P-type, and the first doped region and the second doped region having the same doping type; Bit lines, located on the transistor and electrically connected to the second doped region; An insulating layer is provided, the capacitor structure is located within the insulating layer, and the insulating layer exposes the top surface of the second electrode; the outer wall of the through hole away from the second electrode is in contact with the insulating layer; the through hole is filled by the second electrode and the capacitor dielectric layer, and the top surface of the second electrode is flush with the top surface of the capacitor dielectric layer.

2. The semiconductor structure as described in claim 1, characterized in that, The capacitor dielectric layer is also located on the top surface of the first electrode and the top surface of the insulating layer, and the top surface of the second electrode is flush with the top surface of the capacitor dielectric layer.

3. The semiconductor structure as described in claim 1, characterized in that, The second electrode is also located on the outer wall of the through hole and the top surface of the first electrode, and the second electrode includes: A first main body portion, the first main body portion being located within the through hole; The second main body is located on the outer wall of the through hole. The material of the second main body is the same as that of the first main body, and the thickness of the first main body is greater than that of the second main body in the direction parallel to the surface of the base. An electrical connection portion spans the first main body portion and the second main body portion, and is in contact with the top surfaces of the first main body portion and the second main body portion.

4. The semiconductor structure as described in claim 3, characterized in that, For the same capacitor structure, the second electrode is a one-piece molded structure.

5. The semiconductor structure as described in claim 1, characterized in that, The first electrode includes: The side portion, which is the sidewall portion of the through hole; Bottom connecting portion, wherein the bottom connecting portion is the portion of the bottom surface of the through hole parallel to the base; The semiconductor structure further includes an electrical connection layer located on the substrate and electrically connected to the adjacent bottom connection portion.

6. The semiconductor structure as described in claim 5, characterized in that, The electrical connection layer and the bottom connection portion are integrally formed film layers, and the capacitor dielectric layer is also located on the surface of the electrical connection layer.

7. The semiconductor structure as described in claim 5, characterized in that, The side portion and the bottom connection portion are integrally formed film layers, and the electrical connection layer is also located between the bottom connection portion and the substrate.

8. The semiconductor structure as described in claim 1, characterized in that, The transistor also includes: The channel region is located between the first doped region and the second doped region, and the materials of the channel region, the first doped region and the second doped region include at least one or more of IGZO, IWO or ITO; A gate dielectric layer is disposed around the channel region and located on the sidewall surface of the channel region; A gate conductive layer is disposed around the channel region and located on the sidewall surface of the gate dielectric layer corresponding to the channel region.

9. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, on which an insulating film is formed, and the insulating film has a groove extending through the thickness of the insulating film. A first electrode is formed on the substrate, the first electrode forming a through hole extending in a direction away from the substrate; A second electrode is formed, wherein the second electrode is located at least within the through hole; A capacitor dielectric layer is formed between the first electrode and the second electrode, and the second electrode, the capacitor dielectric layer, and the first electrode constitute a capacitor structure. The steps of forming the capacitor dielectric layer and the second electrode include: removing the remaining insulating film to expose the outer wall of the through hole; forming the capacitor dielectric layer, which is located at the bottom, inner sidewall, and outer sidewall of the through hole; and forming the second electrode, which is located on the surface of the capacitor dielectric layer and also inside the through hole and on the outer wall of the through hole. A transistor is formed, the transistor is located on the capacitor structure, and the transistor includes a first doped region and a second doped region arranged at intervals along a direction perpendicular to the surface of the substrate. The first doped region is electrically connected to the second electrode. The doping type of the first doped region and the second doped region is either N-type or P-type, and the doping type of the first doped region and the second doped region is the same. A bit line is formed, which is located on the transistor and electrically connected to the second doped region.

10. The method for manufacturing a semiconductor structure as described in claim 9, characterized in that, The first electrode is located at the bottom and sidewall of the groove.

11. The method for manufacturing a semiconductor structure as described in claim 10, characterized in that, The remaining insulating film serves as an insulating layer; The steps of forming the capacitor dielectric layer and the second electrode include: The capacitor dielectric layer is formed, and the capacitor dielectric layer is located at the bottom and sidewall of the via. A second electrode layer is formed, which is located on the surface of the capacitor dielectric layer and fills the via.

12. The method for manufacturing a semiconductor structure as described in claim 9, characterized in that, Also includes: An insulating layer is formed on the substrate; The process steps for forming the insulating layer and the second electrode include: A first main body portion and a second main body portion are formed, the first main body portion being located inside the through hole, and the second main body portion being located on the outer side wall of the through hole, the material of the second main body portion being the same as the material of the first main body portion; The insulating layer is formed on the substrate, and the insulating layer is located on the sidewall of the second main body portion; An electrical connection portion is formed, which spans the first main body portion and the second main body portion and is in contact with the top surfaces of the first main body portion and the second main body portion. The electrical connection portion, the first main body portion, and the second main body portion together constitute the second electrode.

13. The method for manufacturing a semiconductor structure as described in claim 9, characterized in that, Before forming the first electrode, the method further includes forming an electrical connection layer on the substrate, the electrical connection layer being electrically connected to the first electrode.

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