Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same, the semiconductor structure comprising: a substrate including an active region; an isolation structure located in the substrate and surrounding the active region, the top surface of the isolation structure being in a step shape, comprising a first step portion facing the active region, a transition step portion with a side wall connected to the top surface of the first step portion, and a second step portion with a side wall connected to the top surface of the transition step portion, the top surfaces of the first step portion, the transition step portion, and the second step portion being successively higher, and the top surface of the second step portion being higher than the substrate surface; a gate oxide layer located on the substrate surface of the active region; a gate layer covering the gate oxide layer of the active region and extending to cover the first step portion and the transition step portion; and a gate plug located above the top of the transition step portion and electrically connected to the gate layer. The present invention allows the gate layer located at the top of the transition step portion to be retained, so that the gate plug is electrically connected to the gate layer located above the top of the transition step portion.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In existing semiconductor devices, devices with different operating voltages are usually formed on a substrate, for example, a low voltage (LV) device, a high voltage device (HV) and a medium voltage (MV) device.

[0003] With the development of semiconductor process technology, the critical dimensions of semiconductor devices are constantly shrinking, resulting in increasingly serious gate depletion effects. In order to better overcome problems such as gate depletion effects, the high k last metal gate last process and the replacement gate process have become commonly used processes.

[0004] Among them, compared with low-voltage devices, high-voltage devices and medium-voltage devices have higher operating voltages, and the sizes of high-voltage devices and medium-voltage devices are correspondingly larger. Therefore, high-voltage devices and medium-voltage devices still use polysilicon gates, while low-voltage devices use metal gates. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, including an active area; an isolation structure, located in the substrate and surrounding the active area, the top surface of the isolation structure adjacent to the active area is stepped, the isolation structure comprises a first step portion facing the active area, a transition step portion whose sidewall is connected to the top surface of the first step portion, and a second step portion whose sidewall is connected to the top surface of the transition step portion, the top surfaces of the first step portion, the transition step portion and the second step portion are successively increased, and the top surface of the second step portion is higher than the substrate surface; a gate oxide layer, located on the substrate surface of the active area; a gate layer, located in the active area and covering the gate oxide layer, the gate layer also extending to cover the first step portion and the transition step portion; a gate plug, located above the top of the transition step portion and electrically connected to the gate layer.

[0007] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a first active region for forming a first device, an isolation structure surrounding the first active region and having a stepped top surface formed in the substrate, the isolation structure comprising a first step portion facing the first active region, and a second step portion having a side wall connected to the top surface of the first step portion, the top surfaces of the first step portion and the second step portion are successively increased, and the top surface of the second step portion is higher than the surface of the substrate, and a first gate oxide layer is formed on the surface of the substrate of the first active region; etching a portion of the second step portion close to one side of the first step portion to form a transition step portion, the side wall of the transition step portion is connected to the top surface of the first step portion, and the top surface of the transition step portion is higher than the top surface of the first step portion; in the first active region, forming a gate layer covering the first gate oxide layer, the gate layer also extending to cover the first step portion and the transition step portion; forming a gate plug electrically connected to the gate layer above the top of the transition step portion.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the semiconductor structure provided by the embodiment of the present invention, the isolation structure surrounding the active area has a stepped top surface, the isolation structure includes a first step portion facing the active area, a transition step portion whose sidewall is connected to the top surface of the first step portion, and a second step portion whose sidewall is connected to the top surface of the transition step portion, the top surface of the second step portion is higher than the substrate surface, and the gate layer extends to cover the first step portion and the transition step portion accordingly; wherein, in the formation process of the semiconductor structure, before the formation process of the gate plug, a planarization process (for example, a planarization process of the interlayer dielectric layer and a planarization process of the metal gate layer) is generally included, by A transition step portion is provided between the first step portion and the second step portion, so that part of the gate layer can be located on the transition step portion, and since the top surfaces of the first step portion, the transition step portion and the second step portion are successively higher, that is, compared with the top surface of the second step portion, the top surface of the transition step portion is lower, therefore, in the planarization process, the probability of over-grinding the gate layer located at the top of the transition step portion is low, so that the gate layer located at the top of the transition step portion can be retained, and then the gate plug can be electrically connected to the gate layer located above the top of the transition step portion, thereby correspondingly improving the performance of the semiconductor structure.

[0010] In the formation method provided by the embodiment of the present invention, an isolation structure surrounding the first active area and having a stepped top surface is formed in the substrate, the isolation structure includes a first step portion facing the first active area, and a second step portion whose sidewall is connected to the top surface of the first step portion, the top surface of the second step portion is higher than the substrate surface, the top surfaces of the first step portion and the second step portion are successively increased, and a first gate oxide layer is formed on the substrate surface of the first active area, before forming the gate layer, a portion of the second step portion close to one side of the first step portion is etched to form a transition step portion, the sidewall of the transition step portion is connected to the top surface of the first step portion, and the top surface of the transition step portion is higher than the top surface of the first step portion; accordingly, after forming the gate layer covering the first gate oxide layer, the gate layer also extends to cover the first gate oxide layer. A step portion and a transition step portion; wherein, before forming the gate plug, a planarization process (for example, a planarization process of the interlayer dielectric layer and a planarization process of the metal gate layer) is usually included, and by setting the transition step portion between the first step portion and the second step portion, part of the gate layer can be located on the transition step portion, and since the top surfaces of the first step portion, the transition step portion and the second step portion are successively increased, that is, compared with the top surface of the second step portion, the top surface of the transition step portion is lower, therefore, in the planarization process, the probability of over-grinding the gate layer located at the top of the transition step portion is low, so that the gate layer located at the top of the transition step portion can be retained, and then the gate plug can be electrically connected to the gate layer located above the top of the transition step portion, and the performance of the semiconductor structure is correspondingly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 4 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure;

[0012] Figure 5 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figures 6 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0014] The performance of the current semiconductor structure needs to be improved. The reasons why the performance needs to be improved are analyzed in combination with a method for forming a semiconductor structure.

[0015] Figures 1 to 4 The present invention is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure.

[0016] refer to Figure 1A substrate 10 is provided, including a first device region 10H for forming a high-voltage device, an isolation structure 11 is formed in the substrate 10 of the first device region 10H, and in the first device region 10H, the isolation structure 11 surrounds an active region 10a, and a gate oxide layer 14 is formed on the surface of the substrate 10 of the active region 10a. As an example, the operating voltage of the high-voltage device is generally greater than 10V.

[0017] It should be noted that, before forming the gate oxide layer 14 , the process generally includes: using a hydrofluoric acid solution to clean the surface of the substrate 10 in the active area 10 a .

[0018] It should also be noted that in the actual process, in order to selectively clean the surface of the substrate 10 in the active area 10a, a mask layer is first formed on the substrate 10 before the cleaning process, and the mask layer exposes the surface of the substrate 10 in the active area 10a and covers other areas that do not need to be cleaned.

[0019] Moreover, in the process of forming the mask layer, in order to increase the process window of the photolithography process, the mask layer also exposes part of the isolation structure 11 at the junction of the substrate 10 and the isolation structure 11 of the active area 10a. Since the material of the isolation structure 11 is usually silicon oxide, the isolation structure 11 with a thickness of part exposed by the mask layer will also be removed during the cleaning process. Accordingly, after the cleaning process, the isolation structure 11 has a stepped top surface. Specifically, in the first device area 10H, the isolation structure 11 includes a first step portion 12 facing the active area 10a, and a second step portion 13 whose sidewalls are connected to the top surface of the first step portion 12, and the top surfaces of the first step portion 12 and the second step portion 13 are successively increased.

[0020] refer to Figure 2 A polysilicon gate layer 20 is formed on the gate oxide layer 14 , and the polysilicon gate layer 20 also extends to cover a portion of the top of the first step portion 12 and the second step portion 13 .

[0021] refer to Figure 3 A bottom interlayer dielectric layer 30 is formed on the substrate 10 at the side of the polysilicon gate layer 20 , and the bottom interlayer dielectric layer 30 exposes the top of the polysilicon gate layer 20 .

[0022] It should be noted that, in the actual process, the substrate 10 further includes a second device region (not shown) for forming a low-voltage device. For example, the operating voltage of the low-voltage device is less than 2V.

[0023] Among them, in order to improve the short channel effect, low-voltage devices usually adopt a metal gate structure, and usually adopt a gate last process to form a metal gate layer. That is, after removing the polysilicon gate layer 20 of the second device area, forming a gate opening in the bottom interlayer dielectric layer 30, a metal gate material layer is filled into the gate opening, and then the metal gate material layer is planarized to remove the metal gate material layer higher than the top of the bottom interlayer dielectric layer 30, and the thickness of the remaining metal gate material layer reaches a preset thickness, and the remaining metal gate material layer after the planarization process is used as the metal gate layer.

[0024] However, since the channel length of the high voltage device is usually greater than the channel length of the low voltage device, that is, the length of the polysilicon gate layer 20 in the first device region 10H is greater, such as Figure 4 As shown in FIG. 1 , the planarization process performed during the formation of the metal gate layer is likely to cause over-grinding of the polysilicon gate layer 20 in the first device region 10H, and after the metal gate layer is formed, the polysilicon gate layer 20 located at the top of the second step portion 13 is likely to be removed (eg, Figure 4 The problem that the top surface of the polysilicon gate layer 20 located above the gate oxide layer 14 is recessed is easily caused.

[0025] In addition, the process of forming the bottom interlayer dielectric layer 30 also includes a planarization step. Accordingly, in the process of forming the bottom interlayer dielectric layer 30, it is also easy to cause the height of the polysilicon gate layer 20 in the first device area 10H to be reduced, thereby further increasing the probability of over-grinding the polysilicon gate layer 20 in the first device area 10H in the process of forming the metal gate layer.

[0026] Subsequently, a gate plug needs to be formed above the top of the second step portion 13, and the gate plug is used to be connected to the polysilicon gate layer 20. Since the polysilicon gate layer 20 at the top of the second step portion 13 is easy to be removed, it is easy for the gate plug to be unable to be electrically connected to the polysilicon gate layer 20, thereby causing adverse effects on the performance of the semiconductor structure.

[0027] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, in which the top surface of the isolation structure surrounding the active area is stepped, and the isolation structure includes a first step portion facing the active area, a transition step portion whose sidewall is connected to the top surface of the first step portion, and a second step portion whose sidewall is connected to the top surface of the transition step portion, wherein the top surface of the second step portion is higher than the substrate surface, and the gate layer extends to cover the first step portion and the transition step portion accordingly; wherein, in the formation process of the semiconductor structure, before the formation process of the gate plug, a planarization process is generally included, by forming a gate plug on the first step portion, A transition step portion is provided between the first step portion and the second step portion, so that part of the gate layer can be located on the transition step portion, and since the top surfaces of the first step portion, the transition step portion and the second step portion are successively higher, that is, compared with the top surface of the second step portion, the top surface of the transition step portion is lower, therefore, in the planarization process, the probability of over-grinding the gate layer located at the top of the transition step portion is low, so that the gate layer located at the top of the transition step portion can be retained, and then the gate plug can be electrically connected to the gate layer located above the top of the transition step portion, thereby correspondingly improving the performance of the semiconductor structure.

[0028] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0029] Figure 5 It is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0030] The semiconductor structure comprises: a substrate 300, comprising an active area (AA) 30a; an isolation structure 301, located in the substrate 300 and surrounding the active area 30a, wherein the top surface of the isolation structure 301 adjacent to the active area 30a is stepped, wherein the isolation structure 301 comprises a first step portion 302 facing the active area 30a, a transition step portion 304 whose sidewall is connected to the top surface of the first step portion 302, and a second step portion 303 whose sidewall is connected to the top surface of the transition step portion 304, wherein the first step portion 302, the transition step portion 304 and the second step portion 303 are connected to each other. 04 and the top surface of the second step portion 303 are successively increased, and the top surface of the second step portion 303 is higher than the surface of the substrate 300; a gate oxide layer 310 is located on the surface of the substrate 300 of the active area 30a; a gate layer 400 is located in the active area 30a and covers the gate oxide layer 310, and the gate layer 400 also extends to cover the first step portion 302 and the transition step portion 304; a gate plug 420 is located above the top of the transition step portion 304 and is electrically connected to the gate layer 400.

[0031] In the formation process of the semiconductor structure, before the formation process of the gate plug 420, a process of planarizing the entire wafer (for example, a planarization process of the interlayer dielectric layer and a planarization process of the metal gate layer) is usually included. By setting a transition step portion 304 between the first step portion 302 and the second step portion 303, part of the gate layer 400 can be located on the transition step portion 304. Since the top surfaces of the first step portion 302, the transition step portion 304 and the second step portion 303 are successively increased, that is, compared with the top surface of the second step portion 303, the top surface of the transition step portion 304 is lower. Therefore, in the planarization process, the probability of over-grinding the gate layer 400 located at the top of the transition step portion 304 is low, so that the gate layer 400 located at the top of the transition step portion 304 can be retained, and then the gate plug 420 can be electrically connected to the gate layer 400 located above the top of the transition step portion 304, thereby correspondingly improving the performance of the semiconductor structure.

[0032] In this embodiment, the semiconductor structure is a planar field effect transistor, and the base 300 is a planar substrate.

[0033] In this embodiment, the substrate 300 is a silicon substrate. In other embodiments, the substrate may also be a substrate of other material types. For example, the material of the substrate may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon substrate on an insulator or a germanium substrate on an insulator.

[0034] In this embodiment, the substrate 300 includes an active area 30a, and the isolation structure 301 is located in the substrate 300 and surrounds the active area 30a. Specifically, the substrate 300 includes a device area 300H for forming a device, and the isolation structure 301 is correspondingly located in the substrate 300 of the device area 300H. In the device area 300H, the area surrounded by the isolation structure 301 is the active area 30a.

[0035] In this embodiment, the device area 300H is defined as a first device area 300H, and the first device area 300H is used to form a first device. Specifically, the first device is a high-voltage device. As an example, the operating voltage of the high-voltage device is greater than 10V.

[0036] In this embodiment, the substrate 300 further includes a second device region (not shown) for forming a second device, and the channel length of the first device is greater than the channel length of the second device.

[0037] In this embodiment, the operating voltage of the first device is greater than the operating voltage of the second device, and accordingly, the channel length of the first device is greater than the channel length of the second device. Specifically, the second device is a low-voltage device. As an example, the operating voltage of the low-voltage device is less than 2V.

[0038] The isolation structure 301 is used to achieve isolation between adjacent devices. In this embodiment, the isolation structure 301 is a shallow trench isolation (STI), so that the isolation structure 301 has a good isolation effect.

[0039] In this embodiment, the material of the isolation structure 301 is an insulating material, and the insulating material includes silicon oxide.

[0040] In the present embodiment, in the device area 300H, the isolation structure 301 adjacent to the active area 30a has a stepped top surface, and the isolation structure 301 includes a first step portion 302 facing the active area 30a, a transition step portion 304 whose side wall is connected to the top surface of the first step portion 302, and a second step portion 303 whose side wall is connected to the top surface of the transition step portion 304, and the top surfaces of the first step portion 302, the transition step portion 304 and the second step portion 303 increase in height successively.

[0041] As an example, in the device area 300H, only the isolation structure 301 on one side of the active area 30a includes a first step portion 302, a transition step portion 304, and a second step portion 303 whose top surfaces increase successively, and the isolation structure 301 on the other side of the active area 30a only includes the first step portion 302 and a second step portion 303 whose side wall is connected to the top surface of the first step portion 302.

[0042] It should be noted that, affected by the process, in this embodiment, the top surface of the second step portion 303 is higher than the surface of the substrate 300 .

[0043] Compared with the top surface of the second step portion 303, the top surface of the transition step portion 304 is lower. Therefore, in the planarization process performed after the gate layer 400 is formed, under the blocking effect of the top surface of the second step portion 303, the probability of over-grinding the gate layer 400 located at the top of the transition step portion 304 is low, so that the gate layer 400 located at the top of the transition step portion 304 can be retained, and then the gate plug 420 can be electrically connected to the gate layer 400 located above the top of the transition step portion 304, correspondingly improving the performance of the semiconductor structure. Moreover, in the process of forming the semiconductor structure, after the gate layer 400 is formed, a gate mask layer (for example, a silicon nitride layer) is usually formed on the top of the gate layer 400. The gate mask layer serves as an etching mask when forming the gate layer 400, and in the planarization process (for example: a planarization process for forming an interlayer dielectric layer) performed after the gate layer 400 is formed, the gate mask layer on the top of the gate layer 400 is usually removed. Among them, compared with the top surface of the first step portion 302, the top surface of the transition step portion 304 is higher. Therefore, in the planarization process performed after the gate layer 400 is formed, it is easy to remove the gate mask layer above the top of the transition step portion 304, thereby exposing the top surface of the gate layer 400 located at the top of the transition step portion 304, so as to facilitate the subsequent formation of a gate silicide layer on the top surface of the gate layer 400 located at the top of the transition step portion 304.

[0044] Accordingly, the distance H from the top of the transition step 304 to the top of the second step 303 should not be too small or too large. If the distance H from the top of the transition step 304 to the top of the second step 303 is too small, which results in the gate layer 400 at the top of the transition step 304 being too thin, then in the planarization process after the gate layer 400 is formed, the gate layer 400 at the top of the transition step 304 is more likely to be over-polished, which can easily result in the gate layer 400 at the top of the transition step 304 being too thin in thickness, or even completely removed, thereby affecting the electrical connection reliability between the gate plug 420 and the gate layer 400 at the top of the transition step 304, or even failing to achieve connection; if the distance H from the top of the transition step 304 to the top of the second step 303 is too small, the gate layer 400 at the top of the transition step 304 is too thin in thickness, or even completely removed, thereby affecting the electrical connection reliability between the gate plug 420 and the gate layer 400 at the top of the transition step 304, or even failing to achieve connection; If the distance H from the top of the second step portion 303 to the top of the transition step portion 304 is too large, it is easy to cause the top surface of the gate layer 400 located at the top of the transition step portion 304 to be too low, and correspondingly cause the top surface of the gate mask layer above the top of the transition step portion 304 to be too low. In the planarization process performed after the gate layer 400 is formed, it is easy to cause the gate mask layer above the top of the transition step portion 304 to be unable to be removed. The gate mask layer above the top of the transition step portion 304 covers the gate layer 400, making it difficult to form a gate silicide layer on the top surface of the gate layer 400 above the top of the transition step portion 304, thereby affecting the contact resistance between the gate layer 400 and the gate plug 420, and correspondingly affecting the performance of the semiconductor structure. For this reason, in this embodiment, the distance H from the top of the transition step portion 304 to the top of the second step portion 303 is to For example, the distance H is or

[0045] The gate oxide layer 310 is located on the surface of the substrate 300 in the active area 30a. Specifically, the gate oxide layer 310 is located between the bottom surface of the gate layer 400 in the device area 300H and the substrate 300. The gate oxide layer 310 serves as a gate dielectric layer of the first device and is used to electrically isolate the gate layer 400 from the channel of the first device. In this embodiment, the material of the gate oxide layer 310 is silicon oxide.

[0046] The gate layer 400 is located in the active region 30 a and covers the gate oxide layer 310 . The gate layer 400 also extends to cover the first step portion 302 and the transition step portion 304 .

[0047] The gate layer 400 is used as a device gate structure of the first device, so as to control the opening or closing of the channel of the first device. In this embodiment, the material of the gate layer 400 includes polysilicon, that is, the gate layer 400 is a polysilicon gate layer.

[0048] As the critical dimensions of the device continue to decrease, the preparation of the second device usually adopts metal gate (MG) technology to improve the short channel effect, and in the process of forming the semiconductor structure, a gate-last process is usually adopted to form a metal gate layer, that is, the process of forming the metal gate layer usually includes the step of flattening the metal gate material. Among them, the larger the line width of the metal gate layer, the higher the probability of the top surface of the metal gate layer being sunken during the process of flattening the metal gate material. Since the channel length of the first device is relatively large, the first device is still made to use a polysilicon gate layer, thereby eliminating the step of flattening the metal gate material in the device area 300H, thereby avoiding the top surface sunken problem of the metal gate layer caused by the large line width.

[0049] In this embodiment, the first device uses a polysilicon gate layer and the second device uses a metal gate layer, thereby maintaining the performance of the second device when the critical dimensions of the semiconductor device continue to shrink. At the same time, the formation process of the first device still uses polysilicon gate technology.

[0050] Since a gate last process is usually used to form the metal gate layer of the second device, in this embodiment, the semiconductor structure also includes: a bottom interlayer dielectric layer 340, a substrate 300 located on the side of the gate layer 400, and the bottom interlayer dielectric layer 340 covers the side walls of the gate layer 400 and exposes the top of the gate layer 400.

[0051] The bottom interlayer dielectric layer 340 is used to provide a process platform for forming a metal gate layer of the second device, and is also used to isolate adjacent devices. The material of the bottom interlayer dielectric layer 340 is an insulating material, and the insulating material may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon nitride oxide. In this embodiment, the material of the bottom interlayer dielectric layer 340 is silicon oxide.

[0052] Accordingly, in this embodiment, the semiconductor structure further includes: a top interlayer dielectric layer 350 covering the gate layer 400 and the bottom interlayer dielectric layer 340. The top interlayer dielectric layer 350 is used to provide a process platform for forming the gate plug 420, and is also used to achieve electrical isolation between adjacent devices and adjacent gate plugs 420.

[0053] The material of the top interlayer dielectric layer 350 is an insulating material, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon oxynitride. In this embodiment, the material of the top interlayer dielectric layer 350 is silicon oxide.

[0054] The gate plug 420 penetrates the top interlayer dielectric layer 350 above the top of the transition step 304 and is electrically connected to the gate layer 400. The gate plug 420 is used to achieve electrical connection between the gate layer 400 and an external circuit or other interconnection structure. In this embodiment, the material of the gate plug 420 is tungsten. In other embodiments, the material of the gate plug can also be a conductive material such as cobalt or ruthenium.

[0055] In this embodiment, the semiconductor structure further includes: a gate silicide layer 410 located on the top surface of the gate layer 400 above the transition step portion 304. As an example, the gate silicide layer 410 is also located on the top surface of the gate layer 400 above the gate oxide layer 310.

[0056] In this embodiment, the gate plug 420 is connected to the gate silicide layer 410 located above the transition step 304. The gate silicide layer 410 is used to reduce the gate resistance of the first device and also to reduce the contact resistance between the gate plug 420 and the gate layer 400.

[0057] In this embodiment, the material of the gate silicide layer 410 may include nickel silicon compound, cobalt silicon compound or titanium silicon compound.

[0058] It should be noted that, during the formation process of the semiconductor structure, the gate layer 400 located at the top of the transition step portion 304 can be retained, and the gate mask layer above the top of the transition step portion 304 can be easily removed to expose the top surface of the gate layer 400 located at the top of the transition step portion 304. Therefore, it is easy to form a gate silicide layer 410 on the top surface of the gate layer 400 at the top of the transition step portion 304.

[0059] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure.

[0060] Figures 6 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0061] Combined with reference Figure 6 and Figure 7, providing a substrate 100, including a first active area 10a for forming a first device, an isolation structure 101 surrounding the first active area 10a and having a stepped top surface is formed in the substrate 100, the isolation structure 101 includes a first step portion 102 facing the first active area 10a, and a second step portion 103 whose sidewall is connected to the top surface of the first step portion 102, the top surfaces of the first step portion 102 and the second step portion 103 are successively increased, and the top surface of the second step portion 103 is higher than the surface of the substrate 100, and a first gate oxide layer 110 (such as Figure 7 shown).

[0062] In this embodiment, the forming method is used to form a planar field effect transistor, and therefore, the base 100 is a planar substrate.

[0063] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may also be a substrate of other material types. For example, the material of the substrate may be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate.

[0064] In this embodiment, the substrate 100 includes a first active region 10 a for forming a first device, and the isolation structure 101 is formed in the substrate 100 and surrounds the first active region 10 a.

[0065] Specifically, the substrate 100 includes a first device region 100H for forming the first device, and the isolation structure 101 is correspondingly formed in the substrate 100 in the first device region 100H. In the first device region 100H, the area surrounded by the isolation structure 101 is the first active region 10a.

[0066] In this embodiment, the substrate 100 further includes a second active region 10b for forming a second device, and the channel length of the first device is greater than the channel length of the second device. Specifically, the substrate 100 further includes a second device region 100L for forming the second device, and the isolation structure 101 is correspondingly formed in the substrate 100 of the second device region 100L. In the second device region 100L, the area surrounded by the isolation structure 101 is the second active region 10b.

[0067] In this embodiment, the operating voltage of the first device is greater than the operating voltage of the second device, and accordingly, the channel length of the first device is greater than the channel length of the second device. Specifically, the first device is a high-voltage device, and the second device is a low-voltage device. As an example, the operating voltage of the low-voltage device is less than 2V, and the operating voltage of the high-voltage device is greater than 10V.

[0068] It should be noted that the substrate 100 also includes a third device area (not shown) for forming a third device. The third device is a medium voltage device, and the operating voltage of the medium voltage device is greater than the operating voltage of the low voltage device and less than the operating voltage of the high voltage device.

[0069] The first gate oxide layer 110 is used as a gate dielectric layer of the first device and is used to electrically isolate a subsequently formed gate layer from a channel of the first device. In this embodiment, the material of the first gate oxide layer 110 is silicon oxide.

[0070] In this embodiment, the substrate 100 further includes a second device region 100L, so a second gate oxide layer 115 is formed on the surface of the substrate 100 in the second active region 10b, and the thickness of the second gate oxide layer 115 is less than the thickness of the first gate oxide layer 110. Specifically, the material of the second gate oxide layer 115 is silicon oxide.

[0071] Among them, the second gate oxide layer 115 and the gate oxide layer of the third device area are formed in the same step, that is, the second gate oxide layer 115 is used as the gate oxide layer of the medium voltage device. Therefore, the second gate oxide layer 115 needs to be removed later to prepare for forming the third gate oxide layer of the second device in the second active area 10b.

[0072] In this embodiment, after forming the isolation structure 101, the first gate oxide layer 110 is sequentially formed on the surface of the substrate 100 in the first active area 10a, and the second gate oxide layer 115 is sequentially formed on the surface of the substrate 100 in the second active area 10b.

[0073] The isolation structure 101 is used to achieve isolation between adjacent devices. In this embodiment, the isolation structure 101 is a shallow trench isolation (STI), so that the isolation structure 101 has a good isolation effect.

[0074] In this embodiment, the isolation structure 101 is made of an insulating material, and the insulating material includes silicon oxide.

[0075] It should be noted that, in the step of forming the isolation structure 101 , the top surface of the isolation structure 101 is a plane.

[0076] like Figure 6 As shown, in this embodiment, after forming the isolation structure 101 and before forming the first gate oxide layer 110 , the process further includes: cleaning the surface of the substrate 100 of the first active region 10 a .

[0077] The cleaning process is a pre-cleaning process before forming the first gate oxide layer 110 , so as to provide a good interface state for the subsequent formation of the first gate oxide layer 110 .

[0078] Specifically, before forming the first gate oxide layer 110, it also includes: forming a second mask layer 108 on the substrate 100, the second mask layer 108 exposing the surface of the substrate 100 of the first active area 10a, and a portion of the isolation structure 101 located at the junction of the substrate 100 and the isolation structure 101 in the first active area 10a.

[0079] The second mask layer 108 exposes a portion of the isolation structure 101 at the junction of the substrate 100 and the isolation structure 101 of the first active region 10 a , thereby increasing the process window of the photolithography process during the process of patterning the second mask layer 108 .

[0080] The second mask layer 108 is used to define the area to be cleaned in the substrate 100, and is also used to define the formation area of ​​the first gate oxide layer 110. The second mask layer 108 also covers the second device area 100L, thereby protecting the second device area 100L. In this embodiment, the material of the second mask layer 108 is silicon nitride.

[0081] Accordingly, in this embodiment, the surface of the substrate 100 exposed by the second mask layer 108 is cleaned. Specifically, the cleaning solution of the cleaning process includes a hydrofluoric acid solution. By using the hydrofluoric acid solution, while achieving a cleaning effect, the oxide layer (e.g., a natural oxide layer, etc.) on the surface of the substrate 100 can be removed, exposing the surface of the substrate 100, thereby providing a growth basis for the subsequent formation of the first gate oxide layer 110.

[0082] The material of the isolation structure 101 is silicon oxide. Therefore, during the cleaning process, the partial thickness of the isolation structure 101 exposed by the second mask layer 108 is also removed. That is to say, at the junction of the substrate 100 of the first active area 10a and the isolation structure 101, a partial thickness of the isolation structure 101 is removed, so that the remaining isolation structure 101 forms a first step portion 102 and a second step portion 103.

[0083] Specifically, the side wall of the second step portion 103 is connected to the top surface of the first step portion 102 , the top surface of the second step portion 103 is higher than the top surface of the first step portion 102 , and the top surface of the second step portion 103 is higher than the surface of the substrate 100 .

[0084] In this embodiment, after the first gate oxide layer 110 is formed, the second mask layer 108 is removed.

[0085] After removing the second mask layer 108 , a second gate oxide layer 115 is formed on the surface of the substrate 100 in the second active area 10 b . Before forming the second gate oxide layer 115 , the surface of the substrate 100 in the second active area 10 b is cleaned.

[0086] It should be noted that the process of cleaning the surface of the substrate 100 of the second active area 10b is similar to the process of cleaning the surface of the substrate 100 of the first active area 10a, and the process of forming the second gate oxide layer 115 is similar to the process of forming the first gate oxide layer 110, which will not be repeated in this embodiment.

[0087] refer to Figure 8 , a portion of the second step portion 103 close to the first step portion 102 is etched to form a transition step portion 104, the side wall of the transition step portion 104 is connected to the top surface of the first step portion 102, and the top surface of the transition step portion 104 is higher than the top surface of the first step portion 102.

[0088] The transition step portion 104 is formed to provide a spatial position for the subsequent formation of a gate layer.

[0089] Specifically, in the first device region 100H, after a gate layer covering the first gate oxide layer 110 is subsequently formed, the gate layer also extends to cover the first step portion 102 and the transition step portion 104 .

[0090] Before forming the gate plug, a planarization process (for example, a planarization process of the interlayer dielectric layer and a planarization process of the metal gate layer) is usually included. By setting a transition step portion 104 between the first step portion 102 and the second step portion 103, part of the gate layer can be formed on the transition step portion 104. Since the top surfaces of the first step portion 102, the transition step portion 104 and the second step portion 103 are successively increased, that is, compared with the top surface of the second step portion 103, the top surface of the transition step portion 104 is lower. Therefore, in the planarization process, under the blocking effect of the top surface of the second step portion 103, the probability of over-grinding the gate layer located at the top of the transition step portion 104 is low, so that the gate layer located at the top of the transition step portion 104 can be retained, and then the gate plug can be electrically connected to the gate layer located above the top of the transition step portion 104, thereby correspondingly improving the performance of the semiconductor structure.

[0091] Moreover, after the gate layer is subsequently formed, a gate mask layer (e.g., a silicon nitride layer) is usually formed on the top of the gate layer, and the gate mask layer is used as an etching mask when forming the gate layer, and the gate mask layer on the top of the gate layer is usually removed in a planarization process (e.g., a planarization process for forming an interlayer dielectric layer) performed after the gate layer is formed. The top surface of the transition step portion 104 is higher than the top surface of the first step portion 102, so that it is easy to remove the gate mask layer above the top of the transition step portion 104 in the planarization process after the gate layer is formed, thereby exposing the top surface of the gate layer located at the top of the transition step portion 104, so as to facilitate the subsequent formation of a gate silicide layer on the top surface of the gate layer located at the top of the transition step portion 104.

[0092] Accordingly, the distance H from the top of the transition step 104 to the top of the second step 103 should not be too small or too large. If the distance H from the top of the transition step 104 to the top of the second step 103 is too small, which results in the thickness of the subsequent gate layer at the top of the transition step 104 being too small, then in the planarization process after the gate layer is formed, the probability of over-grinding the gate layer at the top of the transition step 104 is high, which can easily result in the remaining thickness of the gate layer at the top of the transition step 104 being too small or even being completely removed, thereby affecting the reliability of the electrical connection between the subsequent gate plug and the gate layer at the top of the transition step 104, or even making it impossible to achieve connection; if the distance H from the top of the transition step 104 to the top of the second step 103 is too small, the gate layer at the top of the transition step 104 is too small, and the gate layer at the top of the transition step 104 is too small, the gate layer at the top of the transition step 104 is too small, and the gate layer at the top of the transition step 104 is too small. If the distance H from the top of the second step portion 103 is too large, it is easy to cause the top surface of the gate layer located at the top of the transition step portion 104 to be too low, and correspondingly cause the top surface of the gate mask layer above the top of the transition step portion 104 to be too low. In the planarization process after the gate layer is formed, it is easy to cause the gate mask layer above the top of the transition step portion 104 to be unable to be removed. The gate mask layer above the top of the transition step portion 104 covers the gate layer, making it difficult to form a gate silicide layer on the top surface of the gate layer above the top of the transition step portion 104, thereby affecting the contact resistance between the gate layer and the gate plug, and correspondingly affecting the performance of the semiconductor structure. For this reason, in this embodiment, the distance H from the top of the transition step portion 104 to the top of the second step portion 103 is to For example, the distance H is or

[0093] Specifically, the step of etching a portion of the second step portion 103 close to the first step portion 102 includes: forming a first mask layer 120 covering the substrate 100, the first gate oxide layer 110 and a portion of the isolation structure 101 in the first device area 100H, the first mask layer 120 exposing a portion of the top surface of the second step portion 103 close to the first step portion 102; etching the portion of the second step portion 103 exposed by the first mask layer 120 to form a transition step portion 104.

[0094] In this embodiment, a mask opening 125 is formed in the first mask layer 120 , and a sidewall of the mask opening 125 facing the first active region 10 a is flush with a sidewall of the second step portion 103 .

[0095] As an example, the material of the first mask layer 120 is photoresist.

[0096] It should be noted that, in this embodiment, the formation method further includes: removing the second gate oxide layer 115 (such as Figure 6As shown), and in the process of removing the second gate oxide layer 115, a portion of the second step portion 103 close to one side of the first step portion 102 is etched.

[0097] By utilizing the process of removing the second gate oxide layer 115 , a portion of the second step portion 103 close to the first step portion 102 is etched, thereby simplifying the process steps, making little change to the current process, and having high process compatibility.

[0098] Among them, since the operating voltage of the second device is relatively small, the target thickness of the gate dielectric layer of the second device is correspondingly small. Therefore, by removing the second gate oxide layer 115, preparation is made for the subsequent formation of a third gate oxide layer with a smaller thickness on the surface of the substrate 100 of the second active area 10b.

[0099] In this embodiment, a wet etching process is used to etch a portion of the second step portion 103 near the first step portion 102 and remove the second gate oxide layer 115. The wet etching process is advantageous for completely removing the second gate oxide layer 115. Moreover, the wet etching process has a faster etching rate.

[0100] In this embodiment, the material of the isolation structure 101 is silicon oxide, and the etching solution used in the wet etching process is a hydrofluoric acid solution.

[0101] A mask opening 125 is formed in the first mask layer 120, and the mask opening 125 is used to define the area to be etched in the second step portion 103. Therefore, under the action of the first mask layer 120, even if a wet etching process is used, it is still easy to control the morphology of the transition step portion 104.

[0102] As an example, in the first device region 100H, only the second step portion 103 corresponding to the subsequent formation position of the gate plug is etched, that is, only the isolation structure 101 on one side of the first active region 10a includes the first step portion 102, the transition step portion 104, and the second step portion 103 with the top surfaces increasing in sequence, and the second step portion 103 on the other side of the first active region 10a is not etched. In other embodiments, the second step portions on both sides of the first active region may also be etched, and accordingly, the isolation structures on both sides of the first active region contain the transition step portion.

[0103] Combined with reference Fig. 9 , Fig. 9 Only the first device region is illustrated. In this embodiment, after the transition step portion 104 is formed, the process further includes: removing the first mask layer 120 .

[0104] Specifically, the material of the first mask layer 120 is photoresist, and an ashing process is adopted to remove the first mask layer 120 .

[0105] It should be noted that, unless otherwise specified, only the schematic diagram of the first device area will be illustrated below.

[0106] It should be noted that after removing the first mask layer 120, the method further includes: forming a third gate oxide layer (not shown) on the surface of the substrate 100 in the second active region 10b. The specific description of the step of forming the third gate oxide layer is omitted in this embodiment.

[0107] refer to Fig.10 In the first active region 10 a , a gate layer 200 is formed to cover the first gate oxide layer 110 , and the gate layer 200 also extends to cover the first step portion 102 and the transition step portion 104 .

[0108] The gate layer 200 is used as a device gate structure of the first device, so as to control the opening or closing of the channel of the first device. In this embodiment, the material of the gate layer 200 includes polysilicon, that is, the gate layer 200 is a polysilicon gate layer.

[0109] Specifically, the gate layer 200 is formed in the first device region 100H by sequentially adopting a deposition process and an etching process. As an example, in the step of forming the gate layer 200 , the gate layer 200 also extends to cover a portion of the top of the second step portion 103 .

[0110] In this embodiment, in the step of forming the gate layer 200, the gate layer 200 is also formed on the substrate 100 of the second active region 10b. Specifically, the gate layer 200 is formed on the third gate oxide layer (not shown) of the second device region 100L.

[0111] refer to Fig.11 After forming the gate layer 200 , the method further includes: forming a bottom interlayer dielectric layer 140 on the substrate 100 at the side of the gate layer 200 , wherein the bottom interlayer dielectric layer 140 covers the side wall of the gate layer 200 and exposes the top of the gate layer 200 .

[0112] The bottom interlayer dielectric layer 140 is used to isolate adjacent devices and also to provide a process platform for subsequently forming a metal gate layer in the second device region 100L. The material of the bottom interlayer dielectric layer 140 is an insulating material, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbon nitride oxide. In this embodiment, the material of the bottom interlayer dielectric layer 140 is silicon oxide.

[0113] In this embodiment, a deposition process and a planarization process (for example, a chemical mechanical polishing process) are used to form the bottom interlayer dielectric layer 140. Specifically, the step of forming the bottom interlayer dielectric layer 140 includes: forming a dielectric material layer covering the substrate 100 and the gate layer 200 by a deposition process; and planarizing the dielectric material layer until the top of the gate layer 200 is exposed.

[0114] It should be noted that, since the thickness of the third gate oxide layer (not shown) is less than the thickness of the first gate oxide layer 110, the top of the gate layer 200 of the first device area 100H is usually higher than the top of the gate layer 200 of the second device area 100L. In the process of planarizing the dielectric material layer, the top of the gate layer 200 of the first device area 100H is exposed earlier, so the probability of the gate layer 200 of the first device area 100H being over-polished is higher. Moreover, since the channel length of the first device is greater than the channel length of the second device, the line width of the gate layer 200 of the first device area 100H is correspondingly larger. Therefore, in the process of planarizing the dielectric material layer, the polishing rate of the gate layer 200 of the first device area 100H is faster than that of the second device area 100L, so it is easy to cause the gate layer 200 of the first device area 100H to be polished and removed. As an example, after the bottom interlayer dielectric layer 140 is formed, the top of the remaining gate layer 200 in the first device region 100H is still higher than the second step portion 103 .

[0115] It should be noted that after forming the bottom interlayer dielectric layer 140, the process also includes: removing the gate layer 200 of the second device region 100L, forming a gate opening (not shown) in the bottom interlayer dielectric layer 140; and forming a metal gate layer (not shown) in the gate opening.

[0116] The metal gate layer is used to form a metal gate structure. Since the operating voltage of the second device is relatively small, as the critical dimensions of the device continue to shrink, the use of a metal gate structure is conducive to improving the short channel effect. Moreover, in this embodiment, the first device uses a polysilicon gate layer and the second device uses a metal gate layer, so that the performance of the second device is maintained when the critical dimensions of the semiconductor device continue to shrink, and at the same time, the formation process of the first device still uses polysilicon gate technology.

[0117] Specifically, the step of forming a metal gate layer includes: filling a metal gate material layer (not shown) into the gate opening, wherein the metal gate material layer also covers the top of the bottom interlayer dielectric layer 140; performing a planarization process (e.g., chemical mechanical polishing process) on the metal gate material layer, removing the metal gate material layer that is higher than the top of the bottom interlayer dielectric layer 140, and making the height of the remaining metal gate material layer in the gate opening reach a preset value, and the remaining metal gate material layer after the planarization process serves as the metal gate layer.

[0118] It should be noted that, in the process of planarizing the metal gate material layer, it is also easy to cause loss to the gate layer 200 of the second device area 100H, thereby reducing the thickness of the gate layer 200 of the second device area 100H. In particular, the channel length of the first device is greater than the channel length of the second device, and the line width of the gate layer 200 of the first device area 100H is correspondingly larger. Therefore, in the process of planarizing the metal gate material layer, the grinding rate of the gate layer 200 of the first device area 100H is faster.

[0119] As an example, after the metal gate layer is formed, the top of the gate layer 200 of the first device region 100H is flush with the top of the second step portion 103 .

[0120] It should also be noted that since the top surface of the transition step portion 104 is lower than the top surface of the second step portion 103, during the planarization process of the metal gate material layer, due to the blocking effect of the top surface of the second step portion 103, the probability of over-grinding the gate layer 200 located at the top of the transition step portion 104 is low, thereby allowing the gate layer 200 located at the top of the transition step portion 104 to be retained.

[0121] In addition, before filling the metal gate material layer into the gate opening, the steps of conformally covering the bottom and sidewalls of the gate opening with a high-k gate dielectric layer (not shown) and a work function layer are also included. This embodiment will not be repeated here.

[0122] refer to Fig.12 After forming the metal gate layer, the forming method further includes: forming a gate silicide layer 210 on the top surface of the gate layer 200 , wherein the gate silicide layer 210 is located above the top of the transition step portion 104 .

[0123] The gate silicide layer 210 is used to reduce the gate resistance of the first device and also to reduce the contact resistance between the gate layer 200 and the gate plug formed subsequently. The gate layer 200 located at the top of the transition step portion 104 can be retained, and the gate mask layer above the top of the transition step portion 104 can be easily removed to expose the top surface of the gate layer 200 located at the top of the transition step portion 104. Therefore, it is easy to form the gate silicide layer 210 on the top surface of the gate layer 200 at the top of the transition step portion 104.

[0124] As an example, the gate silicide layer 210 is also located above the top of the first gate oxide layer 110 in the first active region 10 a.

[0125] In this embodiment, the material of the gate silicide layer 210 may include nickel silicon compound, cobalt silicon compound or titanium silicon compound. Specifically, the gate silicide layer 210 is formed by a self-aligned silicide process.

[0126] Therefore, in this embodiment, before forming the gate silicide layer 210, a step of forming a salicide block (SAB) layer (not shown) is further included. By forming the silicide block layer, the region for forming the gate silicide layer 210 is exposed, and the region where the gate silicide layer 210 is not desired to be formed is protected.

[0127] It should be noted that, in this embodiment, the gate silicide layer 210 is formed after the metal gate layer is formed. That is, before the metal gate layer is formed, the gate silicide layer 210 is not formed on the top surface of the gate layer 200, so that the problem of metal contamination can be avoided during the planarization process of the metal gate material layer.

[0128] refer to Fig.13 After forming the gate silicide layer 210 , a top interlayer dielectric layer 150 is formed to cover the gate layer 200 and the bottom interlayer dielectric layer 140 .

[0129] The top interlayer dielectric layer 150 is used to provide a process platform for the subsequent formation of gate plugs, and is also used to achieve electrical isolation between adjacent devices and adjacent gate plugs.

[0130] The material of the top interlayer dielectric layer 150 is an insulating material, which may include one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride and silicon carbon nitride oxide. In this embodiment, the material of the top interlayer dielectric layer 150 is silicon oxide.

[0131] In this embodiment, the top interlayer dielectric layer 150 also covers the gate silicide layer 210 .

[0132] refer to Fig.14 A gate plug 220 electrically connected to the gate layer 200 is formed above the top of the transition step portion 104 .

[0133] The gate plug 220 is used to realize electrical connection between the gate layer 200 and an external circuit or other interconnection structures.

[0134] In this embodiment, the gate plug 220 penetrates the top interlayer dielectric layer 150 above the top of the transition step portion 104 , and is connected to the gate silicide layer 210 located above the top of the transition step portion 104 .

[0135] Specifically, the steps of forming the gate plug 220 include: etching the top interlayer dielectric layer 150 above the top of the transition step portion 104 to form a contact hole (not shown) that penetrates the top interlayer dielectric layer 150 and exposes the top of the gate silicide layer 210; filling the contact hole with a conductive material; and planarizing the conductive material (for example, chemical mechanical polishing) to remove the conductive material above the top of the top interlayer dielectric layer 150, and retaining the remaining conductive material in the contact hole as the gate plug 220.

[0136] In this embodiment, the gate plug 220 is made of tungsten. In other embodiments, the gate plug may be made of a conductive material such as cobalt or ruthenium.

[0137] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: a substrate, including an active region; an isolation structure, located in the substrate and surrounding the active area, wherein the top surface of the isolation structure adjacent to the active area is in a step shape, the isolation structure comprising a first step portion facing the active area, a transition step portion whose sidewall is connected to the top surface of the first step portion, and a second step portion whose sidewall is connected to the top surface of the transition step portion, wherein the top surfaces of the first step portion, the transition step portion, and the second step portion are successively increased in height, and the top surface of the second step portion is higher than the substrate surface; A gate oxide layer, located on the substrate surface of the active area; A gate layer, located in the active area and covering the gate oxide layer, wherein the gate layer also extends to cover the first step portion and the transition step portion; The gate plug is located above the top of the transition step portion and is electrically connected to the gate layer.

2. The semiconductor structure according to claim 1, wherein: The material of the gate layer includes polysilicon.

3. The semiconductor structure according to claim 1 or 2, characterized in that: The semiconductor structure further comprises: a bottom interlayer dielectric layer, located on the substrate at the side of the gate layer, the bottom interlayer dielectric layer covering the sidewall of the gate layer; a top interlayer dielectric layer, covering the gate layer and the bottom interlayer dielectric layer; The gate plug penetrates the top interlayer dielectric layer above the top of the transition step portion.

4. The semiconductor structure according to claim 2, wherein: The semiconductor structure further comprises: a gate silicide layer located on a top surface of the gate layer above the transition step portion; The gate plug is connected to the gate silicide layer located above the transition step portion.

5. The semiconductor structure according to claim 1, wherein: The distance from the top of the transition step portion to the top of the second step portion is to 6. The semiconductor structure according to claim 1, wherein: The active area is used to form a high-voltage device, and the operating voltage of the high-voltage device is greater than 10V.

7. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, including a first active region for forming a first device, wherein an isolation structure surrounding the first active region and having a stepped top surface is formed in the substrate, wherein the isolation structure includes a first step portion facing the first active region, and a second step portion having a sidewall connected to the top surface of the first step portion, wherein the top surfaces of the first step portion and the second step portion are successively increased in height, and the top surface of the second step portion is higher than the surface of the substrate, and a first gate oxide layer is formed on the surface of the substrate of the first active region; Etching a portion of the second step portion close to one side of the first step portion to form a transition step portion, wherein a side wall of the transition step portion is connected to a top surface of the first step portion, and a top surface of the transition step portion is higher than a top surface of the first step portion; In the first active region, a gate layer covering the first gate oxide layer is formed, wherein the gate layer also extends to cover the first step portion and the transition step portion; A gate plug electrically connected to the gate layer is formed on a top of the transition step portion.

8. The method for forming a semiconductor structure according to claim 7, wherein: The material of the gate layer includes polysilicon.

9. The method for forming a semiconductor structure according to claim 7, wherein: In the step of providing a substrate, the substrate further includes a second active area for forming a second device, an operating voltage of the first device is greater than an operating voltage of the second device, a second gate oxide layer is formed on a surface of the substrate of the second active area, and a thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer; Before forming the gate layer, the forming method further comprises: removing the second gate oxide layer; In the process of removing the second gate oxide layer, a portion of the second step portion close to one side of the first step portion is etched.

10. The method for forming a semiconductor structure according to claim 7, wherein: The step of etching a portion of the second step portion close to one side of the first step portion comprises: forming a first mask layer covering the substrate, the first gate oxide layer and a portion of the isolation structure, wherein the first mask layer exposes a portion of the top surface of the second step portion close to a side of the first step portion; Etching a portion of the thickness of the second step portion exposed by the first mask layer to form a transition step portion; After forming the transition step portion, the first mask layer is removed.

11. The method for forming a semiconductor structure according to claim 7 or 8, characterized in that: Before forming the gate plug, the forming method further comprises: forming a bottom interlayer dielectric layer on the substrate at the side of the gate layer, wherein the bottom interlayer dielectric layer covers the side wall of the gate layer; forming a top interlayer dielectric layer covering the gate layer and the bottom interlayer dielectric layer; In the step of forming the gate plug, the gate plug penetrates the top interlayer dielectric layer above the top of the transition step portion.

12. The method for forming a semiconductor structure according to claim 11, wherein: The material of the gate layer includes polysilicon; Before forming the top interlayer dielectric layer, the forming method further comprises: forming a gate silicide layer on the top surface of the gate layer, wherein the gate silicide layer is located above the transition step portion; In the step of forming the gate plug, the gate plug is connected to the gate silicide layer located above the transition step portion.

13. The method for forming a semiconductor structure according to claim 7, wherein: In the step of etching a portion of the second step portion close to one side of the first step portion, the distance from the top of the transition step portion to the top of the second step portion is to 14. The method for forming a semiconductor structure according to claim 7, wherein: A wet etching process is used to etch a portion of the second step portion close to one side of the first step portion.

15. The method for forming a semiconductor structure according to claim 14, wherein: The material of the isolation structure is silicon oxide; the etching solution used in the wet etching process is hydrofluoric acid solution.

16. The method for forming a semiconductor structure according to claim 7, wherein: After forming the isolation structure, forming the first gate oxide layer; Before forming the first gate oxide layer, the method further includes: forming a second mask layer on the substrate, wherein the second mask layer exposes the substrate surface of the first active region and a portion of the isolation structure located at a junction of the substrate of the first active region and the isolation structure; The surface of the substrate exposed by the second mask layer is cleaned, wherein during the cleaning process, a portion of the thickness of the isolation structure exposed by the second mask layer is removed, so that the isolation structure forms a first step portion and a second step portion.

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