Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: a substrate having a plurality of mutually discrete fins on the substrate, the fins extending along a first direction, the fins including an edge region and a middle region along the first direction, the fins including a first region and a second region located on the first region, the sidewalls of the first region being recessed relative to the sidewalls of the second region; an isolation layer located on the substrate; a first gate structure spanning the edge region; and a source-drain doping layer located within the fins. When the isolation layer is subsequently damaged, since the sidewalls of the first region are recessed relative to the sidewalls of the second region, the isolation layer is not likely to expose the sidewalls of the first region, thereby effectively reducing the problem of leakage. In addition, since the sidewalls of the first region are recessed relative to the sidewalls of the second region, the size difference between the first region and the second region along the first direction is small, and when the first gate structure is subsequently turned on, the mobility of carriers is effectively improved, thereby improving the performance of the semiconductor structure finally formed.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] With the development trend of high density integrated circuits, the devices that make up the circuit are placed more closely in the chip to fit the available space of the chip. Correspondingly, the density of active devices per unit area of ​​the semiconductor substrate continues to increase, so effective insulation isolation between devices becomes more important.

[0003] Shallow Trench Isolation (STI) technology has good isolation effects (such as process isolation and electrical isolation), and also has the advantages of reducing the area occupied by the wafer surface and increasing the integration of devices. Therefore, as the size of integrated circuits decreases, the isolation between active areas of devices is mainly done by using shallow trench isolation layers.

[0004] However, the isolation layer formed by the prior art easily leads to a decrease in the electrical performance of the semiconductor device. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

[0006] To solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate having a plurality of mutually discrete fins, the fins extending along a first direction, the fins including edge regions and intermediate regions between the edge regions along the first direction, the fins including a first region and a second region located on the first region, the sidewalls of the first region being recessed relative to the sidewalls of the second region; an isolation layer located on the substrate, the isolation layer covering a portion of the first region, and a top surface of the isolation layer being lower than a top surface of the fins; a first gate structure spanning the edge region, a portion of the first gate structure being located on a portion of the sidewalls and top surface of the fins, and a portion of the first gate structure being located on a portion of the surface of the isolation layer; and a source-drain doped layer located in the fins, the source-drain doped layer being located on one side of the first gate structure.

[0007] Optionally, the material of the isolation layer includes silicon oxide.

[0008] Optionally, the method further includes: a dielectric layer located on the substrate, wherein the dielectric layer covers the sidewalls of the first gate structure.

[0009] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate having a plurality of mutually discrete fins, the fins extending along a first direction, the fins including an edge region and an intermediate region located between the edge regions along the first direction, the fins including an initial first region and a second region located on the initial first region; removing part of the initial first region to form a first region, the sidewalls of the first region being recessed relative to the sidewalls of the second region; forming an isolation layer on the substrate, the isolation layer covering part of the first region, and the top surface of the isolation layer being lower than the top surface of the fin; forming a first gate structure spanning the edge region, part of the first gate structure being located on part of the sidewalls and top surface of the fin, and part of the first gate structure being located on part of the surface of the isolation layer; forming a source-drain doping layer in the fin, the source-drain doping layer being located on one side of the first gate structure.

[0010] Optionally, the method for removing part of the initial first region includes: forming a protective layer on the sidewalls and top surface of the second region; after forming the protective layer, using an etching process to remove part of the initial first region to form the first region.

[0011] Optionally, the etching process includes an isotropic wet etching process.

[0012] Optionally, the material of the protective layer includes organic material.

[0013] Optionally, the method for forming the protective layer includes: a chemical vapor deposition process and a physical vapor deposition process.

[0014] Optionally, the method for forming the isolation layer includes: forming an initial isolation layer on the substrate, the initial isolation layer covering the fin; etching back the initial isolation layer to form the isolation layer, the isolation layer covering a portion of the first region, and the top surface of the isolation layer is lower than the top surface of the fin.

[0015] Optionally, the material of the isolation layer includes silicon oxide.

[0016] Optionally, the initial isolation layer forming process includes: a fluid chemical vapor deposition process.

[0017] Optionally, before forming the gate structure, the method further includes: forming a plurality of first dummy gate structures on the isolation layer, wherein the first dummy gate structures span the edge region of the fin and cover a portion of the sidewalls and the top surface of the fin.

[0018] Optionally, the method for forming the source-drain doped layer includes: etching the fin using the first dummy gate structure as a mask to form a source-drain opening in the fin; and forming the source-drain doped layer in the source-drain opening.

[0019] Optionally, the method for forming the source-drain doped layer in the source-drain opening includes: forming an epitaxial layer in the source-drain opening using an epitaxial growth process; and in the process of forming the epitaxial layer, doping the source-drain ions into the epitaxial layer using an in-situ doping process to form the source-drain doped layer.

[0020] Optionally, after forming the first dummy gate structure, the method further includes: forming a dielectric layer on the substrate, wherein the dielectric layer covers a side wall of the first dummy gate structure.

[0021] Optionally, the method for forming the dielectric layer includes: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first dummy gate structure; and planarizing the initial dielectric layer until the top surface of the first dummy gate structure is exposed to form the dielectric layer.

[0022] Optionally, the method for forming the first gate structure includes: removing the first dummy gate structure, forming a gate opening in the dielectric layer; and forming the first gate structure in the gate opening.

[0023] Optionally, the first dummy gate structure includes: a first dummy gate dielectric layer and a first dummy gate layer located on the first dummy gate dielectric layer.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the structure of the technical solution of the present invention, when the isolation layer is damaged later, since the sidewall of the first region is recessed relative to the sidewall of the second region, the isolation layer is not likely to expose the sidewall of the first region, thereby effectively reducing the leakage problem. In addition, since the sidewall of the first region is recessed relative to the sidewall of the second region, the size difference between the first region and the second region along the first direction is small, and when the first gate structure is turned on later, the mobility of the carriers is effectively improved, thereby improving the performance of the finally formed semiconductor structure.

[0026] In the formation method of the technical solution of the present invention, a portion of the initial first region is removed to form a first region, and the sidewall of the first region is recessed relative to the sidewall of the second region. When the isolation layer is subsequently damaged, since the sidewall of the first region is recessed relative to the sidewall of the second region, the isolation layer is not likely to expose the sidewall of the first region, thereby effectively reducing the leakage problem. In addition, since the sidewall of the first region is recessed relative to the sidewall of the second region, the size difference between the first region and the second region along the first direction is small, and when the first gate structure is subsequently turned on, the mobility of the carriers is effectively improved, thereby improving the performance of the semiconductor structure finally formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 to Figure 2 It is a schematic diagram of the structure of a semiconductor structure;

[0028] Figures 3 to 11 It is a schematic diagram of the structures of each step of an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0029] As described in the background art, the isolation layer formed in the prior art easily leads to the degradation of the electrical performance of the semiconductor device.

[0030] Please refer to Figure 1 , providing a substrate 100, on which a plurality of mutually discrete fins 101 are provided, the fins 101 extending along a first direction X, the fins 101 including edge regions A1 and intermediate regions B1 located between the edge regions A1 along the first direction X, the fins 101 including a first region I and a second region II located on the first region I; forming an isolation layer 102 on the substrate 100, the isolation layer 102 covering a portion of the sidewalls of the fins 101, and a top surface of the isolation layer 102 being lower than a top surface of the fins 101; forming a plurality of dummy gate structures 103 on the substrate 100, the dummy gate structures 103 spanning the edge regions A1 of the fins 101, and the dummy gate structures 103 covering a portion of the sidewalls and the top surface of the fins 101; etching the fins 101 using the dummy gate structures 103 as masks to form source and drain openings in the fins 101; forming a source and drain doping layer 104 in the source and drain openings.

[0031] Please refer to Figure 2 , forming a dielectric layer 105 on the substrate 100, wherein the dielectric layer 105 covers the dummy gate structure 103; removing the dummy gate structure 103, forming a gate opening in the dielectric layer 105; and forming a gate structure 106 in the gate opening.

[0032] In this embodiment, due to the limitation of the manufacturing process, the sidewall of the formed fin 101 is inclined, that is, in the direction along which the fin 101 extends, the length dimension d1 of the first region I is greater than the length dimension d2 of the second region II. In the process of etching the fin 101 to form the source and drain openings, the solution etching the fin 101 will also cause certain damage to the isolation layer 102. Since the length dimension d1 of the first region I is relatively large, the sidewall of the first region I of the isolation layer 102 is easily exposed by the damaged interlayer, which can easily cause leakage problems. In addition, in the process of etching back to form the isolation layer 102 and in the process of removing the pseudo gate structure 103, etching will also cause certain damage to the sidewall of the second region II, which will further increase the difference between the length dimension d2 of the second region II and the length dimension d1 of the first region. When the gate structure 106 is turned on later, it will affect the mobility of the carriers, thereby reducing the performance of the semiconductor structure finally formed.

[0033] On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein a portion of the initial first region is removed to form a first region, wherein the sidewalls of the first region are recessed relative to the sidewalls of the second region. When the isolation layer is subsequently damaged, since the sidewalls of the first region are recessed relative to the sidewalls of the second region, the isolation layer is not likely to expose the sidewalls of the first region, thereby effectively reducing the leakage problem. In addition, since the sidewalls of the first region are recessed relative to the sidewalls of the second region, the size difference between the first region and the second region along the first direction is small, and when the first gate structure is subsequently turned on, the mobility of the carriers is effectively improved, thereby improving the performance of the semiconductor structure finally formed.

[0034] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 3 to 11 It is a structural schematic diagram of a formation process of a semiconductor structure according to an embodiment of the present invention.

[0036] Please refer to Figure 3 A substrate 200 is provided, wherein the substrate 200 has a plurality of mutually discrete fins 201, wherein the fins 201 extend along a first direction X, wherein the fins 201 include edge regions A1 and intermediate regions B1 located between the edge regions A1 along the first direction X, and wherein the fins 201 include an initial first region I' and a second region II located on the initial first region I'.

[0037] In this embodiment, the method for forming the substrate 200 and the fin 201 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate, wherein the patterned layer exposes a portion of the top surface of the initial substrate; etching the initial substrate using the patterned layer as a mask to form the substrate 200 and the fin 201; after forming the substrate 200 and the fin 201, removing the patterned layer.

[0038] In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0039] In this embodiment, the material of the fin 201 is silicon; in other embodiments, the material of the fin may also be germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

[0040] After providing the substrate 200, the method further includes: removing part of the initial first region I' to form a first region, wherein the sidewall of the first region is recessed relative to the sidewall of the second region II. Figures 4 to 5 .

[0041] Please refer to Figure 4 , a protection layer 202 is formed on the sidewalls and top surface of the second region II.

[0042] In this embodiment, the method for forming the protection layer 202 includes: a chemical vapor deposition process and a physical vapor deposition process.

[0043] In this embodiment, the material of the protection layer 202 is an organic material, such as a carbon-containing polymer material.

[0044] The protective layer 202 is formed on the second region II to avoid damage to the sidewall of the second region II when etching part of the initial first region I' later.

[0045] Please refer to Figure 5 After forming the protection layer 202, an etching process is used to remove part of the initial first region I' to form the first region I.

[0046] In this embodiment, the etching process adopts an isotropic wet etching process.

[0047] In this embodiment, after the first region I is formed, the protection layer 202 is removed.

[0048] Please refer to Figure 6After forming the first region I, an isolation layer 203 is formed on the substrate 200 , wherein the isolation layer 203 covers a portion of the first region I, and a top surface of the isolation layer 203 is lower than a top surface of the fin 201 .

[0049] In this embodiment, the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200, wherein the initial isolation layer covers the fin 201; etching back the initial isolation layer to form the isolation layer 203, wherein the isolation layer 203 covers a portion of the first region I, and the top surface of the isolation layer 203 is lower than the top surface of the fin 201.

[0050] In this embodiment, the isolation layer 203 is made of silicon oxide.

[0051] In this embodiment, the initial isolation layer forming process includes: a fluid chemical vapor deposition process.

[0052] After forming the isolation layer 203, the method further includes: forming a first gate structure across the edge area A1, wherein part of the first gate structure is located on part of the sidewall and top surface of the fin 201, and part of the first gate structure is located on part of the isolation layer 203 surface; forming a source-drain doped layer in the fin 201, wherein the source-drain doped layer is located on one side of the first gate structure. For the specific formation process, please refer to Figures 7 to 11 .

[0053] Please refer to Figure 7 , a plurality of first dummy gate structures 204 are formed on the isolation layer 203 , wherein the first dummy gate structures 204 span the edge region A1 of the fin 201 , and the first dummy gate structures 204 cover a portion of the sidewalls and the top surface of the fin 201 .

[0054] In this embodiment, the first dummy gate structure 204 includes: a first dummy gate dielectric layer and a first dummy gate layer (not shown) located on the first dummy gate dielectric layer.

[0055] In this embodiment, the process of forming the first dummy gate structure 204 also includes: forming a plurality of second dummy gate structures 205 on the isolation layer 203, the second dummy gate structure 205 spanning the middle area B1 of the fin 201, and the second dummy gate structure 205 covering part of the sidewalls and top surface of the fin 201.

[0056] Please continue to refer to Figure 7 After forming the first dummy gate structure 204 and the second dummy gate structure 205 , a first spacer 206 is formed on the sidewall of the first dummy gate structure 204 ; and a second spacer 207 is formed on the sidewall of the second dummy gate structure 205 .

[0057] In this embodiment, the method for forming the first side wall 206 and the second side wall 207 includes: forming a side wall material layer (not shown) on the side walls and top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205, and the top surface of the isolation layer 203; and etching back the side wall material layer until the first dummy gate structure 204, the second dummy gate structure 205 and the top surface of the isolation layer 203 are exposed, thereby forming the first side wall 206 and the second side wall 207.

[0058] In this embodiment, the material of the spacer material layer is silicon nitride.

[0059] Please refer to Figure 8 , the fin 201 is etched using the first dummy gate structure 204 as a mask to form source and drain openings 208 in the fin 201 .

[0060] In this embodiment, the method further includes: etching the fin 201 using the second dummy gate structure 205 as a mask to form the source / drain opening 208 in the fin 201 .

[0061] Since the isolation layer 203 will be damaged during the etching of the fin 201 , the isolation layer 203 is likely to expose the sidewall of the first region I, thereby causing a leakage problem.

[0062] In this embodiment, a first region I is formed by removing part of the initial first region I', and the sidewall of the first region I is recessed relative to the sidewall of the second region II. When the isolation layer 203 is damaged, since the sidewall of the first region I is recessed relative to the sidewall of the second region II, the isolation layer 203 is not likely to expose the sidewall of the first region I, thereby effectively reducing the leakage problem.

[0063] Please refer to Fig. 9 , the source-drain doping layer 209 is formed in the source-drain opening 208 .

[0064] In this embodiment, the method for forming the source-drain doped layer 209 in the source-drain opening 208 includes: forming an epitaxial layer (not shown) in the source-drain opening 208 by using an epitaxial growth process; and in the process of forming the epitaxial layer, doping the source-drain ions into the epitaxial layer by using an in-situ doping process to form the source-drain doped layer 209.

[0065] Please refer to Fig.10 After forming the first dummy gate structure 204 , a dielectric layer 210 is formed on the substrate 200 , and the dielectric layer 210 covers the sidewalls of the first dummy gate structure 204 .

[0066] In this embodiment, the method for forming the dielectric layer 210 includes: forming an initial dielectric layer (not shown) on the substrate 200, wherein the initial dielectric layer covers the first pseudo gate structure 204; and planarizing the initial dielectric layer until the top surface of the first pseudo gate structure 204 is exposed to form the dielectric layer 210.

[0067] In this embodiment, the material of the dielectric layer 210 is silicon oxide; in other embodiments, the material of the dielectric layer can also be a low-K dielectric material (a low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-K dielectric material (an ultra-low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 2.5).

[0068] Please refer to Fig.11 , removing the first dummy gate structure 204, forming a gate opening in the dielectric layer 210; and forming the first gate structure 211 in the gate opening.

[0069] In this embodiment, the process of forming the first gate structure 204 further includes: removing the second dummy gate structure 205 to form a gate opening in the dielectric layer 210; and forming the second gate structure 212 in the gate opening.

[0070] Since the side wall of the second region II will be damaged when the first pseudo gate dielectric layer of the first pseudo gate structure 211 is etched during the process of removing the first pseudo gate structure 211, a size difference will exist between the first region I and the second region II in the extension direction of the fin 201, thereby affecting the mobility of the carriers and reducing the performance of the finally formed semiconductor structure.

[0071] In this embodiment, since the sidewalls of the first region I are recessed relative to the sidewalls of the second region II, the size difference between the first region I and the second region II along the first direction X is small. When the first gate structure 204 is subsequently turned on, the mobility of the carriers is effectively improved, thereby improving the performance of the finally formed semiconductor structure.

[0072] Accordingly, the present invention also provides a semiconductor structure, please continue to refer to Fig.11, comprising: a substrate 200, on which a plurality of mutually discrete fins 201 are disposed, the fins 201 extending along a first direction X, the fins 201 along the first direction X including an edge region A1 and an intermediate region B1 located between the edge regions A1, the fins 201 including a first region I and a second region II located on the first region I, the sidewalls of the first region I being recessed relative to the sidewalls of the second region II; an isolation layer 203 located on the substrate 200, the isolation layer 203 covering a portion of the first region I, and a top surface of the isolation layer 203 being lower than a top surface of the fins 201; a first gate structure 211 spanning the edge region A1, a portion of the first gate structure 211 being located on a portion of the sidewalls and top surface of the fins 201, and a portion of the first gate structure 211 being located on a portion of the surface of the isolation layer 203; a source-drain doped layer 209 located in the fins 201, the source-drain doped layer 209 being located on one side of the first gate structure 211.

[0073] In this embodiment, when the isolation layer 203 is damaged, since the sidewall of the first region I is recessed relative to the sidewall of the second region II, the isolation layer 203 is not likely to expose the sidewall of the first region I, thereby effectively reducing the leakage problem. In addition, since the sidewall of the first region I is recessed relative to the sidewall of the second region II, the size difference between the first region I and the second region II along the first direction X is small, and when the first gate structure 211 is subsequently turned on, the mobility of the carriers is effectively improved, thereby improving the performance of the finally formed semiconductor structure.

[0074] In this embodiment, the material of the isolation layer 203 includes silicon oxide.

[0075] In this embodiment, the present invention further includes: a dielectric layer 210 located on the substrate 200 , and the dielectric layer 210 covers the sidewalls of the first gate structure 211 .

[0076] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate having a plurality of mutually separated fins thereon, the fins extending along a first direction, the fins including edge regions and middle regions between the edge regions along the first direction, the fins including a first region and a second region located on the first region, and a sidewall of the first region being recessed relative to a sidewall of the second region; an isolation layer located on the substrate, the isolation layer covering a portion of the first region, and a top surface of the isolation layer being lower than a top surface of the fin; A first gate structure spanning the edge region, a portion of the first gate structure being located on a portion of the sidewall and top surface of the fin, and a portion of the first gate structure being located on a portion of the isolation layer surface; A source-drain doped layer is located in the fin portion, and the source-drain doped layer is located on one side of the first gate structure.

2. The semiconductor structure according to claim 1, wherein: The material of the isolation layer includes silicon oxide.

3. The semiconductor structure according to claim 1, wherein: Also includes: A dielectric layer is located on the substrate, and the dielectric layer covers the sidewalls of the first gate structure.

4. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having a plurality of mutually separated fins, the fins extending along a first direction, the fins including edge regions and middle regions located between the edge regions along the first direction, the fins including an initial first region and a second region located on the initial first region; removing a portion of the initial first region to form a first region, wherein a sidewall of the first region is recessed relative to a sidewall of the second region; forming an isolation layer on the substrate, wherein the isolation layer covers a portion of the first region, and a top surface of the isolation layer is lower than a top surface of the fin; forming a first gate structure across the edge region, wherein a portion of the first gate structure is located on a portion of the sidewall and top surface of the fin, and a portion of the first gate structure is located on a portion of the isolation layer surface; A source-drain doped layer is formed in the fin, and the source-drain doped layer is located on one side of the first gate structure.

5. The method for forming a semiconductor structure according to claim 4, wherein: The method for removing part of the initial first region comprises: forming a protection layer on the sidewall and top surface of the second region; after forming the protection layer, removing part of the initial first region by an etching process to form the first region.

6. The method for forming a semiconductor structure according to claim 5, wherein: The etching process includes an isotropic wet etching process.

7. The method for forming a semiconductor structure according to claim 5, wherein: The material of the protective layer includes organic material.

8. The method for forming a semiconductor structure according to claim 5, wherein: The method for forming the protective layer includes: a chemical vapor deposition process and a physical vapor deposition process.

9. The method for forming a semiconductor structure according to claim 4, wherein: The method for forming the isolation layer comprises: forming an initial isolation layer on the substrate, the initial isolation layer covering the fin; etching back the initial isolation layer to form the isolation layer, the isolation layer covering a portion of the first region, and the top surface of the isolation layer is lower than the top surface of the fin.

10. The method for forming a semiconductor structure according to claim 4, wherein: The material of the isolation layer includes silicon oxide.

11. The method for forming a semiconductor structure according to claim 9, wherein: The initial isolation layer forming process includes: a fluid chemical vapor deposition process.

12. The method for forming a semiconductor structure according to claim 4, wherein: Before forming the gate structure, the method further includes: forming a plurality of first dummy gate structures on the isolation layer, wherein the first dummy gate structures span the edge region of the fin and cover a portion of the sidewalls and the top surface of the fin.

13. The method for forming a semiconductor structure according to claim 12, wherein: The method for forming the source-drain doped layer comprises: etching the fin portion using the first dummy gate structure as a mask to form a source-drain opening in the fin portion; and forming the source-drain doped layer in the source-drain opening.

14. The method for forming a semiconductor structure according to claim 13, wherein: The method for forming the source-drain doped layer in the source-drain opening comprises: forming an epitaxial layer in the source-drain opening by using an epitaxial growth process; and doping source-drain ions into the epitaxial layer by using an in-situ doping process during the formation of the epitaxial layer to form the source-drain doped layer.

15. The method for forming a semiconductor structure according to claim 12, wherein: After forming the first dummy gate structure, the method further includes: forming a dielectric layer on the substrate, wherein the dielectric layer covers the sidewalls of the first dummy gate structure.

16. The method for forming a semiconductor structure according to claim 15, wherein: The method for forming the dielectric layer comprises: forming an initial dielectric layer on the substrate, the initial dielectric layer covering the first dummy gate structure; and performing a planarization process on the initial dielectric layer until the top surface of the first dummy gate structure is exposed to form the dielectric layer.

17. The method for forming a semiconductor structure according to claim 15, wherein: The method for forming the first gate structure includes: removing the first dummy gate structure, forming a gate opening in the dielectric layer; and forming the first gate structure in the gate opening.

18. The method for forming a semiconductor structure according to claim 12, wherein: The first dummy gate structure includes: a first dummy gate dielectric layer and a first dummy gate layer located on the first dummy gate dielectric layer.

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