An Adaptive Droop Control Method Based on Dynamic and Static Power Decoupling

Abstract

An adaptive droop control method based on dynamic and static power decoupling, including: the stability of the system DC bus voltage is jointly completed by the DC regulation terminal with energy storage and the AC regulation terminal; the AC-DC converter at the AC regulation terminal adopts voltage outer loop control and current inner loop control; the DC-DC converter at the DC regulation terminal adopts voltage outer loop control and current inner loop control; the AC regulation terminal and the DC regulation terminal are equivalent to a unified controllable voltage source model with a delay time constant τ v and a reference voltage of U dcrefi . The reference voltage command U dcrefi of the converter at each regulation terminal includes the rated voltage U dcnom , the primary control command U pi , and the secondary control command U s ; the primary control command U pi realizes the dynamic and static separation and adaptive allocation of the total disturbance power of the system; the secondary control command U s is sent to the converters at each regulation terminal for execution to compensate for the static voltage deviation of the DC bus caused by the primary control; determine the time constant of each control level according to the system performance requirements, and then determine the parameters of each control level in sequence according to the parameter design steps.

Description

Technical Field

[0001] The present application relates to the field of intelligent power distribution in power systems, and more specifically, to an adaptive droop control strategy based on dynamic and static power decoupling for a smart soft open points (SOP) system with energy storage. Background Art

[0002] The SOP replaces the traditional tie switch with a back-to-back converter structure and is mostly applied to low-voltage distribution networks. It has the advantages of strong regulation ability, fast switch response speed, low operation cost, and small fault impact. The "AC-DC-AC" operation mode of the SOP is easy to integrate energy storage devices, which can further improve the power regulation ability of the system and enable the system to be connected to weak AC systems or even passive AC systems with small short-circuit capacities. The stability of the SOP system depends on the power balance relationship of the DC bus, so the coordinated control of the DC voltage is the core control problem of the SOP system. Currently, typical coordinated control strategies include master-slave control, DC voltage margin control, and DC voltage droop control. Among them, the multi-layer coordinated control structure based on DC voltage droop control has low communication requirements and good scalability, making it more competitive.

[0003] The DC voltage droop multi-layer coordinated control of the SOP system with energy storage can be decomposed into the power distribution problem between the AC and DC regulation terminals and the power distribution problem within the DC energy storage regulation terminal. Inside the DC regulation terminal, the droop coefficient is generally adaptively changed according to the state of charge (SOC) of each terminal. For SOP systems with the same rated power of the DC regulation terminals, the SOC balancing effect is good. However, if the rated powers of the DC regulation terminals vary greatly, under this method, DC regulation terminals with the same SOC but different powers will bear the same static power, and the power distribution is not reasonable. In addition, due to different power conversion systems (PCS), battery powers, and types, the dynamic and static power capabilities of different regulation terminals are also different. Therefore, it is necessary to explore a coordinated control method that can decouple the disturbance power of the SOP system into dynamic and static components and distribute them reasonably.

[0004] In summary, how to reasonably achieve multi-layer coordination and rationally distribute dynamic and static powers among each DC regulation terminal and AC regulation terminal is a technical problem that needs to be solved urgently by those skilled in the art at present. Summary of the Invention

[0005] The present invention aims to overcome the above-mentioned drawbacks of the prior art and provides an adaptive droop control method based on dynamic and static power decoupling to improve the dynamic and static power distribution performance of the SOP system with energy storage, and enhance the stability and scalability of the system.

[0006] To achieve the above object, the present application provides the following technical solutions:

[0007] An adaptive droop control method based on dynamic and static power decoupling, comprising:

[0008] S11. The stability of the system DC bus voltage is jointly achieved by N regulating terminals, among which M are DC regulating terminals with energy storage, and the remaining N - M + 1 are AC regulating terminals;

[0009] S12. Among the AC regulating terminals, the AC - DC converter adopts voltage outer - loop control and current inner - loop control, where the response time constants of the voltage loop and the current loop are τ v_ACDC and τ i_ACDC ;

[0010] S13. Among the DC regulating terminals, the DC - DC converter adopts voltage outer - loop control and current inner - loop control, where the response time constants of the voltage loop and the current loop are τ v_DCDC and τ i_DCDC ;

[0011] S14. The AC regulating terminals and the DC regulating terminals are equivalent to a unified controllable voltage source model with a delay time constant τ v and a reference voltage of U dcrefi ;

[0012] S15. The reference voltage command U dcrefi of each regulating terminal converter is divided into three parts, including the rated voltage U dcnom , the primary control command U pi , and the secondary control command U s , that is:

[0013] U dcrefi =U dcnom +U pi +U s , i ∈ [1, N] (1)

[0014] S16. The voltage command U pi of the primary control is calculated locally in the converter according to the virtual capacitance C i of each regulating terminal and the adaptively adjusted virtual resistance R i , and can realize the dynamic and static separation and adaptive allocation of the system disturbance power;

[0015] S17. The voltage command U s of the secondary control is calculated by the central controller and sent to each converter for execution after calculation, and can compensate for the DC bus static voltage deviation caused by the primary control;

[0016] S18. Determine the time constants of each control layer according to the system performance requirements, and then determine the parameters of each control layer in turn according to the parameter design steps.

[0017] Preferably, analyze the voltage outer loop control and current inner loop control of the AC-DC converter in step S12 to obtain the response time constants of the voltage loop and current loop, including:

[0018] The adopted voltage outer loop control equation is:

[0019]

[0020] The adopted current inner loop control equation is:

[0021]

[0022] The voltage loop control time constant τ v_ACDC and the current loop control time constant τ i_ACDC are:

[0023]

[0024] Preferably, analyze the voltage outer loop control and current inner loop control of the DC-DC converter in step S13 to obtain the response time constants of the voltage loop and current loop, including:

[0025] The adopted voltage outer loop and current inner loop control equations are:

[0026]

[0027] The voltage outer loop control time constant τ v_DCDC and the current inner loop control time constant τ i_DCDC are:

[0028]

[0029] Preferably, for the step S14 of equivalent the AC regulation terminal and the DC regulation terminal into a unified controllable voltage source model with a delay time constant τ v and a reference voltage of U dcrefi , including:

[0030] By setting τ v_DCDC =τ v_ACDC =τ v , τ i_DCDC =τ i_ACDC =τ i , where τ v >3τ i , the AC regulation terminal and the DC regulation terminal can be equivalent to a unified controllable voltage source model with a delay time constant τ v .

[0031] Preferably, the voltage command U pi of the primary control in step S16 is based on the virtual capacitance C of each regulation terminali and the virtual resistor R with adaptive regulation i It is calculated locally in the converter and can achieve dynamic and static separation and adaptive allocation of the disturbance power, including:

[0032] The voltage command U of the primary control pi Calculation method:

[0033]

[0034] where i oi is the output current of the DC regulation terminal i, and the virtual resistor R of the DC regulation terminal i i is:

[0035]

[0036] The virtual capacitance of each converter is:

[0037]

[0038] The current borne by each converter under the primary control in step S16 will be divided into a static current part i Ri and a dynamic current part i ci :

[0039]

[0040] Under the primary control, the inertia constant τ of the DC bus voltage droop p is:

[0041] τ p = R eq C eq (11)

[0042] Preferably, the voltage command U of the secondary control described in step S17 s is calculated by the central controller, and after calculation, it is sent to each converter for execution, which can compensate for the static voltage deviation of the DC bus caused by the primary control, including:

[0043] The secondary control voltage command U calculated by the central controller and sent to each converter s The calculation method is as follows:

[0044]

[0045] Under the secondary control, the time constant τ of the secondary recovery of the DC bus voltage s is:

[0046]

[0047] Preferably, determining the time constants of each control level according to the system performance requirements, and then sequentially determining the parameters of each control level according to the parameter design steps, including:

[0048] S81: Determine the time constants τ s , τ p , τ v and τ i ;

[0049] S82: Determine the system equivalent virtual resistance R max according to the maximum allowable voltage deviation ΔU max and the maximum load current I eq , and determine the system equivalent capacitance C eq according to Equation (10):

[0050]

[0051] S83: Assuming that the power sharing ratio between the DC side and the AC side is K:1, the virtual resistance R AC_eq of the AC side and the virtual resistance R DC_eq of the DC side can be determined:

[0052]

[0053] S84: Determine the virtual resistance R i and the virtual capacitance C i of each terminal according to the parameters of each adjustment terminal and Equations (7, 8);

[0054] S85: Determine the proportionality coefficient and integral coefficient of the double-loop control and secondary control of the converter according to Equations (3, 5, 12).

[0055] In the above technical solution disclosed in the present application, the stability of the DC bus voltage of the system is jointly completed by N adjustment terminals, where M are DC adjustment terminals with energy storage, and the remaining N - M + 1 are AC adjustment terminals; by analyzing the voltage outer loop control and current inner loop control adopted by the AC-DC converter, the response time constants of its voltage loop and current loop are obtained; by analyzing the voltage outer loop control and current inner loop control adopted by the DC-DC converter, the response time constants of its voltage loop and current loop are obtained; the AC adjustment terminals and DC adjustment terminals are equivalent to a unified controllable voltage source model with a delay time constant τ v and a reference voltage of U dcrefi ; the reference voltage command U dcrefi of each converter is divided into three parts, including the rated voltage U dcnom , the primary control command U pi , and the secondary control command U s ; the voltage command Upi According to the virtual capacitance C of each adjustment terminal i and the virtual resistance R of adaptive adjustment i local calculation is performed in the converter, which can realize the dynamic and static separation and adaptive allocation of the disturbance power; the voltage command U of the secondary control s is calculated by the central controller, and after calculation, it is sent to each converter for execution, which can compensate for the static voltage deviation of the DC bus caused by the primary control; the time constant of each control level is determined according to the system performance requirements, and then the parameters of each control level are determined in turn according to the parameter design steps. The present invention sets the virtual resistance according to the available charge and discharge amount of the energy storage device, and sets the virtual capacitance according to the dynamic power capabilities of each port, realizing the reasonable distribution of the dynamic and static powers of each port, and improving the controllable power margin and stability of the system. Brief Description of the Drawings

[0056] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only the embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained according to the provided drawings.

[0057] Figure 1 It is a flowchart of an adaptive droop control method provided by an embodiment of the present application;

[0058] Figure 2 It is a schematic structural diagram of an AC-DC converter provided by an embodiment of the present application;

[0059] Figure 3 It is a control block diagram of an AC-DC converter provided by an embodiment of the present application;

[0060] Figure 4 It is a schematic structural diagram of a DC-DC converter provided by an embodiment of the present application;

[0061] Figure 5 It is a control block diagram of a DC-DC converter provided by an embodiment of the present application;

[0062] Figure 6 It is a multi-layer coordination control diagram provided by an embodiment of the present application;

[0063] Figure 7 It is a primary control equivalent impedance model diagram provided by an embodiment of the present application;

[0064] Figure 8 It is a secondary control equivalent impedance model diagram provided by an embodiment of the present application;

[0065] Figure 9Schematic diagram of power distribution at the energy storage end during charging provided by an embodiment of the present application;

[0066] Figure 10 Schematic diagram of power distribution at the energy storage end during discharging provided by an embodiment of the present application;

[0067] Figure 11 Schematic diagram of the influence of communication delay on the DC bus voltage provided by an embodiment of the present application. Detailed implementation manners

[0068] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0069] Refer to Figures 1 to 5 , in which, Figure 1 shows a flowchart of an adaptive droop control method provided by an embodiment of the present application, Figure 2 shows a structural diagram of an AC-DC converter provided by an embodiment of the present application, Figure 3 shows a control block diagram of the AC-DC converter provided by an embodiment of the present application, Figure 4 shows a structural diagram of a DC-DC converter provided by an embodiment of the present application, Figure 5 shows a control block diagram of the DC-DC converter provided by an embodiment of the present application. An adaptive droop control method provided by an embodiment of the present application may include:

[0070] S11: The stability of the system DC bus voltage is jointly completed by N regulating ends, where M are DC regulating ends with energy storage, and the remaining N - M + 1 are AC regulating ends.

[0071] S12: Among the AC regulating ends, the AC-DC converter adopts voltage outer loop control and current inner loop control, where the response time constants of the voltage loop and the current loop are τ v_ACDC and τ i_ACDC .

[0072] The AC-DC converter mentioned in the present application refers to a three-phase inverter, specifically such as Figure 2 , by analyzing the mathematical model of the converter, the control equations of the voltage outer loop and the current inner loop can be obtained, and then the control block diagram and the response time constants of the voltage loop and the current loop can be obtained. The control block diagram is as Figure 3 .

[0073] S13: In the DC regulation terminal, the DC-DC converter adopts voltage outer-loop control and current inner-loop control, where the response time constants of the voltage loop and the current loop are τ v_DCDC and τ i_DCDC .

[0074] The DC-DC converter mentioned in this application refers to a bidirectional buck-boost converter, specifically as Figure 4 . By analyzing the mathematical model of the converter, the control equations of the voltage outer-loop and the current inner-loop can be obtained, and then the control block diagram and the response time constants of the voltage loop and the current loop can be obtained. The control block diagram is as Figure 5 .

[0075] S14: Equivalent the AC regulation terminal and the DC regulation terminal into a unified controllable voltage source model with a delay time constant τ v , a reference voltage of U dcrefi .

[0076] Set τ v_DCDC =τ v_ACDC =τ v , τ i_DCDC =τ i_ACDC =τ i , where τ i <<τ v , the AC regulation terminal and the DC regulation terminal can be equivalent to a unified controllable voltage source model with a delay time constant τ v .

[0077] Specifically, see Figures 6 to 8 , where Figure 6 shows the adopted multi-layer coordinated control diagram, Figure 7 shows the primary control equivalent impedance model diagram, Figure 8 shows the secondary control equivalent impedance model diagram.

[0078] S15: The reference voltage command U dcrefi of each converter is divided into three parts, including the rated voltage U dcnom , the primary control command U pi , and the secondary control command U s .

[0079] According to different time scales, the coordinated control mainly includes converter control, primary control, and secondary control, specifically as Figure 6 . The reference voltage command U dcrefi of each converter is divided into three parts, including the rated voltage U dcnom , the primary control command U pi , and the secondary control command U s。 t d2 is the transmission interval time for communication between primary control and converter control. td1 is the transmission interval time for the secondary control to communicate with the primary control. The secondary control relies on the narrow-bandwidth communication channel between the central controller and each regulation terminal. Since the battery capacity changes slowly, the difference between the two transmission signals before and after the communication interval is also very small. Therefore, narrow-band communication can meet the performance requirements. t d1 determines the update speed of the average error of the secondary control DC bus voltage, and its value will directly affect the recovery performance of the DC bus voltage deviation.

[0080] S16: The voltage command U of the primary control pi is calculated locally at the converter according to the virtual capacitance C of each regulation terminal i and the adaptively adjusted virtual resistance R i and can achieve the dynamic and static separation and adaptive allocation of the disturbance power.

[0081] By adopting the equivalent impedance model of the DC source in series and parallel with the virtual resistance-capacitance unit, specifically as Figure 7 . At the moment of power disturbance, since the capacitor is equivalent to a short circuit, the capacitor determines the dynamic current distribution of each unit. In the steady state, since the capacitor is equal to an open circuit, the resistance determines the static current distribution of each unit. In this way, the dynamic and static decoupling separation of the disturbance power can be achieved and distributed according to the design parameters of the virtual RC. The virtual R at the AC end is related to the maximum static power of each AC unit, the virtual R at the DC end is related to the available capacity of each DC unit, and the virtual C of each unit is related to its maximum dynamic power. At the same time, the time constant of the primary control is the product of the virtual RC. Since the value of the virtual resistance is generally much larger than the line resistance, the output voltage of each converter is approximately equal to the DC bus voltage.

[0082] S17: The voltage command U of the secondary control s is calculated by the central controller and sent to each converter for execution after calculation, and can compensate for the static voltage deviation of the DC bus caused by the primary control.

[0083] It can be seen from Figure 7 that the primary control will cause a static error in the steady-state DC bus voltage. In order to eliminate the static error, secondary compensation can be added to the reference voltage to change the system impedance model, specifically as Figure 8 . The time constant of the secondary control is only related to the integral coefficient.

[0084] Specifically refer to Figures 9 to 11 , where Figure 9 shows the schematic diagram of power distribution at the energy storage end during charging, Figure 10 shows the schematic diagram of power distribution at the energy storage end during discharging, Figure 11 shows the schematic diagram of the influence of communication delay on the DC bus voltage.

[0085] S18: Determine the time constants of each control level according to the system performance requirements, and then determine the parameters of each control level in turn according to the parameter design steps.

[0086] S81: Determine the time constant τ of each level according to the system response performance requirements i = 0.1ms, τ v = 1ms, τ d = 50ms, τ s = 0.5s;

[0087] S82: Determine the equivalent virtual resistance R of the system according to the maximum allowable voltage deviation ΔU max = 1kV and the maximum load current I max = 1kA, and determine the equivalent capacitance C of the system according to Equation (10) eq = 50mF: eq

[0088]

[0089] S83: Assume that the power sharing ratio between the DC side and the AC side is 10:1, and the virtual resistance R of the AC side and the virtual resistance R of the DC side can be determined AC_eq DC_eq :

[0090]

[0091] S84: Determine the virtual resistance R of each terminal according to the parameters of each regulating terminal and Equation (7). During discharge, R i = 28.1Ω, R 1 = 18.1Ω, R 2 = 1.8Ω, R 3 = 2.8Ω; During charging, R 4 = 18.3Ω, R 1_DC = 27.5Ω, R 2_DC = 1.8Ω, R 3 = 2.8Ω. Determine the virtual capacitance C of each terminal according to Equation (8) 4 i C 1 = 21.6mF, C 2 = 14.4mF, C 3 = 10.8mF, C 4 = 3.9mF,;

[0092] S85: Determine the proportionality coefficient and integral coefficient of the double-loop control and secondary control of the converter according to Equations (3, 5, 12), k vp = 10, k vi = 0.1, k ip = 5, k i = 50, ki = 2,k p = 0。

[0093] According to the operation results of the parameters designed in the above process, as shown in Figure 9 and Figure 10 shown, the influence results of the DC bus voltage under each communication delay are listed as Figure 11 shown.

[0094] For the above technical solution disclosed in this application, the stability of the DC bus voltage of the system depends on the joint action of N adjustment terminals, where M are DC adjustment terminals with energy storage, and the remaining N - M + 1 are AC adjustment terminals; by analyzing the voltage outer loop control and current inner loop control adopted by the AC-DC converter, the response time constants of its voltage loop and current loop are obtained; by analyzing the voltage outer loop control and current inner loop control adopted by the DC-DC converter, the response time constants of its voltage loop and current loop are obtained; the AC adjustment terminals and DC adjustment terminals are equivalent to a unified controllable voltage source model with a delay time constant τ v , a reference voltage of U dcrefi ; the reference voltage command U dcrefi of each converter is divided into three parts, including the rated voltage U dcnom , the primary control command U pi , the secondary control command U s ; the voltage command U pi of the primary control is calculated locally in the converter according to the virtual capacitance C i of each adjustment terminal and the adaptively adjusted virtual resistance R i , which can realize the dynamic and static separation and adaptive distribution of the disturbance power; the voltage command U s of the secondary control is calculated by the central controller and sent to each converter for execution after calculation, which can compensate for the DC bus static voltage deviation caused by the primary control; the time constants of each control layer are determined according to the system performance requirements, and then the parameters of each control layer are determined in turn according to the parameter design steps. Since the above process directly sets the virtual resistance according to the available capacity of the energy storage device, it is possible to avoid the situation that the energy storage exits in advance due to overcharge or over-discharge. At the same time, the droop coefficients of each port are reasonably set according to their respective static power capabilities and dynamic power capabilities. Therefore, the power margin and stability of the system can be improved.

[0095] An adaptive droop control method provided by an embodiment of this application analyzes the voltage outer loop control and current inner loop control adopted by the AC-DC converter to obtain the time constants of the voltage loop and current loop, which may include:

[0096] The voltage outer loop control equation adopted is:

[0097]

[0098] The current inner-loop control equation adopted is:

[0099]

[0100] The voltage outer-loop control time constant τ v_ACDC and the current inner-loop control time constant τ i_ACDC are:

[0101]

[0102] An adaptive droop control method provided by an embodiment of the present application analyzes the voltage outer-loop control and current inner-loop control adopted by a DC-DC converter to obtain the time constants of the voltage loop and the current loop, which may include:

[0103] The voltage outer-loop and current inner-loop control equations adopted are:

[0104]

[0105] The voltage outer-loop control time constant τ v_DCDC and the current inner-loop control time constant τ i_DCDC are:

[0106]

[0107] An adaptive droop control method provided by an embodiment of the present application equivalently represents the AC regulation terminal and the DC regulation terminal as a unified controllable voltage source model with a delay time constant τ v and a reference voltage of U dcrefi , which may include:

[0108] By setting τ v_DCDC =τ v_ACDC =τ v , τ i_DCDC =τ i_ACDC =τ i , where τ v >3τ i , the AC regulation terminal and the DC regulation terminal can be equivalently represented as a unified controllable voltage source model with a delay time constant τ v .

[0109] An adaptive droop control method provided by an embodiment of the present application divides the reference voltage command U dcrefi of each converter into three parts, including the rated voltage U dcnom , the primary control command U pi , and the secondary control command U s , which may include:

[0110] U dcrefi =U dcnom+U pi +U s , i ∈ [1, N] (1)

[0111] An adaptive droop control method provided by an embodiment of the present application, the voltage command U for primary control pi According to the virtual capacitance C of each regulating terminal i and the adaptively adjusted virtual resistance R i Calculated locally in the converter, it can achieve dynamic and static separation and adaptive allocation of disturbance power, and may include:

[0112] The voltage command U for primary control pi Calculation method:

[0113]

[0114] Among them, the virtual resistance R of converter i i is:

[0115]

[0116] The virtual capacitance of each converter is:

[0117]

[0118] The current borne by each converter under primary control will be divided into a static current part i Ri and a dynamic current part i ci :

[0119]

[0120] Under primary control, the inertia constant τ of the DC bus voltage droop p is:

[0121] τ p = R eq C eq (11)

[0122] An adaptive droop control method provided by an embodiment of the present application, the voltage command U for secondary control s Calculated by the central controller and sent to each converter for execution after calculation, it can compensate for the DC bus static voltage deviation caused by primary control, and may include:

[0123] The secondary control voltage command U calculated by the central controller and sent to each converter s The calculation method is as follows:

[0124]

[0125] Under secondary control, the time constant τ of the secondary recovery of the DC bus voltages is:

[0126]

[0127] An adaptive droop control method provided by an embodiment of the present application determines the time constants of each control level according to system performance requirements, and then determines the parameters of each control level in turn according to the parameter design steps, which may include:

[0128] S81: Determine the time constants τ s , τ p , τ v and τ i ;

[0129] S82: Determine the equivalent virtual resistance R max of the system according to the maximum allowable voltage deviation ΔU max and the maximum load current I eq , and determine the equivalent capacitance C eq of the system according to Equation (10):

[0130]

[0131] S83: Assume that the power sharing ratio between the DC side and the AC side is K:1, and the virtual resistance R AC_eq of the AC side and the virtual resistance R DC_eq of the DC side can be determined:

[0132]

[0133] S84: Determine the virtual resistance R i and the virtual capacitance C i of each terminal according to the parameters of each adjustment terminal and Equations (7, 8);

[0134] S85: Determine the proportionality coefficient and integral coefficient of the double-loop control and secondary control of the converter according to Equations (3, 5, 12).

[0135] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that the elements inherent in a process, method, article or device comprising a series of elements are included. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element. In addition, parts of the above technical solutions provided in the embodiments of the present application that are consistent with the corresponding technical solutions in the prior art are not described in detail to avoid unnecessary repetition.

[0136] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An adaptive droop control method based on dynamic and static power decoupling, characterized in that, it includes: S11. The stability of the system DC bus voltage is jointly completed by N regulating terminals, where M are DC regulating terminals with energy storage, and the remaining N - M + 1 are AC regulating terminals; S12. In the AC regulation terminal, the AC-DC converter adopts voltage outer loop control and current inner loop control, where the response time constants of the voltage loop and the current loop are τ v_ACDC and τ i_ACDC ; S13. In the DC regulation terminal, the DC-DC converter adopts voltage outer loop control and current inner loop control, where the response time constants of the voltage loop and the current loop are τ v_DCDC and τ i_DCDC ; S14. Equivalent the AC regulation terminal and the DC regulation terminal into a unified controllable voltage source model with a delay time constant τ v and a reference voltage of U dcrefi ; S15. The reference voltage command U of each regulating end converter dcrefi is divided into three parts, including the rated voltage U dcnom , the primary control command U pi , and the secondary control command U s , that is: U dcrefi = U dcnom + U pi + U s , i ∈ [1, N] (1) S16. The voltage command U for one-time control pi According to the virtual capacitance C of each adjustment terminal i and the virtual resistance R for adaptive adjustment i Calculate locally in the converter to achieve dynamic and static separation and adaptive allocation of the system disturbance power; S17. Secondary control voltage command U s Calculated by the central controller and sent to each converter for execution after calculation, it can compensate for the static voltage deviation of the DC bus caused by primary control; S18. Determine the time constants of each control level according to the system performance requirements, and then determine the parameters of each control level in sequence according to the parameter design steps; The voltage outer loop control equation adopted by the AC-DC converter described in step S12 is: where, i dref and i qref are respectively the d-axis component and the q-axis component of the reference current on the AC side of the converter, U dcref is the reference value of the DC voltage, U dc , i o are respectively the output voltage and current on the DC side, e d is the d-axis component of the grid phase voltage, Q ref is the reference value of the reactive power output by the converter, k vp , k vi are respectively the proportional coefficient and the integral coefficient of the voltage outer loop; The current inner loop control equation adopted is: where, u dref and u qref are the d-axis component and q-axis component of the reference voltage of the converter's AC output respectively, i d and i q are the d-axis component and q-axis component of the converter's AC-side current respectively, L is the inductance of the AC side, e q is the q-axis component of the grid phase voltage, ω is the synchronous rotation angular velocity of the grid voltage, k ip and k ii are the proportional coefficient and integral coefficient of the inner current loop respectively; The voltage loop control time constant τ v_ACDC and the current loop control time constant τ i_ACDC are respectively: Among them, R L is the internal resistance of the AC-side filter inductor, and R C is the equivalent parallel resistance of the DC-side filter capacitor; The voltage outer loop and current inner loop control equations adopted by the DC-DC converter described in step S13 are: where U dcref and U dc are the reference value and the sampled value of the DC voltage, i Lref and i L are the reference value and the sampled value of the inductor current, i o is the output current, u b is the energy storage device voltage, D is the duty cycle of the switching tube, k vp and k vi are the proportional coefficient and the integral coefficient of the voltage outer loop respectively, k ip and k ii are the proportional coefficient and the integral coefficient of the current inner loop respectively; Voltage outer loop control time constant τ v_DCDC and current inner loop control time constant τ i_DCDC are as follows: Among them, R L is the internal resistance of the DC-side filter inductor, and R C is the equivalent parallel resistance of the output-side DC filter capacitor; The primary control instruction U described in step S16 pi The calculation method is as follows: where i oi is the output current of the DC regulation terminal i, and the virtual resistance R of the DC regulation terminal i i is: Among them, R DC_eq is the equivalent virtual resistance of the equivalent machine for all M DC regulation terminals, and R AC_eq is the equivalent virtual resistance of the equivalent machine for all N - M + 1 AC regulation terminals. Q i and SOC i are the rated battery capacity and state of charge of the DC regulation terminal i respectively. Q charge_total and Q discharge_total are the rechargeable capacity and dischargeable capacity of the DC regulation terminal i respectively. P ACi_max is the maximum static power of the AC unit i; The virtual capacitance C of each adjustment terminal i is as follows: Among them, p i_max is the maximum dynamic power of each adjustment terminal, and C eq is the equivalent virtual capacitance of the equivalent machine of the entire system; The current i borne by each regulating terminal under the voltage command of the primary control described in step S16 oi will be divided into a static current part i Ri and a dynamic current part i ci : Among them, i load is the total load current of the entire system, and R eq is the equivalent virtual resistance of the equivalent machine of the entire system; The inertia time constant τ of the DC bus voltage droop p is as follows: τ p = R eq C eq (11) The voltage command U for secondary control calculated by the central controller in step S17 and sent to each converter s The calculation method is as follows: Among them, U dci is the output voltage of each adjustment terminal, and U dcavg is the average value of the output voltages of each adjustment terminal, and k i is the integral coefficient of the secondary control; The time constant τ for the secondary recovery of the DC bus voltage s is as follows:

2. The adaptive droop control method based on dynamic and static power decoupling according to claim 1, characterized in that, Step S14 is achieved by setting τ v_DCDC = τ v_ACDC = τ v , τ i_DCDC = τ i_ACDC = τ i , where τ v > 3τ i , the AC adjustment terminal and the DC adjustment terminal can be equivalent to a unified controllable voltage source model with a delay time constant τ v .

3. The adaptive droop control method based on dynamic and static power decoupling according to claim 1, characterized in that, The parameter design steps described in step S18 specifically include: S81: Determine the time constants τ of each layer according to the system response performance requirements s , τ p , τ v and τ i ; S82: Determine the equivalent virtual resistance R of the system according to the maximum allowable voltage deviation ΔU max and the maximum load current I max to determine the equivalent capacitance C of the system according to Equation (10) eq : eq : S83: Assuming the power sharing ratio between the DC side and the AC side is K:1, the virtual resistance R of the AC side can be determined AC_eq and the virtual resistance R of the DC side DC_eq : S84: Determine the virtual resistance R and virtual capacitance C of each terminal according to the parameters of each adjustment terminal and formulas (7, 8). i i ;​ S85: Determine the proportionality coefficients and integral coefficients of the converter double-loop control and secondary control according to equations (3, 5, 12).

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