A parallel equalization method based on FPGA

Abstract

The present invention discloses a parallel equalization method based on FPGA, which realizes efficient equalization of communication data by adopting an LMS algorithm with dynamically adjustable step size and a parallel and pipeline filtering structure. First, the tap coefficient of the equalization filter is calculated by an LMS algorithm with dynamically adjustable iteration factor. Secondly, the efficiency of FPGA data processing is improved by a multi-stage pipeline and multi-channel parallel data processing method. The invention can realize that M channels of data are input into the equalization filter in parallel in each clock cycle, and M channels of data are output in parallel. By means of a parallel and pipeline method, the data collected by the high-speed ADC can be efficiently equalized by the FPGA.

Description

Technical Field

[0001] The present invention relates to the field of signal processing in high-speed communication, and in particular to a parallel equalization method based on FPGA, which realizes efficient parallel equalization processing of communication data through FPGA. Background Art

[0002] Equalization is an important technology in communication systems, which is not only used in analog communication, but also in digital communication. In digital communication and high-speed data transmission systems, in order to overcome inter-symbol interference, reduce the influence of amplitude and delay distortion, and increase the transmission rate as much as possible, channel equalization technology is needed. The so-called equalization is to compensate for the distortion of the channel. At the same time, due to the time-varying characteristics of the channel and interference, in order to achieve efficient data transmission, it is necessary to use adaptive technology to automatically adjust the system parameters so that it can automatically track the rapid changes of the signal.

[0003] Among them, the least mean square (LMS) adaptive equalization has received extensive attention in practical engineering because it is simple to implement and does not require the calculation of correlation functions and matrix inversion. However, the traditional LMS has a slow convergence speed due to the fixed iteration step size.

[0004] In addition, since the sampling frequency of ADC is generally as high as GSPS, while the clock processing frequency of FPGA is generally only a few hundred MHZ, the traditional horizontal FIR structure filter used in FPGA cannot achieve efficient processing of large data throughput. Summary of the invention

[0005] In order to solve the above problems, the present invention proposes a parallel equalization method based on FPGA. On the one hand, the convergence speed is accelerated by the LMS algorithm with dynamically adjustable step size. On the other hand, each filtering unit adopts a multi-stage pipeline and overall data parallel processing to realize efficient parallel equalization processing of data.

[0006] In order to overcome the defects of the prior art, the technical solution of the present invention is as follows:

[0007] A parallel equalization method based on FPGA at least includes the following steps:

[0008] Step S1: obtaining a current data frame, which at least includes a preamble and data information;

[0009] Step S2: extract the leading code in the current data frame;

[0010] Step S3: Calculate the variable step size factor μ and the error signal according to the preamble, and update the tap coefficients of the equalization filter according to the variable step size factor μ and the error signal;

[0011] Step S4: acquiring data information in the data frame, and the equalization filter processes the data information according to the updated tap coefficients and outputs the data in parallel until the processing of the current data frame is completed;

[0012] Step S5: Get the next data frame and repeat steps S2 to S5;

[0013] Wherein, in step S4, the equalization filter sets a plurality of filter units in parallel.

[0014] As a further improvement, step S3 further includes the following steps:

[0015] Step S31: The tap coefficient updating module obtains a local training sequence;

[0016] Step S32: sending the preamble code to any filter unit and tap coefficient update module at the same time;

[0017] Step S33: Send y(n) obtained by the filtering unit to the tap coefficient update module to calculate the error signal e(n)=d(n)-y(n), that is, the difference between the filter output result and the local training sequence;

[0018] Step S34: Calculate the variable step size factor μ by the following formula:

[0019]

[0020] Among them, c0, c1α0, α1, and c2 are adjustable coefficients used to accelerate iteration;

[0021] Step S35: Calculate the tap coefficient of the equalization filter by the following formula:

[0022] W(n+1)=W(n)+2μe(n)X(n)

[0023] Where W(n) is the tap coefficient of the equalization filter, X(n) is the input signal, and e(n) is the error signal;

[0024] Step S36: Update the tap coefficients until the error signal converges, otherwise repeat steps S31 to S36.

[0025] As a further improvement, the local training sequence is pre-stored in a non-volatile memory.

[0026] As a further improvement, before acquiring the data frame, the tap coefficients of the filter are initialized, the data cache unit is reset, and the initial cache data is 0.

[0027] As a further reconstruction scheme, in step S31, the local training sequence is the preamble data to be sent by the transmitter known to the receiving end. After the data is transmitted through the channel, due to inter-code interference, noise and other reasons, the received data is inconsistent with the original sent data. In order to solve this problem, it is necessary to find the reverse channel of the channel as much as possible to offset the influence of the channel on data transmission. The data frame first sends a pseudo-random sequence (Pseudorandom Sequence), that is, the preamble part in the frame structure. Since this data is known to the receiver, the receiver passes the received preamble data through a digital filter, and changes the tap coefficient of the digital filter multiple times according to the error between the output result and the known preamble data, so that the characteristics of the digital filter are approximately equivalent to the characteristics of the reverse channel. After the data part in the frame structure passes through this filter, it is equivalent to the data passing through the reverse channel of the original channel, thereby offsetting the influence of data transmission in the channel.

[0028] As a further reconstruction solution, in step S4, the data information is stored in the cache unit for filtering at the next moment, and is sent to the parallel filter units respectively.

[0029] As a further reconstruction plan, each filtering unit uses multi-stage pipeline and parallel technology to process data; multiple data to be added are grouped in pairs and added to the data cache, then added, and then grouped in pairs to form a multi-stage pipeline structure, until the last stage, the addition result is only one number.

[0030] In the above technical solution, the preamble of the data frame is first extracted, and the local training sequence and the preamble are sent to the LMS algorithm tap coefficient update module, and the convergence factor in the LMS algorithm is adjustable to speed up the iteration speed. In order to improve the convergence speed, the present invention adopts the LMS algorithm with adjustable iteration factor. Since the error is relatively large at the beginning of the iteration, a relatively large iteration step size can be used. As the error signal decreases, the iteration step size will also decrease accordingly, that is, μ0>μ1>μ2>…>μ m According to the above principle, μ is a function of the error signal e(n), that is, μ = μ(e(n)), which is used to calculate the appropriate value of each iteration step.

[0031] The above technical solution can obtain the tap coefficient W(n) of the iterative filter, and the output of the data through the equalization filter can be expressed as:

[0032]

[0033] From the above formula, we can know that the output of the kth point of the equalization filter is not only related to the current input x(k), but also to its previous (m-1) input data points. Therefore, in order to achieve multi-channel parallel output, as long as the information of the input point corresponding to each filter and its previous (m-1) input data is known, the output of multi-channel parallel equalization filters can be achieved. Since we need to know the data at the previous moment at the current moment. Therefore, it is necessary to introduce a data cache unit to cache the previous data to the next moment for use by the filter. The amount of data that needs to be cached is determined by the length of the tap coefficient and the number of parallel data.

[0034] Compared with the prior art, the present invention has the following beneficial effects:

[0035] 1. The convergence speed of the LMS algorithm is accelerated by using an adjustable iteration factor μ.

[0036] 2. Use functional module reuse and multi-channel parallelism to improve data throughput.

[0037] 3. Introduce multi-stage pipeline and data cache methods to optimize the hardware implementation structure and increase the maximum clock frequency that the system can achieve.

[0038] 4. The parallel filter of this invention can realize M-way data input and M-way data parallel output at the same time, thus improving data processing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Figure 1 It is an overall framework diagram of a parallel equalization method based on FPGA of the present invention.

[0040] Figure 2 This is a flowchart of a parallel equalization method based on FPGA of the present invention.

[0041] Figure 3 It is a simplified frame format for general communication data, consisting of a preamble and several data blocks.

[0042] Figure 4 This is the internal structure diagram of the data cache module and the eight-way parallel equalization filter module of the present invention.

[0043] Figure 5 It is a diagram of the internal structure of any eight-tap filter unit using a pipeline structure in the present invention. DETAILED DESCRIPTION

[0044] The technical solution provided by the present invention will be further described below in conjunction with the accompanying drawings.

[0045] See also Figure 1, shown is an overall structural block diagram of a parallel equalization method based on FPGA of the present invention, a parallel pipeline equalization filter module and an LMS algorithm tap coefficient update module are set, firstly, the preamble of the data frame is extracted, and the local training sequence and the preamble are sent to the LMS algorithm tap coefficient update module together, and the convergence factor in the LMS algorithm is adjustable to speed up the iteration speed.

[0046] See also Figure 2 , which is a flowchart of a parallel equalization method based on FPGA of the present invention, at least includes the following steps:

[0047] Step S1: Obtain the current data frame, which at least includes a preamble and data information. Figure 3 It is a simplified frame format for general communication data;

[0048] Step S2: extract the leading code in the current data frame;

[0049] Step S3: Calculate the variable step size factor μ and the error signal according to the preamble, and update the tap coefficients of the equalization filter according to the variable step size factor μ and the error signal;

[0050] Step S4: acquiring data information in the data frame, and the equalization filter processes the data information according to the updated tap coefficients and outputs the data in parallel until the processing of the current data frame is completed;

[0051] Step S5: Get the next data frame and repeat steps S2 to S5;

[0052] Wherein, in step S4, the equalization filter sets a plurality of filter units in parallel.

[0053] Wherein, step S3 further comprises the following steps:

[0054] Step S31: The tap coefficient updating module obtains a local training sequence; wherein the local training sequence is a pseudo-random sequence (Pseudorandom Sequence) agreed with the transmitter, namely, the preamble part to be sent in the frame structure.

[0055] Step S32: sending the preamble code to any filter unit and tap coefficient update module at the same time;

[0056] Step S33: Send y(n) obtained by the filtering unit to the tap coefficient update module to calculate the error signal e(n)=d(n)-y(n), that is, the difference between the filter output result and the local training sequence;

[0057] Step S34: Calculate the variable step size factor μ by the following formula:

[0058]

[0059] Among them, c0, c1α0, α1, and c2 are adjustable coefficients used to accelerate iteration;

[0060] Step S35: Calculate the tap coefficient of the equalization filter by the following formula:

[0061] W(n+1)=W(n)+2μe(n)X(n)

[0062] Where W(n) is the tap coefficient of the equalization filter, X(n) is the input signal, and e(n) is the error signal;

[0063] Step S36: Update the tap coefficients until the error signal converges, otherwise repeat steps S31 to S36.

[0064] The tap coefficient W(n) of the iterative filter is obtained, and the output of the data through the equalization filter can be expressed as:

[0065]

[0066] From the above formula, we can know that the output of the kth point of the equalization filter is not only related to the current input x(k), but also to its previous (m-1) input data points. Therefore, in order to achieve multi-channel parallel output, as long as the information of the input point corresponding to each filter and its previous (m-1) input data is known, the output of multi-channel parallel equalization filters can be achieved. Since we need to know the data at the previous moment at the current moment. Therefore, it is necessary to introduce a data cache unit to cache the previous data to the next moment for use by the filter. The amount of data that needs to be cached is determined by the length of the tap coefficient and the number of parallel data.

[0067] See also Figure 4 , shown as Figure 1 The internal architecture of the parallel pipeline equalization filter module and the data cache module. Figure 5 yes Figure 4 The internal structure diagram of any filter unit in .

[0068] Take the example of an equalizing filter with m=8 taps and eight parallel data collected by a high-speed ADC, each clock being given to the equalizing filter. The first filter corresponds to x(jm+1), the second filter corresponds to x(jm+2), and so on, where j is an integer. Each filter only needs the input point at the current moment and the (m-1) data points before it. The first filter inputs x(jm+1). To obtain y(jm+1), the first filter input needs to know the information of the seven input data from x(jm-6) to x(jm) in addition to the information of x(jm+1). The second filter outputs y(jm+2). In addition to the information of x(jm+2), it also needs to know the information of the seven input data from x(jm-5) to x(jm+1), and so on. However, some data information is the data of the previous clock cycle. If you want to obtain it in this clock cycle, you must introduce a data cache unit to obtain the data of the current moment and the previous moment at the same time. The amount of data that needs to be buffered is determined by the length of the tap coefficients and the number of data input in parallel per clock cycle.

[0069] This is very convenient to implement on FPGA. As long as the data collected each time passes through the cache unit composed of multi-level registers, the current clock cycle can simultaneously obtain the data in parallel with the current moment and the previous moment. For this example, as long as the first-level register is introduced, eight-way parallel input and output can be realized. It is not difficult to find that the parallel implementation method only changes the input data of each filter, while the internal structure implementation method of the filter is completely consistent and can be reused. That is, in the process of FPGA implementation, the internal structure of the 8-way parallel equalization filter unit is the same, and only the instantiation needs to be repeated and the input interface data needs to be changed. .

[0070] In addition, when the number of taps of the filter is 8, a traditional lateral filter is used to calculate the data. On the one hand, it takes 7 clock cycles to add the 8 data in sequence. On the other hand, from a hardware perspective, this structure affects the maximum clock frequency that the system can achieve, and this problem becomes more obvious as the number of taps increases. Therefore, by introducing a multi-stage streamline structure, the data is cached through registers, and the data is added two by two until there is only one data at the last stage. Since each stage of the pipeline is executed in parallel, the data operation only requires one clock cycle. The 8-tap filter unit can adopt a 3-stage pipeline structure to achieve efficient parallel equalization filtering. If the number of taps is 2 n , then the number of pipeline levels that need to be added is n.

[0071] The technical solution of the present invention is described in detail below through a specific embodiment 1.

[0072] Example 1

[0073] Based on the above technical concept of the present invention, in this example, the parallel equalization method based on FPGA specifically includes the following steps:

[0074] Step 1: Generate a local training sequence as a coe file and store it in ROM in advance. The local training sequence is a pseudo-random sequence agreed with the transmitter, that is, the preamble part of the frame structure.

[0075] Step 2: The data cache unit is reset, and the initial cache data is 0. The filter tap coefficients are initialized.

[0076] Step 3: Send the received preamble data and the cached preamble data to any filter unit and tap coefficient update module at the same time, and cache the preamble data received this time for use at the next moment.

[0077] Step 4: The y(n) obtained by the filtering unit is sent to the tap coefficient update module. The tap coefficient update module takes out the corresponding expected signal d(n) from the ROM and calculates the error signal e(n) = d(n) - y(n), which is the difference between the filter output result and the local training sequence.

[0078] Step 5: Use the following formula to calculate the variable step size factor μ

[0079]

[0080] Among them, c0, c1α0, α1, and c2 are adjustable coefficients that can be adjusted according to the size of the error signal to accelerate iteration.

[0081] Step 6: The tap coefficient update module calculates the tap coefficient of the equalization filter through the following formula.

[0082] W(n+1)=W(n)+2μe(n)X(n)

[0083] Where W(n) is the tap coefficient of the equalization filter, X(n) is the input signal, and e(n) is the error signal.

[0084] Step 7: Update the tap coefficients. If the error signal converges, go to step 8, otherwise return to step 3.

[0085] Step 8: Input the data collected by the ADC in parallel and update the data cache module. On the one hand, take out the cached data and send it to the parallel equalization filter together with the data collected in this cycle. On the other hand, send the data of this cycle to the data cache module for filtering at the next moment.

[0086] Step 9: Allocate data to each filter unit, and each filter unit uses multi-stage pipeline and parallel technology to process the data. Figure 5 As shown, multiple data to be added are grouped in pairs and added to the data cache, then added, and then grouped in pairs again to form a multi-stage pipeline structure until the last stage.

[0087] Step 10: At the same time, data will complete the filtering operation and be output in parallel. Repeat steps 8, 9, and 10 until a frame of data is completed.

[0088] Step 11: If the next frame of data needs to be processed further, proceed to step 2.

[0089] By adopting the above technical solution, the efficiency of balanced processing of communication data can be improved.

[0090] The above embodiments are only used to help understand the method and core idea of ​​the present invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

[0091] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A parallel equalization method based on FPGA, characterized in that: At least the following steps are included: Step S1: obtaining a current data frame, which at least includes a preamble and data information; Step S2: extract the leading code in the current data frame; Step S3: Calculate the variable step size factor μ and the error signal according to the preamble, and update the tap coefficients of the equalization filter according to the variable step size factor μ and the error signal; Step S4: acquiring data information in the data frame, and the equalization filter processes the data information according to the updated tap coefficients and outputs the data in parallel until the current data frame ends; Step S5: Get the next data frame and repeat steps S2 to S5; Wherein, in step S4, the equalization filter sets multiple filter units in parallel; Step S3 includes the following steps: Step S31: The tap coefficient updating module obtains a local training sequence; Step S32: sending the preamble code to any filter unit and tap coefficient update module at the same time; Step S33: Send y(n) obtained by the filtering unit to the tap coefficient update module to calculate the error signal e(n)=d(n)-y(n), that is, the difference between the filter output result and the local training sequence; Step S34: Calculate the variable step size factor μ by the following formula: Among them, c0, c1α0, α1, and c2 are adjustable coefficients used to accelerate iteration; Step S35: Calculate the tap coefficient of the equalization filter by the following formula: W(n+1)=W(n)+2μe(n)X(n); Where W(n) is the tap coefficient of the equalization filter, X(n) is the input signal, and e(n) is the error signal; Step S36: Update the tap coefficients until the error signal converges, otherwise repeat steps S31 to S36.

2. The FPGA-based parallel equalization method according to claim 1, characterized in that: The local training sequence is pre-stored in a non-volatile memory.

3. The FPGA-based parallel equalization method according to claim 1, characterized in that: Before acquiring the data frame, the data cache unit is reset and the initial cache data is 0.

4. The FPGA-based parallel equalization method according to claim 1, characterized in that: In step S4, the current data information is stored in a cache unit for use in filtering at the next moment, and at the same time, the current data information and the cached data information at the previous moment are taken out and sent to the parallel filter module.

5. The FPGA-based parallel equalization method according to claim 1, characterized in that: Each filter unit processes data using a multi-stage pipeline and parallel technology; wherein, multiple data to be added are grouped in pairs and added to the data cache, then added, and then grouped in pairs again to form a multi-stage pipeline structure until the last stage, when there is only one number.

6. The FPGA-based parallel equalization method according to claim 1, characterized in that: The tap coefficient W(n) of the iterative equalization filter is obtained. The number of taps is m, and the output of the data through the equalization filter is expressed as: The output of the kth point of the equalization filter is not only related to the current input x(k), but also to its previous (m-1) input data points; as long as the information of the input point corresponding to each filter and its previous (m-1) input data is obtained, the output of multiple parallel equalization filters can be realized.

7. The FPGA-based parallel equalization method according to claim 1, characterized in that: In each clock cycle, M data paths are input in parallel to the equalization filter and M data paths are output in parallel.

Images