Defect rate prediction based on lithography model parameters

Abstract

A calibrated lithography model can be used to generate a lithography model output based on an integrated circuit (IC) design layout. Then, at least a chemical parameter can be extracted from the lithography model output. Then, a calibrated defectivity model can be used to predict a defectivity for the IC design layout based on the chemical parameter.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of European patent application No. EP19204192, filed on 18 October 2019, the contents of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0003] This disclosure generally relates to the design and manufacture of integrated circuits (ICs). More specifically, this disclosure relates to predicting defect rates based on lithography model parameters. Background Technology

[0004] Advances in process technology and the ever-growing demand for computing and storage have driven the increase in the size and complexity of IC designs. This progress can be attributed to improvements in semiconductor design and manufacturing technologies, which enable the integration of tens of millions of devices onto a single chip. Accurately predicting defect rates before IC layout is crucial. Summary of the Invention

[0005] Some embodiments described herein can use a calibrated lithography model to generate a lithography model output based on an IC design layout. The embodiments can then extract at least chemical parameters from the lithography model output. The embodiments can then use a calibrated defect rate model to predict the defect rate for the IC design layout based on the chemical parameters.

[0006] In some embodiments, the chemical parameter may correspond to the inhibitor concentration. Specifically, the chemical parameter may be related to the dissolution rate of the resist during resist development.

[0007] Some embodiments may receive a set of IC design layouts and defect rate measurements corresponding to the set of IC design layouts. The embodiments may then fit a defect rate model based on the set of IC design layouts and the defect rate measurements to obtain a calibrated defect rate model. In some embodiments, the defect rate model may include complementary error function terms. In some embodiments, the defect rate model may be a quadratic function. In some embodiments, the defect rate model may be a cubic function. Attached Figure Description

[0008] This disclosure can be understood based on the detailed description and accompanying drawings given below. The drawings are for illustrative purposes only and do not limit the scope of this disclosure. Furthermore, the drawings are not necessarily drawn to scale.

[0009] Figure 1 The illustration shows a process for calibrating a defect rate model according to some embodiments disclosed herein.

[0010] Figure 2The diagram illustrates terms and coefficients in a quadratic model based on some embodiments disclosed herein.

[0011] Figure 3 The diagram illustrates the terms and coefficients in a cubic model according to some embodiments disclosed herein.

[0012] Figure 4 The illustration shows a process for predicting defect rates using a calibrated defect rate model according to some embodiments disclosed herein.

[0013] Figure 5 The illustration shows an IC design layout based on some embodiments disclosed herein.

[0014] Figure 6 The illustration shows the output of a lithographic model according to some embodiments disclosed herein.

[0015] Figure 7 The illustrations depict defects according to some embodiments disclosed herein.

[0016] Figure 8 The illustrations depict example flows of designing, verifying, and manufacturing integrated circuits according to some embodiments described herein.

[0017] Figure 9 An example machine of a computer system is illustrated, which can execute an instruction set therein, which is used to cause the machine to perform any or more of the methods discussed herein. Detailed Implementation

[0018] Defects that occur during photolithography (such as pinches and bridging) can severely impact yield in semiconductor manufacturing. These defects can appear randomly, and even one defect in a critical part of an IC chip can render the entire chip unusable. Predicting defect rates is important because IC chips can contain a large number of critical features.

[0019] Existing technologies have poor predictive accuracy, and some are unacceptably slow. Furthermore, some existing technologies involve manual components and are labor-intensive.

[0020] The embodiments disclosed herein accurately and rapidly predict the defect rate for a given lithography process. The advantages of the embodiments described herein include, but are not limited to, enabling optimization of manufacturable processes, thereby reducing defect rates and improving process costs and development time for new devices or technologies.

[0021] Some embodiments disclosed herein predict defect rates based on one or more lithography parameters, wherein at least one parameter is a chemical parameter (e.g., inhibitor concentration) extracted from the lithography model output in relation to the resist. In this disclosure, the term "lithography model output" refers to the output of a lithography model or simulator that calculates the optical and resist effects of the lithography process.

[0022] According to one definition, the term "defect rate" refers to (1) the probability of a hole (i.e., no resist) appearing in an area where resist is nominally present (i.e., in the absence of random events), or (2) the probability of resist appearing in an area where resist is nominally absent (i.e., in the absence of random events).

[0023] When defect rate measurement data is collected, different defect rate definitions can be used that are more convenient from a measurement perspective. One defect rate metric used in the industry is called "PixNOK". This metric can be defined in the nominally unreplicable space area and in the nominally replicable line area.

[0024] The "PixNOK" metric can be calculated in the blank areas of an IC design layout as follows: From a scanning electron microscope (SEM) image of the printed resist pattern, count the number of "failed" pixels (i.e., those with defects, such as microbridges) along the center line of the blank area. Then, calculate the "PixNOK" metric by dividing the number of "failed" pixels by the total number of pixels.

[0025] Similarly, the "PixNOK" metric can be calculated in the line area of ​​an IC design layout as follows: From the SEM image of the printed resist pattern, count the number of pixels that are "failed" (i.e., have defects such as broken lines or holes) along the center line of the line area. Then, calculate the "PixNOK" metric by dividing the number of "failed" pixels by the total number of pixels.

[0026] Note that the “PixNOK” metric corresponds to the defect rate, as it empirically measures the number of defective pixels in a SEM image. Further details about this metric can be found in Bisschop, PD, “Stochastic printing failures in extreme ultraviolet lithography,” Journal of Micro / Nanolithography, MEMS, and MOEMS 17(4), 041011 (September 25, 2018).

[0027] Figure 1 The illustration shows a process for calibrating a defect rate model according to some embodiments disclosed herein.

[0028] The process can begin by calibrating a lithography model that models the optical and resist effects (102). In this disclosure, the term "lithography model" refers to a software application that models the optical and resist effects, i.e., for a given IC design layout and lithography process, the lithography model can be used to simulate or predict the shape of the resist to be printed on the wafer.

[0029] Generally, any existing lithography model can be used. For example, Synopsys Inc.'s Sentaurus can be used. TM A lithography (S-Litho) simulator. It can provide certain parameters characterizing the lithography process as input to the lithography model. For example, the lithography model can accept the following lithography process parameters as input: exposure dose, optical focus, irradiation, numerical aperture, mask stacking parameters, resist parameters, and wafer stacking parameters. Figure 1 As shown, the value 114 of the lithography process parameter corresponding to the lithography process being used can be input into the lithography model.

[0030] The lithography model can include parameters fitted based on empirical data during calibration. Specifically, resist development can be performed on one or more design layouts using a lithography process, and critical dimensions of various features in the IC design layout can be measured (e.g., by using SEM). The IC design layout 120 and the corresponding critical dimension measurements 112 can then be used to calibrate the lithography model, resulting in a calibrated lithography model 104. Typically, multiple IC design layouts and their corresponding critical dimension measurements can be used to calibrate the lithography model.

[0031] For a given IC design layout, such as IC design layout 116, a calibrated lithography model 104 (which models optical and resist effects) can accurately predict the resist shape expected to be printed after resist development. Specifically, the calibrated lithography model 104 may include one or more calculated parameters that model various physical and chemical phenomena occurring during lithography. Specifically, the lithography model may include calculated parameters whose values ​​at a given point can be used to determine whether resist printing is expected at that point. In some embodiments, the values ​​of the calculated parameters can be compared to a threshold; if the value is greater than the threshold, the lithography model can determine that resist printing is expected; otherwise, the lithography model can determine that resist printing is not expected. Specifically, the values ​​of the calculated parameters can be compared to the threshold on a two-dimensional plane to create a contour of the resist shape expected to be printed.

[0032] In summary, a lithography model can include three types of parameters: (1) input parameters, which are provided as input to the lithography model and correspond to characteristics of the lithography process (e.g., numerical aperture, etc.); (2) fitting parameters (e.g., coefficients), which are fitted during the calibration of the lithography model; and (3) computational parameters, which are calculated by the lithography model for a given IC design layout and lithography process during simulation or prediction, wherein the computational parameters can represent the effects of optical phenomena and / or resist phenomena occurring during lithography. Specifically, in some embodiments, the lithography model can use the parameters shown in the table below.

[0033] Parameter Labels Parameter Description type Correlation Pitch Design spacing I 0.042 LW Line width M 0.029 D Exposure dose I 0.850 Focus Focus of Exposure I 0.080 CD Measured blank width M 0.403 CDSim The simulated blank CD S 0.490 NILS Normalized image log slope S 0.812 ILS Image log slope S 0.411 AImin_x_Dose Spatial image minimum x dose S 0.182 AImax_x_Dose Spatial image maximum x dose S 0.670 AITresh_x_Dose Spatial image maximum x dose S 0.150 InhNILS Inhibitor normalized image log slope S 0.885 InhILS Inhibitor image log slope S 0.596 Imin Minimum inhibitor S 0.888 Imax maximum inhibitor value S 0.181 Ith Inhibitor threshold S 0.554

[0034] In the table above, the "Parameter Label" column contains labels that can be used to reference parameters, and the "Parameter Description" column describes the parameters. The "Type" column specifies the type of the parameter. Specifically, "I" in the "Type" column indicates that the parameter is provided as input, and "M" indicates that the parameter is an empirical parameter (a measurement parameter that can be used to fit the lithography model), for example, measured using SEM measurements. "S" in the "Type" column indicates that the parameter is calculated by the lithography model based on the input parameters and IC design layout. Fitted parameters are not shown in the table.

[0035] Lithography parameters can be correlated with defect rates or the logarithm of defect rates. Specifically, lithography can be performed on a set of IC design layouts to create resist shapes. Defects can then be measured using SEM measurements to calculate the defect rate at different locations within each IC design layout. The calculated defect rate can then be correlated with lithography parameters, thus identifying lithography parameters as good predictors of defect rates. In particular, the higher the correlation, the better the parameter serves as a defect rate predictor.

[0036] The “Correlation” column provides the correlation between the parameter and the logarithm of “PixNOK” (i.e., log(PixNOK)). As can be seen from the table above, “Inhibitor Minimum” has the highest correlation with log(PixNOK). The “Inhibitor” parameter is a chemical concentration parameter of the resist that determines the rate at which the resist dissolves during resist development. In some embodiments, this parameter can have a range of [0, 1], where 0 corresponds to the maximum dissolution rate and 1 corresponds to the minimum dissolution rate. Therefore, a lower value of the inhibitor parameter at a point corresponds to a higher dissolution rate (meaning that the resist is less likely to be present at that point). A lithography model (e.g., S-Litho) can calculate the inhibitor concentration. The “Inhibitor Minimum” can be the minimum inhibitor concentration along a line in the IC design layout (e.g., a blank area or the center line of a line area).

[0037] The correlation between the function of lithography parameters and the defect rate can also be calculated. The following are some examples illustrating the function of lithography parameters and its correlation with the defect rate.

[0038]

[0039]

[0040] The "F" in the "Type" column indicates that the row corresponds to a function with one or more parameters. For example, parameter "Combi1" equals Imin divided by dose D, parameter "Combi2" equals Imin divided by the square of D, and so on. The label "Func1" corresponds to the function shown in the "Parameter Description" column. In this function, the coefficients "A", "B", and "C" fit empirical data, as explained below. Similarly, the functions in rows "Func2" and "Func3" are explained in more detail below.

[0041] As can be seen from the table above, certain functions exhibit a very high correlation with the measured defect rate. Therefore, some embodiments disclosed herein predict defect rates based on a set of parameters, which includes at least the chemical parameters of the resist (e.g., inhibitor concentration). In particular, some embodiments disclosed herein may use functions defined on this parameter set (e.g., one of the functions shown in the table above) to predict defect rates.

[0042] The function shown in line “Func1” can be derived as follows. The inhibitor concentration after exposure and post-exposure baking (PEB) can exhibit statistical fluctuations due to various sources: photon noise, chemical composition fluctuations, etc. These fluctuations, when combined, can cause variations in the inhibitor concentration's distribution around a normal mean. The probability density of the presence of inhibitor concentration at a given location in the resist can be expressed as:

[0043]

[0044] Where I(x,y,z) is the inhibitor concentration (including random fluctuations) at point (x,y,z), Imean(x,y,z) is the average inhibitor concentration at point (x,y,z), and σ is the standard deviation of the inhibitor fluctuations. The value of Imean at a given location can be set to be equal to the inhibitor concentration at that location by the continuum resist model. In other words, the inhibitor concentration calculated by the lithography model (e.g., the lithography model used in S-Litho) at a given point in the IC design layout can be used as the value of Imean.

[0045] Above a certain inhibitor threshold, the resist will not develop (i.e., print). In the equation for "Func1", this value is "Ith". In other words, neglecting fluctuations, if the inhibitor value is greater than Ith, the resist will print, and if the inhibitor value is less than Ith, the resist will not print.

[0046] However, the inhibitor fluctuates due to random phenomena. Thus, I(x,y,z) fluctuates around Imean. At locations where the resist is present without fluctuations, if the fluctuations are large enough such that I(x,y,z) < Ith, hole defects may appear in the line regions. On the other hand, at locations where the resist is absent, if the fluctuations are large enough such that I(x,y,z) > Ith, print defects may appear in the blank regions.

[0047] Adding statistical fluctuations can yield an indicator of the defect failure rate. Specifically, the probability that the inhibitor value is within the range dI around I is given by the following formula:

[0048]

[0049] The probability of print defects in the blank regions can be calculated as follows:

[0050]

[0051] Therefore, the probability of defects can be expressed using the complementary error function erfc as follows:

[0052]

[0053] where,

[0054]

[0055] ΔIth = Ith - Imean,

[0056] For print defects, sign = +1, and for hole defects sign = -1, and

[0057] erfc is the complementary error function.

[0058] Using a calibrated resist model, the simulated Imin for a line spacing pattern was compared with the exposure dose D for a range of representative spacings and blank widths. Based on this comparison, it was observed that the inhibitor concentration / min is a function of the exposure dose D. In other words, the standard deviation of the inhibitor minimum is a function of the dose and its standard deviation (this is the reason for the expression for dose entering defect prediction). Specifically, an exponential function provides a good fit for the change in inhibitor concentration / min relative to the exposure dose D. Therefore, Imin = αe -βD ,and

[0059] σ Imin =σ(αe -βD )=f(σ D D)

[0060] Where f(σ) D The value of D can be obtained through error propagation. Specifically, error propagation can be used to show that:

[0061] σ Imin =β.I.σ D =αβ.e -βD .σ D

[0062] Using the above expression in the defect rate equation, and taking the logarithm of the defect rate, we get:

[0063]

[0064] By assuming that the experimentally measured defect rate log(PixNOK) is proportional to the theoretically derived defect rate, we derive the equation shown for “Func1”:

[0065]

[0066] In the above equation, the coefficients “A”, “B”, and “C” can be fitted using empirical data. For example, (1) SEM measurements can measure defect rate data by printing a set of IC design layouts using a lithography process, (2) the IC design layout can be simulated using a calibrated lithography model, and the Ith and Imean values ​​can be extracted from the lithography model, and (3) the coefficients “A”, “B”, and “C” can be determined based on the best fit when the measured defect rate (e.g., PixNOK), Ith, and Imean values ​​are substituted into the equation. For example, for a specific lithography process, values ​​of 6.49, 0.68, and 0.069 are obtained for A, B, and C.

[0067] Typically, any function can be used to predict the defect rate based on the parameters. For example, a quadratic function defined on the parameters can be used as the prediction function (this corresponds to the "Func2" row in the parameter table), where each term of the quadratic function has a power of at most two.

[0068] Figure 2 The diagram illustrates terms and coefficients in a quadratic model based on some embodiments disclosed herein.

[0069] Alternatively, a cubic function defined on the parameters can be used as a prediction function (this corresponds to the "Func3" row in the parameter table), where each term of the cubic function has a power of at most three.

[0070] Figure 3 The diagram illustrates the terms and coefficients in a cubic model according to some embodiments disclosed herein.

[0071] Return to reference Figure 1 The IC design layout 116 can be provided to a calibrated photolithography model 104. The photolithography process can also be used to print the IC design layout 116, and defect rate measurement data 118 can be obtained. Alternatively, the defect rate measurement data 118 can also be obtained by performing a computationally expensive and detailed Monte Carlo simulation of the photolithography process.

[0072] Then, parameters (106) can be extracted from the lithography model output, wherein the extracted parameters include at least one chemical parameter of the resist. Then, the defect rate model 118 can be calibrated based on the extracted parameters and defect rate measurement data to obtain a calibrated defect rate model 110.

[0073] Figure 4 The illustration shows a process for predicting defect rates using a calibrated defect rate model according to some embodiments disclosed herein.

[0074] The process can begin by providing the IC design layout 404 and the values ​​114 of the lithography process parameters to the calibrated lithography model 104. The process can then extract parameters (402) from the lithography model output, where the extracted parameters may include at least one chemical parameter of the resist. The process can then provide the extracted parameters and the values ​​114 of the lithography process parameters to the calibrated defect rate model 110. The calibrated defect rate model 110 can then generate a defect prediction 406 based on the extracted parameters and the values ​​114 of the lithography process parameters.

[0075] In some embodiments, defect prediction 406 may include two defect maps: (1) a first map for the case where (Ith-Imean)>0 (i.e., the case where printing defects occur in blank areas), and (2) a second map for the case where (Ith–Imean)<0 (i.e., the case where hole defects occur in resist areas).

[0076] Figure 5 The illustration shows an IC design layout according to some embodiments disclosed herein. In IC design layout 502, shaded areas correspond to areas where resist is desired to be printed, and transparent areas correspond to areas where resist should not be present.

[0077] Figure 6 The illustration shows the output of a lithography model according to some embodiments disclosed herein. The shaded areas in the lithography model output 602 illustrate the resist pattern predicted by the calibrated lithography model.

[0078] Figure 7 Defect diagrams according to some embodiments disclosed herein are illustrated. Defect diagram 702 includes a predicted resist pattern and additionally predicts areas where defects may occur. For example, defect diagram 702 includes a predicted defect area 704 where printing defects may occur.

[0079] Figure 8 An example flow 800 for the design, verification, and fabrication of an integrated circuit according to some embodiments described herein is illustrated.

[0080] EDA processes (the acronym "EDA" stands for "Electronic Design Automation") can be used to convert and verify design data and instructions representing integrated circuits. Each of these processes can be structured and enabled as multiple modules or operations.

[0081] Process 800 can begin by creating a product concept 810 using information provided by the designer, which is then transformed and verified using an EDA process 812. Upon completion of the design, it is tape-out 834, which is when the schematics (e.g., geometric patterns) of the integrated circuit are sent to a manufacturing plant to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, semiconductor dies are manufactured 836, and packaging and assembly processes 838 are performed to produce the manufactured IC chip 840.

[0082] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. Using hardware description languages ​​(“HDLs”) such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera, circuits and systems can be designed using high-level abstractions. HDL descriptions can be translated into logic-level register-transfer level (“RTL”) descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of abstraction (i.e., a less abstract description) adds more detail to the design description. Lower levels of abstraction (i.e., less abstract descriptions) can be computer-generated, exported from design libraries, or created by another design automation process. An example of a specification language used to specify lower levels of abstraction that provide more detailed descriptions is SPICE (SPICE stands for “Integrated Circuit Focused Simulation Program”). Each level of abstraction contains enough detail for use by the corresponding tool at that level (e.g., a formal verification tool).

[0083] During system design phase 814, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired properties such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0084] During logic design and functional verification 816, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of that specification is checked. For example, components of a circuit can be verified to generate outputs that match the specification requirements of the designed circuit or system. Functional verification can use simulators and other programs, such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, a special system of components referred to as a 'simulator' or 'prototype system' is used to accelerate functional verification.

[0085] During synthesis and design 818 for testing, HDL code is converted into a netlist. In some embodiments, the netlist may be a graphical structure, where edges of the graphical structure represent components of the circuit, and nodes of the graphical structure represent how the components are interconnected. Both HDL code and netlist are fabricated layered products that can be used by EDA products to verify whether the integrated circuit performs according to a specified design when it is manufactured. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit can be tested to verify that the integrated circuit meets the specifications.

[0086] During netlist verification (820), the netlist is checked to ensure it meets timing constraints and corresponds to the HDL code. During design planning (822), the overall planar diagram of the integrated circuit is built and analyzed for timing and top-level routing.

[0087] During layout or physical implementation of 824, physical placement (placement of circuit components such as transistors or capacitors) and wiring (connection of circuit components through multiple conductors) are performed, and cells can be selected from a library to enable specific logic functions. As used herein, the term 'cell' can specify a collection of transistors, other components, and interconnects that provides Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit 'block' can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and can be enabled for both physical structure and simulation. Parameters such as size are specified for the selected cells (based on 'standard cells') and make them accessible in a database for use in EDA products.

[0088] During analysis and extraction 826, circuit functionality is verified at the layout level, which allows for improvements to the layout design. During physical verification 828, the layout design is checked to ensure that manufacturing constraints (such as DRC constraints, electrical constraints, and lithographic constraints) are correct and that the circuit functionality matches the HDL design specifications. During resolution enhancement 830, the layout geometry is transformed to improve how the circuit design is manufactured.

[0089] During the tape-out process, data is created for use (if appropriate, after applying lithographic enhancement) in the production of a photomask. During mask data preparation 832, the 'tape-out' data is used to generate a photomask for the production of the finished integrated circuit.

[0090] Computer systems (such as, Figure 9 The storage subsystem of the computer system (900) can be used to store programs or data structures used by some or all of the EDA products described herein, and by products used for developing libraries as well as products used for physical and logical designs that use the libraries.

[0091] Figure 9 An example machine of a computer system 900, which can execute an instruction set therein, is illustrated. This instruction set is used to cause the machine to perform any or more of the methods discussed herein.

[0092] In alternative implementations, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment, as a peer-to-peer (or distributed) network environment, or as a server or client computer in a cloud computing infrastructure or environment.

[0093] A machine can be a personal computer (PC), tablet computer, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network cabling, switch, or bridge, or any machine capable of executing a set of instructions (sequential or other instructions) specifying the actions to be performed by that machine. Furthermore, while a single machine is illustrated, the term "machine" should also be understood to include any collection of machines that, individually or collectively, execute a set (or more) of instructions to perform any one or more methods discussed herein.

[0094] Example computer system 900 includes processing device 902, main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), static memory 906 (e.g., flash memory, static random access memory (SRAM) etc.) and data storage device 918, which communicate with each other via bus 930.

[0095] Processing device 902 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements combinations of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 902 may be configured to execute instructions 926 to perform the operations and steps described herein.

[0096] The computer system 900 may further include a network interface device 908 for communication via a network 920. The computer system 900 may also include a video display unit 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generation device 916 (e.g., a speaker), a graphics processing unit 922, a video processing unit 928, and an audio processing unit 932.

[0097] Data storage device 918 may include machine-readable storage medium 924 (also referred to as non-transitory computer-readable medium) storing one or more instruction sets 926 or software embodying any one or more methods or functions described herein. During execution of instruction 926 by computer system 900, instruction 926 may also reside wholly or at least partially in main memory 904 and / or in processing device 902, which also constitute machine-readable storage media.

[0098] In some embodiments, instruction 926 includes instructions for implementing functions corresponding to this disclosure. Although machine-readable storage medium 924 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) for storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for execution by a machine and to cause the machine and processing device 902 to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0099] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the methods used by those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm can be a sequence of operations that lead to a desired result. These operations are operations that require physical manipulation of physical quantities. Such quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0100] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise expressly indicated in this disclosure, it should be understood that throughout this description, certain terms refer to the actions and processes of a computer system or similar electronic computing device that manipulate and convert data represented as physical (electronic) quantities within the registers of the computer system into other data, which are similarly represented as physical quantities within the computer system's memory or registers or other such information storage devices.

[0101] This disclosure also relates to means for performing the operations described herein. Such means may be specifically configured for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. This computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0102] The algorithm and display presented herein are not inherently related to any particular computer or other device. Various other systems may be used with the program based on the teachings herein, or it may be proven easy to construct more specialized devices to execute the method. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0103] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, which can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0104] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific exemplary embodiments. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the present disclosure as set forth in the appended claims. Where elements are referred to in the singular in this disclosure, more than one element may be depicted in the drawings, and the same elements may be labeled with the same reference numerals. Therefore, this disclosure and the drawings should be considered illustrative rather than restrictive.

Claims

1. A method comprising: generating lithography model output based on an integrated circuit (IC) design layout using a calibrated lithography model; extracting, by a processor, from the lithography model output, at least a chemical parameter; and predicting a defectivity for the IC design layout based on the chemical parameter using a calibrated defectivity model, wherein the chemical parameter corresponds to a suppressant concentration.

2. The method of claim 1, wherein the chemical parameter relates to a dissolution rate of resist during resist development.

3. The method of claim 1, comprising: receiving a set of IC design layouts; receiving defectivity measurements for the set of IC design layouts; and fitting a defectivity model based on the set of IC design layouts and the defectivity measurements to obtain the calibrated defectivity model.

4. The method of claim 3, wherein the defectivity model comprises a complementary error function term.

5. The method of claim 3, wherein the defectivity model is a quadratic function.

6. The method of claim 3, wherein the defectivity model is a cubic function.

7. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to: generate lithography model output based on an integrated circuit (IC) design layout using a calibrated lithography model; extract, from the lithography model output, at least a chemical parameter; and predict a defectivity for the IC design layout based on the chemical parameter using a calibrated defectivity model, wherein the chemical parameter corresponds to a suppressant concentration.

8. The non-transitory computer-readable storage medium of claim 7, wherein the chemical parameter relates to a dissolution rate of resist during resist development.

9. The non-transitory computer-readable storage medium of claim 7, wherein the instructions, when executed by the processor, cause the processor to: receive a set of IC design layouts; receive defectivity measurements for the set of IC design layouts; and fit a defectivity model based on the set of IC design layouts and the defectivity measurements to obtain the calibrated defectivity model.

10. The non-transitory computer-readable storage medium of claim 9, wherein the defectivity model comprises a complementary error function term.

11. The non-transitory computer-readable storage medium of claim 9, wherein the defectivity model is a quadratic function.

12. The non-transitory computer-readable storage medium of claim 9, wherein the defectivity model is a cubic function.

13. An apparatus comprising: a memory storing instructions; and a processor coupled with the memory and executing the instructions, which when executed cause the processor to: generate lithography model output based on an integrated circuit (IC) design layout using a calibrated lithography model; extract, from the lithography model output, at least a chemical parameter; and predict a defectivity for the IC design layout based on the chemical parameter using a calibrated defectivity model, wherein the chemical parameter corresponds to a suppressant concentration.

14. The apparatus of claim 13, wherein the chemical parameter is related to a dissolution rate of resist during resist development.

15. The apparatus of claim 13, wherein the instructions, when executed by the processor, cause the processor to: receive a set of IC design layouts; receive defectivity measurements for the set of IC design layouts; and fit a defectivity model based on the set of IC design layouts and the defectivity measurements to obtain the calibrated defectivity model.

16. The apparatus of claim 14, wherein the defectivity model includes a complementary error function term.

17. The apparatus of claim 14, wherein the defectivity model is a quadratic function or a cubic function.

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