Adder tree circuit, adder circuit and method of operating a full adder

Abstract

In some aspects of the application, adder tree circuits are disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subset of FAs, wherein each FA of the first subset of full adders includes a first number of transistors; and a second subset of FAs, wherein each FA of the second subset of full adders includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subset receives a first input from a first one of the second subset of FAs and a second input from a second one of the second subset of FAs, and each FA provides a first output to a third one of the second subset of FAs and a second output to a fourth one of the second subset of FAs. Embodiments of the present application also relate to adder circuits and methods of operating full adders.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to adder tree circuits, adder circuits, and methods of operating a full adder. BACKGROUND

[0002] A full adder is an adder that adds three inputs and produces two outputs. The first two inputs are two operands A and B, and the third input is an input carry Cin. The output carry is designated as Cout, and the sum output is designated as S. Full adders can be used in binary arithmetic circuits that implement addition, subtraction, multiplication, and division. SUMMARY

[0003] Some embodiments of the present application provide an adder tree circuit comprising: a plurality of full adders (FAs) comprising: a first subset of full adders, wherein each full adder of the first subset of full adders comprises a first number of transistors; and a second subset of full adders, wherein each full adder of the second subset of full adders comprises a second number of transistors, the first number being greater than the second number; wherein each full adder of the first subset of full adders receives a first input from a first one of the second subset of full adders and a second input from a second one of the second subset of full adders, and each full adder provides a first output to a third one of the second subset of full adders and a second output to a fourth one of the second subset of full adders.

[0004] Some embodiments of the present application provide an adder circuit comprising: a first stage configured to: receive a first input signal and a second input signal; and provide a first output signal; a second stage coupled to the first stage and configured to invert the first output signal to provide a second output signal; a third stage coupled to the first stage and the second stage and configured to: receive a carry input signal, the first output signal, and the second output signal; and provide a sum signal; and a fourth stage coupled to the first stage and the second stage and configured to: receive the carry input signal, the first input signal, the first output signal, and the second output signal; and provide a carry output signal.

[0005] Yet other embodiments of the present application provide a method of operating a full adder, comprising: receiving, by a first full adder (FA), a first operand from a second full adder, wherein the second full adder has a first drive strength to provide the first operand to the first full adder; receiving, by the first full adder, a second operand from a third full adder, wherein the third full adder has the first drive strength to provide the second operand to the first full adder; and providing, by the first full adder, a sum to a fourth full adder, wherein the first full adder has a second drive strength to provide the sum to the fourth full adder, wherein the second drive strength is less than the first drive strength. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects of the application are best understood from the following detailed description when read in conjunction with the accompanying drawings. It is to be noted, however, that the various components of the application, as well as the relative placement of the various components, are not drawn to scale. Rather, the dimensions of the various components can be arbitrarily increased or decreased for the clarity of discussion and presentation.

[0007] FIG. 1A FIG. 1B FIG. 1C FIG. 1D Each illustrates a block diagram of an adder tree according to some embodiments of the application.

[0008] FIG. 2 illustrates a block diagram of a full adder according to some embodiments of the application.

[0009] FIG. 3 illustrates a circuit diagram of a full adder according to some embodiments of the application.

[0010] FIG. 4A illustrates a flowchart of a method of operating an adder tree according to some embodiments of the application.

[0011] FIG. 4B illustrates a flowchart of another method of operating an adder tree according to some embodiments of the application.

[0012] FIG. 5 is a block diagram showing a configuration of a memory system according to various embodiments of the application. DETAILED DESCRIPTION

[0013] ​​​The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the disclosure in any way. For example, in the following description, a first component forming over or on a second component can include embodiments where the first component and second component are in direct contact, and can also include embodiments where additional components can be formed between the first component and second component such that the first component and second component can not be in direct contact. Furthermore, the present disclosure can refer to a plurality of elements by a single reference number, and / or can refer to a plurality of elements by a single reference number and a hyphen, comma, explosion number, associated reference number, associated shaded region, parentheses, brackets or the like, such that an individual reference numerals can be associated with multiple, possibly all, of the referenced elements. This referencing is used to simplify the figures and is meant in a non-limiting sense. Specifically, singular nouns can have a singular connotation or plural connotation depending on the figure and context.

[0014] In addition, spatially relative terms, such as "under", "below", "lower", "over", "upper" and the like, can be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0015] The present disclosure provides various embodiments of adder trees that provide full adders (FAs) of stronger driving / drive strength (e.g., 28 transistor (28T) adders) interleaved with FAs of weaker driving strength (e.g., 14 transistor (14T) adders). In some embodiments, each FA of a first subset of FAs (e.g., 28T adders) receives a first input (e.g., a carry input) from a first FA of a second subset of FAs (e.g., 14T adders) and a second input (e.g., an operand) from a second FA of the second subset. In some embodiments, the FAs are arranged in rows and columns, the first FA of the second subset is located in the same row as the FAs of the first subset, and the second FA of the second subset is located in the same column as the FAs of the first subset. In some embodiments, each FA of the first subset provides a first output (e.g., a carry output) to a third FA of the second subset and a second output (e.g., a sum) to a fourth FA of the second subset. In some embodiments, the third FA of the second subset is located in the same row as the FAs of the first subset, and the fourth FA of the second subset is located in the same column as the FAs of the first subset. The present disclosure also provides various embodiments of novel 14T FA topologies.

[0016] Advantageously, embodiments of the disclosed adder tree can achieve several benefits. In some embodiments, the disclosed adder tree having two types of FAs has lower silicon (e.g., chip, transistor) area and lower power consumption compared to an adder tree using only FAs with stronger drive strength (e.g., 28 transistor FAs), while the impact on speed / drive strength can be negligible. Furthermore, the speed can be optimized by how the two types of FAs are arranged.

[0017] FIG. 1A A block diagram of an adder tree 100A is shown in accordance with some embodiments of the present application. The adder tree 100A includes a number of full adders (FAs). For example, as shown in FIG. 1A, the adder tree 100A includes FAs 105A, 105B, 105C, 105D, 110A, 110B, 110C, 110D, 115A, 115B, 115C, 115D, 120A, 120B, 120C, and 120D. While 16 adders are shown, the adder tree 100 can include any number of FAs while remaining within the scope of the present application. FIG. 1A

[0018] The FAs of the adder tree 100A can be arranged in rows and columns. For example, a first row can include FAs 105A-105D, a second row can include FAs 110A-110D, a third row can include FAs 115A-115D, and a fourth row can include FAs 120A-120D. While each row is shown as including 4 FAs, each row can include any number of FAs while remaining within the scope of the present application. Furthermore, one row can include a different number of FAs than another row. For example, the first and second rows can include N FAs, the third row can include N+1 FAs, and the fourth row can include N+2 FAs, where N is an integer value. In some embodiments, a first column can include 105A, 110A, 115A, and 120A, a second column can include 105B, 110B, 115B, and 120B, a third column can include 105C, 110C, 115C, and 120C, and a fourth column can include 105D, 110D, 115D, and 120D. While each column is shown as including 4 FAs, each column can include any number of FAs while remaining within the scope of the present application.

[0019] ​In some embodiments, two or more of the rows can be different / stacked layers / tiers of the same row. Rows that include multiple layers can be denoted herein as "row*". For example, a first row including 105A-105D and a second row including 110A-110D can be different layers of the same row*. In some embodiments, the different layers of the same row* (e.g., FA 105A-105D and 110A-110D) are coupled to and provide signals to another row* of FAs (e.g., FAs 115A-115D). For example, FA 105A and FA 110A are different layers of the same row* and FA 105A and FA 110A provide signals to FAs 115 located in another row*. While only two layers are shown in the first row*, one layer is shown in the second row*, and one layer is shown in the third row*, any number of layers can exist for each of the row* without departing from the scope of the application. For example, the first row* can have four layers, the second row* can have two layers, and the third row* can have one layer.

[0020] The FAs of adder tree 100A can be categorized into two subgroups (part, section, class, type, sub-type, plurality, etc.). In some embodiments, each FA of a first subgroup of FAs of adder tree 100A (e.g., FAs 105A, 105C, 110A, 110C, 115B, 115D, 120A, and 120C) includes a first number of transistors. For example, each FA of the first group of FAs includes 28 transistors. As shown in FIG. 1, the first subgroup category can be represented by the unpatterned fill of the corresponding boxes. In some embodiments, each FA of a second subgroup of FAs of adder tree 100A (e.g., FAs 105B, 105D, 110B, 110D, 115A, 115C, 120B, and 120D) includes a second number of transistors. For example, the second group of FAs includes 14 transistors. In some embodiments, each FA of the second subgroup of FAs of adder tree 100A consists of the second number of transistors. As shown in FIG. 1, the second subgroup category can be represented by the patterned fill of the corresponding boxes. FIG. 1A FIG. 1A ​As shown in the middle, the second subset of classifications can be represented by the dot pattern filling of the corresponding box. In some embodiments, the first number of transistors can include any number, for example, including 28, 20, 18, 16, 14, or 10, and the second number of transistors can include any number, for example, including 28, 20, 18, 16, 14, or 10. Any other first and second number of transistors are within the scope of the present disclosure. In some embodiments, the first number of transistors is greater than the second number of transistors. In some embodiments, each of the first subset of FAs has a first drive strength (e.g., a first speed, a first output conductance) to charge or discharge a capacitor coupled to an output of the FA, a first power consumption, and a first device area that are greater than a second drive strength (e.g., a second speed, a second output conductance), a second power consumption, and a second device area, respectively, of each of the second subset of FAs.

[0021] In some embodiments, the FAs are arranged such that the FAs of the second subset are disposed (e.g., inserted, placed, interleaved) between the FAs of the first subset. For example, FA 105B is disposed between FA 105A and FA 105C. In some embodiments, each FA of the first subset (e.g., a first FA, each FA receiving input from and providing output to two FAs) receives a first input (e.g., a carry input) from a first FA of the second subset, receives a second input (e.g., an operand) from a second FA of the second subset, provides a first output (e.g., a carry output) to a third FA of the second subset, and provides a second output (e.g., a sum) to a fourth FA of the second subset. For example, FA 115B receives a carry input from FA 115A through line 115B1 and receives a first operand from FA 105B through line 115B2, and FA 115B provides a carry output to FA 115C through line 115B4 and provides a sum to FA 120B through line 115B5. In some embodiments, each FA of the first subset receives a third input from a fifth FA of the second subset. For example, FA 115B receives a second operand from FA 110B through line 115B3.

[0022] In some embodiments, each FA of the second subset receives a first input from a first FA of the first subset, receives a second input from a second FA of the first subset, provides a first output to a third FA of the first subset, and provides a second output to a fourth FA of the first subset. For example, FA 115C receives a carry input from FA 115B through line 115B4 and receives an operand from FA 105C through line 115C2, and FA 115C provides a carry output to FA 115D through line 115C4 and provides a sum to FA 120C through line 115C5.

[0023] In some embodiments, each adjacent pair of FAs is coupled via a wire (e.g., an electrical wire, a conductor, a connection, etc.). For example, wire 115B1 couples FA 115A to FA 115B, wire 115B2 couples FA 105B to FA 115B, wire 115B3 couples FA 110B to FA 115B, wire 115B4 couples FA 115B to FA 115C, and wire 115B5 couples FA 115B to FA 120B. Further, in some embodiments, wire 115C2 couples FA 105C to FA 115C, wire 115C3 couples FA 110C to FA 115C, wire 115C4 couples FA 115C to FA 115D, and wire 115C5 couples FA 115C to FA 120C. In some embodiments, each of the wires couples a first subset of FAs to a second subset of FAs.

[0024] In some embodiments, a signal is provided to or received from an FA in an adjacent row or column. In some embodiments, each signal represents a bit. In some embodiments, a carry-in (Ci) signal is received by a first FA from a second FA in an adjacent column (e.g., to the left), a first input (A) signal is received by the first FA from a third FA in an adjacent row (e.g., above), a second input (B) signal is received by the first FA from a fourth FA in an adjacent row (e.g., above), a carry-out (Co) signal is provided by the first FA to a fifth FA in an adjacent column (e.g., to the right), and a sum signal is provided by the FA to a sixth FA in an adjacent row (e.g., below).

[0025] The FA can determine (e.g., process, produce, generate) a sum and a Co based on A (e.g., a first operand), B (e.g., a second operand), and Ci. For example, the FA determines a sum signal as a sum of the A signal and the B signal. The following truth table shows a mapping of A, B, and Ci to the output sum and Co.

[0026]

[0027]

[0028] In some embodiments, a signal is provided or received via a respective wire. For example, wire 115B1 provides Ci to 115B, wire 115B2 provides the A signal to 115B, wire 115B3 provides the B signal to 115B, wire 115B4 provides the Co signal from 115B, and wire 115B5 provides the sum signal from 115B.

[0029] Each FA can include a number of ports (e.g., terminals, electrodes) for providing or receiving signals. In some embodiments, each FA includes a port that receives a Ci signal, an A port that receives an A signal, a B port that receives a B signal, a carry-out (Co) port that provides a Co signal, and a port that provides a sum signal.

[0030] Adjacent pairs of FAs in the same row (e.g., in the same layer of the same row) can be coupled between their respective Ci and Co ports. For example, wire 115B1 couples the Co port of FA 115A to the Ci port of 115B. Likewise, the Co port of 115B can be coupled to the Ci port of 115C, and the Co port of 115C can be coupled to the Ci port of 115D.

[0031] Adjacent pairs of FAs in the same column can be coupled between their respective A and sum ports or B and sum ports. For example, wire 115B2 couples the sum port of FA 105B to the A port of 115B. Likewise, the sum port of 110B can be coupled to the B port of 115B, and the sum port of 115B can be coupled to the A port of 120B.

[0032] In some embodiments, the adder is arranged as a number of multi-bit FAs. For example, multi-bit FA 105 can include FAs 105A-105D, multi-bit FA 110 can include FAs 110A-110D, multi-bit FA 115 can include FAs 115A-115D, and multi-bit FA 120 can include FAs 120A-120D. Each multi-bit FA can be arranged along a respective row (e.g., a respective layer of the respective row). In some embodiments, each FA represents one bit of the multi-bit FA. For example, in multi-bit FA 115, FA 115A can represent a first bit, FA 115B can represent a second bit, FA 115C can represent a third bit, and FA 115D can represent a fourth bit. In some embodiments, a carry bit propagates through the FAs of a multi-bit FA via the Ci and Co ports.

[0033] In some embodiments, the first multi-bit FA receives the operands from the second multi-bit FA. For example, multi-bit FA 115 receives a first number of operand bits from multi-bit FA 105. For example, FA 115A receives a first operand bit from FA 105A, FA 115B receives a second operand bit from FA 105B, FA 115C receives a third operand bit from FA 105C, and FA 115D receives a fourth operand bit from FA 105D. Further, in some embodiments, multi-bit FA 115 receives a second number of operand bits from multi-bit FA 110. For example, FA 115A receives a fifth operand bit from FA 110A, FA 115B receives a sixth operand bit from FA 110B, FA 115C receives a seventh operand bit from FA 110C, and FA 115D receives an eighth operand bit from FA 110D.

[0034] In some embodiments, the multi-bit FA that receives the first number of operand bits and the second number of operand bits is a larger multi-bit FA than the multi-bit FA that provides the first number of operand bits and the multi-bit FA that provides the second number of operand bits. For example, multi-bit FA 105 is an N-bit FA, multi-bit FA 110 is an N-bit FA, and multi-bit FA 115 is an N+1-bit FA. In some embodiments, another FA of multi-bit FA 115 receives the first carry-in bit from FA 105D and the second carry-in bit from FA 110D.

[0035] In some embodiments, the first multi-bit FA computes a sum of the operands received from the second multi-bit FA. For example, multi-bit FA 115 computes a sum of the first number of operand bits received from multi-bit FA 105 and the second number of operand bits received from multi-bit FA 110 to generate a number of sum bits. For example, FA 115A computes a sum of the first operand bit from FA 105A and the fifth operand bit from FA 110A to generate a first sum bit, FA 115B computes a sum of the second operand bit from FA 105B and the sixth operand bit from FA 110B to generate a second sum bit, FA 115C computes a sum of the third operand bit from FA 105C and the seventh operand bit from FA 110C to generate a third sum bit, and FA 115D computes a sum of the fourth operand bit from FA 105D and the eighth operand bit from FA 110D to generate a fourth sum bit. In some embodiments, another FA of multi-bit FA 115 computes a sum of the first carry-in bit received from FA 105D and the second carry-in bit received from FA 110D.

[0036] In some embodiments, the first multi-bit FA provides a sum to a third multi-bit FA. For example, multi-bit FA 115 provides a number of sum bits to multi-bit FA 120. For example, FA 115A provides a first sum bit to FA 120A, FA 115B provides a second sum bit to FA 120B, FA 115C provides a third sum bit to FA 120C, and FA 115D provides a fourth sum bit to FA 120D. In some embodiments, the multi-bit FA that receives the number of sum bits is a larger multi-bit FA than the multi-bit FA that provides the number of sum bits. For example, multi-bit FA 115 is an N-bit FA and multi-bit FA 120 is an N+1-bit FA. In some embodiments, FA 115D provides a carry-out bit to another FA of multi-bit FA 120.

[0037] FIG. 1B A block diagram of adder tree 100B is shown, in accordance with some embodiments of the application. In some embodiments, adder tree 100B is a simplified view of adder tree 100A. For example, adder tree 100B omits FAs 110A-110D and omits lines (e.g., 115B3) that provide the second operand to the B port of the FAs. However, it should be understood that such FAs and lines are within the scope of the application and are omitted for the sake of brevity.

[0038] In some embodiments, the FAs are arranged in a pattern / order of one or more C, one or more D, where the pattern is repeating, where C is a first subset of FAs with more transistors, and D is a second subset of FAs with fewer transistors. In some embodiments, such as in the embodiments of FIG. 1B In some embodiments, the FAs are arranged in a pattern / order of C-D-C-D-etc. In some embodiments, the pattern can be arranged as rows. For example, in FIG. 1B In some embodiments, the FAs are arranged in a pattern / order of C-D-C-D-etc. In some embodiments, the pattern can be arranged as rows. For example, in

[0039] FIG. 1C A block diagram of adder tree 100C is shown, in accordance with some embodiments of the application. In some embodiments, adder tree 100C is similar to adder tree 100B, except that the FAs are arranged in a pattern / order of C-D-D-C-D-D-etc. For example, in FIG. 1CIn some embodiments, the FAs of the second subset are coupled to the FAs of the first subset in a pattern of C-D-E-D-C-D-E-D-etc., where E is an FA of the third subset having fewer transistors than D. For example, in FIG. 1B FA 105A(C) is coupled to FA 105B(D), FA 105B(D) is coupled to FA 105E(D), and FA 105E(D) is coupled to FA 105F(C). In some embodiments, FA 105E(D) replaces FIG. 1B FA 105C(C), FA 105F(C) replaces FIG. 1B FA 105D(D), FA 115E(D) replaces FIG. 1B FA 115D(C), and FA 120E(D) replaces

[0040] In some embodiments, each FA of the second subset (e.g., the first FA) receives a first input from a first FA of the first subset, receives a second input from a second FA of the second subset, provides a first output to a third FA of the second subset, and provides a second output to a second FA of the first subset. For example, FA 115C receives a carry input from FA 115B over line 115B4 and an operand from FA 105E over line 115C2, and FA 115C provides a carry output to FA 115E over line 115C4 and a sum to FA 120C over line 115C5. FIG. 1C FIG. 1C

[0041] FIG. 1D A block diagram of adder tree 100D is shown, in accordance with some embodiments of the application. In some embodiments, adder tree 100D is similar to adder tree 100B, except that the FAs of adder tree 100D can be classified into three subsets. In some embodiments, the FAs are arranged in a pattern / order of C-D-E-D-C-D-E-D-etc., where E is an FA of the third subset having fewer transistors than D. For example, in FIG. 1D FA 105A(C) is coupled to FA 105B(D), FA 105B(D) is coupled to FA 105G(E), FA 105G(E) is coupled to FA 105D(D). In some embodiments, FA 105G(E) replaces FIG. 1B FA 105C(C), FA 115G(E) replaces FIG. 1B FA 115D(C), and FA 120G(E) replaces FIG. 1B FA 120A(C).

[0042] ​​In some embodiments, each FA of the second subset (e.g., the first FA) receives a first input from a first FA of the first subset, receives a second input from a first FA of the third subset, provides a first output to a second FA of the third subset, and provides a second output to a second FA of the first subset. For example, FA 115C receives a carry input from FA 115B over line 115B4, and receives an operand from FA 105G of FIG. 1D over line 115C2, and FA 115C provides a carry output to FA 115G of FIG. 1D over line 115C4, and provides a sum to FA 120C over line 115C5.

[0043] While the foregoing FA arrangements have been described, any of a variety of FA patterns are within the scope of the present application. In some embodiments, the pattern includes one or more C, one or more D, wherein the pattern is repeated. For example, the FAs can be arranged in a C-C-D-C-C-D-etc. pattern. In some embodiments, the pattern includes one or more C, one or more D, and one or more E, wherein the pattern is repeated. In some embodiments, the pattern includes three or more subsets.

[0044] FIG. 2 A block diagram of a FA 200 is shown, in accordance with some embodiments of the present application. In some embodiments, FA 200 is an implementation of any of the FAs 105B, 105D, 110B, 110D, 115A, 115C, 120B, and 120D of FIG. 1A In some embodiments, FA 200 is an implementation of any of the FAs 105B, 105D, 110B, 110D, 115A, 115C, 120B, and 120D of FIG. 1A FA 200 includes stage 210. In some embodiments, stage 210 is configured to receive a first input (A) signal, a second input (B) signal, and in some embodiments, a third input signal and provide a first output signal. In some embodiments, stage 210 can be modeled as an exclusive-OR (XOR) gate, for example, taking as inputs the A signal, the B signal, and and taking as output the first output signal. The A signal can be provided via line 212, the signal can be provided via line 214, the B signal can be provided via line 216, and the first output signal can be provided via line 218. The signal can be an inverted instance of the B signal. The signals A, B, and may be provided by another FA or FAs, a global buffer, or any other various component via respective lines, while remaining within the scope of the present application.

[0045] FA 200 includes stage 220 coupled to stage 210 via line 218. In some embodiments, stage 220 is configured to receive the first output signal and provide a second output signal by inverting the first output signal. In some embodiments, stage 220 can be modeled as an inverter, e.g., with the first output signal as input and the second output signal as output. The second output signal can be provided via line 222.

[0046] FA 200 includes stage 230 coupled to stage 210 via line 218 and to stage 220 via line 222. In some embodiments, stage 230 is configured to receive a carry-in (Ci) signal, the first output signal, and the second output signal and provide a sum (S) signal. In some embodiments, stage 230 can be modeled as an XOR gate, e.g., with the Ci signal, the first output signal, and the second output signal as inputs and the S signal as output. In some embodiments, the Ci signal is provided via line 232, and the S signal is provided via line 234.

[0047] FA 200 includes stage 240 coupled to stage 210 via line 218, to stage 220 via lines 212 and 222, and to stage 230 via line 232. In some embodiments, stage 240 is configured to receive the Ci signal, the first output signal, the second output signal, and the A signal, and provide a carry-out (Co) signal. In some embodiments, stage 240 can be modeled as a multiplexer, e.g., with the A signal as a first input, the Ci signal as a second input, the first output signal as a control, the second output signal as a control inverse, and the Co signal as output. In some embodiments, the Co signal is provided via line 242.

[0048] FIG. 3 A circuit diagram of FA 200 is shown, in accordance with some embodiments of the present application. In some embodiments, FA 200 includes 14 transistors. The 14 transistors can be disposed between four stages, as described below.

[0049] In some embodiments, stage 210 includes transistors Ml 1, M12, M13, and M14, although stage 210 can include any various number of transistors without departing from the scope of the application. Transistors Ml 1 and M12 can be complementary (e.g., complementary metal-oxide-silicon or CMOS) pass transistors (e.g., pass gates). In some embodiments, Ml 1 is a p-type MOS (PMOS) transistor and M12 is an n-type MOS (NMOS) transistor, although Ml 1 and M12 can be any various types of transistors without departing from the scope of the application. In some embodiments, the gate, source, and drain of Ml 1 are coupled to lines 216, 212, and 218, respectively. In some embodiments, the gate, source, and drain of M12 are coupled to lines 214, 212, and 218, respectively.

[0050] In some embodiments, in response to receiving a first signal (e.g., bit, state, voltage level, etc.) from line 216, Ml 1 electrically couples line 212 to line 218. In some embodiments, in response to receiving a second signal from line 216, Ml 1 electrically decouples line 212 from line 218. In some embodiments, in response to receiving a first signal from line 214, M12 electrically couples line 212 to line 218. In some embodiments, in response to receiving a second signal from line 214, M12 electrically decouples line 212 from line 218.

[0051] Transistors M13 and M14 can be a complementary (e.g., CMOS) pair of transistors with their gates shorted to each other. In some embodiments, transistor M13 is an NMOS transistor and M14 is a PMOS transistor, although M13 and M14 can be any various types of transistors without departing from the scope of the application. In some embodiments, the gate, source, and drain of M13 are coupled to lines 212, 214, and 218, respectively. In some embodiments, the gate, source, and drain of M14 are coupled to lines 212, 216, and 218, respectively.

[0052] In some embodiments, in response to receiving a first signal from line 212, M13 electrically couples line 214 to line 218. In some embodiments, in response to receiving a second signal from line 212, M13 electrically decouples line 214 from line 218. In some embodiments, in response to receiving a first signal from line 212, M14 electrically couples line 216 to line 218. In some embodiments, in response to receiving a second signal from line 212, M14 electrically decouples line 216 from line 218.

[0053] In some embodiments, stage 220 includes transistors M21 and M22, although stage 220 can include any various number of transistors without departing from the scope of the application. In some embodiments, transistor M21 is a PMOS transistor and M22 is an NMOS transistor, although M21 and M22 can be any various types of transistors without departing from the scope of the application. In some embodiments, the gate, source, and drain of M21 are coupled to line 218, a first reference line (e.g., a VDD line that provides a VDD signal), and line 222, respectively. In some embodiments, the gate, source, and drain of M22 are coupled to line 218, a second reference line (e.g., a ground line that provides a ground signal), and line 222, respectively. In some embodiments, in response to receiving a first signal from line 218, M21 electrically couples line 222 to the first reference line, and M22 electrically decouples line 222 from the second reference line. In some embodiments, in response to receiving a second signal from line 218, M22 electrically couples line 214 to the second reference line, and M21 electrically decouples line 214 from the first reference line.

[0054] In some embodiments, stage 230 includes transistors M31, M32, M33, and M34, although stage 210 can include any various number of transistors without departing from the scope of the application. In some embodiments, stage 230 is similar to stage 210 (e.g., number and arrangement of transistors). For example, M31, M32, M33, and M34 are arranged in a manner similar to M11, M12, M13, and M14, respectively.

[0055] In some embodiments, in response to receiving a first signal from line 218, M31 electrically couples line 232 to line 234. In some embodiments, in response to receiving a second signal from line 218, M31 electrically decouples line 232 from line 234. In some embodiments, in response to receiving a first signal from line 222, M32 electrically couples line 232 to line 234. In some embodiments, in response to receiving a second signal from line 222, M32 electrically decouples line 232 from line 234.

[0056] In some embodiments, in response to receiving a first signal from line 232, M33 electrically couples line 222 to line 234. In some embodiments, in response to receiving a second signal from line 232, M33 electrically decouples line 222 from line 234. In some embodiments, in response to receiving a first signal from line 232, M34 electrically couples line 218 to line 234. In some embodiments, in response to receiving a second signal from line 232, M34 electrically decouples line 218 from line 234.

[0057] In some embodiments, stage 240 includes transistors M41, M42, M43, and M44, although stage 240 can include any various number of transistors without departing from the scope of the application. Transistors M41 and M42 can be a complementary pass gate, and transistors M43 and M44 can be a second complementary pass gate. Each of the transistor pairs M41 / M42 and M43 / M44 can be similar to complementary pass gate Ml l / M12.

[0058] In some embodiments, responsive to receiving a first signal from line 222, M41 electrically couples line 232 to line 242. In some embodiments, responsive to receiving a second signal from line 222, M41 electrically decouples line 232 from line 242. In some embodiments, responsive to receiving a first signal from line 218, M42 electrically couples line 232 to line 242. In some embodiments, responsive to receiving a second signal from line 218, M42 electrically decouples line 232 from line 242.

[0059] In some embodiments, responsive to receiving a first signal from line 218, M43 electrically couples line 212 to line 242. In some embodiments, responsive to receiving a second signal from line 218, M43 electrically decouples line 212 from line 242. In some embodiments, responsive to receiving a first signal from line 222, M44 electrically couples line 212 to line 242. In some embodiments, responsive to receiving a second signal from line 222, M44 electrically decouples line 212 from line 242.

[0060] FIG. 4A A flowchart of a method 400 of operating an adder tree is shown, in accordance with some embodiments of the present application. It should be noted that method 400 is an example and is not intended to limit the present application. Therefore, it is to be understood that additional operations can be provided before, during, and after method 400, and that some other operations can be provided, which are not shown FIG. 4A in accordance with some embodiments of the present application. It should be noted that method 400 is an example and is not intended to limit the present application. Therefore, it is to be understood that additional operations can be provided before, during, and after method 400, and that some other operations can be provided, which are not shown FIGS. 1A-3 in accordance with some embodiments of the present application. It should be noted that method 400 is an example and is not intended to limit the present application. Therefore, it is to be understood that additional operations can be provided before, during, and after method 400, and that some other operations can be provided, which are not shown FIG. 1A in accordance with some embodiments of the present application. It should be noted that method 400 is an example and is not intended to limit the present application. Therefore, it is to be understood that additional operations can be provided before, during, and after method 400, and that some other operations can be provided, which are not shown FIG. 2 in accordance with some embodiments of the present application. It should be noted that method 400 is an example and is not intended to limit the present application. Therefore, it is to be understood that additional operations can be provided before, during, and after method 400, and that some other operations can be provided, which are not shown

[0061] Method 400 begins with a first (e.g., first) of a first FA subset (e.g., 105A, 105C, 110A, 110C, 115B, 115D, 120A, and 120C) of a full adder (e.g., 100) receiving a first input (e.g., A) from a first input line (e.g., 202) and a second input (e.g., B) from a second input line (e.g., 204). FIG. 1A Method 400 begins with a first (e.g., first) of a first FA subset (e.g., 105A, 105C, 110A, 110C, 115B, 115D, 120A, and 120C) of a full adder (e.g., 100) receiving a first input (e.g., A) from a first input line (e.g., 202) and a second input (e.g., B) from a second input line (e.g., 204). FIG. 1A Method 400 begins with a first (e.g., first) of a first FA subset (e.g., 105A, 105C, 110A, 110C, 115B, 115D, 120A, and 120C) of a full adder (e.g., 100) receiving a first input (e.g., A) from a first input line (e.g., 202) and a second input (e.g., B) from a second input line (e.g., 204). FIG. 1A Method 400 begins with a first (e.g., first) of a first FA subset (e.g., 105A, 105C, 110A, 110C, 115B, 115D, 120A, and 120C) of a full adder (e.g., 100) receiving a first input (e.g., A) from a first input line (e.g., 202) and a second input (e.g., B) from a second input line (e.g., 204). FIG. 1AThe 115A receives the first input (e.g., via...). FIG. 1A The operation of line 115B1) 410. In some embodiments, each FA of the first FA subgroup includes a first number of transistors (e.g., 28 transistors), and each FA of the second FA subgroup includes a second number of transistors (e.g., including...). FIG. 3 (14 transistors of M11-M14, M21-M22, M31-M34, and M41-M44), and the first number is greater than the second number. Method 400 continues to the second (e.g., ) from the second FA subgroup. FIG. 1A 105B) receives a second input (e.g., via FIG. 1A Operation 420 of line 115B2). Method 400 continues to the third (e.g., of the second FA subgroup) of the second FA subgroup. FIG. 1A The 115C provides the first output (e.g., via...). FIG. 1A Operation 430 of line 115B4). Method 400 continues to the fourth (e.g., of the second FA subgroup) FIG. 1A The 120B provides a second output (e.g., via...). FIG. 1A Operation 440 of line 115B5).

[0062] In some embodiments, the first input is a first operand (e.g., a first sum generated by the first of the second FA subgroups), the second input is a first carry-out generated by the second of the second FA subgroups, the first output is a second sum generated by the first of the first FA subgroups, and the second output is a second carry-out generated by the first of the first FA subgroups. In some embodiments, the first input is received through port A of the first of the first FA subgroups, and the second input is received through the carry-in port of the first of the first FA subgroups, the first output is provided through the sum port of the first of the first FA subgroups, and the second output is provided through the carry-out port of the first of the first FA subgroups.

[0063] FIG. 4B A flowchart of a method 450 for operating an adder tree according to some embodiments of the present invention is shown. It should be noted that method 450 is merely an example and is not intended to limit the invention. Therefore, it should be understood that... FIG. 4B Additional operations are provided before, during, and after method 450, and some other operations can be briefly described herein. In some embodiments, method 450 is implemented by a full adder, such as... FIGS. 1A-3 Any full adder, including FIG. 1A Full adder 115B, FIG. 2 Full adder 200, etc.

[0064] Method 450 begins with the first full adder (FA) (e.g., FIG. 1A115B) from the second FA (e.g., FIG. 1A 105B) receives the first operand (e.g., via FIG. 1A Operation 460 of line 115B2), wherein the second FA has a first drive strength to provide a first operand to the first FA. The first drive strength may be embodied, modeled, or otherwise represented by a first output conductance of the second FA. The first drive strength may determine or otherwise influence a first rate at which the first FA is charged to a voltage level equal to the magnitude of the first operand.

[0065] Method 450 continues from the first FA to the third FA (e.g., FIG. 1A 110B) receives the second operand (e.g., via FIG. 1A The operation 470 of line 115B3) wherein the third FA has a first drive strength to provide a second operand to the first FA. In some embodiments, the method includes the first FA supplying a second operand to a fourth FA (e.g., line 115B3). FIG. 1A The 115A receives carry input (e.g., via...). FIG. 2-3 Line 115B1), wherein the fourth FA has a first drive strength to provide a carry input to the first FA. In some embodiments, the method includes generating a sum based at least on a first operand and a second operand. In some embodiments, the method includes generating a sum by the first FA based at least on the first operand, the second operand, and the carry input. In some embodiments, the generation includes performing at least one XOR operation and a multiplexing operation. Regarding FIG. 1A Further details of the operations used to generate the sum are described.

[0066] Method 450 continues from the first FA to the fifth FA (e.g., FIG. 1A 120B) provides the sum (e.g., via FIG. 1A Operation 480 of line 115B5, wherein the first FA has a second drive strength to provide a sum to the fifth FA. In some embodiments, the second drive strength is less than the first drive strength. In other embodiments, the second drive strength is greater than the first drive strength. The second drive strength can be embodied, modeled, or otherwise represented by a second output conductance of the first FA. The second drive strength can determine a second speed at which the fifth FA is charged to a voltage level equal to the magnitude of the sum. In some embodiments, the second conductance is less than the first conductance. In other embodiments, the second conductance is greater than the first conductance. In some embodiments, the second speed is less than the first speed. In other embodiments, the second speed is greater than the first speed.

[0067] In some embodiments, the method includes generating a carry output from a first FA based at least on a first operand and a second operand. In some embodiments, the method includes generating a carry output from a first FA based at least on a first operand, a second operand, and a carry input. In some embodiments, the method includes generating a carry output from the first FA to a sixth FA (e.g., FIG. 5 The 115C provides carry output (e.g., via...). FIG. 5 Line 115B4), wherein the first FA has a second drive strength to provide carry output to the sixth FA.

[0068] ​ This is a block diagram illustrating the configuration of a memory system 500 according to various embodiments of the present invention. As shown, the memory system 500 according to various embodiments of the present invention includes a non-volatile memory device 520 and a memory controller 510. In some embodiments, one or more blocks / components of the memory system 500 include an adder tree, such as adder tree 100A.

[0069] The non-volatile memory device 520 may include a 3D memory device, as disclosed herein. Furthermore, the non-volatile memory device 520 may be a multi-chip package comprising a plurality of ferroelectric memory chips.

[0070] Memory controller 510 is configured to control non-volatile memory device 520. Memory controller 510 may include RAM 511, central processing unit (CPU) 512, host interface (I / F) 513, error correction code (ECC) 514, and memory interface 515. RAM 511 serves as operating memory for CPU 512. RAM 511 may include the memory array described herein. CPU 512 implements general control operations for data exchange with memory controller 510. Host interface 513 includes a data exchange protocol coupled to a host computer of memory system 500. Furthermore, ECC 514 can detect and correct errors included in data read from non-volatile memory device 520. Memory interface 515 interfaces with non-volatile memory device 520. Memory controller 510 may also store code data for interfacing with the host computer.

[0071] In some aspects of the present invention, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs), comprising: a first FA subgroup, wherein each FA in the first subgroup includes a first number of transistors; and a second FA subgroup, wherein each FA in the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA in the first subgroup receives a first input from a first FA subgroup and a second input from a second FA subgroup, and each FA provides a first output to a third FA subgroup and a second output to a fourth FA subgroup.

[0072] In some respects, the first input is the operand received from the first of the second FA subgroup, the second input is the first carry-out received from the second of the second FA subgroup, the first output is the sum provided to the third of the second FA subgroup, and the second output is the second carry-out provided to the fourth of the second FA subgroup.

[0073] In some aspects, each FA in the second subgroup receives a third input from the first FA subgroup and a fourth input from the second FA subgroup, and each FA provides a third output to the third FA subgroup and a fourth output to the fourth FA subgroup. In some aspects, each FA in the second subgroup receives a third input from the fifth FA subgroup and provides a third output to the sixth FA subgroup.

[0074] In some aspects, the multiple FAs include multiple multi-bit FAs, wherein each multi-bit FA includes at least one of a first FA subgroup and at least one of a second FA subgroup. In some aspects, each multi-bit FA receives a third input from a first multi-bit FA and provides a third output to a second multi-bit FA. In some aspects, each multi-bit FA includes a third number of FAs, wherein the first multi-bit FA includes a fourth number of FAs, and wherein the second multi-bit FA includes a fifth number of FAs, the third number being one greater than the fourth number, and the fifth number being one greater than the third number.

[0075] In some aspects, each FA in the first subgroup has 28 transistors, and each FA in the second subgroup has 14 transistors. In some aspects, each FA in the first subgroup has 28 transistors, and each FA in the second subgroup has 10 transistors. In some aspects, each FA in the first subgroup has 28 transistors, and each FA in the second subgroup has 20 transistors. In some aspects, each FA in the first subgroup has 28 transistors, and each FA in the second subgroup has 16 transistors.

[0076] In some aspects of the present invention, an adder circuit is disclosed. In some aspects, the adder circuit includes: a first stage configured to receive a first input signal and a second input signal; and to provide a first output signal; a second stage coupled to the first stage and configured to invert the first output signal to provide a second output signal; a third stage coupled to the first and second stages and configured to receive a carry input signal, a first output signal, and a second output signal; and to provide a sum signal; and a fourth stage coupled to the first and second stages and configured to receive a carry input signal, the first input signal, the first output signal, and the second output signal; and to provide a carry output signal.

[0077] In some aspects, the first, second, third, and fourth stages collectively comprise 14 transistors. In some aspects, the first stage performs an XOR operation on the first and second input signals. In some aspects, the third stage performs an XOR operation on the carry-in signal and the first output signal. In some aspects, the fourth stage multiplexes the first output signal between the first input signal and the carry-in signal.

[0078] In some aspects, the first stage receives a third input signal as an inverted instance of the second input signal. In some aspects, the first stage includes a transmission gate and a pair of complementary transistors whose gates are shorted to each other.

[0079] In some aspects, a method of operating a full adder includes: receiving a first operand from a second FA by a first full adder (FA), wherein the second FA has a first drive strength to provide the first operand to the first FA; receiving a second operand from a third FA by the first FA, wherein the third FA has a first drive strength to provide the second operand to the first FA; and providing a sum from the first FA to a fourth FA, wherein the first FA has a second drive strength to provide the sum to the fourth FA, wherein the second drive strength is less than the first drive strength. In some embodiments, the method further includes: receiving a carry input by a fifth FA, wherein the fifth FA has a first drive strength to provide the carry input.

[0080] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An adder tree circuit, comprising a plurality of full adders, wherein the plurality of full adders include: A first full adder subgroup, wherein each full adder in the first full adder subgroup includes a first number of transistors; and The second full adder subgroup, wherein each full adder in the second full adder subgroup includes a second number of transistors, the first number being greater than the second number; In this configuration, each full adder of the first full adder subgroup receives a first input from the first of the second full adder subgroup and a second input from the second of the second full adder subgroup. The first input is an operand received from the first of the second full adder subgroup, and the second input is a first carry-out received from the second of the second full adder subgroup. Furthermore, each full adder of the first full adder subgroup provides a first output to the third of the second full adder subgroup and a second output to the fourth of the second full adder subgroup. The first output is a sum provided to the third of the second full adder subgroup, and the second output is a second carry-out provided to the fourth of the second full adder subgroup.

2. The adder tree circuit according to claim 1, wherein, The drive strength of each full adder in the first full adder subgroup is greater than the drive strength of each full adder in the second full adder subgroup.

3. The adder tree circuit according to claim 1, wherein, Each full adder in the second full adder subgroup receives a third input from the first full adder subgroup and a fourth input from the second full adder subgroup. Each full adder provides a third output to the third full adder subgroup and a fourth output to the fourth full adder subgroup.

4. The adder tree circuit according to claim 1, wherein, Each full adder in the second full adder subgroup receives a third input from the fifth full adder in the second full adder subgroup and provides a third output to the sixth full adder in the second full adder subgroup.

5. The adder tree circuit according to claim 1, wherein, The plurality of full adders include a plurality of multi-bit full adders, wherein each multi-bit full adder includes at least one of the first full adder subgroup and at least one of the second full adder subgroup.

6. The adder tree circuit according to claim 5, wherein, Each multi-bit full adder receives a third input from the first multi-bit full adder and provides a third output to the second multi-bit full adder.

7. The adder tree circuit according to claim 6, wherein, Each multi-bit full adder includes a third number of full adders, wherein the first multi-bit full adder includes a fourth number of full adders, and wherein the second multi-bit full adder includes a fifth number of full adders, wherein the third number is one greater than the fourth number, and the fifth number is one greater than the third number.

8. The adder tree circuit according to claim 1, wherein, Each full adder in the first full adder subgroup has 28 transistors, and each full adder in the second full adder subgroup has 14 transistors.

9. The adder tree circuit according to claim 1, wherein, Each full adder in the first full adder subgroup has 28 transistors, and each full adder in the second full adder subgroup has 10 transistors.

10. The adder tree circuit according to claim 1, wherein, Each full adder in the first full adder subgroup has 28 transistors, and each full adder in the second full adder subgroup has 20 transistors.

11. The adder tree circuit according to claim 1, wherein, Each full adder in the first full adder subgroup has 28 transistors, and each full adder in the second full adder subgroup has 16 transistors.

12. An adder circuit comprising a plurality of full adders, the plurality of full adders including a first full adder subgroup and a second full adder subgroup, each full adder in the first full adder subgroup including a first number of transistors, each full adder in the second full adder subgroup including a second number of transistors, the first number being greater than the second number. in, Each full adder in the first full adder subgroup receives a first input from the first of the second full adder subgroups and a second input from the second of the second full adder subgroups. The first input is an operand received from the first of the second full adder subgroups, and the second input is a first carry-out received from the second of the second full adder subgroups. Each full adder in the first full adder subgroups provides a first output to the third of the second full adder subgroups and a second output to the fourth of the second full adder subgroups. The first output is the sum provided to the third of the second full adder subgroups, and the second output is the second carry-out provided to the fourth of the second full adder subgroups. Each full adder in the second full adder subgroup includes: The first stage is configured to: receive a first input signal and a second input signal; and provide a first output signal; The second stage is coupled to the first stage and configured to invert the first output signal to provide a second output signal; The third stage, coupled to the first and second stages, is configured to: receive a carry input signal, the first output signal, and the second output signal; and provide an AND signal; and The fourth stage is coupled to the first stage and the second stage and is configured to: receive the carry input signal, the first input signal, the first output signal and the second output signal; and provide a carry output signal.

13. The adder circuit according to claim 12, wherein, The first stage, the second stage, the third stage, and the fourth stage together comprise 14 transistors.

14. The adder circuit according to claim 12, wherein, The first stage performs an XOR operation on the first input signal and the second input signal.

15. The adder circuit according to claim 12, wherein, The third stage performs an XOR operation on the carry input signal and the first output signal.

16. The adder circuit according to claim 12, wherein, The fourth stage multiplexes the first input signal and the carry input signal based on the first output signal.

17. The adder circuit according to claim 12, wherein, The first stage receives a third input signal, which is an inverted instance of the second input signal.

18. The adder circuit according to claim 12, wherein, The first stage includes a transmission gate and a pair of complementary transistors whose gates are shorted to each other.

19. A method of operating a full adder, comprising: A full adder is provided, the full adder comprising a first full adder subgroup and a second full adder subgroup; Each of the first full adders in the first full adder subgroup receives a first operand from a second full adder in the second full adder subgroup, wherein the second full adder has a first drive strength to provide the first operand to the first full adder; The first full adder receives a second operand from a third full adder in the second full adder subgroup, wherein the third full adder has the first drive strength to provide the second operand to the first full adder; The first full adder provides a sum to the fourth full adder of the second full adder subgroup, wherein the first full adder has a second drive strength to provide the sum to the fourth full adder, wherein the second drive strength is less than the first drive strength; and The first full adder receives a carry input from the fifth full adder of the second full adder subgroup, the fifth full adder having the first drive strength to provide the carry input.

20. The method according to claim 19, wherein, The first full adder is a multi-bit full adder.

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