An adaptive configuration storage-computing integrated array (SOC) chip and a configuration method

Abstract

The application discloses a self-adaptive configuration memory-computing integrated array SOC chip and a configuration method, the memory-computing integrated array of the self-adaptive configuration memory-computing integrated array SOC chip comprises memory-computing integrated subarrays for respectively executing an operation function and a storage function; a memory-computing control module reads actual execution task information, calculates specific proportions of array memory-computing functions according to a pre-set configuration scheme, and issues a configuration instruction; an array configurator reads the memory-computing mode configuration instruction issued by the memory-computing control module from a bus, and configures part of the subarrays in the memory-computing integrated array as a memory mode and part of the subarrays as a computing mode according to the instruction. The self-adaptive configuration of the memory-computing integrated array in the chip is realized, the memory-computing integrated array in the chip can flexibly adjust the memory-computing function selection of each subarray according to an actual task, and components such as ADC, DAC, CPU, memory, storage and the like can be multiplexed, thereby reducing the chip area, adapting to the needs of integration and miniaturization, and effectively reducing the chip cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor integrated circuits, and more particularly to a self-adaptive configuration memory-computing integrated array SOC chip and a configuration method. BACKGROUND

[0002] When the SOC chip performs a computing data function, the central processor is responsible for reading instructions, decoding instructions, and executing instructions. The memory and the processor perform data transmission through a data bus. In the face of big data analysis application scenarios, the bandwidth of the data bus seriously restricts the performance and energy efficiency of the processor; in addition, when the existing SOC chip needs to operate data in the memory, due to the need for frequent migration of data, the frequent migration of data during computing and memory access will cause serious transmission power consumption problems, resulting in large circuit power consumption and slow response.

[0003] The memory-computing integrated chip exists to solve the above problems, however, once the SOC chip architecture containing the memory-computing integrated array is customized, the circuit structure is fixed, the specific configuration of the memory-computing array and the corresponding function are also fixed, and cannot be flexibly adjusted according to the actual task quantity required by the SOC, resulting in waste of memory-computing array resources, and the method of expanding the memory-computing array area or adding arithmetic operation units is usually used to compensate, but this also leads to a large circuit area, which cannot adapt to the needs of integration and miniaturization.

[0004] Therefore, how to realize flexible configuration of the memory-computing integrated array SOC chip is a problem that those skilled in the art need to solve. SUMMARY

[0005] Therefore, the present application provides a self-adaptive configuration memory-computing integrated array SOC chip and a configuration method, which cooperates with the memory-computing control module, the array configuration device and the memory-computing integrated array in the chip to adaptively configure the memory-computing integrated array according to actual application requirements, can flexibly adjust according to actual tasks, so that the chip can flexibly adjust the conversion of the storage mode and the computing mode of each subarray in the memory-computing integrated array, and the rest of the components such as ADC and DAC can realize multiplexing, thereby reducing the chip area, adapting to the needs of integration and miniaturization, and effectively reducing the chip cost.

[0006] In order to achieve the above purpose, the present application adopts the following technical scheme:

[0007] A self-adaptive configuration memory-computing integrated array SOC chip, comprising: a memory-computing integrated array, an array configuration device and a memory-computing control module;

[0008] The memory-computing integrated array comprises a plurality of memory-computing integrated subarrays working in a storage mode or a computing mode;

[0009] The array configurator comprises an address decoding unit and a mode configuration unit; the address decoding unit is configured to select the storage-computing integrated sub-array to be set to the working mode; and the mode configuration unit is configured to configure the selected storage-computing integrated sub-array to the storage mode or the computing mode.

[0010] The storage-computing control module reads the actual task execution information, calculates the specific proportion of the array storage-computing function in combination with the configuration scheme, and sends a configuration instruction according to the specific proportion of the array storage-computing function.

[0011] Preferably, the self-adaptive configuration storage-computing integrated array SOC chip further comprises:

[0012] A bus is a common communication trunk for transmitting information among various functional components and modules.

[0013] A memory is configured to store programs and various data information.

[0014] A central processing unit is responsible for reading all instructions of the SOC chip, decoding and executing the instructions, and sending access instructions.

[0015] An internal memory is configured to temporarily store operation data in the central processing unit and exchange data with an external memory such as a hard disk; the operation data includes instruction decoding and obtained operands.

[0016] An analog-digital conversion module is connected to the bus at an input end and connected to the storage-computing integrated array at an output end, configured to convert operation data on the bus into an analog signal and transmit the analog signal to the storage-computing integrated array; the storage-computing integrated array performs analog vector-matrix multiplication on the analog signal and outputs an operation result.

[0017] A digital-analog conversion module is connected to the storage-computing integrated array at an input end and connected to the bus at an output end, configured to convert the analog vector-matrix multiplication result into a digital signal and transmit the digital signal to the bus.

[0018] Preferably, the address decoding unit in the array configurator is connected to the storage-computing integrated array and the bus, receives the configuration instruction sent by the storage-computing control module and the access instruction sent by the central processing unit through the bus, and selects the storage-computing integrated sub-array to be set; the storage-computing control module sends the configuration instruction to the bus, the central processing unit sends the access instruction to the bus, and the address decoding unit reads the two instructions from the bus and completes the selection work.

[0019] The mode configuration unit in the array configurator is connected to the storage-computing integrated array and the bus, receives the configuration instruction sent by the storage-computing control module through the bus, and outputs a level signal for configuring the working mode of the array, so as to modify the storage-computing integrated sub-array selected by the address decoding unit to the corresponding working mode.

[0020] Preferably, the memory-computing control module is provided with a configuration scheme, which comprises:

[0021] When the SOC chip does not perform convolution operation, the chip executes configuration scheme 1: in a unit time, the memory-computing control module reads the computing instruction and the access instruction from the bus, records the number of computing instructions N1 and the number of access instructions N2, and then determines the ratio of the number of access instructions to the number of computing instructions obtains the memory-computing ratio; the memory-computing ratio is divided into the current memory-computing ratio R and the working memory-computing ratio R0, wherein the current memory-computing ratio is the memory-computing ratio in the current state, and the working memory-computing ratio is the memory-computing ratio in the working state; when the absolute value of the difference between the working memory-computing ratio and the current memory-computing ratio is less than or equal to 10%, it is determined that the memory-computing integrated array configuration does not need to be updated, and the working memory-computing ratio R0 remains unchanged; when the absolute value of the difference between the working memory-computing ratio and the current memory-computing ratio is greater than 10%, the memory-computing integrated array configuration is updated, and the working memory-computing ratio R0 value is updated to the current memory-computing ratio R; the memory-computing control module obtains the current memory-computing integrated array configuration and calculates the next state configuration, outputs the configuration instruction one according to the current configuration and the next state configuration, the working memory-computing ratio is updated to the current memory-computing ratio, and the number of memory-computing integrated subarrays working in the computing mode / the number of memory-computing integrated subarrays working in the storage mode in the memory-computing integrated array = the working memory-computing ratio; the array configurator selects the memory-computing integrated subarrays whose working mode needs to be changed through the address decoding unit according to the array configuration of the previous state and the latest working memory-computing ratio, and the mode configuration unit changes the working mode of the selected memory-computing integrated subarrays;

[0022] When the SOC chip performs convolution operation of the convolutional neural network, the chip executes configuration scheme 2: the memory-computing control module reads the size of the convolution kernel row and column, calculates the next state configuration; when the row and column numbers are equal, the number of memory-computing integrated subarrays working in the computing mode in the next state should be the number of convolution kernel rows; when the row and column numbers are not equal, the number of memory-computing integrated subarrays working in the computing mode in the next state should be the larger value of the number of convolution kernel rows and columns; the memory-computing control module obtains the configuration of the current memory-computing integrated array, and outputs the configuration instruction two of the memory-computing integrated array according to the number of memory-computing integrated subarrays working in the computing mode in the next state;

[0023] Further, the configuration information one comprises the memory-computing integrated subarrays working in the computing mode and the memory-computing integrated subarrays working in the storage mode, wherein the proportion of the number of memory-computing integrated subarrays working in the computing mode to the number of memory-computing integrated arrays is the same as the working memory-computing ratio R0.

[0024] Furthermore, configuration information 2 includes in-memory compute subarrays that should operate in compute mode and in-memory compute subarrays that should operate in storage mode. The number of in-memory compute subarrays operating in compute mode is the same as the number of rows or columns of the convolution kernel, while the remaining in-memory compute subarrays operate in storage mode. The array configurator sets the corresponding array to operate in compute mode or storage mode according to the configuration information.

[0025] Preferably, the configuration scheme specifically includes: when the in-memory computing control module is listening to the instruction information in the bus, if the density of data retrieval operation instructions in the continuous memory address space within a few clock cycles is greater than a set threshold, then a portion of the in-memory computing subarray in the in-memory computing array is converted into storage mode, and the data in the corresponding address space is mapped to the in-memory computing subarray in storage mode according to a set quantity for storage.

[0026] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a SOC chip and configuration method for an adaptively configurable in-memory computing array. The SOC chip with the adaptively configurable in-memory computing array has multiple modules connected to its bus, including a central processing unit, an in-memory computing control module, an array configurator, an in-memory computing array, memory, and general-purpose memory. The in-memory computing array includes multiple configurable in-memory computing subarrays for dynamically configuring and performing data storage or simulating vector-matrix multiplication / convolution operations. Between the in-memory computing array and the bus, there are digital-to-analog converter (DAC) and analog-to-digital converter (ADC) modules for data conversion. The in-memory computing control module sends control signals to the array configurator for configuring the in-memory computing array via the bus based on bus data information. The array configurator includes a mode configuration unit and an address decoding unit. The mode configuration unit determines the mode that the in-memory computing subarray needs to switch to based on the control signals from the in-memory computing control module, while the address decoding unit selects the corresponding row of the in-memory computing array based on the control signals from the in-memory computing control module, thereby realizing the dynamic configuration of the in-memory computing array in the SOC chip. The SOC chip of this invention can flexibly adjust the working mode of each part of the in-memory computing array according to the actual workload, and the circuits such as ADC, DAC, and address decoding unit can be reused with other modules on the SOC chip, thereby reducing the circuit area and meeting the needs of integration and miniaturization. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0028] Figure 1The drawing is a self-adaptive configuration storage and calculation integrated array SOC chip structure schematic diagram provided by the present application.

[0029] Figure 2 The drawing is a self-adaptive configuration storage and calculation integrated array SOC chip structure schematic diagram provided by the present application.

[0030] Figure 3 The drawing is a configuration method flow schematic diagram provided by the present application.

[0031] Figure 4 The drawing is a configuration scheme one flow schematic diagram provided by the present application.

[0032] Figure 5 The drawing is a configuration scheme two flow schematic diagram provided by the present application.

[0033] Figure 6 The drawing is an array configurator configuration structure schematic diagram provided by the present application.

[0034] Figure 7 The drawing is an MRAM basic storage and calculation unit structure schematic diagram provided by the present application.

[0035] Figure 8 The drawing is an SRAM basic storage and calculation unit structure schematic diagram provided by the present application. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0037] The embodiments of the present application disclose a self-adaptive configuration storage and calculation integrated array SOC chip and a configuration method.

[0038] Embodiment 1

[0039] Figure 1 The drawing is a structure diagram of the self-adaptive configuration storage and calculation integrated array SOC chip of the embodiments of the present application. The self-adaptive configuration storage and calculation integrated array SOC chip comprises a storage and calculation control module 10, an array configurator 20 and a storage and calculation integrated array 30, other IP cores possibly carried by the SOC chip, and an SOC bus 40 carrying the above-mentioned modules.

[0040] The storage and calculation integrated array 30 comprises a plurality of configurable storage and calculation integrated sub-arrays for dynamically configuring to respectively perform data storage or analog vector-matrix multiplication / convolution operation.

[0041] The plurality of configurable memory-computing sub-arrays can be configurable memory-computing sub-arrays with the same structure, as shown in FIG. 1. Figure 2 As shown in FIG. 1, according to actual application requirements, a part of the configurable memory-computing sub-arrays can be configured for data computation, and another part can be configured for data storage. For example, the number of rows and the number of columns of each configurable memory-computing sub-array can be set according to actual application requirements. The embodiments of the present application do not limit this.

[0042] The array configurator 20 includes a mode configuration unit 20-1 and an address decoding unit 20-2, as shown in FIG. 2. Figure 2 The address decoding unit 20-2 selects the corresponding row of the memory-computing array that needs to be converted according to the control signal of the memory-computing control module. The mode configuration unit 20-1 configures the selected row as a storage mode or a computation mode according to the control signal of the memory-computing control module.

[0043] The memory-computing control module 10 combines and configures the configurable memory-computing sub-arrays according to the information on the bus 40, so as to realize dynamic configuration of the memory-computing array in the SOC.

[0044] According to actual application requirements, the configuration instructions required by the memory-computing array can be obtained through the data information transmitted by the bus 40.

[0045] Specifically, the memory-computing control module 10 generates configuration instructions to control the array configurator 20 according to the data information transmitted by the bus 40, sends control signals to the array configurator that configures the memory-computing array through the bus, and controls the mode configuration unit 20-1 and the address decoding unit 20-2 of the array configurator 20 to combine and configure the plurality of configurable memory-computing sub-arrays according to the control signal of the memory-computing control module 10, so as to select and control a certain number of configurable memory-computing sub-arrays to perform data computation, and another part to perform data storage. The dynamic configuration of the memory-computing array carried by the SOC chip is realized. Not only can the configuration of the memory-computing array be flexibly adjusted according to actual tasks, but also the peripheral circuits such as ADC and DAC can be multiplexed, thereby reducing the circuit area and meeting the needs of integration and miniaturization.

[0046] Embodiment 2

[0047] In another optional embodiment based on embodiment 1, as shown in FIG. 3, the adaptive configuration memory-computing array SOC chip can further include a digital-to-analog conversion module 30-1 and an analog-to-digital conversion module 30-2. Figure 2

[0048] ​The input end of the digital-to-analog conversion module 30-1 is connected to the bus 40, and the output end is connected to the input end of the storage-computation integrated array 30, for converting external input data or data to be processed from the bus into an analog signal and inputting the analog signal to the storage-computation integrated array 30, and the storage-computation integrated array 30 performs analog vector-matrix multiplication operation on the analog signal according to a control signal and outputs an analog operation result or stores the analog operation result in the storage-computation integrated array.

[0049] The input end of the analog-to-digital conversion module 30-2 is connected to the storage-computation integrated array 30, and the output end is connected to the bus 40, for converting the analog operation result or the stored data in the storage-computation integrated array into a digital signal and outputting the digital signal to the bus 40 for reading by other modules of the bus.

[0050] The storage-computation control module 10 is connected to the bus 40, for providing storage-computation integrated array configuration information according to bus data information, and the array configuration device receives the storage-computation integrated array configuration information and dynamically configures the configurable storage-computation integrated array according to the storage-computation integrated array configuration information; and the storage-computation control module 10 dynamically configures each circuit module connected thereto according to the configuration information.

[0051] The configuration information includes configuration information of the configurable storage-computation integrated sub-arrays 301-30 n , and includes storage-computation integrated sub-array address signals and storage-computation integrated sub-array mode signals, and the array configuration device dynamically configures the storage-computation integrated array connected thereto according to the configuration information.

[0052] The dynamic configuration can include controlling the working state of the corresponding part of each configurable storage-computation integrated sub-array 301-30 n according to the configuration information of the configurable storage-computation integrated sub-array 301-30 n , and respectively being a storage state and an operation state, so that the plurality of configurable storage-computation integrated sub-arrays 301-30 n achieve dynamic configuration of the working mode.

[0053] Embodiment 3

[0054] In one embodiment, the dynamic configuration method is as shown in Figure 3 , and specifically, when the SOC chip performs convolution operation in the convolutional neural network, scheme 2 is adopted for configuration; and when the convolution operation is not performed, scheme 1 is adopted for configuration.

[0055] When the SOC chip is in a normal working state and the convolution operation is not performed, the chip executes configuration scheme one, as shown in Figure 4 . In a unit time, the storage-computation control module reads the calculation instruction and the access instruction from the bus, records the number N1 of calculation instructions and the number N2 of access instructions, and then determines the ratio of the number of access instructions to the number of calculation instructions The ratio is named as the storage ratio. The storage ratio is divided into a current storage ratio R and a working storage ratio R0. When the absolute value of the difference between the working storage ratio and the current storage ratio is less than 10%, the configuration of the storage-computing array does not need to be updated, and the working storage ratio R0 is unchanged. When the absolute value of the difference between the working storage ratio and the current storage ratio is greater than 10%, the configuration of the storage-computing array is updated, and the working storage ratio R0 is updated to the value of the current storage ratio R. The storage-computing control module obtains the current array configuration and calculates the next state configuration, and outputs configuration information according to the current configuration and the next state configuration. The configuration information one includes the storage-computing integrated sub-arrays 30-3 that should work in the computing mode and the storage-computing integrated sub-arrays 30-3 that should work in the storage mode, wherein the proportion of the number of sub-arrays working in the computing mode to the total number of arrays is the same as the working storage ratio R0. The array configurator sets the corresponding arrays to work in the computing mode or the storage mode according to the configuration information.

[0056] When the SOC chip performs the convolution operation of the convolutional neural network, the chip performs the configuration scheme two, and the flowchart is as shown in Figure 5 The storage-computing control module reads the row and column sizes of the convolution kernel. When the row and column numbers are equal, the number of storage-computing arrays that should work in the computing mode in the next state should be the number of rows (or columns) of the convolution kernel. When the row and column numbers are not equal, the number of storage-computing arrays that should work in the computing mode in the next state should be the larger value of the number of rows and the number of columns of the convolution kernel. The storage-computing control module obtains the working mode of the current storage-computing array, and outputs the configuration information of the storage-computing array according to the number of storage-computing arrays that should work in the computing mode in the next state. The configuration information two includes the storage-computing integrated sub-arrays 30-3 that should work in the computing mode and the storage-computing integrated sub-arrays 30-3 that should work in the storage mode, wherein the number of storage-computing integrated sub-arrays working in the computing mode is the same as the row and column numbers of the convolution kernel, and the remaining storage-computing integrated sub-arrays 30-3 work in the storage mode. The array configurator sets the corresponding arrays to work in the computing mode or the storage mode according to the configuration information.

[0057] Embodiment 4

[0058] In one embodiment, according to the principle of spatial locality: whether it is an access instruction or an access data, the accessed memory cells tend to be aggregated in a smaller continuous area. We can also use the following configuration method: when the memory-computing control module 10 monitors the instruction information in the bus 40, if it is found that there are instructions for taking data from a large continuous memory address space within several clock cycles, in order to reduce the time cost of data taking operation and improve the working performance of the SOC chip, the data in the corresponding address space in the memory need to be collectively mapped to the memory-computing integrated array and stored. That is, the memory-computing control module 10 is always in the state of monitoring the instruction information of the bus 40, if the intensity of the data taking operation instruction from the continuous address space is greater than the set threshold, part of the memory-computing integrated sub-arrays 30-3 in the memory-computing integrated array 30 will be converted to storage mode, and the data of the address space will be mapped to the memory-computing integrated sub-arrays in storage mode according to the set number. The above-mentioned set threshold and set number can be pre-set according to actual conditions.

[0059] Embodiment 5

[0060] On the basis of embodiments 1-4, in one embodiment, the configuration mode of the array configurator is as shown in Figure 6 The array configurator outputs memory-computing cell address information (memory-computing cell is memory-computing integrated sub-array) through two address signal lines, and the memory-computing cell determines whether to work in computing mode or storage mode according to the level of the two connected address signal lines, and then executes the corresponding operation. When the address signal line 1 works and the address signal line 2 is in a silent state, the memory-computing integrated sub-array works in storage mode, and the address signal line 1 is used to select the memory-computing cell of the required memory address to write or read data information from the data line connected with the bus; when the address signal line 1 is in a silent state and the address signal line 2 works, the memory-computing integrated sub-array works in computing mode, and the address signal line 2 is used to select the memory-computing cell working in computing mode. At the same time, the memory-computing control module can read the working state of each memory-computing cell through the address signal line 2, which is used to calculate the configuration information of the next state.

[0061] For the address decoding unit in the array configurator, the array configurator receives the configuration information (including the address information of the memory-computing integrated sub-arrays that should work in storage mode and the memory-computing integrated sub-arrays that should work in computing mode) from the memory-computing control module, according to the binary information of allocating computing mode or storage mode to the memory-computing cell, and uses an n-line-2 n line decoder to control the signals of the two address signal lines.

[0062] For the memory-computing cell, we can use MRAM or SRAM as the basic memory-computing cell, as shown in Figure 7 , Figure 8 respectively.

[0063] The various embodiments described in this specification are implemented in a progressive manner, each embodiment focusing on the differences from other embodiments, and the same or similar parts between embodiments can be mutually referred to. For the apparatus disclosed by the embodiments, since it corresponds to the method disclosed by the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0064] The above description of disclosed embodiments enables one of ordinary skill in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those of ordinary skill in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Therefore, the application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A self-adaptive configuration memory-computing integrated array (SOC) chip, characterized in that, The application relates to a SOC chip, which comprises the following parts: a memory calculation integrated array, an array configurator and a memory calculation control module; the memory calculation integrated array comprises a plurality of memory calculation integrated sub-arrays; the array configurator comprises an address decoding unit and a mode configuration unit; the address decoding unit is used for selecting the memory calculation integrated sub-arrays to be set in a working mode; the mode configuration unit is used for configuring the selected memory calculation integrated sub-arrays into a storage mode or a calculation mode; the memory calculation control module reads actual execution task information, calculates the specific proportion of array memory calculation functions in combination with a configuration scheme, and issues a configuration instruction; two configuration schemes are included, and the specific configuration process is as follows: S1: when the SOC chip does not execute a convolution operation, a configuration scheme one is executed; S11: in a unit time, the memory calculation control module of the SOC chip reads a calculation instruction and a storage instruction, and records the number of calculation instructions and the number of storage instructions; S12: a calculation-storage ratio is obtained according to the ratio of the number of storage instructions to the number of calculation instructions; the calculation-storage ratio comprises a current calculation-storage ratio and a working calculation-storage ratio; S13: the configuration condition of the next state is calculated; when the absolute value of the difference between the working calculation-storage ratio and the current calculation-storage ratio is less than or equal to 10%, it is judged that the configuration condition of the memory calculation integrated array does not need to be updated, and the working calculation-storage ratio is unchanged; when the absolute value of the difference between the working calculation-storage ratio and the current calculation-storage ratio is greater than 10%, the configuration condition of the memory calculation integrated array is updated, and the working calculation-storage ratio value is updated as the current calculation-storage ratio; S14: the memory calculation control module obtains the current configuration condition of the memory calculation integrated array, and outputs a configuration instruction one according to the current configuration condition and the configuration condition of the next state; S2: when the SOC chip executes a convolution operation of a convolutional neural network, a configuration scheme two is executed; S21: the memory calculation control module reads the row and column sizes of a convolution kernel, and calculates the configuration condition of the next state; when the row and column numbers are equal, the number of memory calculation integrated sub-arrays working in the calculation mode in the next state configuration is the number of convolution kernel rows; when the row and column numbers are not equal, the number of memory calculation integrated sub-arrays working in the calculation mode in the next state configuration should be the maximum value of the number of convolution kernel rows and the number of convolution kernel columns; S22: the memory calculation control module obtains the configuration condition of the current memory calculation integrated array, and outputs a configuration instruction two of the memory calculation integrated array according to the current working mode condition and the configuration condition of the next state.

2. The self-adapting configuration storage and computation integrated array (SOC) chip according to claim 1, wherein, Furthermore, the SOC chip comprises the following parts: a bus as a common communication trunk for transmitting data information; a memory for storing programs and data information; a central processing unit responsible for reading all instructions of the SOC chip, decoding and executing the instructions, and issuing storage instructions; an internal memory for temporarily storing operation data in the central processing unit and data exchanged with an external memory; the operation data comprises instruction decoding and obtained operation numbers; a digital-analog conversion module, an input end of which is connected with the bus, and an output end of which is connected with the memory calculation integrated array, used for converting operation data on the bus into an analog signal and transmitting the analog signal to the memory calculation integrated array; the memory calculation integrated array performs analog vector-matrix multiplication operation on the analog signal and outputs operation results; an analog-digital conversion module, an input end of which is connected with the memory calculation integrated array, and an output end of which is connected with the bus, used for converting the operation results into a digital signal and transmitting the digital signal to the bus.

3. The self-adapting configuration storage and computing integrated array (SOC) chip according to claim 2, wherein, The address decoding unit in the array configurator is connected with the storage-computing integrated array and a bus, receives configuration instructions sent by the storage-computing control module and access instructions sent by the central processing unit through the bus, and selects the storage-computing integrated sub-arrays that need to work in the storage mode; The mode configuration unit in the array configurator is connected with the storage-computing integrated array and a bus, receives configuration instructions sent by the storage-computing control module through the bus, and outputs a level signal for configuring the working mode of the array, and modifies the storage-computing integrated sub-arrays selected by the address decoding unit to the corresponding working mode.

4. The self-adapting configuration storage and computation integrated array (SOC) chip according to claim 1, wherein, The configuration information one includes the storage-computing integrated sub-arrays that should work in the computing mode and the storage-computing integrated sub-arrays that should work in the storage mode, and the number of the storage-computing integrated sub-arrays working in the computing mode accounts for the same proportion of the number of the storage-computing integrated array as the working ratio.

5. The self-adapting configuration storage and computation integrated array (SOC) chip according to claim 1, wherein, The configuration information two includes the storage-computing integrated sub-arrays that should work in the computing mode and the storage-computing integrated sub-arrays that should work in the storage mode, and the number of the storage-computing integrated sub-arrays working in the computing mode is the same as the number of rows or columns of the convolution kernel, and the rest of the storage-computing integrated sub-arrays work in the storage mode; the array configurator sets the corresponding array to work in the computing mode or the storage mode according to the configuration information.

6. The self-adapting configuration storage and computation integrated array (SOC) chip of claim 1, wherein, The array configurator of the SOC chip realizes the working mode configuration of the computing-in-memory subarray through the level setting of two address signal lines; adopts n-line-2 n The address signal lines are controlled in level by an n-line-2 decoder.

7. The self-adapting configuration storage and computation integrated array (SOC) chip according to claim 2, wherein, The configuration scheme specifically includes: when the storage-computing control module listens to the instruction information in the bus, if the intensity of the data operation instruction in the continuous memory address space is greater than the set threshold value in a plurality of clock cycles, then the part of the storage-computing integrated sub-arrays in the storage-computing integrated array is converted to the storage mode, and the data of the corresponding address space is mapped to the storage-computing integrated sub-arrays in the storage mode according to the set number for storage.

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