A method and system for optimizing selection of decoupling capacitors

Abstract

The present invention proposes a decoupling capacitor optimization selection method and system, which does not need to be adjusted according to the simulation results each time, but directly selects all decoupling capacitors quantitatively according to the optimization selection strategy, directly achieves the optimization target in the selection process, and does not need to be optimized after selection. The overall calculation amount is small and easy to quantify; combined with the frequency domain characteristics of the PDN impedance curve, the corresponding decoupling capacitors are quantitatively selected through analysis and calculation, and the decoupling capacitor parameters and the layout rules and position distribution of the capacitors on the PCB board are determined by simulating and analyzing the resonant characteristics of the circuit board, so as to achieve the ideal decoupling effect with a small number of capacitors. The optimization selection method of the present invention can quantitatively select decoupling capacitors according to the PDN impedance characteristics, control the number of decoupling capacitors within the minimum range, and achieve the ideal decoupling effect. At the same time, the layout on the board is optimized, the influence of the distribution parameters on the PDN performance is reduced, and the circuit board space and engineering costs are saved.

Description

Technical Field

[0001] The invention belongs to the technical field of electronic circuits, and in particular relates to a method and system for optimizing and selecting a decoupling capacitor. Background Art

[0002] As high-speed, large-scale digital integrated circuits are rapidly developing towards high speed, low power consumption, and high density, the impact of power integrity on circuit design is becoming increasingly greater. Therefore, the design rationality of the power distribution network (PDN) has become a current research hotspot. In high-speed digital integrated circuits, due to the presence of parasitic parameters in the return path of the power supply, the parasitic parameters exist in parallel in the power path impedance and the ground path impedance, which will cause synchronous switching noise, track collapse noise, ground plane bounce noise, etc., thereby causing signal integrity problems. Therefore, the fundamental way to solve the problem of power integrity is to control the PDN impedance so that it does not exceed the target value. The PDN decoupling principle is as follows: Figure 1 As shown, taking the set target impedance as the standard, by adding decoupling capacitors, the PDN impedance meets the design requirements. By setting the target impedance threshold, the PDN impedance is designed and simulated so that it is less than the target impedance threshold within the target frequency range, thereby achieving the purpose of controlling power supply noise.

[0003] The existing methods for selecting decoupling capacitors usually include the large "V" method and the Decade method. The large "V" method is to select multiple capacitors of the same capacitance in parallel, and achieve the design goal of the power distribution network (hereinafter referred to as PDN) by continuously increasing the number of capacitors; the Decade method is to select capacitors of different orders of magnitude and achieve the PDN design goal by controlling the number of capacitors. These methods do not select capacitors in a targeted manner according to the frequency domain characteristics of each power network, but add capacitors of the same capacitance in large quantities to achieve the purpose of decoupling, making the selected decoupling capacitor parameters unreasonable and highly redundant, which to a certain extent causes the problems of complex circuit board wiring, waste of space, poor decoupling effect, and large influence of parasitic parameters, and also increases engineering costs. Summary of the invention

[0004] In view of the above problems, the present invention proposes a method for optimizing the selection of decoupling capacitors, the method comprising:

[0005] Determine the parameter range of total parasitic capacitance and total parasitic inductance that need to add decoupling capacitors;

[0006] Select the decoupling capacitor specifications and determine the total parasitic capacitance and total parasitic inductance of the selected decoupling capacitor;

[0007] Determine whether the total parasitic capacitance and total parasitic inductance of the selected decoupling capacitor are within the parameter range, if so;

[0008] Then, resonance simulation is performed on the PCB board to determine the PCB layout design of the decoupling capacitor and complete the optimal selection of the decoupling capacitor.

[0009] Furthermore, the total parasitic inductance L of the decoupling capacitor needs to be added all The upper limit value L max It is expressed as: Among them, Z o represents the target impedance, f o Indicates the target cutoff frequency; L all ≤L max ;

[0010] The lower limit of the total parasitic capacitance that needs to be added with decoupling capacitors C min It is expressed as: Among them, f e represents [0, f m ] range, the target impedance Z o The intersection point with the actual impedance Z, f m Indicates the maximum anti-resonance frequency of the actual impedance within the target cut-off frequency range; C all ≥C min .

[0011] Further, selecting the decoupling capacitor specifications includes the following steps:

[0012] According to the frequency point f c i Determine the i-th decoupling capacitor C i specifications and draw the decoupling capacitor C i The impedance curve Z Ci ;

[0013] Determine the impedance curve Z Ci With the target impedance Z o The smaller frequency intersection point f1 and the larger frequency intersection point f2;

[0014] If f1<f e And f2>f o , then the decoupling capacitor specification selection is completed, otherwise let i=i+1, according to the frequency point f c i+1 Determine the i+1th decoupling capacitor C i+1 Repeat the above steps to continue adding decoupling capacitors until the decoupling capacitor specification selection is completed.

[0015] Furthermore, according to the frequency point f c i Determine the i-th decoupling capacitor C i Specifications include:

[0016] Select the self-resonance frequency f from the capacitor librarysi Close to f m The capacitance is used as the i-th decoupling capacitor, Among them, f m It represents the maximum anti-resonance point of the actual impedance within the target cut-off frequency range, L is the parasitic inductance value of the selected capacitor, and C is the capacitance value.

[0017] Furthermore, f1≥f e Time frequency point f c i+1 The determination includes the following steps:

[0018] Judgment|f c i -f1|Is it less than 1 / 4*f c i ;

[0019] If |f c i -f1|>1 / 4*f c i , then let the frequency interval Δf1=|f c i -f1|,f c i+1 =f c i -Δf1;

[0020] If |f c i -f1|≤1 / 4*f c i , then let the frequency interval Δf1=1 / 4*f c i , f c i+1 =f c i -Δf1.

[0021] Furthermore, f1<f e And f2≤f o Time frequency point f c i+1 The determination includes the following steps:

[0022] Judgement|f c i -f2|Is it less than 1 / 4*f c i ;

[0023] If |f c i -f2|>1 / 4*f c i , then let the frequency interval Δf2=|fc i -f2|,f c i+1 =f c i +Δf2;

[0024] If |f c i -f2|≤1 / 4*f c i , then let the frequency interval Δf2=1 / 4*f c i , f c i+1 =f c i +Δf2.

[0025] Furthermore, the total parasitic capacitance value C of the selected decoupling capacitor all And the total parasitic inductance value L all It is expressed as:

[0026] If C all ≥C min And L all ≤L max , then perform resonance simulation on the PCB board and complete the optimal selection of decoupling capacitors.

[0027] The present invention also provides a decoupling capacitor optimization selection system, the system comprising a parameter determination unit, a specification selection unit, a calculation unit, a judgment unit, a simulation unit, and a layout design determination unit.

[0028] A parameter determination unit, used to determine the parameter range of the total parasitic capacitance and the total parasitic inductance of the decoupling capacitor to be added;

[0029] A specification selection unit is used to select the specification of the decoupling capacitor;

[0030] A calculation unit, used to determine the total parasitic capacitance value and the total parasitic inductance value of the selected decoupling capacitor;

[0031] A judging unit, used to judge whether the total parasitic capacitance value and the total parasitic inductance value of the selected decoupling capacitor are within the parameter range;

[0032] A simulation unit, used to perform resonance simulation on the PCB board;

[0033] The layout design determination unit is used to determine the PCB layout design of the decoupling capacitor and complete the optimization selection of the decoupling capacitor.

[0034] Furthermore, the parameter determination unit includes an upper limit determination module and a lower limit determination module.

[0035] Upper limit determination module, used to determine the total parasitic inductance L of the decoupling capacitor to be added all The upper limit value L max , Among them, Z o represents the target impedance, f o Indicates the target cutoff frequency; L all ≤L max ;

[0036] The lower limit value determination module is used to determine the lower limit value C of the total parasitic capacitance to which the decoupling capacitor needs to be added. min , Among them, f e represents [0, f m ] range, the target impedance Z o The intersection point with the actual impedance Z, f m Indicates the maximum anti-resonance point of the actual impedance within the target cutoff frequency range; C all ≥C min .

[0037] Furthermore, the specification selection unit includes a first determination module, a curve drawing module, an intersection determination module, a comparison module, and a second determination module.

[0038] The first determination module is used to determine the frequency point f c i Determine the i-th decoupling capacitor C i Specifications;

[0039] Curve drawing module, used to draw the decoupling capacitor C i The impedance curve Z Ci ;

[0040] Intersection point determination module, used to determine the impedance curve Z Ci With the target impedance Z o The smaller frequency intersection point f1 and the larger frequency intersection point f2;

[0041] Comparison module, used to compare the smaller frequency intersection point f1 with f e , the larger frequency intersection point f2 and f o size;

[0042] The second determination module is used when f2≤f o , f1≥f e And f2>f o When, according to the frequency point f c i+1 Determine the i+1th decoupling capacitor C i+1 specifications.

[0043] Furthermore, the first determination module is used to determine the frequency point fc i Determine the i-th decoupling capacitor C i Specifications include:

[0044] Select the self-resonance frequency f from the capacitor library si Close to f m The capacitance is used as the i-th decoupling capacitor, Among them, f m It represents the maximum anti-resonance point of the actual impedance within the target cut-off frequency range, L is the parasitic inductance value of the selected capacitor, and C is the capacitance value.

[0045] Furthermore, the second determination module includes a first judgment submodule and a first frequency point determination submodule.

[0046] The first judgment submodule is used to judge |f c i -f1|Is it less than 1 / 4*f c i ;

[0047] The first frequency point determination submodule is used to determine f1≥f e The frequency point f c i+1 , if |f c i -f1|>1 / 4*f c i , then let the frequency interval Δf1=|f c i -f1|,f c i+1 =f c i -Δf1; if |f c i -f1|≤1 / 4*f c i , then let the frequency interval Δf1=1 / 4*f c i , f c i+1 =f c i -Δf1.

[0048] Furthermore, the second determination module includes a second judgment submodule and a second frequency point determination submodule.

[0049] The second judgment submodule is used to judge |f c i -f2|Is it less than 1 / 4*f c i ;

[0050] The second frequency point determination submodule is used to determine f1<f e And f2≤f o The frequency point f c i+1 , if |f c i -f2|>1 / 4*f c i , then let the frequency interval Δf2=|f c i -f2|,f c i+1 =f c i +Δf2; if |f c i -f2|≤1 / 4*f c i , then let the frequency interval Δf2=1 / 4*f c i , f c i+1 =f c i +Δf2.

[0051] Furthermore, the calculation unit is used to determine the total parasitic capacitance and total parasitic inductance of the selected decoupling capacitor:

[0052] The total parasitic capacitance value C of the selected decoupling capacitor all And the total parasitic inductance value L all It is expressed as:

[0053] The decoupling capacitor optimization selection method and system of the present invention do not need to be adjusted according to the simulation results each time, but directly select all decoupling capacitors quantitatively according to the optimization selection strategy, directly achieve the optimization target in the selection process, and do not need to be optimized after selection. The overall calculation amount is small and easy to quantify; combined with the frequency domain characteristics of the PDN impedance curve, through analysis and calculation, the corresponding decoupling capacitors are quantitatively selected, and the decoupling capacitor parameters and the layout rules and position distribution of the capacitors on the PCB board are determined by simulating and analyzing the resonant characteristics of the circuit board, and the ideal decoupling effect is achieved with a small number of capacitors. The optimization selection method of the present invention can quantitatively select decoupling capacitors according to the PDN impedance characteristics, and control the number of decoupling capacitors within the minimum range while meeting the design requirements, so that the decoupling effect reaches an ideal state. At the same time, the layout on the board is optimized, the influence of the distribution parameters on the PDN performance is reduced, and the circuit board space and engineering costs are saved.

[0054] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the structures pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0056] Figure 1 A schematic diagram of the PDN decoupling principle in an embodiment of the present invention is shown;

[0057] Figure 2 A schematic diagram of the topological structure of the optimization method in an embodiment of the present invention is shown;

[0058] Figure 3 A schematic diagram of the process flow of a method for optimizing and selecting a decoupling capacitor in an embodiment of the present invention is shown;

[0059] Figure 4 A schematic diagram of a power supply impedance curve before optimization in an embodiment of the present invention is shown;

[0060] Figure 5 A schematic diagram of a power supply impedance curve after optimization using the present invention in an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] Usually, when engineers select decoupling capacitors (decoupling capacitors are capacitors installed at the power supply end of components in the circuit. This capacitor can provide a more stable power supply, and can also reduce the noise of the components coupled to the power supply end, and indirectly reduce the influence of the noise of this component on other components), they tend to choose capacitors with large capacitance based on experience, but this not only wastes space and cost, but also the decoupling effect may not meet the design requirements. The present invention is aimed at the power distribution network PDN of the PCB board, PCB is the standard name of the printed circuit board, and proposes an optimization selection strategy for decoupling capacitors. The characteristic of the lowest impedance at the self-resonance point of the capacitor is combined with the PDN impedance curve and the target impedance curve. Through analysis and calculation, the corresponding decoupling capacitors are quantitatively selected, and the optimal placement position of the decoupling capacitor on the PCB is determined in combination with the resonance simulation results of the PCB, so as to further enhance the decoupling effect of the capacitor. The optimization selection strategy proposed by the present invention selects decoupling capacitors quantitatively according to the PDN impedance characteristics, which can control the number of decoupling capacitors within a minimum range while meeting the design requirements, reduce the redundancy of decoupling capacitors, and save circuit board space and engineering costs.

[0063] Figure 2 FIG. 1 shows a schematic diagram of a topological structure of an optimization method in an embodiment of the present invention. Figure 2 The topological structure in the embodiment of the present invention includes target impedance parasitic parameter calculation, decoupling capacitor parameter calculation and selection strategy, decoupling capacitor quantity determination, PCB (printed circuit board) resonance simulation analysis, and PCB layout design of decoupling capacitors.

[0064] An embodiment of the present invention provides a method for optimizing and selecting a decoupling capacitor, the method comprising:

[0065] Determine the parameter range of total parasitic capacitance and total parasitic inductance that need to add decoupling capacitors;

[0066] Select the decoupling capacitor specifications and determine the total parasitic capacitance and total parasitic inductance of the selected decoupling capacitor;

[0067] Determine whether the total parasitic capacitance and total parasitic inductance of the selected decoupling capacitor are within the parameter range, if so;

[0068] Then, resonance simulation is performed on the PCB board to determine the PCB layout design of the decoupling capacitor and complete the optimal selection of the decoupling capacitor.

[0069] Figure 3 FIG. 1 is a schematic diagram showing a flow chart of a method for optimizing and selecting a decoupling capacitor in an embodiment of the present invention. Figure 3 The optimization selection method includes: setting the PDN decoupling target cutoff frequency f o And calculate the target impedance Z o; Through simulation, draw the actual impedance curve Z of the power distribution network PDN; judge in [0, f o ], is Z less than Z o ; if Z ≥ Z o , then calculate the parasitic parameter range of the decoupling capacitor; and execute the decoupling selection strategy to select the decoupling capacitor specification; determine whether the selected capacitor meets the parasitic parameter range; if it meets the parameter range, perform PCB board resonance simulation and determine the placement position of the decoupling capacitor, and end the decoupling capacitor optimization selection; if it does not meet the parameter range, adjust the number of decoupling capacitors until the selected capacitor meets the parasitic parameter range. The specific process of optimizing the selection of decoupling capacitors in the embodiment of the present invention is described in detail.

[0070] 1. Calculation of target impedance and parasitic parameters:

[0071] 1.1 The user sets the target cutoff frequency f of the power distribution network o ;

[0072] 1.2 Input the relevant parameters of the power distribution network and calculate the target impedance Z of the PDN o , draw the target impedance curve, and the target impedance calculation is shown in the following formula, where r is the ripple factor, V is the operating voltage, and I is the transient current of the operation:

[0073] 1.3 Perform PDN impedance analysis on the relevant power network and draw the actual impedance curve Z;

[0074] 1.4 Determine the value of [0, f o ], is Z less than Z o , if Z<Z o Then jump directly to step (4.2), otherwise execute step (1.5);

[0075] 1.5 is within the target frequency range, i.e. [0, f o ], find the maximum anti-resonance point of the impedance curve Z and mark its frequency as f m ; If there is no anti-resonance point in the target frequency range Z, the frequency point corresponding to the maximum impedance value on the curve Z is marked as f m ;

[0076] 1.6 in [0, f m ], find the impedance curves Z and Z o The intersection point f e , that is, Z = Z o The minimum frequency point of

[0077] 1.7 Calculate the parameter range of the total capacitance and total parasitic inductance of the decoupling capacitors that need to be added. The specific steps are as follows:

[0078] First, according to the maximum anti-resonance frequency f of the impedance curve Z m , select a capacitor from the capacitor library whose self-resonance frequency is close to f m The capacitance is used as the i-th decoupling capacitor (initial value i = 1), and its self-resonant frequency is f si , the self-resonant frequency (SRF) is calculated as shown in the formula, where L is the parasitic inductance of the capacitor and C is the capacitance:

[0079] Since the decoupling capacitor is [f e , f si ] is capacitive, in [f si , f o ] is inductive, then based on this characteristic, taking the target impedance as the benchmark, the total capacitance and total parasitic inductance threshold range of the decoupling capacitor can be calculated:

[0080] ① Capacitance at frequency f o When the capacitor is connected in parallel, it is inductive. Since the parasitic resistance (ESR-Equivalent Series Resistance) of the capacitor is very small, the capacitor impedance can be completely determined by its parasitic inductance. Taking the target impedance as the upper limit value, the upper limit value L of the total inductance L after the decoupling capacitors are connected in parallel can be obtained. max for: The total parasitic inductance L of the added decoupling capacitor is all Range: L all ≤L max ;

[0081] ②Capacitance at frequency f e When the decoupling capacitors are connected in parallel, the total capacitance C is capacitive. Since the parasitic resistance (ESR) of the capacitor is very small, the capacitor impedance can be completely determined by its capacitance value. Taking the target impedance as the upper limit, the lower limit C of the total capacitance C after the decoupling capacitors are connected in parallel can be obtained. min for: The total parasitic capacitance C of the added decoupling capacitor is all Range: C all ≥C min .

[0082] 2. Decoupling capacitor parameter calculation and selection method

[0083] 2.1 Initialization: Let variable i = 1, frequency point f c i =f m , where i represents the number of decoupling capacitors added;

[0084] 2.2 According to the frequency point f c i The i-th decoupling capacitor C can be determinedi Specifications: In the capacitor library, select its self-resonant frequency SRF and f c i Similar capacitors, and on this basis, find capacitors with the largest capacitance possible. In addition, to reduce the impedance of the anti-resonance point, you can appropriately choose capacitors with large ESR. The priority is to first choose capacitors with large capacitance, and then choose capacitors with large ESR as much as possible within this range (the former is more critical to choose a large capacitance, and the latter ESR selection is just a more optimized basis on this basis;

[0085] 2.3 Draw the decoupling capacitor C i The impedance curve Z Ci , with the target impedance as the reference, marked as Z Ci With Z o The frequency of the left intersection point is f1, that is, f1 is Z Ci =Z o The left boundary frequency point, that is, f1<f si ,

[0086] 2.4 Determine whether f1 is less than f e , if f1<f e , then execute step (2.10); if f1≥f e , then execute step (2.5);

[0087] 2.5 Judgment |f c i -f1|Is it less than 1 / 4*f c i , if |f c i -f1|>1 / 4*f c i , then execute step (2.7); if |f c i -f1|≤1 / 4*f c i , then execute step (2.6);

[0088] 2.6 Select the i+1th decoupling capacitor with the same specifications as C i Same, that is, C i+1 =C i , let Δf1=1 / 4*f c i , i=i+1, execute step (2.8);

[0089] 2.7 Let the frequency interval Δf1 = |f c i -f1|;

[0090] 2.8 Let f c i+1 =fc i -Δf1, i=i+1, return to execute step (2.2);

[0091] 2.9 Drawing C i The impedance curve Z Ci , with the target impedance as the reference, marked as Z Ci With Z o The right intersection frequency is f2, that is, f2 is Z Ci =Z o The right boundary frequency point, that is, f2>f si ;

[0092] 2.10 Determine whether f2 is greater than f o , if f2>f o , then execute step (2.15); if f2≤f o , then execute step (2.11);

[0093] 2.11 Judgment |f c i -f2|Is it less than 1 / 4*f c i ; if |f c i -f2|>1 / 4*f c i , then execute step (2.13); if |f c i -f2|≤1 / 4*f c i , then execute step (2.12);

[0094] 2.12 Select the i+1th decoupling capacitor with the same specifications as C1, that is, C i+1 =C1, let Δf2 = 1 / 4*f c i , i=i+1, execute step (2.14);

[0095] 2.13 Let the frequency interval Δf2 = |f c i -f2|;

[0096] 2.14 Let f c i+1 =f c i +Δf2, i=i+1, return to execute step (2.2);

[0097] 2.15 End of the decoupling capacitor specification selection step.

[0098] Specifically, in simple terms: First, select the i-th decoupling capacitor according to Section 2.2, and then there are four situations:

[0099] ①f1<f e And f2>f o : End the decoupling capacitor selection, that is, the i decoupling capacitors selected in Section 2.2 meet the requirements, and there is no need to add more decoupling capacitors (the previously added ones have already met the requirements);

[0100] ②f1<f e , f2≤f o : Continue to select decoupling capacitors (the capacitance added previously is not enough to meet the target impedance requirements, so more capacitance needs to be added, so proceed to the corresponding steps below);

[0101] ③f1≥f e , f2>f o : Continue to select decoupling capacitors (the capacitance added previously is not enough to meet the target impedance requirements, so more capacitance needs to be added, so proceed to the corresponding steps below);

[0102] ④f1≥f e , f2≤f o : Continue to select decoupling capacitors (the capacitance added previously is not enough to meet the target impedance requirements, and more capacitance needs to be added, so proceed to the corresponding steps below).

[0103] 3. Determination of the number of decoupling capacitors

[0104] 3.1 Calculate the total parasitic capacitance and total parasitic inductance of the selected capacitor:

[0105] 3.2 According to the parasitic parameter range obtained in step 1.7, determine the total capacitance value C of the selected decoupling capacitor all And the total parasitic inductance value L all Is it within the threshold range: If C all ≥C min And L all ≤L max , then execute step 4.1; otherwise, execute step (3.3);

[0106] 3.3 Let ΔC = C all -C min , from the selected decoupling capacitor C i Select a capacitor close to ΔC and set it as C i+1 , i=i+1, return to execute step (3.1).

[0107] 4. PCB layout design of decoupling capacitors

[0108] 4.1 Perform resonance simulation on the PCB board, mark the location where the resonance is more serious, and install the selected decoupling capacitor near the load chip, specifically in the area where the resonance is more serious, which can further increase the decoupling effect of the capacitor;

[0109] 4.2 Complete the optimization selection of decoupling capacitors.

[0110] 5. Simulation Analysis

[0111] Taking a printed circuit board of a project as an example, the present invention is simulated and verified. The VCC_1V2_2 power supply network is selected as the verification object, the voltage level is 1.2V, the chip working current is set to 0.2A, the ripple factor is 5%, and the decoupling target frequency is 100MHz. The decoupling capacitor optimization strategy proposed in the present invention is simulated and verified using Cadence Sigrity software (circuit design). The simulation results are as follows: Figure 4 , Figure 5 As shown, Figure 4 is the PDN impedance curve before optimization, Figure 5 is the optimized PDN impedance curve, Figure 4 , Figure 4 In the figure, the horizontal axis represents frequency, the vertical axis represents impedance, and the number of decoupling capacitors used before and after optimization is shown in Table 1. From the simulation results, it can be seen that the number of decoupling capacitors used after the optimization of the present invention is less, the cost is lower, the power supply impedance is lower, and the decoupling effect is better. Table 1 shows the results analysis before and after the optimization of the present invention:

[0112] Table 1 Comparison of results before and after optimization using the present invention

[0113]

[0114] In summary, the present invention can be used to quantitatively select decoupling capacitors for the power distribution network of the circuit board and determine the optimal placement position of the decoupling capacitors. On the basis of achieving the decoupling goal, the number of decoupling capacitors can be controlled to a minimum range, saving space and cost of the circuit board.

[0115] The embodiment of the present invention further provides a decoupling capacitor optimization selection system, the system comprising a parameter determination unit, a specification selection unit, a calculation unit, a judgment unit, a simulation unit, and a layout design determination unit.

[0116] A parameter determination unit, used to determine the parameter range of the total parasitic capacitance and the total parasitic inductance of the decoupling capacitor to be added;

[0117] A specification selection unit is used to select the specification of the decoupling capacitor;

[0118] A calculation unit, used to determine the total parasitic capacitance value and the total parasitic inductance value of the selected decoupling capacitor;

[0119] A judging unit, used to judge whether the total parasitic capacitance value and the total parasitic inductance value of the selected decoupling capacitor are within the parameter range;

[0120] A simulation unit, used to perform resonance simulation on the PCB board;

[0121] The layout design determination unit is used to determine the PCB layout design of the decoupling capacitor and complete the optimization selection of the decoupling capacitor.

[0122] Specifically, the parameter determination unit includes an upper limit determination module and a lower limit determination module.

[0123] Upper limit determination module, used to determine the total parasitic inductance L of the decoupling capacitor to be added all The upper limit value L max , Among them, Z o represents the target impedance, f o Indicates the target cutoff frequency; L all ≤L max ;

[0124] The lower limit value determination module is used to determine the lower limit value C of the total parasitic capacitance to which the decoupling capacitor needs to be added. min , Among them, f e represents [0, f m ] range, the target impedance Z o The intersection point with the actual impedance Z, f m Indicates the maximum anti-resonance point of the actual impedance within the target cutoff frequency range; C all ≥C min .

[0125] Specifically, the specification selection unit includes a first determination module, a curve drawing module, an intersection determination module, a comparison module, and a second determination module.

[0126] The first determination module is used to determine the frequency point f c i Determine the i-th decoupling capacitor C i Specifications;

[0127] Curve drawing module, used to draw the decoupling capacitor C i The impedance curve Z Ci ;

[0128] Intersection point determination module, used to determine the impedance curve Z Ci With the target impedance Z o The smaller frequency intersection point f1 and the larger frequency intersection point f2;

[0129] Comparison module, used to compare the smaller frequency intersection point f1 with f e, the larger frequency intersection point f2 and f o size;

[0130] The second determination module is used when f1≥f e 、f1<f e And f2≤f o When, according to the frequency point f c i+1 Determine the i+1th decoupling capacitor C i+1 specifications.

[0131] Specifically, the first determination module is used to determine the frequency point f c i Determine the i-th decoupling capacitor C i Specifications include:

[0132] Select the self-resonance frequency f from the capacitor library si Close to f m The capacitance is used as the i-th decoupling capacitor, Among them, f m It represents the maximum anti-resonance point of the actual impedance within the target cut-off frequency range, L is the parasitic inductance value of the selected capacitor, and C is the capacitance value.

[0133] Specifically, the second determination module includes a first judgment submodule and a first frequency point determination submodule.

[0134] The first judgment submodule is used to judge |f c i -f1|Is it less than 1 / 4*f c i ;

[0135] The first frequency point determination submodule is used to determine f1≥f e The frequency point f c i+1 , if |f c i -f1|>1 / 4*f c i , then let the frequency interval Δf1=|f c i -f1|,f c i+1 =f c i -Δf1; if |f c i -f1|≤1 / 4*f c i , then let the frequency interval Δf1=1 / 4*f c i , f c i+1 =fc i -Δf1.

[0136] Specifically, the second determination module includes a second judgment submodule and a second frequency point determination submodule.

[0137] The second judgment submodule is used to judge |f c i -f2|Is it less than 1 / 4*f c i ;

[0138] The second frequency point determination submodule is used to determine f1<f e And f2≤f o The frequency point f c i+1 , if |f c i -f2|>1 / 4*f c i , then let the frequency interval Δf2=|f c i -f2|,f c i+1 =f c i +Δf2; if |f c i -f2|≤1 / 4*f c i , then let the frequency interval Δf2=1 / 4*f c i , f c i+1 =f c i +Δf2.

[0139] Specifically, the calculation unit is used to determine the total parasitic capacitance value and the total parasitic inductance value of the selected decoupling capacitor: the total parasitic capacitance value C of the selected decoupling capacitor all And the total parasitic inductance value L all It is expressed as:

[0140] The decoupling capacitor optimization selection method and system of the present invention do not need to be adjusted according to the simulation results each time, but directly select all decoupling capacitors quantitatively according to the optimization selection strategy, directly achieve the optimization target in the selection process, and do not need to be optimized after selection. The overall calculation amount is small and easy to quantify; combined with the frequency domain characteristics of the PDN impedance curve, the corresponding decoupling capacitors are quantitatively selected through analysis and calculation, and the decoupling capacitor parameters and the layout rules and position distribution of the capacitors on the PCB board are determined by simulating and analyzing the resonant characteristics of the circuit board, so as to achieve the ideal decoupling effect with a small number of capacitors. The optimization selection method of the present invention can quantitatively select decoupling capacitors according to the PDN impedance characteristics, and control the number of decoupling capacitors within a minimum range while meeting the design requirements, so that the decoupling effect reaches an ideal state. At the same time, the layout on the board is optimized, the influence of the distribution parameters on the PDN performance is reduced, and the circuit board space and engineering costs are saved. The present invention can control the number of decoupling capacitors within a minimum range while meeting the design requirements, reduce the redundancy of the decoupling capacitors, and save the circuit board space and engineering costs.

[0141] Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent substitutions for some of the technical features therein; and these modifications or substitutions do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for optimizing the selection of decoupling capacitors, characterized in that: The method comprises: Determine the parameter range of total parasitic capacitance and total parasitic inductance of added decoupling capacitors; Select the decoupling capacitor specifications and determine the total parasitic capacitance and total parasitic inductance of the selected decoupling capacitor; Determine whether the total parasitic capacitance and total parasitic inductance of the selected decoupling capacitor are within the parameter range, if so; Then, resonance simulation is performed on the PCB board to determine the PCB layout design of the decoupling capacitor and complete the optimal selection of the decoupling capacitor; Selecting the decoupling capacitor specifications involves the following steps: According to the frequency point f c i Determine i Decoupling capacitors C i specifications and draw the decoupling capacitor C i Impedance curve Z Ci ; Determining the impedance curve Z Ci With target impedance Z o The smaller frequency crossover point f 1. Large frequency intersection f 2; like f 1< f e and f 2> f o , then the decoupling capacitor specification selection is completed, otherwise i = i +1, according to the frequency point f c i+1 Determine i +1 decoupling capacitor C i+1 Repeat the above steps to continue adding decoupling capacitors until the decoupling capacitor specification selection is completed.

2. The decoupling capacitor optimization selection method according to claim 1, characterized in that: Add the total parasitic inductance of the decoupling capacitors L all Upper limit of L max It is expressed as: ,in, Z o represents the target impedance, f o represents the target cutoff frequency; L all ≤ L max ; The lower limit of the total parasitic capacitance that needs to be added with decoupling capacitors C min It is expressed as: ,in, f e represents [0, f m ] range, the target impedance Z o The actual impedance Z The intersection of f m Indicates the maximum anti-resonance frequency of the actual impedance within the target cut-off frequency range; C all ≥ C min , C all Represents the total parasitic capacitance value of the selected decoupling capacitor.

3. The decoupling capacitor optimization selection method according to claim 1, characterized in that: According to the frequency point f c i Determine i Decoupling capacitors C i Specifications include: Select the self-resonance frequency from the capacitor bank f si near f m The capacitance is used as the i A decoupling capacitor, ,in, f m Indicates the maximum anti-resonance point of the actual impedance within the target cutoff frequency range. L To select the parasitic inductance value of the capacitor, C is the capacitance value.

4. The decoupling capacitor optimization selection method according to claim 1 or 3, characterized in that: f 1≥ f e Time frequency point f c i+1 The determination includes the following steps: Judgment | f c i - f 1|Is it less than 1 / 4* f c i ; If | f c i - f 1|>1 / 4* f c i , then let the frequency interval Δ f 1=| f c i - f 1|, f c i+1 = f c i -Δ f 1; If | f c i - f 1|≤1 / 4* f c i , then let the frequency interval Δ f 1=1 / 4* f c i , f c i+1 = f c i -Δ f 1.

5. The method for optimizing and selecting decoupling capacitors according to claim 4, characterized in that: f 1< f e and f 2≤ f o Time frequency point f c i+1 The determination includes the following steps: Judgment | f c i - f 2|Is it less than 1 / 4* f c i ; If | f c i - f 2|>1 / 4* f c i , then let the frequency interval Δ f 2=| f c i - f 2|, f c i+1 = f c i +Δ f 2; If | f c i - f 2|≤1 / 4* f c i , then let the frequency interval Δ f 2=1 / 4* f c i , f c i+1 = f c i +Δ f 2.

6. The method for optimizing and selecting decoupling capacitors according to claim 1, characterized in that: The total parasitic capacitance value of the selected decoupling capacitor C all and total parasitic inductance L all It is expressed as: , ; like C all ≥ C min and L all ≤ L max , then perform resonance simulation on the PCB board and complete the optimal selection of decoupling capacitors.

7. A decoupling capacitor optimization selection system, characterized in that: The system includes a parameter determination unit, a specification selection unit, a calculation unit, a judgment unit, a simulation unit, and a layout design determination unit. A parameter determination unit, used to determine the parameter range of the total parasitic capacitance and the total parasitic inductance of the added decoupling capacitor; A specification selection unit is used to select the specification of the decoupling capacitor; A calculation unit, used to determine the total parasitic capacitance value and the total parasitic inductance value of the selected decoupling capacitor; A judging unit, used to judge whether the total parasitic capacitance value and the total parasitic inductance value of the selected decoupling capacitor are within the parameter range; A simulation unit, used to perform resonance simulation on the PCB board; A layout design determination unit is used to determine the PCB layout design of the decoupling capacitor and complete the optimization selection of the decoupling capacitor; The specification selection unit includes a first determination module, a curve drawing module, an intersection determination module, a comparison module, and a second determination module. The first determination module is used to determine the frequency point f c i Determine i Decoupling capacitors C i Specifications; Curve drawing module for drawing decoupling capacitors C i Impedance curve Z Ci ; Intersection point determination module for determining impedance curves Z Ci With target impedance Z o The smaller frequency crossover point f 1. Large frequency intersection f 2; Comparison module for comparing smaller frequency intersections f 1 and f e , Larger frequency intersection f 2 and f o size; The second determining module is used when f 2≤ f o , f 1≥ f e and f 2> f o When, according to the frequency point f c i+1 Determine i +1 decoupling capacitor C i+1 specifications.

8. The decoupling capacitor optimization selection system according to claim 7, characterized in that: The parameter determination unit includes an upper limit determination module and a lower limit determination module. Upper limit determination module, used to determine the total parasitic inductance of the decoupling capacitor to be added L all Upper limit of L max , ,in, Z o represents the target impedance, f o represents the target cutoff frequency; L all ≤ L max ; A lower limit determination module is used to determine the lower limit of the total parasitic capacitance to which the decoupling capacitor needs to be added C min , ,in, f e represents [0, f m ] range, the target impedance Z o The actual impedance Z The intersection of f m Indicates the maximum anti-resonance point of the actual impedance within the target cut-off frequency range; C all ≥ C min , C all Represents the total parasitic capacitance value of the selected decoupling capacitor.

9. The decoupling capacitor optimization selection system according to claim 7, characterized in that: The first determination module is used to determine the frequency point f c i Determine i Decoupling capacitors C i Specifications include: Select the self-resonance frequency from the capacitor bank f si near f m The capacitance is used as the i A decoupling capacitor, ,in, f m Indicates the maximum anti-resonance point of the actual impedance within the target cutoff frequency range. L To select the parasitic inductance value of the capacitor, C is the capacitance value.

10. The decoupling capacitor optimization selection system according to claim 7 or 9, characterized in that: The second determination module includes a first judgment submodule and a first frequency point determination submodule. The first judgment submodule is used to judge | f c i - f 1|Is it less than 1 / 4* f c i ; The first frequency point determination submodule is used to determine f 1≥ f e Frequency point f c i+1 , if | f c i - f 1|>1 / 4* f c i , then let the frequency interval Δ f 1=| f c i - f 1|, f c i+1 = f c i -Δ f 1; if | f c i - f 1|≤1 / 4* f c i , then let the frequency interval Δ f 1=1 / 4* f c i , f c i+1 = f c i -Δ f 1.

11. The decoupling capacitor optimization selection system according to claim 10, characterized in that: The second determination module includes a second judgment submodule and a second frequency point determination submodule. The second judgment submodule is used to judge | f c i - f 2|Is it less than 1 / 4* f c i ; The second frequency point determination submodule is used to determine f 1< f e and f 2≤ f o Frequency point f c i+1 , if | f c i - f 2|>1 / 4* f c i , then let the frequency interval Δ f 2=| f c i - f 2|, f c i+1 = f c i +Δ f 2; if | f c i - f 2|≤1 / 4* f c i , then let the frequency interval Δ f 2=1 / 4* f c i , f c i+1 = f c i +Δ f 2.

12. The decoupling capacitor optimization selection system according to claim 7, characterized in that: Calculation unit to determine the total parasitic capacitance and total parasitic inductance of the selected decoupling capacitors: The total parasitic capacitance value of the selected decoupling capacitor C all and total parasitic inductance L all It is expressed as: , .

Images