Control circuit, integrated circuit, electronic converter and operating method

Abstract

Embodiments of the present disclosure relate to control circuits, integrated circuits, electronic converters, and operating methods. A sensing circuit for a power EFT monitors the current flowing through a FET and includes a regulating circuit that regulates a first current flowing through a sensing resistor so that a voltage drop in the sensing resistor corresponds to a voltage drop between the FET terminals. A measurement circuit provides a second circuit corresponding to (or proportional to) the first circuit. A first switch selectively applies a second current to a resistor based on a first control signal, and a low-pass filter generates a low-pass filtered signal by filtering out the resistance at the control circuit. A voltage follower generates a replica of the low-pass filtered signal, and a second switch selectively applies the replica to the resistor, and when the FET is closed, the control circuit closes the first electronic switch and opens the second electronic switch. When the FET is open, the control circuit opens the first electronic switch and closes the second electronic switch.

Description

[0001] Priority claim

[0002] This application claims the benefit of priority from Italian Patent Application No. 102020000028832, filed on November 27, 2020, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] Embodiments of the present disclosure relate to methods for measuring current flow in an electronic power converter, eg for controlling the electronic power converter and / or for reducing power losses in the electronic power converter. Background Art

[0004] Power supply circuits, such as AC / DC or DC / AC switching mode power supplies, are well known in the art. There are many types of electronic power converters, which are mainly divided into isolated converters and non-isolated converters. For example, non-isolated electronic power converters are "buck", "boost", "buck-boost", "SEPIC" and "ZETA" type converters. Different examples of isolated converters are "flyback", "forward", "half-bridge" and "full-bridge" type converters. Converters of this type are well known to those skilled in the art, as demonstrated, for example, by published application note AN 513 / 0393 "Topologies for switched-mode power supplies", L Wuidart, 1999, ST Microelectronics, the contents of which are incorporated herein by reference.

[0005] Figure 1 FIG is a schematic diagram of a DC / DC electronic power converter 20. Specifically, the universal electronic power converter 20 includes a circuit for receiving a DC voltage V in The two input terminals 200a and 200b are used to provide a DC voltage V out For example, the input voltage V in It can be provided by a DC voltage source 10 such as a battery, or it can be obtained from an AC voltage by using a rectifier circuit (such as a bridge rectifier) ​​and possibly a filtering circuit. out It can be used to supply power to the load 30 .

[0006] As is well known, an electronic power converter includes one or more reactive components, such as inductors and / or capacitors, and one or more electronic switches, which are configured to control: current flow from input terminals 200a and 200b to the one or more reactive elements, and / or current flow from the one or more reactive elements to output terminals 202a and 202b.

[0007] In order to reduce the power consumption of the converter, it has recently been proposed to use power switch partitioning, wherein one or more electronic switches of the electronic power converter 20 are implemented with: multiple electronic switches connected in parallel, and / or FETs, where the width of the active channel can be selectively controlled, thereby virtually implementing multiple electronic switches connected in parallel.

[0008] For example, Figure 2 An example is shown in which the electronic switch Q is implemented with a plurality of field effect transistors (FETs), such as four FETs Qa, Qb, Qc, and Qd, connected in parallel. In this case, the drain terminals of the plurality of FETs Qa-Qd are connected to a first terminal T1 and the source terminals of the plurality of FETs Qa-Qd are connected to a second terminal T2. Conversely, each of the gate terminals of the plurality of FETs Qa-Qd is connected to a corresponding terminal for receiving a corresponding drive signal, such as drive signals DRVa, DRVb, DRVc, and DRVd. In general, any number of parallel-connected electronic switches having corresponding drive signals may also be used.

[0009] Therefore, in this case, the control circuit of the electronic power converter may be configured to generate the drive signals DRVa-DRVd for the electronic switches Qa-Qd so as to select the number of electronic switches that should be closed simultaneously.

[0010] In practice, the primary source of losses in a switching power supply typically varies with different load currents. For example, at high output loads (high current flowing), the primary source of losses is the power converted into heat across the resistance of the electronic switch and the reactive element(s). At low output loads (low current flowing), the primary source is switching the electronic switch on and off. For example, the power required to switch the gate of a FET is typically fairly constant at any load, but as more current is drawn by the load, the power used to switch the gate becomes a less significant portion of the total power converted.

[0011] Therefore, when the electronic switch is divided into multiple parallel electronic switches, the effective size of the power switch can be controlled and the control circuit of the electronic power converter can be balanced: when the number of closed electronic switches is increased, the total on-resistance R DSon decreases; and when the number of closed electronic switches is reduced, switching losses are reduced.

[0012] For example, the control circuit can be configured to close more electronic switches Qa-Qd when high current flows, thereby reducing the on-resistance R DSon In this embodiment, the power loss in the switching operation is reduced, and when the low current flows, fewer electronic switches Qa-Qd are closed, thereby reducing the switching loss required to close the electronic switches Qa-Qd.

[0013] For example, in order to determine the number of electronic switches Qa-Qd that should be closed, i.e. the division of the electronic switches, the control circuit can determine a value that represents (and is preferably proportional to) the average current flowing through the electronic switches Q, i.e. the total current flowing through the electronic switches Qa-Qd.

[0014] Furthermore, in many applications, it may be useful to monitor (directly or indirectly) other currents (instantaneous or average values) of the electronic power converter 20, such as the current flowing through one or more reactive components and / or the current provided via the output terminals 202a / 202b. For example, such currents may be used to regulate the electronic power converter 20.

[0015] In view of the above, there is a need in the art to provide methods for monitoring current in electronic power converters, for example for determining the number of parallel-connected electronic switches to be closed. Summary of the Invention

[0016] According to one or more embodiments, one or more of the above objects are achieved by a control circuit for an electronic power converter. In addition, the embodiments also relate to related integrated circuits, electronic power converters, and methods for operating electronic power converters.

[0017] As described above, various embodiments of the present disclosure relate to sensor systems, for example, implemented in an integrated circuit. In various embodiments, the sensor system includes a power FET, the power FET including a first terminal and a second terminal defining a current path, and a gate terminal configured to receive a drive signal. The sensor system also includes a sensor circuit configured to monitor the current flowing through the power FET.

[0018] Specifically, in various embodiments, the sensor circuit includes a sensing resistor and a regulator circuit. Specifically, the regulator circuit is configured to: set a first current flowing through the sensing resistor to zero when a drive signal applied to a gate terminal indicates that the power FET is open, and to regulate the first current flowing through the sensing resistor so that a voltage drop across the sensing resistor corresponds to a voltage drop across a first terminal and a second terminal of the power FET when a drive signal applied to the gate terminal indicates that the power FET is closed.

[0019] For example, in various embodiments, the regulator circuit has a first FET that is a scaled version of a power FET, wherein a first terminal of the first FET is connected to a first terminal of the power FET, wherein a gate terminal of the first FET is configured to be driven with a drive signal of the power FET, wherein an on-resistance of the first FET represents a sense resistance. In this case, the sensor circuit may include:

[0020] an operational amplifier, wherein a first input terminal of the operational amplifier is connected to the second terminal of the power FET and a second input terminal of the operational amplifier is connected to the second terminal of the first FET, and

[0021] a variable current source configured to generate a first current according to a signal at an output terminal of the operational amplifier, wherein the first current generated by the variable current source is applied to the second terminal of the first FET, whereby the operational amplifier regulates the voltage at the second terminal of the first FET to the voltage at the second terminal of the power FET via the variable current source, and a first current flows through the first FET, the first current being proportional to the current flowing through the power FET.

[0022] For example, the variable current source may include a second FET, wherein a gate terminal of the second FET is connected to the output terminal of the operational amplifier. The variable current source may also include a current mirror configured to apply the current generated by the second FET to the second terminal of the first FET.

[0023] Therefore, as previously described, in various embodiments, the first current flowing through the sense resistor is proportional to the current flowing through the power FET. Therefore, the measurement circuit can be configured to provide a second current corresponding to or proportional to the first current. For example, a variable current source can directly provide the second current, or the measurement circuit can include: a third FET, wherein the gate terminal of the third FET is connected to the output terminal of the operational amplifier, or the measurement circuit further includes a current mirror configured to generate the second current by mirroring the current generated by the second FET.

[0024] In various embodiments, the sensor circuit is thus configured to monitor the second current. Specifically, in various embodiments, the sensor circuit includes a resistor and a first electronic switch configured to selectively apply the second current to the resistor according to a first control signal.

[0025] In various embodiments, the low-pass filter is configured to generate a low-pass filtered signal by filtering the voltage at the resistor, the voltage follower is configured to generate a copy of the low-pass filtered signal, and the second electronic switch is configured to selectively apply the copy of the low-pass filtered signal to the resistor.

[0026] Specifically, in various embodiments, the control circuit is configured to:

[0027] - when the power FET is closed, closing the first electronic switch and opening the second electronic switch, whereby the voltage at the resistor is proportional to the instantaneous value of the current flowing through the power FET, and

[0028] - when the power FET is off, opening the first electronic switch and closing the second electronic switch, whereby the voltage at the resistor corresponds to a low-pass filtered signal, and wherein the low-pass filtered signal is proportional to an average value of the current flowing through the power FET during the period when the power FET is closed.

[0029] For example, in this way, the control circuit can be configured to use two measurement phases. Specifically, during the first measurement phase, the control circuit can be configured to:

[0030] - when the power FET is closed, closing the first electronic switch and opening the second electronic switch, whereby the voltage at the resistor is proportional to the instantaneous value of the current flowing through the power FET, and

[0031] - when the power FET is off, opening the first electronic switch and closing the second electronic switch, whereby the voltage at the resistor corresponds to a low-pass filtered signal, and wherein the low-pass filtered signal is proportional to an average value of the current flowing through the power FET during the period when the power FET is closed.

[0032] Conversely, during the second measurement phase, the control circuit may be configured to maintain the second electronic switch open, and:

[0033] - when the power FET is closed, closing the first electronic switch, and

[0034] - opening the first electronic switch when the power FET is off, wherein the low-pass filtered signal is proportional to an average value of the current flowing through the power FET during the periods when the power FET is on and off.

[0035] For example, such a sensor system can be used in an electronic power converter. For example, in various embodiments, the electronic power converter includes two input terminals for receiving an input voltage and two output terminals for providing a regulated output voltage or a regulated output current. A switching circuit is connected between the two input terminals and the two output terminals, wherein the switching circuit includes at least one inductor, and a first power FET and a second power FET are configured to control a current flowing through the inductor.

[0036] In various embodiments, a control circuit is configured to generate control signals for a first power FET and a second power FET, wherein the control circuit is configured to operate an inductor of an electronic power converter in a continuous conduction mode by driving the first power FET and the second power FET using a switching cycle, the switching cycle comprising: a first phase in which the first power FET is closed and the second power FET is open, wherein a current flowing through the inductor linearly increases; and a second phase in which the first power FET is open and the second power FET is closed, wherein the current flowing through the inductor linearly decreases.

[0037] Thus, in this case, the sensor circuit according to the present disclosure can be used to monitor the current flowing through the first power FET or the second power FET, whereby (as will be described in more detail below) the low-pass filtered signal is proportional to the average value of the current flowing through the inductor.

[0038] In various embodiments, the first power FET is implemented by a first plurality of parallel FETs and the second power FET is implemented by a second plurality of parallel FETs. In this case, the control circuit can be configured to:

[0039] - obtaining a low-pass filtered signal proportional to the average value of the current flowing through the power FET during the period when the power FET is closed;

[0040] - determining a given number of FETs to be closed based on a low-pass filtered signal that is proportional to the average value of the current flowing through the power FETs during the period in which the power FETs are closed;

[0041] - during the first phase, closing a given number of FETs of the first plurality of parallel FETs; and

[0042] - During the second phase, a given number of FETs of the second plurality of parallel FETs are closed.

[0043] Additionally or alternatively, the control circuit can also use the signal generated by the sensor circuit to control the electronic power converter. For example, in various embodiments, the sensor circuit is configured to monitor the current flowing through the first power FET, and the control circuit can be configured to start the second phase when the voltage at the resistor reaches a given threshold.

[0044] Alternatively, the control circuit may be configured to vary the duration of the first phase and / or the second phase in dependence on an average value of the current flowing through the power FET during periods when the power FET is on and off.

[0045] This document also discloses a sensor circuit for a power FET. The sensor circuit is configured to monitor current flowing through the power FET and includes a sensing resistor and a regulator circuit configured to regulate a first current flowing through the sensing resistor such that a voltage drop across the sensing resistor corresponds to a voltage drop between a first terminal and a second terminal of the power FET. A measurement circuit is configured to provide a second current corresponding to or proportional to the first current.

[0046] In particular, the sensor circuit includes: a resistor; a first electronic switch configured to selectively apply a second current to the resistor based on a first control signal; and a low-pass filter configured to generate a low-pass filtered signal by filtering a voltage at the resistor. The sensor circuit also includes: a voltage follower configured to generate a copy of the low-pass filtered signal; and a second electronic switch configured to selectively apply the copy of the low-pass filtered signal to the resistor.

[0047] When the power FET is closed, the control circuit closes the first electronic switch and opens the second electronic switch, whereby the voltage at the resistor is proportional to the instantaneous value of the current flowing through the power FET. Conversely, when the power FET is open, the control circuit opens the first electronic switch and closes the second electronic switch, whereby the voltage at the resistor corresponds to a low-pass filtered signal, and wherein the low-pass filtered signal is proportional to the average value of the current flowing through the power FET during the period in which the power FET is closed. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Embodiments of the present disclosure will now be described with reference to the accompanying drawings, provided by way of non-limiting example only, in which:

[0049] Figure 1 An example of a known electronic power converter is shown;

[0050] Figure 2 An embodiment of a known power switch having multiple FETs connected in parallel is shown;

[0051] Figure 3 An embodiment of a buck converter disclosed herein is shown;

[0052] Figure 4 Shown Figure 3 Exemplary waveforms of the operation of the converter;

[0053] Figure 5A shows an exemplary waveform diagram of the electronic power converter disclosed herein when operating in CCM;

[0054] Figure 5B shows exemplary waveforms when the electronic power converter disclosed herein operates in DCM;

[0055] Figure 6 An embodiment of a buck converter including one or more current sensors as disclosed herein is shown;

[0056] Figure 7 An embodiment of a boost converter disclosed herein is shown;

[0057] Figure 8 and Figure 9 An embodiment of an electronic power converter disclosed herein is shown;

[0058] Figure 10 An embodiment of a sensor circuit configured to measure current flowing through an electronic switch of a boost converter as disclosed herein is shown;

[0059] Figure 11 An embodiment of a sensor circuit configured to measure an average current flowing through an inductor of a boost converter as disclosed herein is shown;

[0060] Figure 12 Shown Figure 11 An exemplary waveform diagram of the operation of the sensor circuit;

[0061] Figure 13 An embodiment of a sensor circuit configured to measure an average current flowing through an inductor of a buck or boost converter as disclosed herein is shown;

[0062] Figure 14 An embodiment of a sensor circuit configured to measure an average current flowing through an inductor of a buck converter as disclosed herein is shown;

[0063] Figure 15 A first embodiment of a sensor circuit configured to measure an average current of an inductor of a converter as disclosed herein is shown; and

[0064] Figure 16 A second embodiment of a sensor circuit as disclosed herein configured to measure an average current flowing through an inductor of a buck-boost converter is shown. DETAILED DESCRIPTION

[0065] In the following description, numerous specific details are provided to provide a thorough understanding of the embodiments. The embodiments may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0066] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0067] The headings provided herein are for convenience only and do not interpret the scope or meaning of the embodiments.

[0068] Already referenced Figure 1 and Figure 2 Described below Figures 3 to 16 Parts, elements or components in the drawings are indicated by the same reference numerals used previously in these figures; in order not to overburden the detailed description of the present invention, the description of these previously described elements will not be repeated below.

[0069] As above, the description of the present disclosure relates to methods for monitoring current in an electronic power converter, for example for performing partitioning of one or more electronic switches of the electronic power converter.

[0070] Figure 3 FIG. 1 shows a circuit diagram of an embodiment of a buck converter 20 a. In particular, the buck converter 20 a includes a circuit for receiving a DC input voltage V in The two input terminals 200a and 200b are used to provide a regulated voltage V out The two output terminals 202a and 202b, where the output voltage is equal to or lower than the input voltage V in .

[0071] In the embodiment considered, the buck converter 20a comprises two electronic switches Q1 and Q2 (with their current paths) connected in series (e.g., directly) between the input terminals 200a and 200b, wherein the intermediate node between the electronic switches Q1 and Q2 represents the switching node Lx. Specifically, the electronic switch Q1 is a high-side switch connected (e.g., directly) between the (positive) terminal 200a and the switching node Lx, and the electronic switch Q2 is a low-side switch connected (e.g., directly) between the switching node Lx and the (negative) terminal 200b, which generally represents ground GND. The (high-side) switch Q1 and the (low-side) switch Q2 thus represent the circuits configured to connect the switching node Lx to the terminal 200a (voltage V in ) or half bridge of terminal 200b (ground GND).

[0072] In various embodiments, switches Q1 and / or Q2 are transistors, such as field effect transistors (FETs), such as metal oxide semiconductor field effect transistors (MOSFETs) (e.g., n-channel FETs), such as NMOS transistors. Often, the second electronic switch Q2 is also implemented simply as a diode, with the anode connected to terminal 200b and the cathode connected to the switching node Lx.

[0073] In the example considered, an inductor L (such as an inductor) is connected (eg directly) between the switching node Lx and the (positive) output terminal 202a. Conversely, the (negative) output terminal 202b is connected (eg directly) to the (negative) input terminal 200b.

[0074] In the example considered, in order to stabilize the output voltage V out , the converter 20 typically includes a capacitor Cout connected (eg, directly) between the output terminals 202a and 202b.

[0075] In this context, Figure 4 Exemplary waveforms of signals of such an electronic power converter are shown, where:

[0076] - Figure 4 a shows a signal DRV1 for switching the electronic switch Q1;

[0077] - Figure 4 b shows a signal DRV2 for switching the second electronic switch Q2;

[0078] - Figure 4 c shows the current I through the electronic switch Q1 Q1 ;

[0079] - Figure 4 d shows the voltage V at the switching node Lx Lx (ie, the voltage at the second switch Q2); and

[0080] - Figure 4 e shows the current I through the inductor L L .

[0081] Specifically, when the electronic switch Q1 is closed at time t1 (ON state), the current I in the inductor L L (Basically) linear increase. At the same time, the electronic switch Q2 is turned off. On the contrary, when the electronic switch Q1 is at interval T2 ON1 After that, when the electronic switch Q2 is disconnected at time t2 (OFF state), the current I L Finally, the switch Q1 is switched off during the interval T OFF1In the example considered, when the switch Q1 is open, the switch Q2 is therefore closed, and vice versa. L It can therefore be used to charge capacitor Cout, which provides a voltage V at terminals 202a and 202b. out .

[0082] In the embodiment considered, the electronic power converter 20a therefore comprises a control circuit 22, the control circuit 22T ON1 T OFF1 is configured to drive the switching of the switch Q1 and the switch Q2 for periodically repeating the interval T ON1 and T OFF1 For example, the buck converter 20 typically further includes a feedback circuit 24 (such as a voltage divider) configured to generate an output voltage V out (and preferably with the output voltage V out The feedback signal FB is proportional to the reference signal (such as the reference voltage V ref ) are compared to generate driving signals DRV1 and DRV2.

[0083] A large number of driving schemes for generating the driving signals DRV1 and DRV2 are known. These schemes have in common that the interval T is adjusted. ON1 and / or interval T OFF1 The duration of the regulated output voltage V out possibility.

[0084] For example, in various embodiments, the control circuit 22 generates a pulse width modulation (PWM) signal DRV1 with a duty cycle T ON1 / (T ON1 +T OFF1 ) is variable, and the switching interval T SW =T ON1 +T OFF1 For example, a typical control scheme includes: a regulator circuit with at least one integral component, such as PI (proportional-integral) or PI D (Proportional-Integral-Derivative) regulator, changes the interval T ON1 duration.

[0085] Typically, a buck converter can operate in the following modes: continuous conduction mode (CCM), discontinuous conduction mode (DCM), or transition mode (TM). Typically, the control circuit can also be configured to selectively operate the switching stage in high power mode (HPM) or low power mode (LPM).

[0086] For example, in high power mode, the control circuit 22 may be configured to drive the switch in CCM mode. Figure 5A As shown, when the control circuit 22 operates the converter in CCM mode, the current I flowing through the inductor L L During the switching period T SW In this case, the control circuit 22 uses two switching phases T1 and T2, where T SW =T1+T2, where:

[0087] - In stage T1 (T1 = T ON1 =T OFF2 ), switch Q1 is closed and switch / diode Q2 is open; and

[0088] - In phase T2 (T2 = T OFF1 =T ON2 ), switch Q1 is open and switch / diode Q2 is closed.

[0089] In various embodiments, CCM uses constant frequency PWM modulation. For example, in this case, time t1 can be at a constant time T SW Then it starts periodically. On the contrary, time t2 can be determined based on the feedback signal FB and the reference signal V ref It is determined, for example:

[0090] - By using a device that is configured to directly change the duty cycle or on-time T ON1 Proportional Integral (PI) or Proportional Integral Derivative (PI D ) regulator to adjust the feedback signal FB to the reference signal V ref ;or

[0091] -When the current I flows through the inductor L L (or the value representing the current) reaches the maximum threshold value and ends the on-interval T ON1 , where PI or PI D The regulator is configured to change the maximum threshold in order to adjust the feedback signal FB to the reference signal V ref .

[0092] In contrast, in low power mode, the control circuit 22 can be configured to drive the switches in burst mode. Specifically, in this case, the control circuit 22 is configured to alternately close the electronic switches Q1 and Q2 for one or more cycles and then open the two electronic switches. Thus, in this case, the control circuit 22 actually uses (at least for the last burst) three switching phases T1, T2 and T3, where T SW =T1+T2+T3, where:

[0093] - In stage T1 (T1 = T ON1 ) during which switch Q1 is closed and switch / diode Q2 is open;

[0094] - In phase T2 (T2 = T ON2 ), switch Q1 is open and switch / diode Q2 is closed; and

[0095] -In stage T3(T OFF1 =T2+T3 and T OFF2 = T3 + T1), the switch Q1 is turned off and the switch / diode Q2 is turned off.

[0096] For example, Figure 5B As shown, the control circuit 22 can be configured to:

[0097] - opening the switch Q1 and closing the switch Q2 at a time t2 after a constant on-time or after an on-time determined according to the feedback signal FB;

[0098] -Preferably when the current I L Turning off the electronic switch Q2 when time t3 reaches zero, thereby reducing switching losses; and

[0099] - When the feedback signal FB reaches the lower threshold, a new switching cycle starts at time t1.

[0100] For example, the lower threshold may be based on the output voltage V out The reference signal V ref was determined.

[0101] In various embodiments, (typically fixed) dead times may also be introduced between switching of the drive signals, e.g., between the falling edge of signal DRV1 and the rising edge of signal DRV2, and similarly (in CCM mode) between the falling edge of signal DRV2 and the rising edge of signal DRV1. In this case, these intervals are typically longer than the duration T ON and T OFF These intervals are short and will not be considered in detail below.

[0102] Therefore, in essence, burst mode can correspond to a special case of DCM, where when the current I L When zero is reached, the electronic switch Q2 turns off (and remains off during interval T3).

[0103] like Figure 6 As shown, for this purpose, the control circuit 22 may include or be connected to a zero current detection (ZCD) circuit 26, which is configured to generate a zero current signal ZC, which indicates (at least) when the current IL The instant t3 at which the current reaches zero, in particular at least during the interval T2. For example, such a zero current detection circuit 26 may comprise a current sensor 26a connected directly in series with the inductor L, wherein the current sensor 26a provides an indication (and preferably is related to the current I L proportional to the current I flowing through the inductor L L signal CS1.

[0104] In various embodiments, current sensor 26a may also be replaced by a current sensor 26c connected directly in series with electronic switch Q2, wherein current sensor 26c provides an indication of (and is preferably related to) current I Q2 The current I flowing through the switch Q2 is proportional to Q2 The signal CS3 corresponds to the current I flowing through the inductor L during the interval T2. L .

[0105] For example, the zero current signal ZC may be determined via a comparator (so-called zero current comparator) of the circuit 26, which is configured, for example, to determine whether the monitored signal CS1 or CS3 falls below a given threshold (usually close to zero). Figure 5B An example of a zero current signal ZC is shown in FIG. 8 , which is set high when the measured current is less than a threshold value (close to zero).

[0106] Thus, in the embodiment considered, the electronic switches Q1 and Q2 are the power switches of the electronic power converter 20a. Figure 2 , such electronic switches Q1 and Q2 can be replaced by K parallel electronic switches or one electronic switch, and the K parallel electronic switches or one electronic switch can be divided into K sections. In this case, the control circuit 22 is therefore configured to generate a corresponding number K of drive signals (e.g., DRVa-DRVd) for each electronic switch Q1 and Q2, which select the number N of electronic switches Qa-Qd that should be closed. For example, in various embodiments, the electronic switches Q1 and Q2 are implemented with the same number of parallel-connected electronic switches Qa-Qd, i.e., K1=K2=K, and the control circuit 22 is configured to determine the number N of electronic switches Qa-Qd based on the measurement signal CS1, CS2, or CS3, and set the numbers N1 and N2 to N, i.e., N1=N2=N.

[0107] For example, to close a given number N1 of electronic switches Qa-Qd, the control circuit 22 may set the N1 drive signals DRVa-DRVd of the electronic switch Q1 to the aforementioned drive signal DRV1, and set the other K1-N1 drive signals DRVa-DRVd of the electronic switch Q1 to a logic level to keep the respective switches open (e.g., low). Similarly, to close a given number N2 of electronic switches Qa-Qd, the control circuit 22 may set the N2 drive signals DRVa-DRVd of the electronic switch Q2 to the aforementioned drive signal DRV2, and set the other K2-N2 drive signals DRVa-DRVd of the electronic switch Q2 to a logic level to keep the respective switches open (e.g., low).

[0108] As described above, to this end, the control circuit 22 should be able to monitor the average current flowing through each electronic switch Q1 and Q2, particularly during the intervals when the corresponding electronic switch Q1 or Q2 is closed, i.e., during interval T1 of electronic switch Q1 and during interval T2 of electronic switch Q2.

[0109] For example, Figure 6 , where the electronic power converter 20a further comprises a current sensor 26b connected directly in series with the electronic switch Q1, wherein the current sensor 26b provides a signal CS2 indicative of (and preferably proportional to) the current flowing through the switch Q1, the current flowing through the switch Q1 corresponding to the current I flowing through the inductor L during the interval T1. L .

[0110] Thus, in various embodiments, the electronic power converter 20a may include:

[0111] - a current sensor 26b configured to generate a current I indicative of the current flowing through the electronic switch Q1 Q1 a signal CS2 which is the instantaneous value of (and preferably proportional to)

[0112] - a current sensor 26c configured to generate a current I indicative of the current flowing through the electronic switch Q2 Q2 a signal CS3 which is the instantaneous value of (and preferably proportional to)

[0113] a current sensor 26a configured to generate a current I indicative of the current flowing through the inductor L; L A signal CS1 is generated which is a signal indicating the instantaneous value of (and preferably proportional to) .

[0114] In various embodiments, the electronic power converter 20a may further include a current sensor configured to generate a current indicative of the current i provided via the output terminal. out A signal that is an instantaneous value of (and preferably proportional to)

[0115] For example, as mentioned above, the current I Q1 and I Q2 The average value of can be used to control the section of power switches Q1 and Q2. L and / or i out The (instantaneous and / or average) value of the current i provided via the output terminals 202a and 202b can be used to regulate the current i out or voltage V out .

[0116] In this respect, the inventors have observed that when the converter is operated in CCM mode (in steady state, ie without load transients), the current I flowing through the electronic switch Q1 during the interval T1 is Q1 The average value corresponds to the current I flowing through the electronic switch Q2 during the interval T2 Q2 The average value of the current I L There is a triangular waveform with linear behavior in each interval T1 and T2. In addition, the current I Q1 and I Q2 The average value of (during intervals T1 and T2, respectively) corresponds to the current I flowing through the inductor L during intervals T1 and T2 L In addition, in the case of a buck converter, the current I L The average value of the current i out The average value of .

[0117] Therefore, in various embodiments, to determine the number N1 of electronic switches Qa-Qd of electronic switch Q1 (which should be turned on during interval T1) and the number N2 of electronic switches Qa-Qd of electronic switch Q2 (which should be turned on during interval T2), and / or to regulate the electronic power converter 20a, the control circuit 22 is configured to monitor (and possibly in detail) only one of the signals CS1, CS2 and CS3.

[0118] Typically, in cases where converter 20a can also operate in DCM, it is preferred to use one of current sensors 26a or 26c, since these sensors also provide the current I L The zero crossing information.

[0119] Similar problems also exist in other electronic power converters including a switching stage having an inductor L and two electronic switches Q1 / Q2 configured to control the current flowing through the inductor L, whereby the current I flowing through the inductor L L has a triangular waveform. This applies, for example, to various types of half-bridge converters, where Figure 3The inductor L shown is replaced by the primary winding of a transformer. In this case, the output terminals are not connected to the capacitor Cout, but the secondary winding of the transformer is connected to the output terminals 202a and 202b via a rectifier and filter circuit.

[0120] Other types of electronic power converters suitable for operation in CCM and having a triangular waveform are boost and buck-boost converters comprising two electronic switches. Figure 7 An example of a boost converter is shown. Specifically, in the example considered, an inductor L, such as an inductor, is connected (e.g., directly) between a positive input terminal 200a and a switching node Lx. Switching node Lx is connected (e.g., directly) to a negative input terminal 200b via (the current path of) a first electronic switch Q1, which is in turn typically connected (e.g., directly) to a negative output terminal 202b. Switching node Lx is also connected (e.g., directly) to a positive output terminal 202a via (the current path of) a second electronic switch Q2. A capacitance Cout, such as a capacitor, is typically connected between output terminals 202a and 202b.

[0121] For example, in CCM, the control circuit 22 can again generate the PWM signal DRV1 for the electronic switch Q1, where the duty cycle is determined according to the feedback signal FB and the reference voltage V ref Via PI or PI D For example, the feedback signal FB may also be provided by a voltage sensor 24, which is configured to generate a signal indicating the output voltage V out (and preferably with the output voltage V out The control circuit 22 can also generate a signal DRV2 for the electronic switch Q2, which (again neglecting possible dead time) corresponds to an inverted version of the signal DRV1.

[0122] Thus, also in this case, the electronic power converter 22a may include a current sensor configured to generate a signal indicative of (and preferably proportional to)

[0123] - Current I flowing through the inductor L L The instantaneous value of

[0124] - Current I flowing through the electronic switch Q1 Q1 The instantaneous value of

[0125] - Current I flowing through the electronic switch Q2 Q2 The instantaneous value of .

[0126] Specifically, in various embodiments, the control circuit 22 (or directly, the current sensor) is configured to process the signal to determine:

[0127] - Current I flowing through the inductor L L The average value of

[0128] - When the electronic switch Q1 is closed, the current I flows through the electronic switch Q1 Q1 the average value of

[0129] - When the electronic switch Q2 is closed, the current I flows through the electronic switch Q2 Q2 The average value of .

[0130] In practice, in this case as well, these values ​​correspond. For example, as previously described, in this case as well, the electronic switches Q1 and / or Q2 can be replaced by a plurality of electronic switches connected in parallel, and the control circuit 22 can be configured to determine the number N1 and / or N2 of electronic switches to be closed based on one of the previous average values.

[0131] In the case of a boost converter, the monitoring current I Q2 Can be useful because:

[0132] - In DCM, the corresponding measurement signal can be used to determine the current I flowing through the inductor L L The zero current moment of

[0133] - In the absence of load transients, the current I Q2 The average value corresponds to the current i out The average value (for the entire switching cycle).

[0134] Alternatively, the current I Q1 , since this signal can be used in the case of peak current regulation, where the current I Q1 And the corresponding current I L The electronic switch Q1 is turned off when a given (maximum) threshold is reached. However, this signal can similarly be used in the case of valley current regulation, where the current I Q2 And the corresponding current I L When a given (minimum) threshold is reached, the electronic switch Q2 is turned off.

[0135] Thus, in various embodiments, the control circuit 22 (or direct current sensor) is configured to process (via analog and / or digital circuitry) a measurement signal indicative of an instantaneous value of the current flowing through one of the power switches in order to determine at least one of the following:

[0136] - a first average value of the current when the corresponding power switch is closed; and

[0137] A second average value of the current for a complete switching period.

[0138] For example, the first average value (also representing the average value of the current flowing through the inductor) can be used to control the section of the power switch. In addition, the instantaneous value and / or the first average value and / or the second average value can be used to control the switching operation of the electronic power converter 20a.

[0139] Thus, generally speaking, embodiments herein relate to a control circuit 22 for an electronic power converter 22a, the control circuit 22 comprising a switching stage having an inductor L and two electronic switches Q1 / Q2 configured to measure a current flowing through the inductor L in CCM mode (where the current I flowing through the inductor L is L with a triangular waveform) or measuring current i out And optimize power loss.

[0140] This is also Figure 8 Specifically, in the embodiment considered, the electronic power converter 20a comprises a switching stage / circuit 28 connected between input terminals 200a, 200b and output terminals 202a, 202b. Such a switching stage 28 comprises at least one inductor L, such as an inductor or a transformer, and a circuit configured to control a current I flowing through the inductor L. L At least two electronic switches Q1 and Q2. Optionally, the switching stage 28 further comprises at least one capacitor Cout. For example, in a buck converter ( Figure 3 ) or a boost converter ( Figure 7 ), these components are electronic switch Q1, electronic switch Q2, inductor L and capacitor Cout.

[0141] As mentioned above, the switching stage 28 is configured such that the current flowing through the inductor L can be controlled in CCM (via the electronic switches Q1 and Q2 ).

[0142] For example, Figure 5A As shown, in CCM, the control circuit 22 uses two switching phases T1 and T2, where T SW =T1+T2, where:

[0143] - In stage T1 (T1 = T ON1 =T OFF2 ), the switch Q1 is closed and the switch Q2 is open; and

[0144] - In phase T2 (T2 = T OFF1 =T ON2 ), the switch Q1 is open and the switch Q2 is closed.

[0145] In general, how the embodiments described herein manage these phases is not particularly relevant. For example, as described above, the switching period T SWThe duration of the on-state can be constant, and the on-state duration T ON1 Can be through PI or PI D regulator to determine whether the PI or PI D The regulator is configured to regulate the reference signal V ref and the difference between the feedback signal FB provided by the feedback circuit 24, wherein the feedback signal FB indicates the output voltage V between the terminals 202a / 202b. out .

[0146] For example, this is schematically illustrated via a PWM generator circuit 220 configured to generate a PWM signal DRV having a switching period T SW (eg, having a fixed or predetermined period), wherein the signal DRV is on for a first duration T ON is set to a first logic level (eg, high) within a second duration T OFF is set to a second logic level (e.g., low), where T SW =T ON +T OFF (See also Figure 9 For example, circuit 220 may be an analog and / or digital PI or PI D regulator, which is configured to vary the on-time T ON , so that the reference signal V ref The difference between the feedback signal FB is adjusted to zero.

[0147] Therefore, in this case, the driver circuit 210 can be configured to detect rising and falling edges in the drive signal DRV, and

[0148] in response to a rising edge of the drive signal DRV, setting the signal DRV2 for the electronic switch Q2 to low (e.g. immediately) and setting the signal DRV1 for the electronic switch Q1 to high (e.g. after a first dead time); and

[0149] In response to a falling edge in the drive signal DRV, signal DRV1 is set low (eg, immediately) and signal DRV2 is set high (eg, after a second dead time).

[0150] Therefore, also in this case, the electronic switches Q1 and / or Q2 may be replaced by electronic switches K1 and / or K2 connected in parallel, and the control circuit 22 may be configured to determine the number N1 and / or N2 of electronic switches to be closed according to:

[0151] - Current I flowing through the inductor L L The average value of

[0152] - When the electronic switch Q1 is closed, the current I flows through the electronic switch Q1 Q1 the average value of

[0153] - When the electronic switch Q2 is closed, the current I flows through the electronic switch Q2 Q2 The average value of .

[0154] The inventors have observed that the current I flowing through the inductor L can be directly measured via a shunt resistor connected in series with the inductor. L This is generally inconvenient because the resistor may not be easily integrated into an integrated circuit comprising the control circuit 22a, and power losses are incurred by such a shunt resistor.

[0155] An embodiment will be described below in which the control circuit 22a is configured to measure the current flowing through one of the electronic switches Q1 or Q2 and then determine the control parameters N1 and / or N2 based on the average current flowing through the electronic switch when the electronic switch is closed.

[0156] For example, Figure 10 Again, an embodiment of a boost converter is shown. Specifically, Figure 7 The boost converter includes a device for receiving a DC input voltage V in The two input terminals 200a and 200b and the regulated voltage V out or the regulated current i out The negative output terminal 202b is connected (eg, directly) to the negative input terminal 200b representing the ground GND.

[0157] In the embodiment under consideration, an inductor L and a p-channel FET Q2 (e.g., a PMOS) are connected in series (e.g., directly) between the positive input terminal 200a and the positive output terminal 202a. Specifically, a first terminal of the inductor L is connected (e.g., directly) to the terminal 200a, a second terminal of the inductor L is connected (e.g., directly) to the drain terminal of the transistor Q2 (hereafter again identified as node Lx), and a source terminal of the transistor Q2 is connected (e.g., directly) to the terminal 202a.

[0158] In the embodiment considered, the electronic switch Q1 is connected (e.g., directly) between the node Lx (the midpoint between the inductor L and the transistor Q2) and the ground GND. For example, the electronic switch Q1 can be a transistor, such as an n-channel FET, such as an NMOS. Specifically, the electronic switch Q1 is configured to selectively connect the node Lx to the ground GND.

[0159] In various embodiments, capacitor COUT may be connected (eg, directly) between output terminals 200a and 202b.

[0160] As described above, in various embodiments, electronic switches Q1 and Q2 may be implemented using multiple (physical or virtual) electronic switches connected in parallel, for example, multiple K1 n-channel FETs for switch Q1 and multiple K2 p-channel FETs for switch Q2. As described above, the gate terminals of transistor Q1 and transistor Q2 are driven by respective drive signals, schematically represented as DRV1 and DRV2, although in practice, multiple drive signals may be used, each driven by a control circuit 22a ( Figure 10 Multiple driving signals K1 and K2 are generated by (not shown).

[0161] In the embodiment considered, the electronic power converter further comprises a sensor circuit 26 configured to generate a signal indicative of the current I flowing through the p-channel transistor Q2 or through a reference transistor among the plurality of transistors Q2. Q2 Specifically, the reference transistor Q2 corresponds to one of N2 (with 1≤N2≤K2) transistors Q2, which is closed by the control circuit 22a during the interval T2. For example, the reference transistor can be fixed and, for example, corresponds to the first transistor Qa.

[0162] For example, in the embodiment under consideration, sensor circuit 26 is implemented as described in U.S. Patent No. 10,644,599 (incorporated by reference). Specifically, sensor circuit 26 includes a p-channel FET Q3. Specifically, in various embodiments, p-channel FET Q3 corresponds to a scaled version of p-channel FET Q2 or a corresponding reference FET. Specifically, in various embodiments, the ratio W / L (width to length) of transistors Q2 and Q3 is scaled. For example, in various embodiments, the length L of transistors Q2 and Q3 corresponds, but the width W is different. However, in general, length L can also be varied, or both parameters can be varied. For example, to this end, sensor circuit 26 and one or more p-channel FETs Q2 can be integrated into the same integrated circuit. For example, in the case of a boost converter, switch Q1, transistor Q2, control circuit 22a, and sensor circuit 26 can be implemented in an integrated control IC.

[0163] In the embodiment under consideration, the sensor circuit 26 further comprises an operational amplifier 260, a variable current source 262, and a current mirror 264. Specifically, in the embodiment under consideration, the non-inverting / positive terminal (or generally the first input terminal) of the operational amplifier 260 is connected (e.g., directly) to the source terminal of the transistor Q2 or a corresponding reference FET. Conversely, the inverting / negative terminal (or generally the second input terminal) of the operational amplifier 260 is connected (e.g., directly) to the drain terminal of the transistor Q2 or a corresponding reference FET via the p-channel FET Q3. Specifically, in the embodiment under consideration, the source terminal of the transistor Q3 is connected to the inverting / negative terminal of the operational amplifier 260, and the drain terminal of the transistor Q3 is connected to the drain terminal of the transistor Q2 or a corresponding reference FET. Finally, the drive signal applied to the gate terminal of the transistor Q3 corresponds to:

[0164] - the drive signal DRV2 for transistor Q2 (in the case of a single transistor Q2), or

[0165] - a driving signal for the corresponding reference transistor Q2 (in case of multiple transistors Q2).

[0166] In the embodiment considered, the output of the operational amplifier 260 drives the variable current generator 262 , which is therefore configured to generate a current I as a function of the signal at the output of the operational amplifier 260 . G .

[0167] Specifically, in the case of a boost converter, the second / source terminal of transistor Q2 or the corresponding reference FET is connected to the output terminal 202a and thus to the regulated voltage V OUT Therefore, the variable current source 262 can be controlled by the voltage V OUT However, another regulated voltage may also be used to provide the variable current source 262 .

[0168] For example, in the embodiment considered, the variable current source 262 is implemented by a p-channel FET Q4, such as a PMOS. Specifically, in the embodiment considered, the source terminal of the transistor Q4 is connected (for example, directly) to the source terminal of the transistor Q2 or to a corresponding reference FET (i.e., to a voltage V OUT ), and the gate terminal is connected to the output of the operational amplifier 260. Thus, the drain terminal of the transistor Q4 will provide a current I determined by (e.g., at least partially proportional to) the signal at the output of the operational amplifier 260. G .

[0169] In the embodiment considered, the variable current I generated by the current generator 262 GThe current (eg, provided via the drain terminal of transistor Q4 ) is applied to the source terminal of transistor Q3 , eg, via current mirror 264 .

[0170] For example, in the embodiment under consideration, current mirror 264 is connected to ground GND, and the current mirror is thus implemented using a current mirror including two n-channel FETs Q5 and Q6, such as NMOS transistors. Specifically, in the embodiment under consideration, the drain terminal of transistor Q5 is connected to the output of current generator 262, for example, the drain terminal of transistor Q4, the source terminal of transistor Q5 is connected to ground GND, and the gate terminal of transistor Q5 is connected to the drain terminal of transistor Q5. Conversely, the gate terminal of transistor Q6 is connected to the gate terminal of transistor Q5, the source terminal of transistor Q6 is connected to ground GND, and the drain terminal of transistor Q6 is connected to the source terminal of transistor Q3.

[0171] Thus, in various embodiments, the sensor circuit 26 is configured (eg, via the current mirror 264) to also generate the current I generated by the variable current generator 262. G Applied to transistor Q3.

[0172] Therefore, the sensor circuit 26 is configured to implement the current I provided by the current source 262 G Specifically, the operational amplifier 260 is configured to change the current I generated by the current generator 262 via the feedback loop. G , to keep the voltage V- at the inverting / negative input of the operational amplifier 260 equal to the voltage V+ at the non-inverting / positive input of the operational amplifier 260. Therefore, under the stable condition (V+=V-), the voltage V between the drain terminal and the source terminal of the transistor Q3 is D S3 corresponds to the voltage V between the drain and source terminals of transistor Q2 or the corresponding reference FET D S2.

[0173] However, due to the scaling of transistor Q2 or the corresponding reference FET relative to transistor Q3, the current I flowing through transistor Q2 or the corresponding reference transistor Q2 A portion of the current I flowing through transistor Q3 will flow through transistor Q3. S and the current I flowing through transistor Q2 or the corresponding reference transistor Q2 Proportional.

[0174] I S =I Q2 / M (2)

[0175] Therefore, in various embodiments, knowing the number N2 (ie, the number of switches closed for switch Q2), the control circuit 22a can also calculate the total current flowing through the N2 closed transistors.

[0176] Typically, the current mirror 264 can also perform scaling, that is, the current I provided by the current generator 262 G It is not necessary to compare with the current I S The same, but can only be with the current I S Proportional.

[0177] Therefore, to determine the current I flowing through transistor Q2 Q2 To determine the instantaneous value of (and preferably proportional to) the value of , the sensor circuit 26 may include measurement circuitry configured to measure, for example:

[0178] - Current I flowing through transistor Q3 S (e.g., corresponding to the current flowing through the output of current mirror 264); and / or

[0179] - Current I provided by variable current generator 262 G (eg, corresponding to the current flowing through the input of current mirror 264).

[0180] For example, in the embodiment considered, the sensing measurement circuit comprises a variable current generator 268 configured to generate a current according to the current I G Generates variable current I D , the current I G Therefore, the current I Q2 Proportional.

[0181] For example, in the embodiment under consideration and similar to the current generator 262, the variable current generator 268 is a p-channel FET, such as a PMOS. Specifically, in the embodiment under consideration, the source terminal of the transistor Q7 is connected to the source terminal of the transistor Q2 (i.e., to the voltage V OUT ), and the gate terminal is connected to the gate terminal of transistor Q4. Therefore, in the embodiment considered, the p-channel FETs Q4 and Q7 are driven by the same gate-source voltage, thereby providing the same current (or current I G and I D Again at least proportional). Thus, the drain terminal of transistor Q7 will provide a current I that is equal to the current flowing through transistor Q2 or the corresponding reference transistor. Q2 The instantaneous value of the current I D .

[0182] Therefore, the sensed / measured signal S may correspond to the current I DIn the case where the sense signal S should be a voltage signal, the sensing device 266 may further include a current-to-voltage converter 270, such as a resistor R connected (for example directly) between the output terminal of the variable current generator 268 (for example, the drain terminal of the transistor Q7) and the ground GND. D Therefore, in the embodiment considered, the resistor R D The voltage V D will be compared with the current I flowing through transistor Q2 or the corresponding reference transistor M Proportional.

[0183] In various embodiments, a chopping circuit 272 can be associated with the operational amplifier 260. Specifically, the chopping circuit 272 is configured to switch the input and output of the operational amplifier 260 so as to shift the offset of the operational amplifier 260 at a higher frequency relative to the signal frequency. The operation of such a chopping circuit 272 is known in the art, for example, from R. Wu et al., Precision Instrumentation Amplifiers and Read-Out Integrated Circuits, "Chapter 2 - Dynamic Offset Cancellation Techniques for Operational Amplifiers", Analog Circuits and Signal Processing, DOI: 10.1007 / 978-1-4614-3731-4_2, Springer Science+Business Media New York, 2013, the contents of which are incorporated herein by reference. Typically, the chopping circuit 272 can also be integrated into the operational amplifier 260.

[0184] Specifically, in the embodiment under consideration, the chopping circuit 272 is configured to perform a chopping operation based on the signal CHOP. For example, in various embodiments, the signal CHOP may be provided by the control circuit 22a. For example, in various embodiments, CHOP may be a pulse signal with a duration T SW1 (ie, one switching cycle of the switch Q2) CHOP is periodically set to the first logic level and then for a duration T SW1 (ie, one switching cycle of the switch Q2 ) CHOP is set to a second logic level.

[0185] Thus, by switching the input and output of the operational amplifier 260, the chopping circuit 260 shifts the offset of the operational amplifier 260 to a higher frequency relative to the signal frequency. Thus, in the embodiment considered, the offset of the operational amplifier 260 will be proportional to the frequency F of the signal CHOP.chop to modulate, which can be, for example, F chop =1 / (2T SW1 Therefore, in various embodiments, the sensor circuit 26 and / or the control unit 22a may include a filter 274 configured to filter the sensed signal S (eg, the current I D or voltage V D ) is filtered to remove the frequency F chop .

[0186] For example, the filter 274 may have a minimum frequency F less than the signal CHOP. chop An analog low-pass or band-pass filter for the upper frequencies of

[0187] For example, in the embodiment considered, the analog low-pass filter 274 is connected between the signal S and ground, ie in parallel with the current-to-voltage converter 270, whereby the voltage V D has represented the filtered signal, in which the modulation offset of the operational amplifier 260 has been removed. For example, in the embodiment considered, by connecting the capacitor CD with the resistor R D The passive low-pass filter 274 is realized in parallel.

[0188] Figure 10 The sensor circuit 26 is also capable of monitoring the current I for a small voltage drop between the drain and source terminals of the transistor Q2. M , for a typical switch resistance of 50 mΩ for transistor Q2, this small voltage drop (for low power applications) may be in the range of 1 mV to 5 mV.

[0189] In various embodiments, electronic switch Q8 is connected between current generator 268 and filter and current-to-voltage conversion circuitry 270 / 274 .

[0190] In various embodiments, the control circuit 22a may also generate a drive signal DRV8 for the switch Q8 so as to:

[0191] a) when transistor Q2 or the corresponding reference transistor is closed and current flows through transistor Q2 or the corresponding reference transistor (interval T2), closing switch Q8, and

[0192] b) When transistor Q2 or the corresponding reference transistor is turned off (interval T1), switch Q8 is turned off.

[0193] However, when the switch Q8 is off, the output terminal of the variable current generator 268 is in principle floating. However, due to the parasitic capacitance Cpar at the output of the current generator 268, the voltage at the output terminal will generally increase. For example, in the embodiment considered, the voltage at the drain terminal of the transistor Q7 may increase substantially to the output voltage V OUT When the switch Q8 is closed again, the filter and current-to-voltage conversion circuit 270 / 274 will be connected to the output of the current generator 268 again.

[0194] For example, in the embodiment considered, the parasitic capacitance Cpar will at this moment transfer the charge Q par Moving on to the filter and current-to-voltage conversion circuits 270 / 274, corresponding to, for example:

[0195] Q par =Cpar(V OUT -V D )

[0196] At the current I D When it is high, the parasitic charge Q par can be ignored. In contrast, in actual implementation, the current I D should be as small as possible in order to reduce electrical losses. Therefore, in this case, the parasitic charge Q par Can significantly change the voltage V D .

[0197] Therefore, in various embodiments, the stabilizer circuit 276 is configured to apply a voltage V at the output terminal of the current generator 268 when the switch Q8 is turned off (interval T1). D .

[0198] For example, in various embodiments, the stabilizer circuit 276 includes a voltage follower 278 configured to provide a voltage V at its output. D For example, in the embodiment under consideration, the voltage follower 278 is implemented using an operational amplifier 280 that receives a voltage V at its non-inverting / positive input. D , and the output of the operational amplifier 280 is connected to the inverting / negative input of the operational amplifier 280. The stabilizer circuit 276 also includes an electronic switch Q9 that is configured to selectively connect the output of the voltage follower 278 / op-amp 280 to the output of the current generator 268.

[0199] Therefore, in various embodiments, switch Q9 is closed when switch Q8 is open, and switch Q9 is open when switch Q8 is closed.For example, in various embodiments, control circuit 22a can also generate a drive signal DRV9 for switch Q9.

[0200] US Patent No. 10,644,599 also mentions that the filter 274 can be used to directly obtain the average value of the signal S, thereby obtaining the current I Q2 However, as mentioned above, the control circuit 22a is able to determine the current I of the cycle when the electronic switch Q2 is closed. Q2 In fact, this value also indicates the current flowing through the inductor L. As mentioned above, the control circuit 22a can be configured to control the current I during the period when the switch Q2 is closed. Q2 The average value of the determined numbers N1 and N2.

[0201] However, the inventors have observed that when the control circuit should be able to measure the current I L When the average value of Figure 10 The method shown is not appropriate. In fact, as mentioned above, during the period when the electronic switch Q2 is closed, the current I L The average value of the current I can be determined by Q2 is determined by the average value of .

[0202] For example, as described above, the control circuit 22a may be configured to determine the numbers N1 and N2 based on the average value.

[0203] However, since the switching losses of a DC-DC converter depend on the coil current, measuring the average value of the current flowing through the inductor L is also useful for optimizing the efficiency curve of the DC-DC converter. This is quite obvious in the context of a boost converter, for example. Specifically, when considering V out and i out Under static conditions with a constant average value, the current I L According to the input voltage V in And change.

[0204] therefore, Figure 11 Another embodiment is shown in which the filter 274 is smaller so that when the electronic switch Q8 is closed (interval T2), it provides substantially the same current I D The instantaneous value of the voltage V D Furthermore, an additional low pass filter 282 and an additional voltage follower 286 have been added.

[0205] Specifically, the low-pass filter 282 (eg, including a resistor RF and a capacitor C connected in series) F ) receives voltage V at the input D , and at the output (e.g., at the capacitor C F The voltage V corresponding to the signal S is provided at the terminal DFurthermore, a voltage follower 284, implemented for example with an operational amplifier 286, receives at its input a voltage V corresponding to the signal S. D A low-pass filtered version (e.g., across capacitor C F In the embodiment considered, the voltage at the output of the voltage follower 284 is selectively applied to the filter and current-to-voltage conversion circuit 270 / 274 via the electronic switch Q10.

[0206] Specifically, in various embodiments, the control circuit 22 a is configured to open the electronic switch Q10 when the electronic switch Q8 is closed (interval T2 ), and to close the electronic switch Q10 when the electronic switch Q8 is open (interval T1 ).

[0207] Therefore, in the embodiment considered, the voltage follower 284, the electronic switch Q10 and the capacitor C F A sample-and-hold circuit is also implemented.

[0208] Specifically, if Figure 12 As shown, when the control circuit 22a closes the electronic switch Q2 (interval T2), the control circuit 22a also closes the electronic switch Q8 and opens the electronic switch Q10. Therefore, the voltage V provided by the filter and the current-voltage conversion circuit 270 / 274 is D and the current I flowing through transistor Q2 or the corresponding reference transistor Q2 (the instantaneous value) is proportional.

[0209] On the contrary, when the control circuit 22a turns off the electronic switch Q2 (interval T1), the control circuit 22a also turns off the electronic switch Q8 and turns on the electronic switch Q10. Therefore, due to the buffer 284, the voltage V D is maintained at voltage S.

[0210] Therefore, with this drive, the signal S corresponds to the current I during the period when the switch Q2 is closed. Q2 As mentioned above, this value also corresponds to the coil current I flowing through the inductor L. L The average value of .

[0211] In various embodiments, the control circuit 22a can also directly measure the current I Q2 (Instantaneous value) proportional to voltage V D For example, this signal can be used to control the switching of electronic switches Q1 and Q2.

[0212] Additionally or alternatively, according to Figure 10 As described above, the control circuit 22a can also keep the switch Q10 always open, wherein the signal S corresponds to the current I Q2The average value during the entire switching period. For example, in the case of a boost converter, this value corresponds to the current i out For example, in various embodiments, the control circuit 22a may be configured to use two measurement phases:

[0213] -In the first stage (including multiple switching cycles T SW ), the control circuit 22a also switches the switch Q10 (when the switch Q2 is closed, Q10 is open, and vice versa), thereby obtaining the coil current I Q2 the average value of

[0214] - In the second phase (including multiple switching cycles T SW ), the control circuit 22a keeps the switch Q10 turned off, thereby obtaining the output current i in the case of a boost converter. out The average value of .

[0215] Typically, when the electronic switch is a low-side n-channel FET (e.g. Figure 3 The electronic switch Q2 of the buck converter shown or Figure 7 The described method can also be used to measure the average current when the electronic switch Q1 of the boost converter is shown.

[0216] For example, Figure 13 A sensor circuit 26 is shown for a low-side electronic switch Q1 of a boost converter. Specifically, also in this case, the electronic power converter includes a power switch indicated as Q1, which can be implemented using a FET or a plurality of K1 FETs connected in parallel, one of which represents a reference transistor. The FET or reference FET includes a gate terminal, and first and second terminals (drain and source) that define a current path for the FET.

[0217] Specifically, the sensor circuit 26 includes a FET Q3 that is a scaled version of the FET Q1 or a corresponding reference FET, wherein a first terminal of the FET Q3 is connected to a first terminal of the FET Q1 or a corresponding reference FET, and a gate terminal of the FET Q3 is configured to be driven by a drive signal DRV1 of the FET Q1 or the corresponding reference FET. Specifically, in the embodiment considered, the first terminal of the FET Q1 (or the corresponding reference FET) and the FET Q3 are source terminals.

[0218] In the embodiment considered, the sensor circuit 26 comprises an operational amplifier 260, wherein a first input terminal of the operational amplifier 260 is connected to a second terminal of the (power) FET Q1 or a corresponding reference FET, and a second input terminal of the operational amplifier 260 is connected to a second terminal of the FET Q3. In particular, in the embodiment considered, the second terminals of the FET Q1 (or the corresponding reference FET) and the FET Q3 are drain terminals.

[0219] In the embodiment considered, the variable current source 262 (for example implemented using an n-channel FET) is configured to generate a current as a function of the signal at the output terminal of the operational amplifier 260, wherein the current is applied to the second terminal of the FET Q3. Specifically, in this case, the current mirror 264 is omitted.

[0220] Thus, operational amplifier 260 regulates the voltage at the second terminal of FET Q3 to the voltage at the second terminal of (power) FET Q1 via variable current source 262 and regulates the current flowing through FET Q3, which is proportional to the current flowing through (power) FET Q1 or a corresponding reference transistor.

[0221] In the embodiment considered, the sensor circuit comprises a measurement circuit configured to generate a measurement signal representative of the current flowing through the (power) FET by monitoring (the instantaneous value of) the current flowing through the FET Q3 and / or the current generated by the variable current source 262 .

[0222] For example, in the embodiment considered, the measurement circuit includes a current mirror 268, wherein the input of the current mirror 268 receives the current generated by the variable current source 262 and when the FET Q1 or the corresponding reference transistor is closed, the output of the current mirror 268 provides a current I proportional to the current flowing through the FET Q1 or the corresponding reference transistor. D .

[0223] Therefore, the measurement circuit may include information about Figure 11 The other components (270, 274, Q8, 276, 282, 284, Q10) are described to determine the current I when the electronic switch Q1 is closed. Q1 The average value of the signal S is proportional to the average coil current.

[0224] In various embodiments, Figure 13 The sensor circuit shown in may also include a chopping circuit 272 associated with the operational amplifier, wherein the chopping circuit is configured to switch input terminals and possibly also output terminals of the operational amplifier according to a chopping control signal, thereby moving the offset of the operational amplifier at a higher frequency relative to the signal frequency (i.e., the frequency of the chopping control signal).

[0225] Figure 14 Also shown are embodiments that can be used, for example, to determine the current flowing through the high-side p-channel FET Q1 (e.g. Figure 3 The average current of the buck converter shown.

[0226] Specifically, in this case as well, the electronic power converter includes a power switch Q1, which can be implemented with a FET or a plurality of K1 FETs connected in parallel, one of which represents a reference transistor. The FET Q1 or reference FET includes a gate terminal and a first terminal and a second terminal (drain and source) that define a current path for the FET.

[0227] Specifically, the sensor circuit 26 includes a FET Q3 that is a scaled version of the FET Q1 or the corresponding reference FET, wherein a first terminal of the FET Q3 is connected to a first terminal of the FET Q1 or the corresponding reference FET, and a gate terminal of the FET Q3 is configured to be driven by a drive signal DRV1 of the FET Q1 or the corresponding reference FET. Specifically, in the embodiment considered, the first terminal of the FET Q1 (or the corresponding reference FET) and the FET Q3 are source terminals.

[0228] In the embodiment considered, the sensor circuit 26 comprises an operational amplifier 260, wherein a first input terminal of the operational amplifier 260 is connected to a second terminal of the (power) FET Q1 or a corresponding reference FET, and a second input terminal of the operational amplifier 260 is connected to a second terminal of the FET Q3. In particular, in the embodiment considered, the second terminals of the FET Q1 (or the corresponding reference FET) and the FET Q3 are drain terminals.

[0229] In the embodiment considered, the variable current source 262 (for example, implemented using a p-channel FET) is configured to generate a current as a function of the signal at the output terminal of the operational amplifier 260, wherein the current is applied to the second terminal of the FET Q3. In particular, in this case, the current mirror 264 is again omitted.

[0230] Therefore, the operational amplifier 260 again adjusts the voltage at the second terminal of the FET Q3 to the voltage at the second terminal of the (power) FET Q1 via the variable current source 262, and adjusts the current flowing through the FET Q3, which is proportional to the current flowing through the (power) FET Q1 or the corresponding reference transistor.

[0231] In the embodiment considered, the sensor circuit comprises a measurement circuit configured to generate a measurement signal S indicative of the current flowing through the (power) FET Q1 by monitoring the current flowing through the FET Q3 and / or (the instantaneous value of) the current generated by the variable current source 262 .

[0232] For example, in the embodiment under consideration, when the FET Q1 or the corresponding reference transistor is closed, the current generator 262 directly provides a current I proportional to the current flowing through the FET Q1 or the corresponding reference transistor. D .

[0233] Therefore, the measurement circuit may include information about Figure 11 The other components (270, 274, Q8, 276, 282, 284, Q10) described are used to determine the current I when the electronic switch Q1 is closed. Q1 The average value of the signal S is proportional to the current I Q1 The average value of therefore corresponds to the average coil current.

[0234] Figure 15 and 16 Also shown is an embodiment of a sensor circuit 26 suitable for use with an inverting buck-boost converter.

[0235] Typically, a buck-boost converter includes a circuit for receiving an input voltage V in The two input terminals 200a and 200b and the regulated output voltage V out Or output current i out The two output terminals 202a and 202b.

[0236] In addition, the buck-boost converter also includes two electronic switches Q1 and Q2, and an inductor L, typically an inductor. Specifically, in the buck-boost converter, the two electronic switches Q1 and Q2 are connected in series between terminals 200a and 202b. Specifically, in the embodiment considered, (the current path of) the electronic switch Q2 is connected between terminal 200a and the switching node Lx (e.g., directly), and (the current path of) the electronic switch Q1 is connected between the switching node Lx and terminal 202b (e.g., directly). In addition, the inductor L is connected between the switching node Lx and the terminal 200b representing the ground (e.g., directly). Typically, the output terminal 202a is also connected to the ground / terminal 200b. In various embodiments, a capacitor Cout can be connected between terminals 202a and 202b.

[0237] Therefore, when the electronic switch Q2 is closed (and the electronic switch Q1 is open), the inductor L is connected to the input terminals 200a and 200b, whereby the current I flows through the inductor L. LIn contrast, when the electronic switch Q1 is closed (and the electronic switch Q2 is open), the inductor L is connected to the output terminals 202a and 202b, whereby the current I flowing through the inductor L is L Specifically, due to the direction of current flow, terminal 202b is a negative output terminal, and terminal 202a is a positive output terminal.

[0238] In the embodiment considered, the electronic switches Q1 and Q2 are again power FETs, for example two n-channel FETs, which can therefore again be replaced by a plurality of FETs connected in parallel.

[0239] Figure 15 An embodiment of a sensor circuit for an electronic switch Q1 is shown. Specifically, the electronic switch Q1 is a low-side switch, and Figure 15 The sensor circuit 13 shown corresponds essentially to Figure 13 The sensor circuit is shown.

[0240] Thus, also in this case, the first (e.g., source) terminal of FET Q3 is connected to the first (e.g., source) terminal of power FET Q1, and the second (e.g., drain) terminal of FET Q3 and the second (e.g., drain) terminal of power FET Q1 are connected to the inputs of operational amplifier 260, which regulates the current I flowing through FET Q3 via current source 262 (such as FET Q4). S , until the voltage drops V DS，Q3 The voltage drop V between the first terminal and the second terminal of FET Q3 DS,Q3 Corresponding to the voltage drop V between the first and second terminals of the power FET Q1 DS,Q1 , whereby (due to the scaling of transistors Q3 and Q1) a current flows through FET Q3 which is equal to the current I flowing through power FET Q1 Q1 Therefore, this current can be provided to the measurement circuit R (eg, via current mirror 268). D ,CD,RF,C F , Q8, Q9, Q10, 280, 286.

[0241] Typically, as previously described, by applying a drain-source voltage drop V at the power FET Q1 across the sensor FET Q3 DS,Q1 To generate the measurement current. Specifically, Figure 15 As shown, in fact, the current can be controlled via an ideal electronic switch Q3' and an on-resistance R connected in series with the electronic switch Q3' (current path). DS_on To simulate the FET. Therefore, in the case where FET Q3 is a scaled version of FET Q1, the corresponding on-resistance RDS_on Furthermore, due to the scaling and proper placement of the sensor FET Q3 near the FET Q1, both FETs are exposed to the same process and temperature variations, whereby the on-resistance R DS_on However, an additional resistor may also be connected in series with the sensor FET Q3 in order to reduce the current flowing through the FET.

[0242] In this regard, the electronic switch Q3' is used to enable or disable the DS_on The current I S , that is, current flow is enabled when the corresponding drive signal instructs the power FET to close, and current flow is disabled when the corresponding drive signal instructs the power switch to open.

[0243] on the contrary, Figure 16 An embodiment of a sensor circuit for an electronic switch Q2 is shown. In general, when the electronic switch Q2 is implemented using a p-channel FET, a Figure 14 In contrast, in the embodiment considered, the electronic switch Q2 is an n-channel FET. In this case, it is possible to use Figure 15 However, Figure 16 Different embodiments are shown.

[0244] Specifically, as previously described, the sensor circuit according to the aforementioned embodiment is configured to, when the power FET to be monitored (i.e., FET Q2 in the embodiment under consideration) is closed, regulate the drain-source voltage drop at the power FET (i.e., V in the embodiment under consideration) via a regulator circuit comprising, for example, an operational amplifier 260 and a current source 262. DS,Q2 ) is applied to the (sense) resistor. In the embodiment considered above, the (sense) resistor uses the on-resistance R of FET Q3. DS_on accomplish.

[0245] On the contrary, Figure 16 An embodiment is shown in which a discrete resistor Rb is used as the (sense) resistor.

[0246] For example, in the embodiment considered, the electronic switch Q3' (such as a FET) is configured to selectively connect a resistor Ra in parallel with the power FET to be monitored (i.e., Q2 in the embodiment considered). Specifically, in the embodiment considered, the source terminal of FET Q3' is connected to the source terminal of FET Q2, the drain terminal of FET Q3' is connected to the drain terminal of FET Q2 via resistor Ra, and the gate terminal of FET Q3' is connected to the gate terminal of FET Q2. Therefore, when FETQ2 and Q3' are closed (via drive signal DRV2), resistor Ra is connected in parallel to FET Q2. Therefore, by using resistor Ra, the drain-source voltage drop V at the power FET Q2 is reduced. DS，Q2 is applied to the resistor Ra, which has a resistance significantly greater than the on-resistance of the switch Q3 ′.

[0247] In the embodiment under consideration, the operational amplifier 260 and the current source 262 are thus used to apply the voltage drop across the resistor Ra to the sensing resistor Rb. For example, in the embodiment under consideration, the first terminal of the resistor Rb is connected to the first terminal of the resistor Ra (the drain terminal of the FET Q2). The second terminal of the resistor Rb is connected to the current source 262. Finally, the first input terminal of the operational amplifier 260 is connected to the second terminal of the resistor Ra (the intermediate node between the resistor Ra and the electronic switch Q3'), the second input terminal of the operational amplifier 260 is connected to the second terminal of the resistor Rb (the intermediate node between the resistor Rb and the current source 262), and the output terminal of the operational amplifier 260 drives the current source 262.

[0248] Thus, similar to the previous description, when power FET Q2 is closed (as detected via switch Q3′), operational amplifier 260 sets the current of current source 262 until the voltage at resistor Rb corresponds to the drain-source voltage drop V across power FET Q2. DS，Q2 Therefore, the current flowing through the sensing resistor Rb can be provided to the measuring circuit R D ,CD,RF,C F , Q8, Q9, Q10, 280, 286.

[0249] Also in this case, the electronic switch Q3' is used to enable or disable the current I through the sensing resistor Rb S , that is, the current is enabled when the corresponding drive signal instructs the power FET to close, and the current is disabled when the corresponding drive signal instructs the power switch to open. Although in the previous embodiment, the electronic switch Q3' is directly connected to the sensing resistor R DS_on Connected in series, electronic switch Q3' now deactivates one of the inputs of operational amplifier 260. Typically, similar to Figure 15In the illustrated embodiment, the electronic switch Q3 ′ may also disable the output of the current generator 262 .

[0250] Thus, essentially, the operational amplifier 260, the electronic switch Q3' and the current source 262 (and optional current mirror 264) represent a regulator circuit that is configured to:

[0251] -When the drive signal applied to the gate terminal instructs the power FET to turn off, current will flow through the sense resistor R DS_on or Rb current is set to zero, and

[0252] -When the drive signal applied to the gate terminal instructs the power FET to close, the current flowing through the sense resistor R DS_on or Rb, so that the sensing resistor R DS_on The voltage drop across Rb corresponds to the drain-source voltage drop across the power FET. Conversely, the remaining sensor circuit is used to monitor (directly or indirectly) the current flowing through the sense resistor R DS_on Or the current of Rb.

[0253] Therefore, in the embodiment considered, one or preferably both of the electronic switches Q1 and Q2 of the electronic power converter can be implemented with multiple electronic switches connected in parallel, and the control circuit can determine the number of electronic switches to be closed based on the average current flowing through one of the electronic switches Q1 and Q2.

[0254] As described above, the sensor circuit 26 for a power FET described herein has the advantage that the sensor circuit 26 can be used to:

[0255] -When the power FET is closed, a value I is generated which is proportional to the instantaneous value of the current flowing through the power FET D / V D ;

[0256] - generating a signal S proportional to the average value of the current flowing through the inductor L by driving the switch Q10 according to the driving signal of the power FET; and

[0257] - Optionally, by keeping the switch Q10 open, a current is generated over multiple switching cycles T SW The signal S is proportional to the average value of the current flowing through the power FET.

[0258] In fact, as mentioned above, in various embodiments, the average value of the current flowing through the power FET for multiple switching cycles may correspond to the output current i out The average value of .

[0259] The claims are an integral part of the technical teaching of the disclosure provided herein.

[0260] Of course, without prejudice to the principle contained in the present disclosure, the details of construction and the embodiments may vary widely with respect to what is described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A sensor system comprising: A power field effect transistor FET comprising: a first conductive terminal and a second conductive terminal defining a current path, and a gate terminal configured to receive a drive signal; and a sensor circuit configured to monitor current flowing through the power FET; The sensor circuit comprises: a sense resistor; and The regulator circuit is configured as: setting a first current flowing through the sense resistor to zero when the drive signal applied to the gate terminal is set to turn off the power FET; and adjusting the first current flowing through the sense resistor so that a voltage drop across the sense resistor corresponds to a voltage drop between the first and second conductive terminals of the power FET when the drive signal applied to the gate terminal is set to turn on the power FET; a measurement circuit configured to provide a second current corresponding to or proportional to the first current; resistors; a first electronic switch configured to selectively apply the second current to the resistor according to a first control signal; a low-pass filter configured to generate a low-pass filtered signal by filtering a voltage at the resistor resulting from applying the second current to the resistor; a voltage follower configured to generate a replica of the low-pass filtered signal; a second electronic switch configured to selectively apply the replica of the low-pass filtered signal to the resistor; and The control circuit is configured as follows: When the power FET is turned on, closing the first electronic switch and opening the second electronic switch to generate a voltage at the resistor that is proportional to an instantaneous value of a current flowing through the power FET; and When the power FET is turned off, the first electronic switch is opened and the second electronic switch is closed to generate a voltage at the resistor that corresponds to the low-pass filtered signal, and wherein the low-pass filtered signal is proportional to an average value of a current flowing through the power FET during a period when the power FET is turned on.

2. The sensor system of claim 1 , wherein the control circuit is configured to: During the first measurement phase: When the power FET is turned on, closing the first electronic switch and opening the second electronic switch to generate a voltage at the resistor that is proportional to an instantaneous value of a current flowing through the power FET; as well as opening the first electronic switch and closing the second electronic switch when the power FET is off to generate a voltage at the resistor that corresponds to the low-pass filtered signal, and wherein the low-pass filtered signal is proportional to the average value of the current flowing through the power FET during the on-time period of the power FET; as well as During a second measurement phase, the second electronic switch is maintained open, and: When the power FET is turned on, the first electronic switch is closed, and When the power FET is off, the first electronic switch is opened to generate the low-pass filtered signal proportional to the average value of the current flowing through the power FET during on and off periods of the power FET.

3. The sensor system of claim 1 , wherein the regulator circuit comprises: a first FET that is a scaled version of the power FET, wherein a first conductive terminal of the first FET is connected to the first conductive terminal of the power FET, wherein a gate terminal of the first FET is configured to be driven using the drive signal of the power FET, wherein an on-resistance of the first FET represents the sense resistance; an operational amplifier, wherein a first input terminal of the operational amplifier is connected to the second conduction terminal of the power FET, and a second input terminal of the operational amplifier is connected to the second conduction terminal of the first FET; as well as a variable current source configured to generate a first current according to a signal at an output terminal of the operational amplifier, wherein the first current generated by the variable current source is applied to the second conductive terminal of the first FET, wherein the operational amplifier adjusts the voltage at the second conductive terminal of the first FET to the voltage at the second conductive terminal of the power FET via the variable current source, and the first current flows through the first FET, the first current being proportional to the current flowing through the power FET. 4 . The sensor system of claim 3 , wherein the variable current source comprises a second FET, wherein a gate terminal of the second FET is connected to the output terminal of the operational amplifier. 5 . The sensor system of claim 4 , wherein the variable current source comprises a current mirror arrangement configured to apply the current generated by the second FET to the second conduction terminal of the first FET. 6 . The sensor system of claim 4 , wherein the measurement circuit comprises a third FET, wherein a gate terminal of the third FET is connected to the output terminal of the operational amplifier. 7 . The sensor system of claim 4 , wherein the measurement circuit comprises a further current mirror arrangement configured to generate the second current by mirroring the current generated by the second FET. 8 . The sensor system of claim 1 , wherein the low-pass filter comprises a further resistor and a capacitor, and wherein the low-pass filtered signal corresponds to a voltage at the capacitor.

9. The sensor system of claim 1, implemented as an integrated circuit.

10. An electronic power converter comprising: Two input terminals for receiving input voltage; two output terminals for providing a regulated output voltage or a regulated output current; a switching circuit connected between the two input terminals and the two output terminals, wherein the switching circuit includes an inductor and a first power field effect transistor (FET) and a second power field effect transistor (FET), wherein the first power FET and the second power FET are configured to control a current flowing through the inductor; a control circuit configured to generate control signals for the first power FET and the second power FET, wherein the control circuit is configured to operate the inductor in a continuous conduction mode by driving the first power FET and the second power FET in a switching cycle, the switching cycle comprising: a first phase in which the first power FET is turned on and the second power FET is turned off, wherein the current flowing through the inductor increases linearly, and a second phase, wherein the first power FET is turned off and the second power FET is turned on, wherein the current flowing through the inductor decreases linearly; and a sensor circuit configured to monitor a current flowing through the first power FET or the second power FET, wherein a low-pass filtered signal is proportional to an average value of the current flowing through the inductor; The sensor circuit comprises: a sense resistor; and The regulator circuit is configured as: setting a first current flowing through the sense resistor to zero when a drive signal applied to a gate terminal of the first power FET or the second power FET is set to turn off the power FET; and When the drive signal applied to the gate terminal is configured to turn on the power FET, regulating the first current flowing through the sense resistor so that a voltage drop across the sense resistor corresponds to a voltage drop between a first conductive terminal and a second conductive terminal of the power FET; and The control circuit is configured to start the second phase when the voltage at the sensing resistor reaches a given threshold.

11. The electronic power converter of claim 10 , wherein the first power FET is implemented by a first plurality of parallel FETs and the second power FET is implemented by a second plurality of parallel FETs, and wherein the control circuit is configured to: obtaining the low-pass filtered signal proportional to an average value of a current flowing through the first power FET or the second power FET during a period in which the first power FET or the second power FET is closed; determining a given number of FETs in the first and second pluralities of parallel FETs to be closed based on the low-pass filtered signal that is proportional to an average value of current flowing through the first or second power FET during a period in which the first or second power FET is closed; During the first phase, closing the given number of FETs in the first plurality of parallel FETs; as well as During the second phase, the given number of FETs of the second plurality of parallel FETs are closed. 12 . The electronic power converter according to claim 10 , wherein the control circuit is configured to change the duration of the first phase and / or the second phase according to an average value of the current flowing through the first power FET or the second power FET.

13. A method of operating an electronic power converter, comprising: An inductor of the electronic power converter is operated in a continuous conduction mode by driving a first power FET and a second power FET of the electronic power converter in a switching cycle comprising: a first phase in which the first power FET is turned on and the second power FET is turned off, wherein the current flowing through the inductor increases linearly, and a second phase, wherein the first power FET is turned off and the second power FET is turned on, wherein the current flowing through the inductor decreases linearly; and monitoring the current flowing through the first power FET or the second power FET using a sensor circuit of the electronic power converter, whereby a low-pass filtered signal is proportional to an average value of the current flowing through the inductor; The second phase is started when a voltage at a resistor that is proportional to an instantaneous value of a current flowing through the first power FET or the second power FET reaches a given threshold.

14. The method of claim 13, wherein the power field effect transistor (FET) is the first power FET or the second power FET; and wherein: During the first measurement phase: When the power FET is turned on, closing the first electronic switch and opening the second electronic switch to generate a voltage at the resistor that is proportional to the instantaneous value of the current flowing through the power FET; as well as When the power FET is turned off, the first electronic switch is opened and the second electronic switch is closed to generate a voltage at the resistor that corresponds to the low-pass filtered signal, and wherein the low-pass filtered signal is proportional to an average value of a current flowing through the power FET during a period when the power FET is turned on.

15. The method according to claim 14, wherein: During a second measurement phase, the second electronic switch is maintained open, and: When the power FET is turned on, the first electronic switch is closed, and When the power FET is off, the first electronic switch is opened to generate the low-pass filtered signal proportional to an average value of the current flowing through the power FET during on and off periods of the power FET.

16. An electronic power converter comprising: Two input terminals for receiving input voltage; Two output terminals for providing regulated output voltage or regulated output current; a switching circuit connected between the two input terminals and the two output terminals, wherein the switching circuit comprises an inductor, and a first power field effect transistor (FET) and a second power field effect transistor (FET) configured to control a current flowing through the inductor; a control circuit configured to generate control signals for the first power FET and the second power FET, wherein the control circuit is configured to operate the inductor by driving the first power FET and the second power FET in a switching cycle, the switching cycle comprising: a first phase in which the first power FET is turned on and the second power FET is turned off, in which the current flowing through the inductor increases linearly, and a second phase, wherein the first power FET is turned off and the second power FET is turned on, wherein the current flowing through the inductor decreases linearly; and a sensor circuit configured to monitor a current flowing through a power FET corresponding to the first power FET or the second power FET, whereby a low-pass filtered signal is proportional to an average value of the current flowing through the inductor; The sensor circuit comprises: Sense resistor; The regulator circuit is configured as: setting a first current flowing through the sense resistor to zero when a drive signal applied to a gate terminal of the power FET is set to turn off the power FET; and When the drive signal applied to the gate terminal is configured to turn on the power FET, regulating the first current flowing through the sense resistor so that a voltage drop across the sense resistor corresponds to a voltage drop between a first conductive terminal and a second conductive terminal of the power FET; a measurement circuit configured to provide a second current corresponding to or proportional to the first current; resistors; a first electronic switch configured to selectively apply the second current to the resistor according to a first control signal; a low-pass filter configured to generate a low-pass filtered signal by filtering, at the resistor, a voltage generated by applying the second current to the resistor; a voltage follower configured to generate a replica of the low-pass filtered signal; and a second electronic switch configured to selectively apply the replica of the low-pass filtered signal to the resistor; The control circuit is further configured to: closing the first electronic switch and opening the second electronic switch when the power FET is turned on, wherein the voltage at the resistor is proportional to an instantaneous value of the current flowing through the power FET; and When the power FET is turned off, the first electronic switch is opened and the second electronic switch is closed, wherein the voltage at the resistor corresponds to the low-pass filtered signal, and wherein the low-pass filtered signal is proportional to an average value of the current flowing through the power FET during the period when the power FET is turned on.

17. The electronic power converter of claim 16, wherein the first power FET is implemented using a first plurality of parallel FETs and the second power FET is implemented using a second plurality of parallel FETs, and wherein the control circuit is configured to: obtaining the low-pass filtered signal proportional to an average value of the current flowing through the first power FET or the second power FET during a period in which the first power FET or the second power FET is closed; determining a given number of FETs to be closed based on the low-pass filtered signal that is proportional to an average value of the current flowing through the first power FET or the second power FET during a period in which the first power FET or the second power FET is closed; During the first phase, closing the given number of FETs of the first plurality of parallel FETs; as well as During the second phase, the given number of FETs of the second plurality of parallel FETs are closed.

18. The electronic power converter of claim 16, wherein the sensor circuit is configured to monitor current flowing through the first power FET, and wherein the control circuit is configured to begin the second phase when the voltage at the resistor reaches a given threshold.

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