A dynamic D flip-flop based on negative feedback to improve pseudo-static loop

Abstract

The present invention relates to a dynamic D flip-flop based on negative feedback to improve a pseudo-static loop. The traditional dynamic D flip-flop uses charge to store data information, which results in data loss caused by charge discharge through resistance under a low-frequency clock. The traditional optimization is to add a small-sized inverter to charge and discharge the capacitor to keep the data stable. However, the two-stage inverter cascade constitutes a positive feedback register structure, which requires a stronger write capability or a longer write time when the data changes. The structure proposed by the present invention is controlled by timing. When data is written, the pseudo-static loop is disconnected from the main circuit, and self-discharge or self-charging is performed in advance through negative feedback to reduce the transmission delay of the data. When the data is maintained, the pseudo-static circuit is connected to the main circuit to keep the data stable. The present invention ensures the stability of low-frequency data without affecting the high-frequency characteristics of the dynamic D flip-flop.

Description

Technical Field

[0001] The invention relates to a dynamic D trigger for improving a pseudo-static loop based on negative feedback. Background Art

[0002] The traditional CMOS dynamic D flip-flop is different from the CMOS static D flip-flop. The CMOS static D flip-flop requires 4 inverters and 4 transmission gates, while the dynamic D flip-flop maintains data by increasing the input stage capacitor to store charge. However, if the data input by the next clock is different from the stored data, it is very likely that the input stage capacitor will be charged and discharged, resulting in bit errors. In order to solve the problem of unstable stored charge, the traditional method maintains the charge by adding a pseudo-static circuit. Figure 1 As shown in FIG. 1 , a register structure is formed by adding a small-sized inverter to the inverter in the dynamic D flip-flop. The design of the pseudo-static loop greatly improves the noise resistance of the storage node. Its essence is to force the storage node to be locked at 0 or 1 through a positive feedback loop. Figure 1 In the embodiment, the first transmission gate TG1 has one end connected to the input signal D, and the other end connected to the first charge storage capacitor C1 and the input end of the first inverter INV1; the other end of the first charge storage capacitor C1 is grounded, the NMOS gate end of the first transmission gate TG1 is connected to the first positive clock CLK, and the PMOS gate end is connected to the first positive clock CLK. The input and output of the first inverter INV1 and the first feedback inverter SINV1 are connected end to end to form a positive feedback register structure. The output of the first inverter INV1 is connected to the input of the second transmission gate TG2, and the output of the second transmission gate TG2 is connected to the second charge storage capacitor C2 and the second inverter INV2; the second charge storage capacitor is grounded from the other end of C2, and the NMOS gate of the second transmission gate TG2 is connected to the second reverse clock The gate terminal of the PMOS is connected to the first positive clock CLK. The input and output of the second inverter INV2 and the second feedback inverter SINV2 are connected end to end to form a positive feedback register structure. The output of the second inverter INV2 is the output Q level of the dynamic D flip-flop.

[0003] However, the addition of a pseudo-static loop will also bring corresponding problems. First, the pseudo-static loop will increase the setup time of the D flip-flop, thereby increasing the delay of data transmission. The advantage of the dynamic D flip-flop is that its structure is simple and the delay is much smaller than other types of D flip-flops, so it can be widely used in digital integrated circuits with high-frequency clocks. If the pseudo-static loop is not designed properly, it will increase the delay. Second, the pseudo-static loop will form a positive feedback closed loop locally. Every time different data is written to the previous level, the local positive feedback loop must be broken to refresh the charge of the storage node. If the size of the pseudo-static loop is too large, different data cannot be written into the D flip-flop, making the function of the D flip-flop invalid. Summary of the invention

[0004] The present invention solves the problem of pseudo-static loop of dynamic D flip-flop and proposes a structure based on timing control and negative feedback control. Figure 2 shown.

[0005] Figure 2 In the embodiment, the first transmission gate TG1 has one end connected to the input signal D, and the other end connected to the first charge storage capacitor C1 and the input end of the first inverter INV1; the other end of the first charge storage capacitor C1 is grounded, the NMOS gate end of the first transmission gate TG1 is connected to the first positive clock CLK, and the PMOS gate end is connected to the second reverse clock The input end of the first inverter INV1 is connected to the source of the first transistor MOS1, and the drain of the first transistor MOS1 is connected to the output of the third inverter INV3; the output end of the first inverter INV1 is connected to the drain of the second transistor MOS2, and the source of the second transistor MOS2 is connected to the input of the third inverter INV3. The input of the third inverter INV3 is connected to the drain of the third transistor MOS3, and the output end of the third inverter INV3 is connected to the source of the third transistor MOS3. The gate of the first transistor MOS1 and the gate of the second transistor MOS2 are connected to the second reverse clock The gate of the third transistor MOS3 is connected to the first positive clock CLK.

[0006] The output end of the first inverter INV1 is connected to the input end of the second transmission gate TG2, and the output end of the second transmission gate TG2 is connected to the second charge storage capacitor C2 and the second inverter INV2; the second charge storage capacitor C2 is grounded, and the NMOS gate end of the second transmission gate TG2 is connected to the second reverse clock The gate terminal of the PMOS is connected to the first positive clock CLK. The input terminal of the second inverter INV2 is connected to the source of the fourth transistor MOS4, and the drain of the fourth transistor MOS4 is connected to the output of the fourth inverter INV4; the output terminal of the second inverter INV2 is connected to the drain of the fifth transistor MOS5, and the source of the fifth transistor MOS5 is connected to the input of the fourth inverter INV4. The input of the fourth inverter INV4 is connected to the drain of the sixth transistor MOS6, and the output terminal of the fourth inverter INV4 is connected to the source of the sixth transistor MOS6. The gate of the fourth transistor MOS4 and the gate of the fifth transistor MOS5 are connected to the first positive clock CLK, and the gate of the sixth transistor MOS6 is connected to the second reverse clock The output of the second inverter INV2 is the output stage Q of the improved dynamic D flip-flop. Figure 2 The arrows in the diagram represent the direction of signal transmission, and “+” and “-” represent positive feedback and negative feedback, respectively.

[0007] The working process of the dynamic D flip-flop based on negative feedback control is described as follows.

[0008] Step 1: When data is transmitted to the input D of the dynamic D flip-flop and the first positive clock CLK is high, the second reverse clock is low level, the first transmission gate TG1 is turned on, and the D-end data is transmitted into the dynamic D flip-flop. The first transistor MOS1 and the second transistor MOS2 are turned off, and the output stage writing only needs to charge the first charge storage capacitor C1, without breaking the closed-loop positive feedback formed by the first inverter INV1 and the third inverter INV3. During operation, INV1 adopts a larger width-to-length ratio, the width-to-length ratio of the NMOS transistor is about 250μm to 0.18μm, and the width-to-length ratio of the PMOS transistor is about 500μm to 0.18μm. C1 is its parasitic capacitance, and its size is about ten femtofarads to one hundred femtofarads, so no additional layout area is required. At this time, the third transistor MOS3 is turned on, which is equivalent to short-circuiting the input and output of the third inverter INV3 in principle, forming a self-discharging or self-charging negative feedback structure, so that the voltage value of the input and output of the third inverter INV3 is stabilized at half the power supply voltage, and the transmission of the voltage signal is as follows. Figure 2 Indicated by the arrow marked with “-”.

[0009] Step 2: When the first positive clock CLK is at a low level, the second reverse clock is high, the first transmission gate TG1 is disconnected, the first transistor MOS1 and the second transistor MOS2 are turned on, and the third transistor MOS3 is turned off. At this time, the closed-loop negative feedback of the third transistor MOS3 is terminated, and the input and output of the third inverter INV3 are short-circuited with the output input of the first inverter INV1, forming a closed-loop positive feedback register structure, thereby stabilizing the charge of the first charge storage capacitor C1. The transmission of the voltage signal is as follows Figure 2 In this stage, when the written data changes, the first inverter INV1 only needs to pull the input end of the third inverter INV3 from half the power supply voltage to the power supply or to the ground, instead of pulling it down from the power supply to the ground, or from the ground to the power supply, which reduces the charging and discharging time by half, thereby reducing the delay of data transmission.

[0010] Step 3: When the first positive clock CLK is at a low level, the second reverse clock is high, the second transmission gate TG2 is turned on, and the signal is transmitted to the second transmission gate TG2 to turn on. At this time, the sixth transistor MOS6 is turned on, and the input and output of the fourth inverter INV4 are short-circuited, forming a self-discharging or self-charging negative feedback structure, so that the input and output voltage values ​​of the fourth inverter INV4 are stabilized at half of the power supply voltage, and the pressure of writing data is reduced by self-charging or self-discharging.

[0011] Step 4: When the first positive clock CLK is at a high level, the second reverse clock When the voltage is low, the second transmission gate TG2 is disconnected, and the data is transmitted to the output terminal Q of the dynamic D flip-flop. The fourth transistor MOS4 and the fifth transistor MOS5 are turned on, and the sixth transistor MOS6 is turned off. At this time, the closed-loop negative feedback of the sixth transistor MOS6 is terminated, and the input and output of the fourth inverter INV4 are short-circuited with the output input of the second inverter INV2, forming a closed-loop positive feedback register structure, thereby stabilizing the charge of the second charge storage capacitor C2. The transmission of the voltage signal is as follows: Figure 2 In this stage, when the written data changes, the second inverter INV2 only needs to pull the input end of the fourth inverter INV4 from half the power supply voltage to the power supply voltage or pull it down to the ground terminal at 0 potential, instead of pulling it down from the power supply to the ground, or from the ground to the power supply, which reduces the charging and discharging time by half, thereby reducing the delay of data transmission.

[0012] Beneficial Effects

[0013] The present invention proposes a dynamic D flip-flop structure based on timing control and negative feedback control, the essence of which is to greatly optimize the pseudo-static loop, which not only ensures the function of the pseudo-static loop, but also improves the delay and data writing problems of the pseudo-static loop. Compared with the traditional dynamic D flip-flop, it has the following beneficial effects.

[0014] 1. The improved pseudo-static loop is based on timing control. On the basis of ensuring data stability, it avoids encountering a register structure in a positive feedback loop when writing data in principle. In order to ensure data stability, the traditional D flip-flop structure adds a small-sized inverter to form a pseudo-static loop. However, the register structure composed of two inverters connected end to end will increase the difficulty of writing data, because its input load is no longer a pure capacitor, but also includes a resistor, thereby increasing the requirements for the load capacity of the previous level and increasing the corresponding delay. The present invention disconnects the pseudo-static loop from the main circuit during the data writing stage through the control of the timing switch, thereby reducing the requirements for writing capacity and ensuring the high-speed advantage of the dynamic D flip-flop.

[0015] 2. The improved pseudo-static loop is based on negative feedback control, which further reduces the requirements for writing capability. The first transistor MOS1 is taken as an example below and is referred to as MOS1. From a physical analysis, the essence of the MOS tube forming a switch is to control its equivalent resistance through the gate voltage. When the written data changes, such as from "0" to "1", MOS1 with a low gate voltage is in a high-impedance state, thereby disconnecting the input of INV1 and the output of INV3. But in fact, there is still a small current passing through MOS1. However, through the negative feedback structure of MOS3, the output end of INV3 quickly becomes half the power supply voltage, and the current passing through can be described by the following equations (1) and (2). R off is the equivalent resistance of MOS1 when it is disconnected, i is the current flowing through MOS1 without negative feedback control, i′ is the current flowing through MOS1 with negative feedback control, and VDD is the power supply voltage.

[0016]

[0017]

[0018] From formula (1) and formula (2), we know that, in principle, negative feedback control can increase the equivalent resistance of MOS1 when it is turned off by two times, thereby further reducing the requirement for writing capability.

[0019] 3. The improved pseudo-static loop is based on negative feedback control, which reduces the delay of data transmission. The second transmission gate TG2 is taken as an example below and is referred to as TG2 for short. When TG2 is turned on, the data is output from the first inverter INV1 to the Q terminal through the second inverter INV2. The main delay is reflected in the time for charging and discharging the capacitors at both ends of TG2. For the second charge storage capacitor C2, maintaining strong "1" and strong "0" means keeping the data stable, while the parasitic capacitance at the input end of the third inverter INV3 brings unnecessary delays. In the clock cycle before TG2 is turned on, the negative feedback loop keeps the input and output ends of the third inverter INV3 at half the power supply voltage. When TG2 is turned on, which is also when the second transistor MOS2 is turned on, taking the data at TG2 changing from "0" to "1" as an example, the first inverter INV1 does not need to charge the fan-in capacitor of the third inverter INV3 from 0 to VDD, but from Charging to VDD reduces the charging time by half, thereby reducing the delay in data transmission.

[0020] 4. The improved pseudo-static loop is based on timing control and negative feedback control, which reduces the size requirements of the pseudo-static loop and thus reduces the design difficulty. Figure 1In the example, the size selection of the first feedback inverter SINV1 and the second feedback inverter SINV2 is a dilemma. If the size of the feedback inverter is too large, it will form a strong positive feedback register structure, and it is difficult for the outside world to change its state. If the size of the feedback inverter is too small, the charge of the charge storage capacitor will be unstable, thereby reducing the stability of the data. Figure 2 In the architecture, there are two working states for the first inverter INV1. One is the data writing state, in which the first transistor MOS1 and the second transistor MOS2 are not turned on, and INV3 is in a negative feedback state to reduce the requirements for writing capability and the delay of data transmission. The second is the data holding state, in which the first transistor MOS1 and the second transistor MOS2 are turned on, and the first inverter INV1 and the third inverter INV3 form a positive feedback register structure to maintain data stability. For designers, the first inverter INV1 and the third inverter INV3 include other transistors, and can adopt the same size to ensure the matching of the layout; the size can also be flexibly designed to meet the needs of different application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 For traditional dynamic D flip-flop and traditional pseudo-static loop

[0022] Figure 2 The internal structure of the dynamic D flip-flop based on the negative feedback pseudo-static loop improvement proposed by the present invention

[0023] Figure 3 A 4-bit pseudo-random sequence generator constructed by using the dynamic D flip-flop proposed by the present invention

[0024] Figure 4 A divide-by-two frequency divider constructed by using the dynamic D flip-flop proposed by the present invention

[0025] Figure 5 This is the time domain waveform of the pseudo-random sequence generator under a 4.95GHz clock signal

[0026] Figure 6 The time domain waveform of the pseudo-random sequence generator under a 0.5Hz clock signal

[0027] Figure 7 The time domain waveform of the divide-by-two frequency divider under a 5GHz clock signal

[0028] Figure 8 The time domain waveform of the divide-by-two frequency divider under a 0.5Hz clock signal

[0029] Fig. 9The time domain waveform of the frequency divider composed of a dynamic D flip-flop for removing a pseudo-static loop under a clock signal of 0.5 Hz is shown to verify the improvement of the low-frequency characteristics of the present invention. DETAILED DESCRIPTION

[0030] The dynamic circuit structure of the pseudo-static loop based on negative feedback control proposed by the present invention is improved, that is, Figure 2 The circuit structure shown in is packaged into a dynamic D flip-flop, which is embodiment 1. The dynamic D flip-flop is respectively applied to the 4-bit pseudo-random sequence generator in embodiment 2 and the divide-by-two frequency divider in embodiment 3. The embodiment uses TSMC 180nm process library for actual design and simulation verification. Specific embodiment 1

[0032] The following combination Figure 2 The specific circuit connection and implementation mode as well as device parameters of the present invention are described.

[0033] The present invention proposes a circuit based on timing control and negative feedback control to solve the pseudo-static loop problem of a dynamic D flip-flop. The entire circuit consists of a transmission gate, a charge storage device, an inverter and a MOS transistor. Figure 2 The first stored charge C1 and the second stored charge C2 are replaced by the parasitic capacitance of the gate in the first inverter INV1 and the second INV2 input stage. Using the parasitic capacitance as the charge storage capacitor can reduce the data writing time and reduce the layout area.

[0034] The connection relationship of the specific embodiment 1 is as follows: the first transmission gate TG1 has one end connected to the input signal D and the other end connected to the input end of the first inverter INV1; the NMOS gate end of the first transmission gate TG1 is connected to the first positive clock CLK, and the PMOS gate end is connected to the second reverse clock The input end of the first inverter INV1 is connected to the source of the first transistor MOS1, and the drain of the first transistor MOS1 is connected to the output of the third inverter INV3; the output end of the first inverter INV1 is connected to the drain of the second transistor MOS2, and the source of the second transistor MOS2 is connected to the input of the third inverter INV3. The input of the third inverter INV3 is connected to the drain of the third transistor MOS3, and the output end of the third inverter INV3 is connected to the source of the third transistor MOS3. The gate of the first transistor MOS1 and the gate of the second transistor MOS2 are connected to the second reverse clock The gate of the third transistor MOS3 is connected to the first positive clock CLK.

[0035] The output terminal of the first inverter INV1 is connected to the input terminal of the second transmission gate TG2, and the output terminal of the second transmission gate TG2 is connected to the second inverter INV2; the NMOS gate terminal of the second transmission gate TG2 is connected to the second reverse clock The gate terminal of the PMOS is connected to the first positive clock CLK. The input terminal of the second inverter INV2 is connected to the source of the fourth transistor MOS4, and the drain of the fourth transistor MOS4 is connected to the output of the fourth inverter INV4; the output terminal of the second inverter INV2 is connected to the drain of the fifth transistor MOS5, and the source of the fifth transistor MOS5 is connected to the input of the fourth inverter INV4. The input of the fourth inverter INV4 is connected to the drain of the sixth transistor MOS6, and the output terminal of the fourth inverter INV4 is connected to the source of the sixth transistor MOS6. The gate of the fourth transistor MOS4 and the gate of the fifth transistor MOS5 are connected to the first positive clock CLK, and the gate of the sixth transistor MOS6 is connected to the second reverse clock The output of the second inverter INV2 is the output stage Q of the improved dynamic D flip-flop.

[0036] The inverters INV1, INV2 and the transmission gates TG1, TG2 in the circuit are composed of a PMOS and a NOMS transistor. Among them, the inverters INV3 and INV4 are designed separately, and their NMOS and PMOS lengths are both 220.0nm and their widths are both 180.0nm. The lengths of the NMOS and PMOS transistors of the inverters INV1 and INV2 are 1.95μm and their widths are 180.0nm. The lengths and widths of the NMOS and PMOS transistors of the transmission gates TG1 and TG2 are both 1.9μm and their widths are both 180.0nm. The lengths and widths of the remaining MOS transistors are the same, with a length of 220.0nm and a width of 180.0nm. The detailed parameters of each device are shown in Table 1.

[0037] Table 1. Parameters of each device

[0038]

[0039]

[0040] The working description of the dynamic D flip-flop feedback in negative feedback is as follows.

[0041] Step 1: When data is transmitted to the input D of the dynamic D flip-flop and the first positive clock CLK is high, the second reverse clock is low level, the first transmission gate TG1 is turned on, and the D-end data is transmitted into the dynamic D flip-flop. The first transistor MOS1 and the second transistor MOS2 are turned off, and the output stage writing only needs to charge the first charge storage capacitor C1, without breaking the closed-loop positive feedback formed by the first inverter INV1 and the third inverter INV3. During operation, INV1 adopts a larger width-to-length ratio, the width-to-length ratio of the NMOS transistor is about 250μm to 0.18μm, and the width-to-length ratio of the PMOS transistor is about 500μm to 0.18μm. C1 is its parasitic capacitance, and its size is about ten femtofarads to one hundred femtofarads, so no additional layout area is required. At this time, the third transistor MOS3 is turned on, which is equivalent to short-circuiting the input and output of the third inverter INV3 in principle, forming a self-discharging or self-charging negative feedback structure, so that the voltage value of the input and output of the third inverter INV3 is stabilized at half the power supply voltage, and the transmission of the voltage signal is as follows. Figure 2 Indicated by the arrow marked with “-”.

[0042] Step 2: When the first positive clock CLK is at a low level, the second reverse clock is high, the first transmission gate TG1 is disconnected, the first transistor MOS1 and the second transistor MOS2 are turned on, and the third transistor MOS3 is turned off. At this time, the closed-loop negative feedback of the third transistor MOS3 is terminated, and the input and output of the third inverter INV3 are short-circuited with the output input of the first inverter INV1, forming a closed-loop positive feedback register structure, thereby stabilizing the charge of the first charge storage capacitor C1. The transmission of the voltage signal is as follows Figure 2 In this stage, when the written data changes, the first inverter INV1 only needs to pull the input end of the third inverter INV3 from half the power supply voltage to the power supply or to the ground, instead of pulling it down from the power supply to the ground, or from the ground to the power supply, which reduces the charging and discharging time by half, thereby reducing the delay of data transmission.

[0043] Step 3: When the first positive clock CLK is at a low level, the second reverse clock is high, the second transmission gate TG2 is turned on, and the signal is transmitted to the second transmission gate TG2 to turn on. At this time, the sixth transistor MOS6 is turned on, and the input and output of the fourth inverter INV4 are short-circuited, forming a self-discharging or self-charging negative feedback structure, so that the input and output voltage values ​​of the fourth inverter INV4 are stabilized at half of the power supply voltage, and the pressure of writing data is reduced by self-charging or self-discharging.

[0044] Step 4: When the first positive clock CLK is at a high level, the second reverse clock When the voltage is low, the second transmission gate TG2 is disconnected, and the data is transmitted to the output terminal Q of the dynamic D flip-flop. The fourth transistor MOS4 and the fifth transistor MOS5 are turned on, and the sixth transistor MOS6 is turned off. At this time, the closed-loop negative feedback of the sixth transistor MOS6 is terminated, and the input and output of the fourth inverter INV4 are short-circuited with the output input of the second inverter INV2, forming a closed-loop positive feedback register structure, thereby stabilizing the charge of the second charge storage capacitor C2. The transmission of the voltage signal is as follows: Figure 2 In this stage, when the written data changes, the second inverter INV2 only needs to pull the input end of the fourth inverter INV4 from half the power supply voltage to the power supply voltage or pull it down to the ground terminal at 0 potential, instead of pulling it down from the power supply to the ground, or from the ground to the power supply, which reduces the charging and discharging time by half, thereby reducing the delay of data transmission.

[0045] Example 2

[0046] Figure 3 is a logical structure diagram of pseudo-random sequence generation, wherein the input D terminal and output Q terminal of the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3, and the fourth D flip-flop DFF4 are cascaded, that is, the output Q1 terminal of the first D flip-flop DFF1 is connected to the input D2 terminal of the second D flip-flop DFF2, the output Q2 terminal of the second D flip-flop DFF2 is connected to the input D3 terminal of the third D flip-flop DFF3, the output Q3 terminal of the third D flip-flop DFF3 is connected to the input D4 terminal of the fourth D flip-flop DFF4, the output Q3 terminal of the third D flip-flop DFF1 and the output Q4 terminal of the fourth flip-flop DFF4 are connected to the input terminal of the XOR gate XOR in the figure to perform XOR operation, and the output terminal of the XOR gate XOR is connected to the input terminal of the first flip-flop DFF1. The clock terminals of the first D flip-flop DFF1, the second D flip-flop DFF2, the third D flip-flop DFF3, and the fourth D flip-flop DFF4 are connected to the first positive clock CLK of the same frequency, and the output terminals Q1, Q2, Q3, and Q4 of the four are the signal output terminals of the pseudo-random sequence.

[0047] The biggest advantage of the present invention is that it greatly broadens the frequency application range of the dynamic D flip-flop through clock control and negative feedback control. The operating frequency of the dynamic D flip-flop mainly refers to the operating frequency of the switch inside the D flip-flop controlled by the clock signal. Figure 5 The time domain waveform of the 4-bit pseudo-random sequence generator constructed based on the present invention at a clock period of 202ps, that is, a clock frequency of 4.95GHz is demonstrated. From the simulation results, it can be seen that the pseudo-random sequence generator can still work normally at a higher switching frequency close to 5G. Figure 6The 4-bit pseudo-random sequence constructed by the present invention is shown in the time domain waveform when the clock cycle is 2s and the clock frequency is 0.5Hz. From the simulation results, it can be seen that under the low frequency of 0.5Hz, the pseudo-static loop works normally and ensures the data stability of the dynamic D flip-flop. Figure 5 and Figure 6 It can be seen that the dynamic D flip-flop improved based on the negative feedback pseudo-static loop of the present invention has higher frequency adaptability and can work normally in low frequency or high frequency conditions.

[0048] Example 3

[0049] Figure 4 The figure shows a frequency divider formed by the dynamic D flip-flop of the present invention. The clock terminal of the first D flip-flop DFF1 is connected to the first positive clock CLK, the output Q1 terminal is connected to the input terminal of the first inverter INV1 and the input terminal of the second inverter INV2, the output terminal of the first inverter INV1 is connected to the input terminal D1 of the first D flip-flop, and the output terminal of the second inverter INV2 is a frequency-divided signal OUT of the first positive clock CLK.

[0050] The frequency division buffer stage of the second inverter INV2 improves the driving capability of the frequency division. Figure 7 The time domain waveform of the binary divider formed by the dynamic D flip-flop structure improved by the negative feedback pseudo-static loop is shown. The input is a high-frequency 5GHz clock signal, and the output is a 2.5GHz binary frequency signal. Figure 8 The example shows that the input clock signal is 0.5Hz, and the output is a 0.25Hz divided-by-two signal. Figure 2 The first transistor MOS1, the second transistor MOS2, the third transistor MOS3, the fourth transistor MOS4, the fifth transistor MOS5, the sixth transistor MO6, the third inverter INV3 and the fourth inverter INV4 in the circuit are removed, that is, the pseudo-static loop is removed, and the circuit is returned to the traditional dynamic D flip-flop, and the circuit is packaged and applied in Figure 4 In the divide-by-two frequency divider shown, we get Fig. 9 The waveform shown in the figure inputs a 0.5Hz clock signal, but the output is an incorrect waveform. This shows that under low frequency conditions, the traditional dynamic D flip-flop loses data due to the loss of stored charge, thus losing its triggering function. Figure 8 and Fig. 9 It can be seen that the present invention can significantly improve the low-frequency characteristics of the dynamic D flip-flop and has a higher frequency application range.

Claims

1. A dynamic D flip-flop based on negative feedback to improve pseudo-static loop, characterized in that: The first transmission gate TG1 has one end connected to the input signal D, and the other end connected to the first charge storage capacitor C1 and the input end of the first inverter INV1; the other end of the first charge storage capacitor C1 is grounded, the NMOS gate end of the first transmission gate TG1 is connected to the first positive clock CLK, and the PMOS gate end is connected to the second reverse clock The input end of the first inverter INV1 is connected to the source of the first transistor MOS1, and the drain of the first transistor MOS1 is connected to the output of the third inverter INV3; the output end of the first inverter INV1 is connected to the drain of the second transistor MOS2, and the source of the second transistor MOS2 is connected to the input of the third inverter INV3; the input of the third inverter INV3 is connected to the drain of the third transistor MOS3, and the output end of the third inverter INV3 is connected to the source of the third transistor MOS3; the gate of the first transistor MOS1 and the gate of the second transistor MOS2 are connected to the second reverse clock The gate of the third transistor MOS3 is connected to the first positive clock CLK; The output end of the first inverter INV1 is connected to the input end of the second transmission gate TG2, and the output end of the second transmission gate TG2 is connected to the second charge storage capacitor C2 and the second inverter INV2; the second charge storage capacitor C2 is grounded, and the NMOS gate end of the second transmission gate TG2 is connected to the second reverse clock The gate of the PMOS is connected to the first positive clock CLK; the input of the second inverter INV2 is connected to the source of the fourth transistor MOS4, and the drain of the fourth transistor MOS4 is connected to the output of the fourth inverter INV4; the output of the second inverter INV2 is connected to the drain of the fifth transistor MOS5, and the source of the fifth transistor MOS5 is connected to the input of the fourth inverter INV4; the input of the fourth inverter INV4 is connected to the drain of the sixth transistor MOS6, and the output of the fourth inverter INV4 is connected to the source of the sixth transistor MOS6; the gate of the fourth transistor MOS4 and the gate of the fifth transistor MOS5 are connected to the first positive clock CLK, and the gate of the sixth transistor MOS6 is connected to the second reverse clock The output of the second inverter INV2 is the output stage Q of the improved dynamic D flip-flop.

2. A dynamic D flip-flop based on negative feedback to improve a pseudo-static loop as claimed in claim 1, characterized in that: Step 1: When data is transmitted to the input D of the dynamic D flip-flop and the first positive clock CLK is high, the second reverse clock is low level, the first transmission gate TG1 is turned on, and the D-end data is transmitted into the dynamic D flip-flop; the first transistor MOS1 and the second transistor MOS2 are turned off, and the output stage writing only needs to charge the first charge storage capacitor C1, and the third transistor MOS3 is turned on, which is equivalent to short-circuiting the input and output of the third inverter INV3, forming a self-discharging or self-charging negative feedback structure, so that the input and output voltage values ​​of the third inverter INV3 are stabilized at half the power supply voltage; Step 2: When the first positive clock CLK is at a low level, the second reverse clock is high level, the first transmission gate TG1 is disconnected, the first transistor MOS1 and the second transistor MOS2 are turned on, and the third transistor MOS3 is turned off; at this time, the closed-loop negative feedback of the third transistor MOS3 is terminated, and the input and output of the third inverter INV3 are short-circuited with the output input of the first inverter INV1, forming a closed-loop positive feedback register structure, thereby stabilizing the charge of the first charge storage capacitor C1; when the written data jumps, the first inverter INV1 only needs to pull the input end of the third inverter INV3 from half the power supply voltage to the power supply or pull it down to the ground, reducing half the charging and discharging time, thereby reducing the delay of data transmission; Step 3: When the first positive clock CLK is at a low level, the second reverse clock is high level, the second transmission gate TG2 is turned on, and the signal is transmitted to the second transmission gate TG2 to turn on; at this time, the sixth transistor MOS6 is turned on, and the input and output of the fourth inverter INV4 are short-circuited, forming a self-discharging or self-charging negative feedback structure, so that the input and output voltage values ​​of the fourth inverter INV4 are stabilized at half of the power supply voltage, and the pressure of writing data is reduced by self-charging or self-discharging; Step 4: When the first positive clock CLK is at a high level, the second reverse clock When it is at a low level, the second transmission gate TG2 is disconnected, and data is transmitted to the output terminal Q of the dynamic D flip-flop; the fourth transistor MOS4 and the fifth transistor MOS5 are turned on, and the sixth transistor MOS6 is turned off; at this time, the closed-loop negative feedback of the sixth transistor MOS6 is terminated, and the input and output of the fourth inverter INV4 are short-circuited with the output input of the second inverter INV2, forming a closed-loop positive feedback register structure, thereby stabilizing the charge of the second charge storage capacitor C2; when the written data jumps, the second inverter INV2 only needs to pull the input terminal of the fourth inverter INV4 from half the power supply voltage to the power supply voltage or pull it down to the ground terminal at 0 potential, reducing the charging and discharging time by half, thereby reducing the delay of data transmission.

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