Integrated level detection chip circuit and its application

Abstract

The integrated level detection chip circuit and application disclosed in the present invention obtain a selection signal by comparing an off-chip input with a reference voltage. The selection signal selects an oscillation circuit to output a square wave for transmission, and drives an off-chip display module through a buffer to detect the input level. At the same time, the reference voltage generation circuit is controlled by two off-chip signals to achieve use in different application environments. It has a high degree of integration. A system built with this circuit chip and simple peripheral devices can detect different battery power states, which can significantly reduce production costs.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit design, and in particular relates to an integrated level detection chip circuit. The present invention also relates to a method for performing on-chip level detection using the integrated level detection chip circuit. Background Art

[0002] With the increasing prevalence of motor vehicles, automotive electronics are becoming increasingly diverse. Battery testers, as a type of automotive electronics, have also seen rapid development, with a growing variety and increasingly comprehensive functionality. Some battery testers directly read the voltage, others use a pointer, and still others use indicator lights to determine the voltage level. Regardless of the reading method, these battery testers require a level detection circuit. Battery testers on the market use a variety of functional chips, and the entire level detection circuit is built from a large number of single-function chips, resulting in high costs. Furthermore, different applications require different battery testers with varying voltage ranges. The fewer functional chips used in a circuit, the more functions each chip can integrate, resulting in a higher level of integration and wider applicability, which can significantly reduce product manufacturing costs.

[0003] Every battery tester requires a level detection circuit, and the manufacturing cost of this circuit directly determines the production cost of the entire level tester. The more functional chips required in the level detection circuit, the higher the cost. Therefore, researching a power detection chip with integrated multiple functional modules is of great significance. Summary of the Invention

[0004] The object of the present invention is to provide an integrated level detection chip circuit, which can integrate a level detection functional circuit into the same chip.

[0005] Another object of the present invention is to provide a method for performing on-chip level detection using an integrated level detection chip circuit, which can be used for detection in different level ranges and reduce application costs.

[0006] The first technical solution adopted by the present invention is: an integrated level detection chip circuit, including a reference voltage and current generating circuit, the output end of the reference voltage and current generating circuit is respectively connected to a reference voltage generating circuit, an oscillation circuit and a comparator group, the output end of the reference voltage generating circuit is connected to the comparator group, and the output end of the comparator group and the output end of the oscillation circuit are commonly connected to an output selection drive circuit group.

[0007] The first technical solution of the present invention is also characterized in that:

[0008] The comparator group includes multiple hysteresis comparators connected to the reference voltage and current generating circuit, one input end of each hysteresis comparator is connected to a group of reference voltages output by the reference voltage generating circuit, and the other input end of each hysteresis comparator is connected to the detection voltage input end VIN.

[0009] The output selection driving circuit group includes a plurality of AND gates connected one by one with the output ends of the plurality of hysteresis comparators, the other input end of each AND gate is connected with the output end of the oscillation circuit, and the output end of each AND gate is connected with a buffer.

[0010] The reference voltage generating circuit includes a negative input terminal of an operational amplifier A1 connected to an output terminal of a reference voltage and current generating circuit. The output terminal of the operational amplifier A1 is connected to a gate of a PMOS transistor M1. The source of the PMOS transistor M1 is connected to a power supply, and the drain is connected to a resistor. The resistor is connected to ground via a series resistor of four parallel switches. A node between one resistor and the four parallel switches is connected to a positive input terminal of the operational amplifier A1. The drain of the PMOS transistor M1 is also connected to a negative input terminal of an operational amplifier A2. The output terminal of the operational amplifier A2 is connected to a gate of a PMOS transistor M2. The source of the PMOS transistor M2 is connected to a power supply, and the drain is connected to a positive input terminal of the operational amplifier A2 via a resistor. The positive input terminal of the operational amplifier A2 is grounded via a series resistor. The node between two resistors in the series resistor serves as the output.

[0011] The second technical solution adopted by the present invention is: a method for performing on-chip level detection using an integrated level detection chip circuit, comprising the following steps:

[0012] Step 1: After the circuit is powered on, the reference voltage and current generating circuit provides the required voltage and current for the reference voltage generating circuit, the oscillator circuit, and the comparator group. The reference voltage generating circuit outputs a set of reference voltages as an input of each hysteresis comparator in the comparator group. The oscillator circuit outputs a square wave of a certain frequency as an input of all AND gates in the output selection drive circuit group.

[0013] Step 2: The hysteresis comparator in the comparator group compares the input voltage to be measured VIN with the voltage generated by the reference voltage generating circuit simultaneously. The output of the hysteresis comparator is a high or low level, which is input as a selection signal to the output selection drive circuit group.

[0014] Step 3. The high or low level output by the hysteresis comparator is ANDed with the square wave output by the oscillation circuit. When the level is high, the AND gate outputs a square wave which is output to the off-chip display module through the step-by-step buffer. When the level is low, the AND gate remains low and the corresponding step-by-step buffer output also remains low and cannot drive the off-chip display module, thereby realizing level detection.

[0015] The second technical solution of the present invention is also characterized in that:

[0016] In step 1, the reference voltage generation circuit outputs a set of reference voltages Vr1, Vr2, Vr3, ..., Vrn to the comparator group based on the two-bit control signal MS<0:1> input from the chip. When the detection environment changes, the control signal MS<0:1> is used to adjust the reference voltage range generated by the reference voltage generation circuit.

[0017] The present invention provides the following beneficial effects: the integrated level detection chip circuit and its application integrate four functional modules: a reference generation circuit, a comparison circuit, an oscillation circuit, and an output circuit. Furthermore, the detection range can be adjusted via a control signal. The level detection circuit constructed using the level detection chip proposed in the present invention reduces the number of chips required for conventional battery testing instruments, has advantages such as a simple structure and low production cost, and can detect the status of automobile batteries, thus having wide applicability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a circuit block diagram of an integrated level detection chip of the present invention;

[0019] Figure 2 It is an internal circuit diagram of the reference voltage generating circuit in the integrated level detection chip circuit block diagram of the present invention;

[0020] Figure 3 This is a working timing diagram of the integrated level detection chip circuit of the present invention.

[0021] In the figure, 1. reference voltage and current generating circuit, 2. reference voltage generating circuit, 3. oscillation circuit, 4. comparator group, 5. hysteresis comparator, 6. output selection drive circuit group, 7. AND gate, 8. buffer. DETAILED DESCRIPTION

[0022] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] The present invention provides an integrated level detection chip circuit, such as Figure 1As shown, the reference voltage and current generating circuit 1 is connected to the reference voltage generating circuit 2, the oscillation circuit 3 and each hysteresis comparator 5 in the comparator group 4 to provide voltage or current. The input control signal MS<0:1> is connected to the reference voltage generating circuit 2. A set of reference voltages output by the reference voltage generating circuit 2 is connected one-to-one with one input end of each hysteresis comparator 5 in the comparator group 4. The other input end of each hysteresis comparator 5 in the comparator group 4 is connected to the detection voltage input end VIN. The output end of each hysteresis comparator 5 in the comparator group 4 is connected one-to-one with one input end of each AND gate 7 in the output selection driving circuit group 6. The other input end of each AND gate 7 in the output selection driving circuit group 6 is connected to the output of the oscillation circuit 3. The output of each AND gate 7 in the output selection driving circuit group 6 is respectively connected one-to-one with the input of a buffer 8. The output of each progressive buffer 8 in the output selection driving circuit group 6 serves as the chip output end to drive the off-chip display module.

[0024] Among them, the implementation circuit of the reference voltage generating circuit 2 is as follows Figure 2 As shown, the negative input terminal of an operational amplifier A1 is connected to the output terminal of a reference voltage and current generating circuit 1. The output terminal of the operational amplifier A1 is connected to the gate of a PMOS transistor M1. The source of the PMOS transistor M1 is connected to a power supply, and the drain is connected to a resistor. The resistor is connected to ground via a series resistor of four parallel switches. A node between one resistor and the four parallel switches is connected to the positive input terminal of the operational amplifier A1. The drain of the PMOS transistor M1 is also connected to the negative input terminal of an operational amplifier A2. The output terminal of the operational amplifier A2 is connected to the gate of a PMOS transistor M2. The source of the PMOS transistor M2 is connected to the power supply, and the drain is connected to the positive input terminal of the operational amplifier A2 via a resistor. The positive input terminal of the operational amplifier A2 is grounded via a group of resistors in series. The node between two resistors in the resistor string serves as the output of the reference voltage generating circuit 2. The principle is as follows: the bandgap voltage Vbg output by the integrated voltage and current generating circuit 1 is input to the positive input terminal of the operational amplifier A1. After passing through the feedback circuit formed by A1, MOS transistor M1, and resistors, the output Vsel is a voltage proportional to the input Vbg. The proportion is determined by the resistance value selected by the input control signal MS<0:1>. Vsel serves as the input of the operational amplifier A2. After passing through the feedback circuit formed by A2, MOS transistor M2, and resistors, the outputs Vr1, Vr2, Vr3…Vrn serve as reference voltages and are proportional to Vsel.

[0025] The principle underlying the present invention is that the off-chip input circuit to be detected is compared with a set of set reference voltages. The comparison result determines whether the driving circuit is turned on. When the circuit is turned on, the clock signal drives the corresponding off-chip display module. The reference voltage is set to different detection ranges by a two-bit off-chip input digital control resistor network. All detection, judgment and driving circuits can be integrated in the same chip.

[0026] The present invention also provides a method for performing on-chip level detection using an integrated level detection chip circuit. The level detection circuit, as the core of the entire detection chip, can compare the input level with the reference voltage to determine the range of the input voltage. The output judgment signal is used as the chip output to drive the off-chip display module through the selection drive circuit. The level detection circuit that can be integrated into the chip is mainly composed of a reference circuit, a reference circuit, a comparison circuit, an oscillation circuit, and an output selection drive circuit. The reference circuit outputs an adjustable reference voltage to meet the application requirements of different detections. The comparison circuit samples the hysteresis comparator to avoid false flips caused by irrational factors to improve reliability. The oscillation circuit is used to drive the clock signal of the off-chip display to increase service life. Figure 3 The chip circuit of the present invention is specifically implemented according to the following steps:

[0027] Step 1: When the circuit starts working, the reference voltage and current generation circuit first provides the required voltage and current to the reference voltage generation circuit, comparator group, and oscillation circuit, so that each circuit can establish a correct working state.

[0028] Step 2: After each circuit establishes its working state, in a certain application environment, the reference voltage generation circuit outputs a set of reference voltages Vr1, Vr2, Vr3…Vrn to the comparator group based on the two-bit control signal MS<0:1> input from the off-chip. The oscillator circuit outputs a square wave Vck with a frequency of 50Hz to one input terminal of all AND gates in the output selection drive circuit group.

[0029] Step 3: Use the hysteresis comparator in the comparator group to compare the input voltage VIN with a set of voltages generated by the reference voltage generation circuit one by one at the same time, and the hysteresis comparator output is a high or low level;

[0030] Step 4: The high or low level output of the hysteresis comparator in the comparator group is simultaneously input into the other input end of the AND gate in the output selection drive circuit group. When the hysteresis comparator output of the AND gate is high, the AND gate outputs a square wave with the same frequency as Vck. When the hysteresis comparator output of the AND gate is low, the AND gate output remains at a low level.

[0031] Step 5: The square wave output from the AND gate in the output selection driving circuit group is increased in driving capability by a step-by-step buffer and then output to the off-chip driving display module. If the AND gate output is low, the output remains at a low level after the step-by-step buffer.

[0032] Step 6: When the detection environment changes, the voltage generated by the reference voltage generating circuit is adjusted using the control signal MS<0:1>, and then steps 3 to 5 are repeated to achieve detection of other level ranges.

[0033] Through the above approach, the present invention provides a level detection circuit that can be integrated into a CMOS chip. This circuit compares an off-chip input with a reference voltage to generate a selection signal. The selection signal selects an oscillator circuit to output a square wave for transmission, which then drives an off-chip display module via a buffer to detect the input level. Simultaneously, two off-chip signals are used to control the reference voltage generation circuit, enabling use in various application environments. This reduces the implementation cost of the level detection device and improves system integration.

Claims

1. The integrated level detection chip circuit is characterized by: The invention comprises a reference voltage and current generating circuit (1), wherein the output end of the reference voltage and current generating circuit (1) is respectively connected to a reference voltage generating circuit (2), an oscillating circuit (3) and a comparator group (4), wherein the reference voltage generating circuit (2) comprises a negative input end of an operational amplifier A1 connected to the output end of the reference voltage and current generating circuit (1), the output end of the operational amplifier A1 is connected to the gate of a PMOS tube M1, the source of the PMOS tube M1 is connected to a power supply, the drain of the PMOS tube M1 is connected to a resistor, the resistor is connected to ground through four parallel switches in series with resistors, a node between a resistor and the four parallel switches is connected to the positive input end of the operational amplifier A1, the drain of the PMOS tube M1 is simultaneously connected to the negative input end of the operational amplifier A2, the output end of the operational amplifier A2 is connected to the gate of the PMOS tube M2, the source of the PMOS tube M2 is connected to the power supply, the drain of the PMOS tube M2 is connected to the positive input end of the operational amplifier A2 through a resistor, and the operational amplifier A2 is connected to the negative input end of the operational amplifier A2. The positive input end of the reference voltage generating circuit (2) is grounded through a group of resistor strings, and the node between two resistors in the resistor string is used as the output. The output end of the reference voltage generating circuit (2) is connected to the comparator group (4). The comparator group (4) includes a plurality of hysteresis comparators (5) connected to the reference voltage current generating circuit (1). One input end of each hysteresis comparator (5) is connected to a group of reference voltages output by the reference voltage generating circuit (2). The other input end of each hysteresis comparator (5) is connected to the detection voltage input end VIN. The output end of the comparator group (4) and the output end of the oscillation circuit (3) are commonly connected to an output selection drive circuit group (6). The output selection drive circuit group (6) includes a plurality of AND gates (7) connected one to one with the output ends of the plurality of hysteresis comparators (5). The other input end of each AND gate (7) is connected to the output end of the oscillation circuit (3). The output end of each AND gate (7) is connected to a buffer (8).

2. A method for performing on-chip level detection using the integrated level detection chip circuit according to claim 1, characterized in that: The following steps are involved: Step 1: After the circuit is powered on, the reference voltage and current generating circuit (1) provides the required voltage and current for the reference voltage generating circuit (2), the oscillating circuit (3) and the comparator group (4); the reference voltage generating circuit (2) outputs a set of reference voltages as an input of each hysteresis comparator (5) in the comparator group (4); the oscillating circuit (3) outputs a square wave of a certain frequency as an input of all AND gates (7) in the output selection driving circuit group (6); wherein the reference voltage generating circuit (2) outputs a set of reference voltages Vr1, Vr2, Vr3 ... Vrn to the comparator group (4) according to the two-bit control signal MS<0:1> inputted from the chip; when the detection environment changes, the reference voltage range generated by the reference voltage generating circuit (2) is adjusted by using the control signal MS<0:1>; Step 2: The hysteresis comparator (5) in the comparator group (4) compares the input voltage to be measured VIN with the voltage generated by the reference voltage generating circuit (2) one by one at the same time. The output of the hysteresis comparator (5) is a high or low level, which is input as a selection signal to the output selection drive circuit group (6); Step 3: The high or low level output by the hysteresis comparator (5) is ANDed with the square wave output by the oscillation circuit (3). When the level is high, the AND gate outputs the square wave, which is output to the off-chip display module through the step-by-step buffer (8). When the level is low, the AND gate remains low, and the corresponding step-by-step buffer (8) output also remains low and cannot drive the off-chip display module, thereby realizing level detection.

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