Method and apparatus for testing comparators

Abstract

Embodiments of this disclosure relate to methods and apparatus for testing comparators. An apparatus for a system-on-a-chip (SoC) includes a comparator comprising a first input port, a second input port, and an output port. The first input signal and the second input signal are divided into N bit pairs, each N bit pair including one bit from the first input signal and one bit from the second input signal. The comparator is configured such that a mismatch between the first input signal and the second input signal causes the output signal to exhibit a first expected state. The apparatus also includes a test controller for performing a first operability test by causing a mismatch in the N bit pairs and verifying that the output signal exhibits the first expected state.

Description

TECHNICAL FIELD

[0001] The present invention relates to a method and apparatus for testing a comparator. BACKGROUND

[0002] Comparators often play an important role in testing and verifying that components of various machines and devices are operating correctly. In many applications, the health and safety of users can depend on the reliable operation of one or more comparators. However, errors can occur in comparators themselves. It can be advantageous to test the operation of comparators with built-in self-test (BIST) to detect errors in comparators and prevent them from affecting the functioning of a device or verifying the functioning of a device. Such BIST can also test for self-failure. SUMMARY

[0003] According to an embodiment of the invention, a built-in self-test apparatus for a system on a chip (SOC) comprises: a comparator disposed on the SOC, the comparator comprising: a first input port to receive a first input signal; a second input port to receive a second input signal; an output port to produce an output signal; and wherein the first input signal and the second input signal are divided into N pairs of bits, each pair of bits comprising one bit from the first input signal and one bit from the second input signal; and wherein the comparator is configured such that a mismatch between the first input signal and the second input signal causes the output signal to comprise a first expected state. The built-in self-test apparatus on the SOC further comprises a test controller disposed on the SOC and coupled with the first input port, the second input port, and the output port, the test controller configured to perform a first operability test by: generating a mismatch for each of the N pairs of bits, and verifying that the output signal comprises the first expected state in response to the mismatch for each of the N pairs of bits.

[0004] According to an embodiment of the invention, a system for testing operation of a comparator, the comparator comprising: a first input port configured to receive N bits; a second input port configured to receive N bits, wherein the N bits of the second input port and the N bits of the first input port are divided into N pairs of bits; and an output port configured to produce an output signal having a first expected state when any of the N pairs of bits mismatch. The system further comprises: a first circuit configured to produce a first signal comprising N bits; a second circuit configured to produce a second signal comprising N bits; a test controller configured to produce a test enable signal; a selection circuit coupled to the first circuit, the second circuit, and the test controller, the selection circuit configured to: pass the first signal to the first input port and the second signal to the second input port when the test enable signal is in a first state, and pass a first test signal from the test controller to the first input port and a second test signal from the test controller to the second input port when the test enable signal is in a second state; and wherein the test controller is configured to perform an operability test on the comparator by setting the test enable signal to the second state and changing the first test signal, the second test signal, or both the first test signal and the second test signal to mismatch the N pairs of bits.

[0005] According to an embodiment of the invention, a method of testing operation of a comparator on a system on a chip (SOC) comprises: receiving, by a test controller disposed on the SOC, an initialization signal; matching, using the test controller, a first signal received by the comparator with a second signal received by the comparator; checking an output signal from the comparator comprises an expected output for matching inputs; mismatching, using the test controller, the first signal received by the comparator with the second signal received by the comparator; and checking the output signal comprises an expected output for mismatching inputs.

[0006] According to embodiments of the present application, a system for testing the operation of comparators includes a plurality of comparators, each comparator including: a first input port configured to receive N bits; a second input port configured to receive N bits, wherein the N bits of the second input port and the N bits of the first input port are divided into N pairs of bits; and an output port configured to produce an output signal having a first expected state when any one of the N pairs of bits mismatches. According to embodiments, the system further includes: a first circuit configured to deliver a first signal including N bits to the first input port of each comparator of the plurality of comparators; a second circuit configured to deliver a second signal to the second input port of each comparator of the plurality of comparators; and wherein a test controller is configured to perform an operability test by instructing the first circuit, the second circuit, or both the first circuit and the second circuit to cause the N pairs of bits of each comparator of the plurality of comparators to mismatch. BRIEF DESCRIPTION OF DRAWINGS

[0007] One or more embodiments will now be described, by way of example only, with reference to the attached drawings in which:

[0008] Figure 1 A comparator-based redundant system according to embodiments is depicted;

[0009] Figure 2 A memory management system according to embodiments is shown;

[0010] Figure 3 An embodiment of a comparator BIST device for a system-on-a-chip according to embodiments is depicted;

[0011] Figure 4 A system for testing comparators with a BIST device of a system-on-a-chip according to embodiments is depicted;

[0012] Figure 5A A system for testing comparators with a BIST device 400 of a system-on-a-chip having an error test controller according to embodiments is depicted;

[0013] Figure 5B A system for testing comparators on a system-on-a-chip according to embodiments is depicted;

[0014] Figure 6 An embodiment of a comparator BIST device according to embodiments is depicted;

[0015] Figure 7 An embodiment of a test controller according to embodiments is depicted;

[0016] Figure 8 A state diagram of a finite state machine according to embodiments is depicted;

[0017] Figure 9 is an example waveform diagram depicting a comparator BIST device according to embodiments;

[0018] Figure 10 depicts a comparator BIST for multiple comparator signals according to embodiments;

[0019] Figure 11 depicts a comparator BIST device for testing comparators of a memory management system according to embodiments;

[0020] Figure 11A depicts a comparator BIST device for testing comparators of multiple memory management systems concurrently according to embodiments; and

[0021] Figure 12 depicts a method of testing operation of comparators on a system on a chip according to embodiments. DETAILED DESCRIPTION

[0022] In the following description, one or more specific details are described to provide an example embodiment of the present disclosure. However, embodiments can be used in other ways that have not been specifically described herein without departing from the scope of the present disclosure. In other instances, well-known structures, materials, or operations have not been described in detail in order to avoid obscuring aspects of embodiments.

[0023] Reference throughout this specification to “an embodiment” or “one embodiment” means that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase “in an embodiment” or “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment. Furthermore, the particular configurations, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0024] Comparators can play an important role in many different types of devices in many applications including, but not limited to, automotive, aerospace, and industrial applications. In many cases, comparators can be used for tasks that involve safety considerations. Accordingly, it is advantageous to have reliable comparators and reliable components for checking the operation of comparators.

[0025] A redundancy checker provides one example of a system that includes comparators. A redundant system can provide a backup system to check the operation of a functional system of a device.

[0026] Figure 1 A comparator-based redundant system 100 is depicted.

[0027] The comparator-based redundancy system of claim 1 can include a functional circuit 102 and a redundant circuit 104. The functional circuit 102 can receive an input 108 to perform a function and generate an output 110. The redundant circuit 104 can be used to test the performance of the functional circuit 102. The redundant circuit 104 can be configured to mimic the response of the functional circuit. The redundant circuit 104 can receive the same input 108 as the functional circuit 104. If the system 100 is operating properly, the redundant circuit 104 will generate an output 112 that is identical to the output 110 generated by the functional circuit 102.

[0028] To check whether the comparator-based redundancy system 100 is operating properly, both the output 110 generated by the functional circuit 102 and the output 112 generated by the redundant circuit 104 are sent to a comparator 106. The comparator 106 will then compare the output 110 generated by the functional circuit 102 to the output 112 generated by the redundant circuit 104. The comparator 106 is configured to produce an output 114 having a first state if the output 110 generated by the functional circuit 102 is identical to the output 112 generated by the redundant circuit 104, and a different state if the output 110 generated by the functional circuit 102 is different from the output 112 generated by the redundant circuit 104. The output 114 can also be coupled to an error collector (not shown) that is informed by the output 114 when a discrepancy between the signals occurs.

[0029] The comparator-based redundancy system 100 can be used in critical safety components. The redundancy can allow for errors to be discovered and appropriate action taken. This can be especially important when the comparator-based redundancy system 100 is used in systems that have health and safety implications.

[0030] The comparator can also be used to detect new information. Data stored in memory can be compared to a potential new data set to determine whether the new data set is unique. In various embodiments, the new data set can be saved to memory if the new data is different from any previously existing data.

[0031] Figure 2 A memory management system 200 is shown.

[0032] Memory management system 200 can include memory storage circuitry 202. In various embodiments, memory storage circuitry 202 can store existing data sets. Memory management system 200 can also receive new data sets at input 203. Memory storage circuitry 202 can include a plurality of locations for storing data sets. For example, memory storage circuitry can include 128 locations, where each location can store a 49-bit data set. A data set can include an error packet, which includes information about the location of an error within the system. A data set can also include additional information about the characteristics of the error, such as the size of the error (single bit, double bit, etc.).

[0033] In various embodiments, a new data set can be delivered to buffer circuitry 204. It can be advantageous to compare the new data set to existing data sets already stored in memory storage circuitry 202. In various embodiments, buffer circuitry 204 can store arbitrated and synchronized data. Each location of memory storage circuitry 202 can need to be searched to confirm whether the new data set is unique.

[0034] Memory management system 200 can include one or more comparators to enable comparison between data sets stored in memory storage circuitry 202 and new data sets. The number of comparators in the memory storage system can correspond to the number of data set locations in the memory storage device. For example, if there are 128 locations for storing data sets, in various embodiments, the memory storage system can include 128 comparators: one comparator for each data set location. In various embodiments, the number of comparators can be different than the number of data set locations. For example, there can be 64 comparators that sequentially perform data set comparisons in the first 64 data set locations, and then sequentially perform data set comparisons in the next 64 data set locations.

[0035] First comparator 206 can receive a first input signal 206A from memory storage circuitry 202 and a second input signal 206B from buffer circuitry 204. During normal operation, the first input signal 206A received by first comparator 206 can correspond to a first data set stored in memory storage circuitry 202. Also, the second input signal 206B received by first comparator 206 can convey a new data set received by memory management system 200 during normal operation of memory management system 200.

[0036] Similarly, the second comparator 208 can receive a first input signal 208A from the memory storage circuit 202 and a second input signal 208B from the buffer circuit 204. During normal operation, the first input signal 208A received by the second comparator 208 can correspond to the second set of data stored in the memory storage circuit 202. Also, the second input signal 208B received by the second comparator 208 can convey the new set of data during normal operation.

[0037] The memory management system 200 can include additional comparators to receive additional signals from the memory storage circuit 202 and the buffer circuit 204. The Nth comparator 210 can receive a first input signal 210A from the memory storage circuit 202 and a second input signal 210B from the buffer circuit 204. During normal operation, the first input signal 210A received by the Nth comparator 210 can correspond to the Nth set of data stored in the memory storage circuit 202. Also, the second input signal 210B received by the Nth comparator 210 can convey the new set of data during normal operation.

[0038] Each comparator from the first comparator 206 to the Nth comparator 210 can compare the respective signals received. The first comparator 206 can produce a first comparator output 206C. The second comparator 208 can produce a second comparator output 208C. The Nth comparator 210 can produce an Nth comparator output 210C. The output of a comparator can include a first state when the inputs to the comparator are identical and a second state when the inputs to the comparator are not identical. For example, the output signal of one of the comparators can include a "1" if the inputs are identical and a "0" if the inputs are not identical. In various embodiments, the output signal can include a "0" if the inputs are identical and a "1" if the inputs are not identical.

[0039] The output of the comparators can be directed to a combinational logic circuit 212. In various embodiments, the combinational logic circuit 212 can include an AND tree that receives the comparator outputs. This can allow the memory management system 200 to determine when a new data set received by the memory management system includes a unique data set that is not currently saved in the memory storage. For example, in various embodiments, a comparator can output a "1" if the input signals received by the respective comparator mismatch, and a "0" if the input signals received by the comparator match, when operating without error. If the new data matches a data set stored in any location, the corresponding comparator will output a "0" because all of the inputs to that comparator match. Any zeros received by the AND tree will be pushed through until the output 213. Thus, an output signal that includes a "0" at the output 213 can indicate that the new data set is not unique and already exists somewhere in the existing data.

[0040] For example, if there is a match between the data set stored in the first location of the memory storage circuit 202 and the new data set, the first comparator 206 can output a "0" when operating correctly. The "0" will pass to the combinational logic circuit 212 and matriculate through the AND tree, forcing the output 213 of the combinational logic circuit 212 to also include a "0," indicating that the new data set is not unique. It should be understood that in various embodiments, this result can be achieved by a comparator that outputs a "1" when there is a match between the input signals, using different combinational logic, such as a NAND gate.

[0041] In various embodiments, the memory storage circuit 202 can include a memory error table. In various embodiments, the buffer circuit 204 can include a new error buffer circuit.

[0042] Both the comparator-based redundancy system 100 and the memory management system 200 rely on one or more comparators operating as expected. If a comparator does not operate correctly, the comparator-based redundancy system 100 can not be able to detect an error, or the memory management system can not be able to properly identify a unique data set. Comparators can experience permanent faults, such as a fault stuck at "0," where they only output a signal that includes a "0." In some cases, they can also experience a fault stuck at "1," where they only output a signal that includes a "1." In various applications, it can be advantageous to check the comparators to ensure that they are operating properly.

[0043] On-chip component testing hardware can be used. This allows a chip or system on a chip (SOC) to perform self-testing. Built-in self-testing (BIST) (e.g., logic BIST) can add complexity to a chip, and current techniques are challenged as SOCs themselves become more complex. Comparators can be distributed among different locations on a SOC and on different clock domains. And, this can make information gathering and component connection for BIST difficult.

[0044] In various cases, BIST can be performed at boot. For example, when a car is turned on, various tests can be performed to ensure safe operation of the car during subsequent operation. It can be desirable to perform the tests as quickly as possible to avoid deleterious impact on the user experience. In some cases, the need for BIST can require completion in less than 5ms. Moreover, power considerations can also constrain options as power usage should not exceed the maximum transient current limit of an internal voltage regulator. A more simplified BIST for testing comparators can be advantageous to provide fast, reliable, and efficient testing for comparators.

[0045] Figure 3 An embodiment of a comparator BIST apparatus 300 for a SOC is depicted.

[0046] In various embodiments, the comparator BIST apparatus 300 can include a comparator 306. The comparator 306 can include a first input port 306A and a second input port 306B. The first input port 306A can be configured to receive a first input signal. In various embodiments, the first signal can include a different number of bits.

[0047] The comparator BIST apparatus 300 can also include a second input port 306B. The second input port 306B can be configured to receive a second input signal. In various embodiments, the first input signal can include a different number of bits. The second input signal can include the same number of bits as the first input signal. The comparator 306 can also include an output port 306C for producing an output signal. The output port 306C can be coupled with an error collector (not depicted in Figure 3 The output port 306C can also be coupled with a test controller 310.

[0048] In various embodiments, a comparison between the first input signal and the second input signal can be done by the comparator 306 on a bit-by-bit basis. For example, individual bits from the first input signal can be compared with corresponding bits from the second input signal. Thus, a first input signal including N bits and a second input signal including N bits can be arranged as N bit pairs.

[0049] In various embodiments, the comparator 306 can receive N bit pairs. Each bit pair of the N bit pairs can be input to an exclusive OR (XOR) gate of the comparator 306, which when operating as intended outputs a "1" if the bits of the bit pair are not exactly the same. For the purposes of this disclosure, a bit pair will be referred to as a mismatch when the bits of the bit pair are not exactly the same. In various embodiments, when the two bits of a bit pair are exactly the same, the XOR gate for the bit pair can be configured to output a "0". The output of each of the N XOR gates of the comparator 306 can be input to an OR tree. As a result, when any one of the N bit pairs is mismatched, the OR tree should receive a "1" as input, and the OR tree should also output a "1".

[0050] The comparator BIST device 300 can include a test controller 310, which can be disposed on the SOC and coupled with the first input port 306A and the second input port 306B. The test controller 310 can be configured to test the operation of the comparator 306 for permanent or temporary faults within the components of the comparator 306, such as stuck-at- "1" or stuck-at- "0" internal logic gates.

[0051] In various embodiments, the test controller 310 can test the operation of the comparator 306 by mismatching a bit pair. The test controller 310 can change the signal received at the first input port 306A, at the second input port 306B, or at both the first input port 306A and the second input port 306A, such that a bit pair is mismatched. For example, the test controller can cause one bit of a bit pair to include a "1" and the second bit of the bit pair to include a "0", while keeping all other bit pairs of the comparator matched. When operating as intended, the comparator should identify the mismatch and exhibit an expected output, which can be either a "1" or a "0" depending on the configuration.

[0052] In various embodiments, the test controller 310 can be coupled with the output port 306C and determine whether the mismatch injected into the comparator 306 causes an expected response in the output signal of the comparator 306. If the output signal exhibits the expected output, the comparator 306 will pass the operability test for that bit pair. It can be appreciated that in various embodiments, the test controller 310 can not be coupled with the output port 306C and the output signal of the comparator 306 can be delivered to a different component to determine whether the output matches the expected output.

[0053] The process can be repeated for each bit pair to test whether the comparator 306 will detect the presence of a mismatch between any of the bit pairs. The mismatches can be made one bit pair at a time until all of the bit pairs have been tested. In various embodiments, the test controller 310 can cause a first bit pair to be mismatched while keeping the other bit pairs matched during one clock cycle. During a subsequent clock cycle, the test controller 310 can cause a second bit pair to be mismatched while keeping the others constant. This can continue with one bit pair being mismatched each clock cycle until all of the bit pairs have been tested. In various embodiments, the test controller 310 can keep the first input signal constant while changing the bits of the second signal to test the comparator 306. In various embodiments, the test controller 310 can keep the second input signal constant while changing the bits of the first signal to test the comparator 306

[0054] The test controller 310 can also test whether the comparator 306 responds as expected when all of the bit pairs are matched. For example, in various embodiments, the comparator 306 can be configured to produce an output signal that includes a "0" when all of the bit pairs input to the comparator 306 are matched. When the comparator 306 receives the input from the first circuit 302 and the input from the second circuit 304, the test controller 310 can receive the signal from the comparator 306 from the output port 306C to confirm that the output is a "0." In various embodiments, the comparator 306 can be configured to produce an output signal that includes a "1" when all of the bit pairs input to the comparator 306 are matched. The test controller 310 can receive the signal from the output port 306C and confirm that the output is a "1."

[0055] In various embodiments, the test controller 310 can include an initialization input port 311 to receive an initialization signal 312 to initialize the operability test of the comparator 306. The test controller 310 can include a test completion output port 313 to produce a test completion signal 314. The test completion signal can convey when the operability test of the comparator 306 has completed. The test controller 310 can also include a test result output 315 to produce a test result signal 316. The test result signal 316 can indicate whether the comparator 306 has passed or failed the operability test. For example, if the output of the comparator 306 always includes the expected output of the comparator 306 during the operability test, the test result signal 316 can convey that the operability test has passed. Otherwise, the test result signal 316 can convey that the operability test has failed. In various embodiments, the test result signal 316 can be sticky, meaning that if the output of the comparator 306 deviates from the expected output at any point during the operability test, the test result signal will convey a failure.

[0056] When operability testing is not performed, the comparator 306 can receive the first circuit signal from the first circuit 302 and the second circuit signal from the second circuit 304. The comparator 306 can compare the signals during normal operation. In various embodiments, the first circuit 302 can comprise a functional circuit and the second circuit 304 can comprise a redundant circuit. In various embodiments, the second circuit can operate with a delay of one or two clock cycles. This can allow the comparator 306 to capture transient errors in clock signals, power lines, or other coupling factors.

[0057] The comparator BIST device 300 can also include a selection circuit 308. The selection circuit 308 can determine whether the comparator 306 is receiving signals from the first circuit 302 and the second circuit 304 or receiving signals controlled by the test controller 310. In various embodiments, the selection circuit 308 can comprise a MUX (multiplexer). The selection circuit 308 can include a first input 308A, a second input 308B, a control input 308C, and an output 308D. The MUX can receive signals at the first input 308A and the second input 308B and pass one of the signals to the output 308D depending on a signal transmitted to the control input 308C. For example, after the test controller 310 receives the initialization signal 312, the test controller 310 can deliver a control signal to the selection circuit 308 that causes the selection circuit to pass the signal received from the test controller 310. It will be understood that the selection circuit 308 can also include inputs to receive additional signals and include additional outputs. For example, the selection circuit 308 can include an input to receive a signal from the first circuit 302 and determine whether to pass the signal from the first circuit 302 to the first input port 306A of the comparator 306.

[0058] It can be understood that many SOC or other devices can include multiple comparators. In various embodiments, multiple comparator BIST devices 300 can be utilized in combination to test more than one comparator 306.

[0059] Figure 4 A system for testing comparators of a SOC with a BIST device 400 is depicted.

[0060] A system for testing comparators of a SOC with a BIST device 400 can include more than one comparator BIST device 300. Any one comparator BIST device 300 can include any embodiment of a comparator BIST device 300 described in this disclosure.

[0061] In various embodiments, the test controller 310 of each comparator BIST device 300 can be coupled to a comparator BIST ("CBIST") collector 402. Each comparator BIST device 300 can be coupled to the CBIST collector through an input connection 300A and an output connection 300B. The initialization signal 312 of each test controller 310 can be delivered from the CBIST collector 402 to the initialization input port 311 of the test controller 310. The test completion signal 314 can be delivered from the test completion output port 313 to the CBIST collector 402. Also, in various embodiments, the CBIST collector 402 can also receive test result signals 316 from the test result output 315 of the test controller 310.

[0062] Positioning the test controller 310 near the comparator 306 can be advantageous. Also, the CBIST collector 402 can be used to collect test results and signals from more than one test controller 310. This can be advantageous because it can allow for shorter connections between the test controller 310 and the comparator 306. In various embodiments, the CBIST collector 402 can receive an initialization signal 404 for operability testing, which can be distributed by the CBIST collector 402 to the appropriate comparator BIST device 300 through the input connection 300A. The CBIST collector 402 can also output test results 406 that relay the results of the operability testing performed by the test controller 310 and received by the CBIST collector 402 at the output connection 300B. Similarly, the CBIST collector can also output a test completion signal 408 that relays information received at the output connection 300B indicating when the operability testing performed by the test controller 310 is complete. In various embodiments, the CBIST collector 402 can serve as an intermediary between the comparator BIST device 300 and the error test controller. The CBIST collector 402 can route signals between the test controller 310 and the error test controller 502.

[0063] In various embodiments, it can also be desirable to test for stuck-at-0 failures in the reporting logic for the output test results 406 (starting with the test results signal 316 from the test controller 310 and continuing to the error test controller 502). As can be appreciated, this can require additional logic to allow for error injection between components. It can be desirable to perform this test routine during initial startup of the system. It can also be desirable to perform a test routine to test for stuck-at-l failures in the test complete signal 408 (starting with the test complete signal 314 from the test controller 310 and continuing to the error test controller 502). As can be appreciated, this can require additional logic to allow for error injection between components.

[0064] Testing of the internal operation of the test controller 310 can also be advantageous. This can be accomplished by setting the output of the test results signal 316 to a known output (either "1" or "0" depending on the embodiment) and confirming that the test results signal 316 actually responds as expected. In various embodiments, if the test results signal does not pass the internal operation test, the test complete signal 314 will not be asserted. And, various embodiments can implement a timeout watchdog for the test complete signal 408 in the error test controller to detect when the test results signal and the internal operation of the test controller 310 fail the internal operation test. In various embodiments, it can be desirable to perform the internal operation test prior to performing the operability test.

[0065] Figure 5A A system 500 for testing comparators with a BIST device 400 is depicted with an error test controller.

[0066] In various embodiments, the system 500 can include an error test controller 502. The error test controller 502 can be coupled to more than one system for testing comparators with a BIST device 400. The error test controller 502 can also be responsible for controlling other safety tests on the SOC, such as memory BIST or logic BIST. The CBIST collector 402 of the BIST device 400 can be coupled with the error test controller 502 through an input / output coupling 502A. The output test results 406 and the output test complete signal 408 can be transmitted from the CBIST collector 402 to the error test controller 502 through the input / output coupling 502A. The error test controller 502 can thus receive test results and test complete signals from multiple CBIST collectors 402, where each CBIST collector 402 acts as an intermediary between the error test controller 502 and one or more comparator BIST devices 300.

[0067] The error test controller 502 can initiate the operability test for the comparator BIST device 300 by delivering a signal to the CBIST collector 402, where each CBIST collector 402 acts as an intermediary between the error test controller 502 and one or more comparator BIST devices 300. The CBIST collector 402 can then pass a start (initiation signal) to the test controller 310, which in turn can provide a test enable signal.

[0068] It can be advantageous to utilize the CBIST collector 402 as an intermediary between the error test controller 502 and the comparator BIST device 300 because this can reduce complexity. The comparators 306 can be dispersed in various locations on the SOC. The comparators can be separated by logical (e.g., time domain) or physical partitions. Wringing more than one test controller 310 individually to the error test controller 502 can require many long connections between the test controllers 310 and the error test controller 502. However, the CBIST collector 402 can be located relatively close to the test controllers 310 coupled with the CBIST collector 402. The wiring from the multiple test controllers 310 to the CBIST collector 402 can be relatively short. And, the signals from the multiple test controllers 310 can be transmitted to the error test controller 502 along a small number of wires connecting the CBIST collector 402 to the error test controller 502, rather than along a large number of individual connections between the test controllers 310 and the error test controller 502. However, in various embodiments, it can be desirable to connect all or some of the test controllers 310 directly to the error test controller 502.

[0069] Figure 5B A system for testing comparators on an SOC is depicted.

[0070] The system 500 can be disposed on the SOC 511. In various embodiments, the CBIST collector 402 can act as an intermediary between the multiple comparator BIST devices 300 and the error test controller 502, which can reduce complexity of the SOC 511.

[0071] Returning to Figure 5A In various embodiments, the input / output coupling 502A can include three connections: a connection for an initiation signal; a connection for a test result signal; and a connection for a test completion signal. In various embodiments, the test result signal can convey only whether the operability test has passed or failed. However, additional information can be included, such as a location of a fault within the comparator 306.

[0072] In various embodiments, the CBIST collector 402 is coupled only to comparator BIST devices 300 that are in the same time domain. This can be advantageous because it can reduce the number of clock signals required for the CBIST collector 402. However, in various embodiments, the CBIST collector 402 can be coupled to comparator BIST devices 300 from different time domains. Additional logic for the CBIST collector 402 can be required to interface comparators 306 from asynchronous time domains on the SOC.

[0073] Figure 6 An embodiment of a comparator BIST device 300 is depicted

[0074] In various embodiments, a selection circuit 308 is coupled to the first circuit 302 and the second circuit 304. The selection circuit 308 can receive an N-bit first circuit signal from the first circuit 302. The selection circuit 308 can receive an N-bit second circuit signal from the second circuit 304. The test controller 310 can be configured to generate a test enable signal 601. In various embodiments, the selection circuit 308 can be configured to pass the first circuit signal from the first circuit 302 to a first input port 306A of the comparator 306 and pass the second circuit signal from the second circuit 304 to a second input port 306B of the comparator 306, depending on the test enable signal: when the test enable signal is in a first state, or pass a first test signal from the test controller 310 to the first input port 306A and pass a second test signal 603 from the test controller 310 to the second input port 306B, when the test enable signal is in a second state.

[0075] In various embodiments, a first bit 605A of the first circuit signal of the first circuit 302 can be coupled with a first AND gate 618A of the selection circuit 308. A second bit 605B of the first circuit signal can be coupled with a second AND gate 618B of the selection circuit 308. Additional bits of the first circuit signal of the first circuit 302 can be coupled with additional AND gates. The first test signal delivered from the test controller 310 to the selection circuit 308 can include a test enable signal 601 that has been inverted and coupled to the first AND gate 618A, the second AND gate 618B, and additional AND gates coupled to additional bits of the first circuit signal of the first circuit 302. When the test enable signal includes a “0”, it can be inverted to a “1” and delivered to the first AND gate 618A, the second AND gate 618B, and additional AND gates coupled to additional bits of the first circuit signal of the first circuit 302, thereby allowing the first circuit signal to be passed to the first input port 306A of the first comparator. When the test enable signal 601 includes a “1”, it will be inverted before reaching the first AND gate 618A, the second AND gate 618B, and additional AND gates coupled to additional bits of the first circuit signal of the first circuit 302, thereby setting each bit delivered to the first input port 306A of the comparator 306 to a “0”

[0076] In various embodiments, the second circuit signal of the second circuit 304 can include a first bit 607A that is transmitted to the first MUX 620A of the selection circuit 308. The second circuit signal of the second circuit 304 can include a second bit 607B that is transmitted to the second MUX 620B of the selection circuit 308. Additional bits of the second circuit signal of the second circuit 304 can be transmitted to additional MUXs.

[0077] The first MUX 620A can also receive a first bit 603 A of the second test signal 603. The second MUX 620B can also receive a second bit 603B of the second test signal 603. Additional MUXs of the selection circuit 308 can receive additional bits of the second test signal 603. The first MUX 620A, the second MUX 620B, and the additional MUXs receiving additional bits of the second test signal 603 can also receive a control signal to select a MUX output. In various embodiments, the control signal can include the test enable signal 601. Also, in various embodiments, when the test enable signal 601 includes a "1," the first MUX 620A, the second MUX 620B, and the additional MUXs receiving additional bits of the second test signal 603 can output the respective bits received from the second test signal 603. In various embodiments, when the test enable signal includes a "0," the first MUX 620A, the second MUX 620B, and the additional MUXs receiving additional bits of the second test signal 603 can output the respective bits of the second circuit signal of the second circuit 304. In various embodiments, the binary value of the test enable signal can be toggled.

[0078] In various embodiments, the comparator 306 includes an OR tree 604. The OR tree can include an OR tree output 604A to produce an OR tree output signal. The comparator can also include a first exclusive OR (XOR) gate 606A. The first XOR gate 606A can receive a first bit pair 608A. The first bit pair 608A can include a first bit of a first input signal, which in various embodiments can include a first bit 605A of the first circuit signal or a first bit of the first test signal, depending on the test enable signal 601. The first bit pair 608A can also include a first bit of a second input signal, which in various embodiments can include a first bit 607A of the second circuit signal or a first bit of the second test signal 603, depending on the test enable signal 601. The first XOR gate 606A should output a "0" when operating without failure when the first bit pair 608A matches. The first XOR gate 606A should output a "1" when operating without failure when the first bit pair 608A mismatches. The output of the first XOR gate 606A can be coupled to an input 604B of the OR tree 604.

[0079] The comparator 306 can also include a second XOR gate 606B. The second XOR gate 606B can receive a second bit pair 608B. The second bit pair 608B can include a second bit of the first input signal, which in various embodiments can include either a second bit 605B of the first circuit signal or a second bit of the first test signal, depending on the state of the test enable signal 601. The second bit pair can include a second bit of the second input signal, which can include either a second bit 607B of the second circuit signal or a second bit of the second test signal 603, depending on the state of the test enable signal. When the second bit pair 608B matches, the second XOR gate 606B outputs a "0" when operating without failure. When the second bit pair 608B mismatches, the second XOR gate 606B outputs a "1" when operating without failure. The output of the second XOR gate 606B can be coupled to an input 604B of the OR tree 604. Additional bit pairs can be coupled with additional XOR gates. In various embodiments, the comparator 306 can include one XOR gate for each bit pair.

[0080] In various embodiments, when operating without failure, the OR tree 604 should produce an output signal that includes a "1" when the OR tree 604 receives a "1" at any input. When operating without failure, the OR tree should produce an output that includes a "0" when all of the inputs to the OR tree are "0." The comparator 306 can also include a flip-flop 619 that can synchronize the OR tree output 604A with a clock signal.

[0081] The comparator 306 can also include a gating circuit 612 coupled to the output port 306C of the comparator 306. The gating circuit 612 can prevent a failing error from being reported to an error collector. The operability test of the comparator 306 can cause the comparator output signal, if received by other components, can be interpreted as an error. In various embodiments, the gating circuit 612 can prevent this by coupling the output port 306C of the comparator 306 to an AND gate. In various embodiments, the test enable signal 601 can be inverted and also delivered to the AND gate. When the test of the comparator is in progress, the test enable signal 601 can include a "1." After inversion, a "0" can be input to the AND gate, thereby preventing the output port 306C from delivering a signal to the error collector.

[0082] In various embodiments, the gating circuit 612 can include a first AND gate 612A, a second AND gate 612B, and an OR gate 612C. The first AND gate 612A and the second AND gate 612B can be coupled at their inputs to the output port 306C and the test enable signal 601 (if needed, after inversion). The outputs of the first AND gate 612A and the second AND gate 612B can be input to the OR gate 612C. The OR gate 612C can prevent a stuck-at-‘0’ failure in either the first AND gate 612A or the second AND gate 612C from preventing an error from reaching the error collector that occurs outside of the operability test.

[0083] In various embodiments, the comparator 306 can include an OR gate 617. A first input of the OR gate 617 can be coupled to the OR tree output 604A. The OR gate 617 can be used to test for failures in the gating circuit 612. The OR gate 617 can receive a signal at input 617A. This signal can inject an error into the comparator 306. And, the output 612D of the gating circuit can be tested to confirm that the error is picked up by the gating circuit 612. The signal delivered to input 617A can be delivered by a controller (not shown).

[0084] Figure 7 An embodiment of the test controller 310 is depicted.

[0085] In various embodiments, the test controller 310 can include a finite state machine (“FSM”) 702 that receives the initialization signal 312. In various embodiments, the FSM can also output the test completion signal 314, the test result signal 316, the test enable signal 601, and receive the output from the output port 306C.

[0086] The test controller 310 can also include a binary counter 704. The FSM 702 can be in communication with the binary counter 704. The FSM can be configured to prompt the binary counter 704 to begin counting by delivering an enable signal (start_cnt) to the binary counter after the FSM 702 has received the initialization signal to begin the operability test. The range of the count performed by the binary counter can be equal to the number of bit pairs of the comparator 306 to be tested. For example, if an operability test is being performed on N bit pairs, the binary counter can count from 1 to N, resulting in a count of N cycles.

[0087] The binary counter 704 can be coupled to a binary decoder 706 to convert the count performed by the binary counter into an output. The output of the binary decoder 706 can comprise the second test signal 603. A first output of the binary decoder 706 can produce a first bit 603A of the second test signal 603, a second output of the binary decoder 706 can produce a second bit 603B of the second test signal 603, and additional bits of the binary decoder 706 can produce additional bits of the second test signal 603. The number of outputs of the binary decoder can equal the number of bit pairs of the comparator.

[0088] As the binary counter 704 counts, the binary decoder can output a "1" to the corresponding output. For example, when the count is 1, the binary decoder can output a "1" as the first bit 603A of the second test signal 603, while the remaining bits are set to "0". When the count is 2, the binary decoder can output a "1" at the second bit 603B of the second test signal 603, while the remaining bits are set to "0". This can continue until the count is complete.

[0089] Figure 8 A state diagram of a finite state machine ("FSM") 702 is depicted.

[0090] The FSM begins in an idle state 801. In various embodiments, the test can be triggered by an initialization signal 312. The initialization signal 312 can be received from the CBIST collector 402 that is an intermediary of the error test controller 502. In various embodiments, the test can be performed each time the system is started. For example, when a car is turned on. As a result, the initialization signal 312 can be asserted each time the system is turned on. In different embodiments, the initialization signal can be asserted with different values. For example, an initialization signal comprising a "1" can trigger the operability test. And, in various embodiments, an initialization signal comprising a "0" can trigger the operability test.

[0091] Receiving the initialization signal 312 asserted triggers the FSM to exit the idle state. In various embodiments, at 802, the FSM can assert a test start signal. The test start signal can be configured to last a predetermined number of clock cycles corresponding to the time required to complete the test. The test start signal can be internal to the FSM. The test start signal can trigger the internal operation test. This can be accomplished by setting the output of the test result signal 316 to a known output and testing to see if it reacts as expected. For example, the test result signal 316 can be set to a "1" and tested to ensure that the test result signal 316 does not get stuck at a "0". It can be appreciated that a clock delay can cause a test initialized in one clock period to complete in a subsequent clock period.

[0092] At 803, the FSM includes checking the initial level state. At this time, the test enable signal 601 can be asserted. The test enable signal 601 can be timed to be de-asserted after a set number of clock cycles have elapsed. The number of clock cycles can depend on the number of bit pairs being checked. For example, the test enable signal can be timed to be de-asserted after all bit pairs have mismatched.

[0093] During the checking of the initial level state 803, bit pairs can be matched to determine whether the comparator 306 produces the expected output when all inputs match. In various embodiments, the inputs to the comparator 306 can be matched by using the selection circuit 308. In various embodiments, the selection circuit 308 can be coupled only to the second circuit 304. The first circuit can not receive inputs, and as a result, the output of the first circuit 302 can be known, and thus it can be desirable to couple only the second circuit 304 to the selection circuit 308.

[0094] In various embodiments, the checking of the initial level state 803 can have a duration equal to a single clock cycle. At 804, the FSM triggers the binary counter 704 to begin counting. For example, in various embodiments, this can occur by delivering a start_cnt signal comprising a "1" to the input ENB of the binary counter 704. From 805 to 806, bit pairs of the comparator 306 are mismatched one by one as the binary counter 704 counts and the binary decoder 706 generates outputs. During states 803 to 806, the FSM can monitor the signal at the output port 306C to check whether the output matches the expected output. For example, if the signal at the output port 306C deviates from the expected output (either a "1" or a "0" depending on the embodiment), the test result signal 316 can be asserted to indicate an error. In various embodiments, there can be a delay between the time the operability test is initialized and the time the output is verified. The delay can vary depending on the configuration of the comparator BIST device 300. For example, the delay can comprise one clock cycle, two clock cycles, three clock cycles, or another number of clock cycles. At state 808, the FSM can report the results of the operability test. In various embodiments, the test complete signal 314 can be asserted if the internal operation test passes. In various embodiments, the test complete signal 314 can be timed to be asserted after the last bit pair has been matched if the internal operation test passes.

[0095] In various embodiments, the value of the count can be checked at state 808 to confirm that the count equals N. This can be performed to detect a self-failure in the counter (e.g., 704) or the FSM 800. After the value of the count has been checked, the clear_cnt signal can be set to "1."

[0096] In various embodiments, it can be advantageous to monitor the test enable signal 601 of the test controller 310 when the FSM 702 is in the idle state 801. The FSM can include the idle state 801 when the first circuit 302 is used for operation, which can be referred to as task mode. A test enable signal 601 that is falsely asserted during task mode can interfere with the proper operation of the comparator 306 testing the first circuit 302 and the second circuit 304. Thus, it can be advantageous to monitor the test enable signal 601 during task mode. If the test enable signal 601 is asserted while the FSM 702 is in the idle state, the FSM 702 can be configured to assert the test result signal 316 to indicate that there is an error. In various embodiments, the FSM 702 can be configured to control the state of the test result signal 316. For example, the FSM 702 can be configured to assert the test result signal 316 if the test enable signal is detected while the FSM 702 is in the idle state 801. The test result signal 316 can be coupled to other components that process and report errors (e.g., at least with reference to the CBIST collector 402 and error test controller 502 described above). In various embodiments, the timing of the state-to-state transitions of the FSM can be controlled by a clock signal, and various states can be configured to last for a specified number of clock periods. In various embodiments, some of the states can transition by counting. Figure 5A The described CBIST collector 402 and error test controller 502). In various embodiments, the timing of the state-to-state transitions of the FSM can be controlled by a clock signal, and various states can be configured to last for a specified number of clock periods. In various embodiments, some of the states can transition by counting.

[0097] In various embodiments, the test result signal 316 can include a "1" if the output at the output port 306C deviates from the expected output for any clock interval. In various embodiments, the test result signal 316 can include a "0" if the output at the output port 306C deviates from the expected output at any one clock interval. In various embodiments, a test result signal 316 including a "0" can indicate that the operability test has passed, and the "0" can indicate that the operability test has failed. At step 809, the initialization signal returns to its initial state.

[0098] Figure 9 is a graph depicting example waveforms of the comparator BIST device 300.

[0099] As Figure 9 shown, when the initialization signal 312 is asserted, the operability test of the comparator 306 can be initialized. The test start signal can then be asserted at the next clock period, clock period "0". The test start signal can trigger the assertion of the internal operation test and the test enable signal 601, which will start the next clock period, clock period "1". For the internal operation test, the test result signal can be asserted at 902.

[0100] At clock cycle 1, the FSM moves out of the idle state 801. In various embodiments, the test enable signal 601 can be set such that the selection circuit 308 passes the signal from the test controller 310 to the state of the comparator 306. In various embodiments, the delay between receiving the initialization signal 312 and asserting the test enable signal 601 can be more than one clock cycle, depending on the architecture. After receiving the initialization signal 312, and after any delay, the comparator BIST device 300 can move into operability and self-failure testing to check whether the output of the comparator includes the expected output when all inputs to the comparator match (in various embodiments, when the count from the binary counter 704 is 0 and all outputs are “0”).

[0101] During this time period, if the output from the comparator at the output port 306C does not match the expected output, the test result signal 316 can be asserted to indicate an error. For this example, the expected output when the bit pair matches can be “0”. And, the expected output when the bit pair mismatches can be “1”. As a result, in this example, if the output from the output port 306C of the comparator is “1”, the test result signal 316 will be asserted during the time period represented in region 904 to indicate an error. In Figure 9 In the example shown, the test result signal 316 is not asserted in 904 because the comparator output is maintained at “0”, the expected output. In various embodiments, this can be performed during the startup of the device.

[0102] At clock cycle 2, the count reaches 1, and the first bit 603A of the second test signal 603 produces a "1". After a 1 -clock cycle delay, the output from the output port 306C of the comparator 306 rises to "1" at clock cycle 3. As the count continues, the outputs of the second bit 603B, the third bit 603C, the fourth bit 603D, and the fifth bit 603E rise and fall, which tests that the comparator 306 can detect a mismatch at each of these pairs of bits. In the depicted example waveform, the expected output of the comparator remains "1" as long as the pairs of bits mismatch. If there is a deviation between the expected output and the output received from the output port 306C, the test fails, and the test result signal 316 is asserted to indicate an error. One pair of bits can be checked per cycle of the count period. If there is an error detected with the first pair of bits, the test result signal can be asserted during the time period denoted as 906. If there is an error detected with the second pair of bits, the test result signal can be asserted during the time period denoted as 908. If there is an error detected with the third pair of bits, the test result signal can be asserted during the time period denoted as 910. If there is an error detected with the fourth pair of bits, the test result signal can be asserted during the time period denoted as 912. If there is an error detected with the fifth pair of bits, the test result signal can be asserted during the time period denoted as 914. For each of these time periods, the test result signal 316 is asserted. For the time periods denoted as 916, 918, 920, 922, and 924, the test result signal 316 is de-asserted. The test result signal 316 is de-asserted for the time periods denoted as 916, 918, 920, 922, and 924 because the expected output of the comparator 306 matches the output received from the output port 306C. The test result signal 316 is asserted for the time periods denoted as 906, 908, 910, 912, and 914 because the expected output of the comparator 306 does not match the output received from the output port 306C. Figure 9 For the duration of these time periods, the comparator output remains at the expected output (which is "1" in this example), so the test result signal 316 is not asserted.

[0103] From clock cycle 6 to clock cycle 7, the last pair of bits is mismatched as the output of 603E is set to 1. And, after a clock delay, at clock cycle 8, the comparator output from the output port 306C returns to "0". During the operability test, the comparator output always matches the expected output. And, the test complete signal is given a "1". It can be appreciated that the binary values of some of these waveforms can be inverted in various embodiments of the comparator BIST device 300. The states of the FSM 702 can be stored in a flip-flop.

[0104] In various embodiments, the test controller 310 can include a walking one pattern injector to mismatch pairs of bits for testing the comparator 306. In various embodiments, the walking one pattern injector is implemented with a shift register. In various embodiments, the shift register can be implemented using the first circuit 302 and the second circuit 304.

[0105] It can be advantageous to compare a single signal between more than one comparator 306. For example, a comparison between 16-bit signals can be performed using two comparators 306 (each comparator including 8 bits) rather than a single 16-bit comparator. This can be preferable for high frequency applications.

[0106] Figure 10 Comparators BIST for multiple comparator signals are depicted.

[0107] Figure 10 First comparator 306-1 and second comparator 306-2 are depicted. Unless otherwise noted, first comparator 306-1 and second comparator 306-2 can include any embodiment of comparators 306 referenced in this disclosure. It should be noted that, Figure 10 Couplings between first comparator 306-1, second comparator 306-2, test controller 310, error test controller 502, or gating circuit 612 are depicted. However, comparators BIST for multiple comparator signals can also include first circuit 302, second circuit, and other components described elsewhere in this disclosure.

[0108] In various embodiments, both first comparator 306-1 and second comparator 306-2 can be coupled with test controller 310 to receive second test signal 603. A first portion of second test signal 603 can be delivered to first comparator 306-1 and a second portion of second test signal 603 can be delivered to second comparator 306-2. For example, the first 4 bits of an 8-bit second test signal 603 can be delivered to first comparator 306-1 and the last 4 bits of an 8-bit second test signal 603 can be delivered to second comparator 306-2. In various embodiments, each bit of the 8 bits can be changed one at a time to test for faults in first comparator 306-1 and second comparator 306-2.

[0109] The output 306C-1 of the first comparator 306-1 and the output of the second comparator 306C-2 can be coupled to an OR gate 1001. The OR gate output 1003 can be coupled to a flip-flop 1002. Also, the output 1004 of the flip-flop 1002 can be coupled to the test controller 310. The output generated at the output 1004 can be used for comparison to an expected output. For example, in various embodiments, when all of the inputs to the first comparator 306-1 and the second comparator 306-2 are exactly the same, the output signal generated at the output 1004 can be expected to include a "0." Also, when the inputs to the first comparator 306-1 and the inputs to the second comparator 306-2 are offset, the output can be expected to include a "1." It should also be appreciated that the inclusion of the flip-flop 1002 can also introduce an additional delay of one clock cycle. In various embodiments, the test enable signal 601 can be delivered to the selection circuit 308, as described at least with reference to Figure 3 and Figure 6

[0110] It can also be advantageous to test the comparators of the memory management system 200 for potential malfunctions.

[0111] Figure 11 A comparator BIST apparatus 1100 for testing the comparators of the memory management system 200 is depicted.

[0112] The N comparators of the memory management system 200 can include any of the embodiments of the comparators 306 described elsewhere in the present disclosure. In various embodiments, the test controller 310 can receive an initialization signal 312 to begin operability testing of the N comparators of the memory management system 200. The test controller 310 can deliver a test enable signal 601 to the buffer circuit 204 and the memory storage circuit 202. In various embodiments, the comparator BIST apparatus 1100 can also include a selection circuit 308 disposed between the buffer circuit 204 or the memory storage circuit 202 and the comparators. The selection circuit 308 can include any of the embodiments of the present disclosure, for example, as described with reference to Figure 3 and Figure 6 In various embodiments, the selection circuit 308 can be included as part of the memory storage circuit 202 and the buffer circuit 204. When the test enable signal 601 is asserted, the selection circuit 308 can pass data for performance of the operability testing to the comparators. When the test enable signal 601 is not asserted, the memory storage circuit 202 and the buffer circuit 204 can be in reference Figure 2 ​The described functionality or task mode. The buffer circuit can include a selection circuit 308, and the first test signal can be passed to the N comparators. In various embodiments, the selection circuit 308 can include an AND gate for each bit of the output of the buffer circuit 204. The AND gate for each bit can also receive the test enable signal 601 that has been inverted. In various embodiments, the selection circuit 308 can include a multiplexer (MUX) for each bit of the output of the memory storage circuit 202. Each multiplexer can receive one bit of output from the memory storage circuit 202 and one bit of the second test signal 603. Each multiplexer can also receive the test enable signal 601 to select between the bit received from the memory storage circuit 202 and the bit received from the second test signal 603. In various embodiments, the test signal delivered to the N comparators can include the test enable signal 601 or the test enable signal 601 that has been inverted. In various embodiments, the first test signal can be passed as the second input signal 206B, the second input signal 208B, the second input signal 210B, and any additional second input signal of any additional comparators.

[0113] The test controller 310 can also be configured to deliver a second test signal 603 to the memory storage circuit 202. The memory storage circuit 202 can pass the second test signal 603 to the N comparators. In various embodiments, the second test signal can be passed as the first input signal 206A, the second input signal 208A, the first input signal 210A, and any additional first input signal of any additional comparators. The bit pair of a comparator can include a first bit from the first test signal and a second bit from the second test signal.

[0114] The test controller 310 can perform the operability test by instructing the memory storage circuit 202, the buffer circuit 204, or both the memory storage circuit 202 and the buffer circuit 204 to mismatch one bit pair at a time in each comparator of the N comparators. For example, during a first clock cycle, the first bit pair of the first comparator 206 can be mismatched. The remaining bit pairs of the first comparator will be matched. If operating properly, the first comparator 206 should produce a signal at the first comparator output 206C that includes the expected state for the mismatch signal. Also, during the first clock cycle, the first bit pair of the second comparator 208 can be mismatched. The remaining bit pairs of the second comparator will be matched. If operating properly, the second comparator 208 should produce a signal at the second comparator output 208C that includes the expected state for the mismatch signal. This can be repeated such that each comparator of the N comparators has one mismatched bit pair during one clock cycle. Each comparator of the N comparators should produce a signal that includes the expected state (which can be either a "1" or a "0" in different embodiments) for the mismatch signal. However, if any of the N comparators fails to respond as expected, the fault will push a "0" through the combinational logic circuit 212, thereby revealing the fault. This process can be repeated for each bit pair. For example, if each comparator of the N comparators has 49 bit pairs, the process will be repeated 49 times, once for each bit pair.

[0115] In various embodiments, the comparator BIST device 1100 can include a flip-flop at the output of the combinational logic circuit 212.

[0116] In various embodiments, the test controller 310 can be used to test multiple memory management systems 200 simultaneously. Figure 11A A comparator BIST device 1100A is depicted that tests comparators of multiple memory management systems simultaneously.

[0117] In various embodiments, the test controller 310 can be coupled with a first memory management system 200A and a second memory management system 200B to deliver a test enable signal 601 and a second test signal 603. In various embodiments, the comparator BIST device 1100A can include more memory management systems. The output 213A of the first memory management system 200A and the output 213B of the second memory management system 200B can be input to an OR logic 1102 and an output 1102A is provided to the test controller 310 to allow both the first memory management system 200A and the second memory management system 200B to be tested simultaneously. It can be appreciated that in various embodiments, the comparator BIST device 1100A can include more memory management systems 200 coupled with the OR logic 1102.

[0118] Figure 12 A method 1200 of depicting a test operation of a comparator on a system on a chip is depicted.

[0119] In various embodiments, the method 1200 can include receiving, by a test controller disposed on the SOC, an initialization signal at step 1202, matching, using the test controller, a first signal received by the comparator with a second signal received by the comparator at step 1204, checking an output signal from the comparator includes an expected output for a matched input at step 1206, mismatching, using the test controller, the first signal received by the comparator with the second signal received by the comparator at step 1208, and checking the output signal includes an expected output for a mismatched input at step 1210.

[0120] In various embodiments, the method 1200 can further include receiving, by the test controller, the output signal.

[0121] In various embodiments, the method 1200 further includes performing the checking of the output signal from the comparator includes the expected output for the matched input during a boot up of the SOC.

[0122] The method 1200 can further include wherein the test controller is to check the output signal includes the expected output for the matched input, and the test controller is to check the output signal includes the expected output for the mismatched input.

[0123] In various embodiments, the method 1200 can further include determining, by the test controller, the output signal does not include the expected output for the mismatched input, and generating, by the test controller, an error signal.

[0124] In various embodiments, the method 1200 can further include performing an internal operation test by confirming the error signal can be toggled from a first state to a second state.

[0125] In various embodiments, the method 1200 can further include wherein the first signal includes N bits, and the second signal includes N bits.

[0126] In various embodiments, the method 1200 further includes dividing the first signal and the second signal into N pairs of bits, each pair of bits including one bit from the first signal and one bit from the second signal, and wherein mismatching, using the test controller, the first signal received by the comparator with the second signal received by the comparator includes mismatching each of the N pairs of bits one at a time.

[0127] In various embodiments, the method 1200 can further include, wherein the test controller asserts the test enable signal during the first operability test and asserts the test enable signal during the second operability test, and wherein the test controller generates the error signal if the test enable signal is asserted when neither the first test nor the second test is performed.

[0128] In various embodiments, the method 1200 further includes asserting, by the test controller, the test enable signal during the test operation of the comparator on the system on a chip, and generating, by the test controller, the error signal when the test enable signal is asserted when the test operation is not performed.

[0129] In various embodiments, the method 1200 further includes asserting, by the test controller, the test enable signal during the test operation of the comparator on the system on a chip, and generating, by the test controller, the error signal when the test enable signal is asserted when the test operation is not performed.

[0130] Example 1. A built-in self-test apparatus for a system on a chip (SOC), the built-in self-test apparatus comprising: a comparator disposed on the SOC and comprising: a first input port to receive a first input signal; a second input port to receive a second input signal; an output port to produce an output signal; wherein the first input signal and the second input signal are divided into N pairs of bits, each pair of bits comprising one bit from the first input signal and one bit from the second input signal; and wherein the comparator is configured such that a mismatch between the first input signal and the second input signal causes the output signal to comprise a first expected state; and a test controller on the SOC and coupled with the first input port, the second input port, and the output port, the test controller configured to perform a first operability test by: generating a mismatch for each of the N pairs of bits, and verifying that the output signal comprises the first expected state in response to the mismatch for each of the N pairs of bits.

[0131] Example 2. The apparatus of example 1, wherein the test controller is configured to mismatch the N pairs of bits one at a time.

[0132] Example 3. The apparatus of example 1 or 2, wherein the comparator is configured such that a match between the first input signal and the second input signal causes the output signal to comprise a second expected state; and the test controller is configured to perform a second operability test by matching the N pairs of bits and verifying that the output signal comprises the second expected state.

[0133] Example 4. The apparatus of examples 1-3, wherein the comparator comprises: an OR tree comprising an OR tree output for producing an OR tree output signal; and N XOR gates, each XOR gate receiving one of the N pairs of bits and each XOR gate comprising a XOR output coupled with an input of the OR tree.

[0134] Example 5. The apparatus of examples 1-4, wherein the test controller is configured to: receive an initialization signal to initialize the first operability test; output a test completion signal; and output a test result signal.

[0135] Example 6. The apparatus of examples 1-5, further wherein: the test controller comprises: a finite state machine to receive the initialization signal; a binary counter in communication with the finite state machine and configured to initialize a count from 1 to N after the finite state machine receives the initialization signal; and wherein the test controller is configured to perform the first operability test by generating a mismatch for each of the N pairs of bits one at a time based on the count.

[0136] Example 7. The apparatus of examples 1-6, further wherein: each of the N XOR gates comprises a first XOR input to receive a first bit from a first input signal and a second XOR input to receive a second bit from a second input signal; and wherein the test controller further comprises a binary decoder coupled with the binary counter, the binary decoder comprising N binary counter outputs coupled with the second XOR inputs of the N XOR gates.

[0137] Example 8. The apparatus of examples 1-7, further comprising one or more additional comparators according to example 1, wherein the test controller is coupled with a first input port, a second input port, and an output port of each of the one or more additional comparators and is configured to perform the first operability test for each of the one or more additional comparators.

[0138] Example 9. A system comprising one or more apparatuses according to examples 1-8 and further comprising an error test controller disposed on a SOC and coupled with each test controller of the one or more apparatuses and configured to deliver an initialization signal to each test controller of the one or more apparatuses to begin the first operability test, and the error test controller is configured to receive a data signal from the test controllers conveying a result of the first operability test.

[0139] Example 10. The system of example 9, comprising a comparator collector coupled with the error test controller and a plurality of devices according to example 1, wherein the comparator collector is to route initialization signals and data signals between the error test controller and test controllers of the plurality of devices.

[0140] Example 11. A system for testing operation of a comparator, the comparator comprising: a first input port configured to receive N bits; a second input port configured to receive N bits, wherein the N bits of the second input port and the N bits of the first input port are divided into N pairs of bits; and an output port configured to produce an output signal having a first expected state when any of the N pairs of bits mismatch. The system further comprising: a first circuit configured to produce a first signal comprising N bits; a second circuit configured to produce a second signal comprising N bits; a test controller configured to produce a test enable signal; a selection circuit coupled to the first circuit, the second circuit, and the test controller, the selection circuit configured to: pass the first signal to the first input port and the second signal to the second input port when the test enable signal is in a first state, and pass a first test signal from the test controller to the first input port and a second test signal from the test controller to the second input port when the test enable signal is in a second state; and wherein the test controller is configured to perform an operability test on the comparator by setting the test enable signal to the second state and changing the first test signal, the second test signal, or both the first test signal and the second test signal to mismatch the N pairs of bits.

[0141] Example 12. The system of example 11, wherein the selection circuit comprises a multiplexer.

[0142] Example 13. The system of example 11 or 12, wherein the comparator is configured such that the output signal comprises a second expected state when all of the N pairs of bits match; and wherein the test controller is configured to perform a second operability test on the comparator by setting the test enable signal to the second state and matching the first test signal to the second test signal such that all N pairs of bits match.

[0143] Example 14. The system of examples 11-13, wherein the comparator comprises: an OR tree comprising an OR tree output for producing an OR tree output signal; and N exclusive OR gates, each exclusive OR gate receiving one of the N pairs of bits, and each exclusive OR gate comprising an exclusive OR output coupled with an input of the OR tree.

[0144] Example 15. The system of examples 11-14, further comprising a gating circuit, the gating circuit comprising: a gating circuit input to receive the or tree output signal and the test enable signal; a gating circuit output to produce a gating circuit output signal; and wherein the gating circuit is configured to set the gating circuit output signal to the second expected state when the test enable signal is set to the second state.

[0145] Example 16. The system of examples 11-15, wherein the first circuit comprises a functional circuit and the second circuit comprises a redundancy checker circuit.

[0146] Example 17. The system of examples 11-16, wherein the system comprises a task mode, and wherein the test controller is configured to output an error signal when the test enable signal comprises the second state while the system is in the task mode.

[0147] Example 18. A method of testing operation of a comparator on a system on a chip (SOC), comprising: receiving, by a test controller disposed on the SOC, an initialization signal; matching, using the test controller, a first signal received by the comparator with a second signal received by the comparator; checking that an output signal from the comparator comprises an expected output for the matching inputs; mismatching, using the test controller, the first signal received by the comparator with the second signal received by the comparator; and checking that the output signal comprises an expected output for the mismatching inputs.

[0148] Example 19. The method of example 18, further comprising receiving, by the test controller, the output signal; and wherein the test controller is to check that the output signal comprises the expected output for the matching inputs, and the test controller is to check that the output signal comprises the expected output for the mismatching inputs.

[0149] Example 20. The method of examples 18 or 19, further comprising determining, by the test controller, that the output signal does not comprise the expected output for the mismatching inputs; and generating, by the test controller, an error signal.

[0150] Example 21. The method of examples 18-20, wherein the first signal comprises N bits and the second signal comprises N bits; the method further comprising dividing the first signal and the second signal into N pairs of bits, each pair of bits comprising one bit from the first signal and one bit from the second signal; and wherein mismatching, using the test controller, the first signal received by the comparator with the second signal received by the comparator comprises mismatching each of the N pairs of bits one at a time.

[0151] Example 22. The method of examples 18-21, further comprising asserting, by the test controller, the test enable signal during a test operation of the comparator on the SOC, and generating, by the test controller, an error signal when the test enable signal is asserted when no test operation is being performed.

[0152] Example 23. The method of examples 18-22, further comprising performing, during a boot of the SOC, a check that an output signal from the comparator includes an expected output for a matching input.

[0153] Example 24. A system for testing operation of a comparator, comprising a plurality of comparators, each comparator comprising: a first input port configured to receive N bits; a second input port configured to receive N bits; wherein the N bits of the second input port and the N bits of the first input port are divided into N pairs of bits; and an output port configured to produce an output signal having a first expected state when any pair of bits of the N pairs of bits mismatches. The system further comprising: a first circuit configured to deliver a first signal comprising N bits to the first input port of each comparator of the plurality of comparators; a second circuit configured to deliver a second signal to the second input port of each comparator of the plurality of comparators; and wherein a test controller is configured to perform an operability test by instructing the first circuit, the second circuit, or both the first circuit and the second circuit to cause the N pairs of bits of each comparator of the plurality of comparators to mismatch.

[0154] Example 25. The system for testing operation of a comparator of example 24, wherein the test controller performs an operability test by instructing the first circuit, the second circuit, or both the first circuit and the second circuit to cause one pair of bits of the N pairs of bits to mismatch at a time for each comparator of the plurality of comparators.

[0155] Example 26. The system for testing operation of a comparator of example 24 or 25, further comprising a gating circuit that inputs the output signal of each comparator of the plurality of comparators.

[0156] Example 27. The system for testing operation of a comparator of examples 24-26, wherein the test controller is coupled with an output of the gating circuit, and the test controller is configured to generate a test failure signal when the output of the gating circuit deviates from an expected output during the operability test.

[0157] Example 28. The system for testing operation of a comparator of examples 24-27, wherein the first circuit comprises a memory error table, and the second circuit comprises a new error buffer circuit.

[0158] Unless otherwise stated or apparent from the context, parts depicted in the figures with the same numbers can include the same devices.

[0159] The references used herein are for convenience only and are not intended to limit the scope of protection or the scope of embodiments.

[0160] Reference throughout this specification to an "aspect" or "embodiment" means that a particular feature, structure, or characteristic described in connection with the aspect or embodiment is included in at least one aspect or embodiment. Thus, appearances of the phrases "in one aspect" or "in an aspect" in various places throughout this specification are not necessarily all referring to the same aspect, or aspect by way of example, but there are circumstances where those phrases refer to the same aspect, and there are circumstances where those phrases refer to different aspects. Consequently, the particular features, structures, or characteristics can be combined in any suitable manner on an individual basis. The reference in this specification to claims that are "dependent on" or "supported by" other claims, means that the dependent claims are included in solution combinations with the other claims on which the dependent claims are dependent.

Claims

1. A built-in self-test device for a System-on-a-Chip (SoC), the built-in self-test device comprising: A comparator, disposed on the SOC, and comprising: The first input port is used to receive the first input signal; The second input port is used to receive the second input signal; The output port is used to generate output signals; The first input signal and the second input signal are divided into N bit pairs, each bit pair including one bit from the first input signal and one bit from the second input signal; and The comparator is configured such that a mismatch between the first input signal and the second input signal causes the output signal to include a first expected state; and A test controller, disposed on the SOC and coupled to the first input port, the second input port and the output port, is configured to perform a first operability test by generating a mismatch for each of the N bit pairs and verifying that the output signal includes the first expected state in response to the mismatch for each of the N bit pairs.

2. The device of claim 1, wherein the test controller is configured to mismatch the N bit pairs one at a time.

3. The apparatus of claim 1, wherein the comparator is configured such that a match between the first input signal and the second input signal results in the output signal including a second expected state; and The test controller is configured to perform a second operability test by matching the N bit pairs and verifying that the output signal includes the second expected state.

4. The device of claim 1, wherein the comparator comprises: OR tree, including OR tree outputs used to generate OR tree output signals; as well as There are N XOR gates, each receiving one bit pair from the N bit pairs, and each XOR gate includes an XOR output coupled to the input of the OR tree.

5. The device according to claim 4, wherein the test controller is configured to: receive an initialization signal to initialize the first operability test; output a test completion signal; and output a test result signal.

6. The device according to claim 5, further wherein: The test controller includes: A finite state machine that receives the initialization signal; A binary counter, communicating with the finite state machine, is configured to initialize a count from 1 to N after the finite state machine receives the initialization signal; and The test controller is configured to perform the first operability test by generating the mismatch of each of the N bit pairs one at a time based on the count.

7. The apparatus according to claim 6, further wherein: Each of the N XOR gates includes a first XOR input for receiving a first bit from the first input signal and a second XOR input for receiving a second bit from the second input signal; and The test controller further includes a binary decoder coupled to the binary counters, the binary decoder including N binary counter outputs coupled to the second XOR inputs of the N XOR gates.

8. The device of claim 1, further comprising one or more additional comparators of claim 1, wherein the test controller is coupled to the first input port, the second input port, and the output port of each of the one or more additional comparators, and is configured to perform the first operability test for each of the one or more additional comparators.

9. A system for testing the operation of a comparator, comprising one or more devices according to claim 1, and further comprising an error test controller disposed on the SOC and coupled to each test controller of the one or more devices, and configured to deliver an initialization signal to each test controller of the one or more devices to initiate a first operability test, and the error test controller being configured to receive from the test controller a data signal conveying the result of the first operability test.

10. The system of claim 9, comprising a comparator collector coupled to the error test controller and a plurality of devices of claim 1, wherein the comparator collector is configured to route initialization signals and data signals between the error test controller and the test controllers of the plurality of devices.

11. A system for testing the operation of a comparator, comprising: The comparator includes: The first input port is configured to receive N bits; The second input port is configured to receive N bits. The N bits of the second input port and the N bits of the first input port are divided into N bit pairs; and The output port is configured to generate an output signal with a first expected state when any bit pair in the N bit pairs mismatches. The first circuit is configured to generate a first signal comprising N bits. The second circuit is configured to generate a second signal comprising N bits. The test controller is configured to generate a test enable signal; A selection circuit, coupled to the first circuit, the second circuit, and the test controller, is configured to: When the test enable signal is in the first state, the first signal is transmitted to the first input port, and the second signal is transmitted to the second input port. When the test enable signal is in the second state, the first test signal is transmitted from the test controller to the first input port, and the second test signal is transmitted from the test controller to the second input port; and The test controller is configured to perform an operability test on the comparator by setting the test enable signal to the second state and changing the first test signal, the second test signal, or both the first test signal and the second test signal to cause the N bit pairs to mismatch.

12. The system of claim 11, wherein the selection circuitry includes a multiplexer.

13. The system of claim 11, wherein the comparator is configured such that when all N bit pairs match, the output signal includes a second expected state; and The test controller is configured to perform a second operability test on the comparator by setting the test enable signal to the second state and matching the first test signal with the second test signal such that all N bit pairs match.

14. The system of claim 13, wherein the comparator comprises: OR tree, including OR tree outputs used to generate OR tree output signals; as well as There are N XOR gates, each receiving one bit pair from the N bit pairs, and each XOR gate includes an XOR output coupled to the input of the OR tree.

15. The system of claim 14, further comprising a gating circuit, the gating circuit comprising: A gated circuit input is used to receive the OR tree output signal and the test enable signal; The gate circuit output is used to generate the gate circuit output signal. and The gating circuit is configured to set the output signal of the gating circuit to the second expected state when the test enable signal is set to the second state.

16. The system of claim 11, wherein the first circuit includes a functional circuit, and the second circuit includes a redundancy checker circuit.

17. The system of claim 11, wherein the system includes a task mode, and wherein the test controller is configured to output an error signal when the test enable signal includes the second state and the system is in the task mode.

18. A method for testing the operation of a comparator on a system-on-a-chip (SOC), comprising: The initialization signal is received by the test controller located on the SOC; The test controller is used to match the first signal received by the comparator with the second signal received by the comparator; The output signal from the comparator is examined to include the expected output for a matched input; The test controller is used to cause a mismatch between the first signal received by the comparator and the second signal received by the comparator; and The output signal is checked to include the expected output for the mismatched input. The first signal comprises N bits, and the second signal comprises N bits; the method further comprises: dividing the first signal and the second signal into N bit pairs, each bit pair comprising one bit from the first signal and one bit from the second signal; and wherein mismatching the first signal received by the comparator with the second signal received by the comparator using the test controller comprises: mismatching each of the N bit pairs one at a time.

19. The method of claim 18, wherein the output signal is received by the test controller; and wherein the test controller is configured to check that the output signal includes the expected output for a matched input, and the test controller is configured to check that the output signal includes the expected output for a mismatched input.

20. The method of claim 19, further comprising the test controller determining that the output signal does not include the expected output for a mismatched input; and An error signal is generated by the test controller.

21. The method of claim 18, further comprising: During the test operation of the comparator on the SOC, the test controller asserts a test enable signal, and when the test enable signal is asserted when the test operation is not performed, the test controller generates an error signal.

22. The method of claim 18, further comprising: During the startup of the SOC, a check is performed on the output signal from the comparator, including the expected output for a matched input.

23. A system for testing the operation of a comparator, comprising: Multiple comparators, each comparator including: The first input port is configured to receive N bits; The second input port is configured to receive N bits; The N bits of the second input port and the N bits of the first input port are divided into N bit pairs; and The output port is configured to generate an output signal having a first expected state when any bit pair in the N bit pairs mismatches. A first circuit is configured to deliver a first signal comprising N bits to the first input port of each of the plurality of comparators; A second circuit is configured to deliver a second signal to the second input port of each of the plurality of comparators; and The test controller is configured to perform an operability test by instructing the first circuit, the second circuit, or both the first circuit and the second circuit to mismatch the N bit pairs of each of the plurality of comparators.

24. The system for testing the operation of a comparator according to claim 23, wherein the test controller performs the operability test by instructing the first circuit, the second circuit, or both the first circuit and the second circuit to mismatch one bit pair of the N bit pairs one at a time by each of the plurality of comparators.

25. The system for testing the operation of a comparator according to claim 24, further comprising a gating circuit that receives the output signal of each of the plurality of comparators.

26. The system for testing the operation of a comparator according to claim 25, wherein the test controller is coupled to the output of the gating circuit, and the test controller is configured to generate a test failure signal when the output of the gating circuit deviates from an expected output during the operability test.

27. The system for testing the operation of a comparator according to claim 26, wherein the first circuitry includes a memory error table and the second circuitry includes a new error buffer circuitry.

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