Functional verification method, system and computer-readable storage medium for cross-clock domain asynchronous circuit

Abstract

The present invention provides a method, system and computer-readable storage medium for functional verification of a cross-clock domain asynchronous circuit, wherein the method comprises: using a hardware description language to describe the design code of the cross-clock asynchronous circuit; developing a software tool to analyze and process the design code to achieve functional simulation of metastable phenomena that appear and / or disappear in the cross-clock asynchronous circuit; using the analyzed and processed design code to perform functional verification of test cases, thereby discovering design problems existing in the cross-clock asynchronous circuit. The present invention achieves simulation of asynchronous circuit design anomalies by processing the asynchronous circuit design code, thereby reducing verification costs and improving verification efficiency.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, system and computer-readable storage medium for verifying the function of a cross-clock domain asynchronous circuit in a chip digital circuit design part. Background Art

[0002] In the design of digital circuits on chips, if there is cross-clock domain asynchronous circuit design in the design part, then this part of the design needs to be paid special attention. Designers usually use some special methods to avoid functional errors caused by the circuit entering the metastable state during operation. However, if the designer fails to notice the cross-clock domain problem in the design, or uses the wrong avoidance method, then it is impossible to avoid the circuit entering the metastable state and causing functional errors.

[0003] Since the timing information of the circuit is not considered in the existing functional simulation stage, this erroneous asynchronous circuit design cannot be discovered in ordinary functional verification. Although subsequent timing simulation can discover cross-clock domain asynchronous circuit design problems, due to the increasing size of current designs, the time cost of timing simulation is too huge, and only a small number of test cases can be run; in addition, unreasonable timing constraints may be introduced during the integrated wiring process, which may cause some cross-clock domain asynchronous circuit design problems to be concealed. Summary of the invention

[0004] In view of this, the embodiments of the present invention provide a method, system and computer-readable storage medium for functional verification of cross-clock domain asynchronous circuits to eliminate or improve the defects existing in the existing cross-clock domain asynchronous circuit verification technology. Specifically, the present invention uses software tools to process the design code described in the hardware description language, realizes the simulation of asynchronous circuit design anomalies, and improves the verification efficiency while reducing the verification cost.

[0005] A first aspect of the present invention provides a method for functional verification of a cross-clock domain asynchronous circuit, comprising:

[0006] Use hardware description language to describe the design code of cross-clock asynchronous circuit;

[0007] Developing software tools to analyze and process the design code to achieve functional simulation of metastable phenomena that appear and / or disappear in cross-clock asynchronous circuits;

[0008] Use the analyzed and processed design code to perform functional verification of test cases and discover design problems in cross-clock asynchronous circuits.

[0009] Optionally, the hardware description language is Verilog HDL or VHDL.

[0010] Optionally, developing a software tool to analyze and process the above design code to achieve functional simulation of metastable phenomena that appear and / or disappear in cross-clock asynchronous circuits specifically includes:

[0011] Analyze the description code related to the register in the meter code, and extract all input variables that affect one or more assignment results in the description code;

[0012] Insert a function code, the inserted function code is used to monitor the change time of the input variable. If the difference between the monitored change time and the time of the register latch clock edge is less than a certain range, the output of the register is changed to the X state to simulate the phenomenon that the register output is in a metastable state.

[0013] Optionally, changing the output of the register to an X state includes: only setting the changed bits in the output of the register to an X state, and not setting the unchanged bits to an X state.

[0014] Optionally, changing the output of the register to an X state includes: maintaining the X state for a fixed time or a time until the next register latch clock edge.

[0015] Optionally, part of the function code is implemented by a module program module.

[0016] A second aspect of the present invention provides a function verification system for a cross-clock domain asynchronous circuit, comprising a processor and a memory, wherein the memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. Specifically, the system comprises:

[0017] The circuit description module describes the design code of the cross-clock asynchronous circuit through the hardware description language;

[0018] A software simulation module, used for developing software tools to analyze and process the design code to achieve functional simulation of metastable phenomena that appear and / or disappear in cross-clock asynchronous circuits;

[0019] The functional verification module performs functional verification of test cases on the analyzed and processed design codes, thereby discovering design problems existing in cross-clock asynchronous circuits.

[0020] Optionally, the circuit description module uses Verilog HDL or VHDL as the hardware description language.

[0021] Optionally, the software simulation module specifically includes:

[0022] A code analysis module, which analyzes the description code related to the register in the design code and extracts all input variables that affect one or more assignment results in the description code;

[0023] The code processing module inserts a function code, wherein the inserted function code is used to monitor the change time of the input variable. If the difference between the monitored change time and the time of the register latch clock edge is less than a certain range, the changed bit in the output of the register is set to the X state, and the unchanged bit is not set to the X state; the maintenance time of the X state can be a fixed time or the time until the next register latch clock edge; thereby simulating the phenomenon that the register output is in a metastable state.

[0024] A third aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the function verification method of the cross-clock domain asynchronous circuit when the program is executed by a processor.

[0025] The present invention realizes functional simulation of metastable phenomena that may exist in the design process of cross-clock asynchronous circuits by processing the cross-clock domain asynchronous circuit design code, which can solve the problem that ordinary functional verification cannot discover the cross-clock domain asynchronous circuit design; at the same time, it avoids the problems of high time cost and incomplete test cases in existing timing simulation.

[0026] Additional advantages, objects, and features of the present invention will be described in part in the following description, and will become apparent to those skilled in the art after studying the following, or may be learned from the practice of the present invention. The objects and other advantages of the present invention may be realized and obtained by the structures and method steps specifically pointed out in the written description and claims and the accompanying drawings.

[0027] Those skilled in the art will appreciate that the objectives and advantages that can be achieved with the present invention are not limited to the above specific description, and the above and other objectives that can be achieved by the present invention will be more clearly understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The drawings described herein are used to provide a further understanding of the present invention, constitute a part of this application, and do not constitute a limitation of the present invention.

[0029] Figure 1 Schematic diagram of the principle of metastable state in cross-clock domain asynchronous circuit design.

[0030] Figure 2 Schematic diagram of existing design methods for eliminating metastable states.

[0031] Figure 3 The present invention is a flow chart of a method for verifying the function of a cross-clock domain asynchronous circuit.

[0032] Figure 4 It is the Verilog HDL original design code of the digital circuit in the embodiment of the present invention.

[0033] Figure 5 It is a partially modified code and module program module in the embodiment of the present invention.

[0034] Figure 6 It is the modified Verilog HDL design code in the embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the embodiments and the accompanying drawings. The schematic embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should also be noted that, in order to avoid blurring the present invention due to unnecessary details, only structures and / or processing steps closely related to the solutions according to the present invention are shown in the accompanying drawings, while other details that are not closely related to the present invention are omitted.

[0036] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, elements, steps or components, but does not exclude the presence or addition of one or more other features, elements, steps or components.

[0037] For ease of understanding, before introducing the embodiments of the present invention, a metastable phenomenon occurring in a clock domain crossing (CDC) asynchronous circuit and a design method commonly used to eliminate the metastable phenomenon are briefly described.

[0038] In digital circuit design, there are often problems with cross-clock domain design. Figure 1 The basic principle of metastable phenomenon in cross-clock domain asynchronous circuit design is shown. Figure 1 As shown in the figure, when the input of register group A changes in a short time before or after the latch clock edge, the stabilization time of "register group A input" will be difficult to meet the setup or hold time of register group A, and the output of each register of register group A will be a fuzzy state between "0" (low level) and "1" (high level), that is, metastable phenomenon occurs; this fuzzy state will maintain a decision time, and finally stay at "0" (low level) or "1" (high level), and the metastable state disappears. When this fuzzy state is output and further drives the subsequent circuit, the subsequent circuit will also enter a fuzzy state due to the uncertainty of the input, resulting in the continuous transmission of the metastable state.

[0039] In digital circuit design, the following methods can be considered to eliminate metastable states: ①Use a slower clock design; ②Use a faster circuit based on the process or unit device; ③The output of the metastable state is directly connected in series with a register; Figure 2 The existing design methods for eliminating metastable states are shown. The above methods ① and ② can reduce the ratio of decision time to clock cycle. The advantage of this treatment is that the fuzzy state can be stabilized to a stable state before the next register clock edge arrives. Method ③ reduces the occurrence of metastable phenomena by reducing the crosstalk probability of metastable output.

[0040] It is worth noting here that eliminating metastability does not mean that there will be no problems in the design of digital circuits. In the actual design process of cross-clock domain asynchronous circuits, it is often necessary to adopt corresponding special designs according to design requirements, such as extending the signal width of the fast clock domain or using asynchronous FIFOs to ensure the correct logical function of the circuit.

[0041] In fact, as long as there are asynchronous elements in the digital circuit system, the metastable phenomenon is unavoidable. Therefore, in order to solve the problem that cross-clock domain asynchronous circuit design cannot be discovered through ordinary functional verification at this stage; at the same time, to avoid the problems of high time cost and incomplete test cases in the existing verification method through timing simulation; the present invention proposes a functional verification method for cross-clock domain asynchronous circuits based on software tools.

[0042] The embodiments of the present invention are described in detail and clearly below in conjunction with the accompanying drawings.

[0043] Figure 3 The flowchart of the function verification method of the cross-clock domain asynchronous circuit of the present invention is shown. Figure 3 As shown, the basic steps of the function verification method provided by the embodiment of the present invention are as follows:

[0044] The design code of the digital circuit including the cross-clock asynchronous circuit is described by the hardware description language. The description language may be an existing standardized hardware description language, specifically including but not limited to VerilogHDL and / or VHDL; it may also be other existing hardware description languages, or hardware description languages ​​that will be further developed and applied in the future. The above process of describing the design code of the digital circuit by the hardware description language can be realized by conventional means through conventional expressions; taking Verilog HDL as an example, the functions of each functional module of the digital circuit can be described by constructing program modules in a hierarchical manner, and the program modules can be interconnected and called to realize the description of the overall structure and function of the digital circuit. Due to the characteristics of the hardware description language itself, the timing characteristics of the digital circuit can be reflected in the process of describing the design code, so the description and simulation of the cross-clock asynchronous circuit can be realized more ideally.

[0045] The design code is analyzed and processed by developing a software tool to achieve functional simulation of metastable phenomena that appear and / or disappear in cross-clock asynchronous circuits. Specifically, in this embodiment, the developed software tool can analyze the design code of a digital circuit containing cross-clock asynchronous circuits described by Verilog HDL or VHDL. When it is found that there is a description code related to a register in the design code, for example, when an always block or a process block corresponding to a related register is found, the software tool will extract all input variables that affect one or more assignment results.

[0046] In order to better explain this embodiment, the above analysis and processing process is described below using a Verilog HDL code as an example. Figure 4 The Verilog HDL original design code of the digital circuit in this embodiment is shown; the software tool developed is used to Figure 4 Analyze the original design code in , when you see "always@(posedge clk...)begin...end", you will know that this always code is the register-related description code. Then further analyze this always block, you can find that the input variables of the a input include:

[0047] ina[25:22],ina[28:26],inb[5],inb[4:0],inc,ind[5:0];

[0048] The input variables of b input are also:

[0049] ina[25:22],ina[28:26],inb[5],inb[4:0],inc,ind[5:0];

[0050] within this range.

[0051] At this point, a careful analysis of the input variables of input b shows that its actual range may be smaller than:

[0052] ina[25:22],ina[28:26],inb[5],inb[4:0],inc,ind[5:0];

[0053] This set, but this has little effect on the final functional simulation, because the bit representing the change of the registered output simulated by the program software enters a metastable state, and the redundant input bit will not affect the registered output of the b input, that is, the output result will not produce a significant change that affects the analysis result. Therefore, in this embodiment, when analyzing the input variables of the b input, the same input variables as the a input can be used, thereby simplifying the process of analyzing the input variables in the software implementation process. In addition, these input variables may be the registered outputs of other clock domains, so during the functional simulation, if the frequency and initial phase of each clock are random, then the changes in these input variables may occur very close to the current clk (clock signal).

[0054] After the software tool extracts all input variables that affect one or more assignment results, it will further insert some functional codes into the design code. The purpose of inserting these functional codes is to monitor the change time of the above-mentioned input variables; if the difference between the monitored change time and the time of the register latch clock edge is less than a certain range, it is considered that this register operation does not meet the setup or hold time, and then the output of the register is forced (forced to a value) or other logical operations to change it to the X state. It can be understood that this process simulates the change of the input of the register that appears in the cross-clock asynchronous circuit in a short time before or after the latch clock edge, and the X state here simulates the fuzzy state between the register output being between "0" (low level) and "1" (high level).

[0055] It should be noted that it is not required to set all output bits of the register group to the X state. If the registered data of some bits in this register operation has not changed compared with the registered data of the previous clock, they will not be set to the X state. The maintenance time of the X state can be determined by a fixed time through macro definition or parameter setting, or it can be from the current change time to the next register clock latch edge. After that, if the output of this X state directly drives the next level register, the registered output of the bit driven by the X state will be a randomly determined 0 or 1. If the output of the X state enters another combinational logic, no special processing is performed and it is processed by the simulator. It can be understood that the above process simulates the process in which the fuzzy state in the cross-clock asynchronous circuit finally stays at "0" (low level) or "1" (high level) after a decision time.

[0056] Specifically, Figure 5 The modified code and module program module of this embodiment are shown, and the process of metastable state generation and / or disappearance in the cross-clock asynchronous circuit is simulated by inserting the code into the original design code of Verilog HDL. Figure 5 As shown, in one implementation of this embodiment, the 56th to 58th lines of code in the partially modified design code simulate the change time of the collected input variable, and the 60th to 75th lines of code simulate the difference between the change time of the input variable and the time of the register clock edge to monitor and judge. If the difference is less than the set range, the control signal is_meta becomes 1. The duration of is_meta can last until the next register latch clock edge according to the mode setting, or it can last for a fixed time, which can be set through macro definition. If the value of is_meta is 1, it means that some bits of the current register output may have entered a metastable state.

[0057] It should be noted that some recommended coding styles require the output of the register to be delayed for a while to avoid some simulation competition problems. At this time, most of the registered outputs will change a certain time after the latch clock edge. This situation easily causes the next level of registered output to be judged as not meeting the hold time. Therefore, in this embodiment, by setting HOLD_TIME_THRESHHOLD to be less than the delay time LATCH_DELAY_TIME of the registered output, the erroneous result of triggering the metastable state due to the difference in coding styles can be avoided.

[0058] An implementation of this embodiment further provides an exemplary functional code to simulate the emergence and transmission process of the metastable state. Figure 5As shown in the figure, the 77th to 89th lines of code are used to calculate which bits will change if the register output is in a metastable state. The bits that have not changed mean that the input data (bit-level data) that determines the output of the bit has not changed, and the setup and hold time is met, so the output has not changed. The bits that have changed mean that the input data (bit-level data) that determines the output of the bit has changed. If the change is too close to the register clock edge, the output bit will be in the X state. Figure 5 In the function code shown, the above judgment process is simulated by the value of meta_output. When the metastable state disappears after a period of time, the bit enters the stable state of 0 or 1, which is simulated by meta_resolve_output.

[0059] Figure 6 The modified Verilog HDL design code in the embodiment of the present invention is shown. Figure 6 As shown, in one implementation of this embodiment, after the software tool performs the above operations and returns to the original design code, the software tool will instantiate meta_detector into the original design code. At this time, meta_detector can already implement most of the functions, such as checking input data changes and simulating metastable output values. However, at this time, the modification of specific registered outputs needs to be completed in the original design code. Figure 6 , the 131st to 138th lines of the modified Verilog HDL design code in this embodiment show that the output of input a is modified according to a_meta_out_vld, and the output of input b is modified according to b_meta_out_vld. Afterwards, when the software tool scans the original design code, it will be found that a_reg is a direct registered output of input a. This treatment usually prevents the further backward propagation of the metastable state, while b_composition_reg will not. Therefore, the 141st to 147th lines of code process the assignment of a_reg. Specifically, when a_meta_out_vld is 1, a_reg will be equal to a_meta_resolve_out to simulate the final resolution state of the metastable state. b_composition_reg does not need special treatment, and the code modification is now complete.

[0060] Finally, the modified code can be used for functional verification of various test cases in the process of cross-clock domain asynchronous circuit design. The processed code is functionally verified by a large number of test cases, and the design problem of the asynchronous circuit is discovered by simulating the abnormal simulation behavior of the design code of the digital circuit. The functional verification method provided in this embodiment can realize the simulation of various digital circuits with cross-clock domain asynchronous circuit design problems using only software methods, and then discover the metastable phenomenon that is easy to occur in the cross-clock domain asynchronous circuit during its design process, which solves the problem that the conventional functional verification at this stage cannot find problems in time, and the problems of high time cost and incomplete test cases in the existing verification method of test cases through timing simulation.

[0061] The second embodiment of the present invention provides a functional verification system for a cross-clock domain asynchronous circuit, including a processor and a memory, wherein the memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. The processor and the memory can be connected via a bus or other means; the processor can be a central processing unit (CPU); the processor can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above chips.

[0062] The memory is a non-transient computer-readable storage medium that can be used to store non-transient software programs, non-transient computer executable programs and modules, such as the program instructions / modules corresponding to the functional verification method for the cross-clock domain asynchronous circuit in the above method embodiment of the present invention. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the functional verification method for the cross-clock domain asynchronous circuit in the method embodiment of the present invention is implemented.

[0063] Specifically, the function verification system of the cross-clock domain asynchronous circuit in this embodiment includes the following functional modules:

[0064] The circuit description module describes the design code of the cross-clock asynchronous circuit through a hardware description language; the description language may be an existing standardized hardware description language, specifically including but not limited to VerilogHDL and / or VHDL; it may also be other existing hardware description languages, or hardware description languages ​​that will be further developed and applied in the future. The above process of describing the design code of the digital circuit through the hardware description language can be implemented by conventional means through conventional expressions; the description of the design code of the cross-clock asynchronous circuit by the circuit description module can more ideally realize the simulation of the cross-clock asynchronous circuit. Thereby, the functional verification system of the cross-clock domain asynchronous circuit in this embodiment can realize the analysis and processing of the design code in a software environment.

[0065] The software simulation module is used to develop software tools to analyze and process the design code to achieve functional simulation of metastable phenomena that appear and / or disappear in cross-clock asynchronous circuits; specifically, the software tool developed in this embodiment can analyze and process the design code of digital circuits described by Verilog HDL or VHDL that contain cross-clock asynchronous circuits.

[0066] As an implementation method in this embodiment, the software simulation module may include a code analysis submodule and a code processing submodule. Among them, the code analysis submodule can analyze the description code related to the register in the design code, and extract all input variables that affect one or more assignment results in the description code. The code processing submodule can be used to insert a function code into the design code, and the function code is specifically used to monitor the change time of all input variables extracted by the code analysis module. When the difference between the change time monitored by the function code and the time of the register latch clock edge is less than a certain range, the bit that has changed in the register output is set to the X state, and the bit that has not changed is not set to the X state. Among them, the maintenance time of the X state can be a fixed time, or it can be the time that lasts until the next register latch clock edge, and then the function verification system in this embodiment can simulate the phenomenon of the register output being metastable.

[0067] The function verification module performs function verification of the test case on the analyzed and processed design code, and then finds the design problems existing in the cross-clock asynchronous circuit. The function verification system provided in this embodiment can carry the function verification method in the above method embodiment of the present invention, and use software methods to realize the simulation of various digital circuits with cross-clock domain asynchronous circuit design problems.

[0068] A third embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which is executed by a processor to implement the functional verification method of the cross-clock domain asynchronous circuit in the aforementioned method embodiment. The computer-readable storage medium may be a tangible storage medium, such as a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a floppy disk, a hard disk, a removable storage disk, a CD-ROM, or any other form of storage medium known in the technical field.

[0069] It should be clear that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the embodiments of the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for functional verification of a cross-clock domain asynchronous circuit, characterized in that: include: Use hardware description language to describe the design code of cross-clock asynchronous circuit; Developing software tools to analyze and process the design code to achieve functional simulation of metastable phenomena that appear and / or disappear in cross-clock asynchronous circuits; Use the analyzed and processed design code to perform functional verification of test cases, thereby discovering design problems in cross-clock asynchronous circuits; The analyzing and processing of the design code to realize functional simulation of metastable phenomena appearing and / or disappearing in the cross-clock asynchronous circuit includes: Analyze the description code related to the register in the design code, and extract all input variables that affect one or more assignment results in the description code; Insert the function code to monitor the change time of the input variable. If the difference between the monitored change time and the time of the register latch clock edge is less than a certain range, the output of the register is changed to the X state, thereby simulating the phenomenon that the register output is in a metastable state.

2. The method according to claim 1, characterized in that: The hardware description language is VerilogHDL or VHDL.

3. The method according to claim 1, characterized in that The changing the output of the register to the X state includes: only setting the changed bits in the output of the register to the X state, and not setting the unchanged bits to the X state.

4. The method according to claim 1, characterized in that: Changing the output of the register to the X state includes: the X state can be maintained for a fixed time or until the next register latch clock edge.

5. The method according to claim 1, characterized in that: Part of the function code is implemented by the module program module.

6. A functional verification system for a cross-clock domain asynchronous circuit, comprising a processor and a memory, characterized in that: The memory stores computer instructions, and the processor is used to execute the computer instructions stored in the memory. Specifically, the system includes: The circuit description module describes the design code of the cross-clock asynchronous circuit through the hardware description language; A software simulation module, used for developing software tools to analyze and process the design code to achieve functional simulation of metastable phenomena that appear and / or disappear in cross-clock asynchronous circuits; Functional verification module: performs functional verification of test cases on the analyzed and processed design codes, thereby discovering design problems in cross-clock asynchronous circuits; The software simulation module comprises: A code analysis module, used for analyzing the description code related to the register in the design code, and extracting all input variables that affect one or more assignment results in the description code; The code processing module is used to insert the function code to monitor the change time of the input variable. If the difference between the monitored change time and the time of the register latch clock edge is less than a certain range, the output of the register is changed to the X state, thereby simulating the phenomenon that the register output is in a metastable state.

7. The system according to claim 6, characterized in that: The circuit description module uses VerilogHDL or VHDL as the hardware description language.

8. The system according to claim 6, characterized in that Changing the output of the register to an X state comprises: Only the changed bits in the output of the register are set to the X state, and the unchanged bits are not set to the X state; the X state is maintained for a fixed time or until the next register latch clock edge.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 5 is implemented.

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