Data processing method, device, computer equipment and storage medium

Abstract

The present disclosure relates to a data processing method, apparatus, computer equipment and storage medium. The disclosed board includes: a storage device, an interface device and a control device and a chip provided with a data processing device; wherein the data processing device is connected to the storage device, the control device and the interface device respectively; the storage device is used to store data; the interface device is used to realize data transmission between the data processing device and an external device; the control device is used to monitor the status of the data processing device. The data processing method, apparatus, computer equipment and storage medium provided by the embodiments of the present disclosure can split and layout the data based on the split index in the dynamic tag information when executing the neural network operation task, so that the second data can adapt to the multiple memory channels of the multi-core processor, so as to utilize the multiple computing cores in the multi-core processor to perform the operation operation, thereby improving the processing efficiency and speed of the neural network operation task.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a data processing method, apparatus, computer device, and storage medium. Background Art

[0002] With the development of computer technology, neural networks have also made significant progress. Neural network operations can now be performed using specific or general-purpose processors. However, the speed of neural network operations is greatly limited by factors such as the large number of data types, the large amount of computation required, and hardware limitations. Summary of the Invention

[0003] In view of this, the present disclosure proposes a data processing method, apparatus, computer device, and storage medium.

[0004] According to one aspect of the present disclosure, a data processing method is provided, which is applied to a multi-core processor, wherein the multi-core processor includes multiple computing core clusters, each computing core cluster includes multiple computing cores, and the method includes:

[0005] Acquire first data and tag information of the first data, wherein the tag information includes dynamic tag information, and the dynamic tag information includes identification information of a split index and a target storage space;

[0006] Splitting the first data into a plurality of second data according to the splitting index;

[0007] According to the identification information of the target storage space, the plurality of second data are stored in the corresponding target storage space respectively,

[0008] The dynamic tag information is used to represent information associated with the first data and the multi-core processor.

[0009] According to another aspect of the present disclosure, a data processing device is provided, which is applied to a multi-core processor, wherein the multi-core processor includes multiple computing core clusters, each computing core cluster includes multiple computing cores, and the device includes:

[0010] An acquisition module is configured to acquire first data and tag information of the first data, wherein the tag information includes dynamic tag information, and the dynamic tag information includes a split index and a target storage space;

[0011] a splitting module, splitting the first data into a plurality of second data according to the splitting index;

[0012] The storage module stores the plurality of second data in the corresponding target storage space according to the identification information of the target storage space.

[0013] The dynamic tag information is used to represent information associated with the first data and the multi-core processor.

[0014] According to another aspect of the present disclosure, a machine learning computing device is provided, the device comprising:

[0015] One or more of the aforementioned data processing devices are configured to obtain data to be processed and control information from other processing devices, perform specified machine learning operations, and transmit the execution results to other processing devices via I / O interfaces;

[0016] When the machine learning operation device includes a plurality of the data processing devices, the plurality of the data processing devices may be connected and transmit data through a specific structure;

[0017] Among them, multiple data processing devices are interconnected and transmit data through a fast peripheral device interconnection bus PCIE bus to support larger-scale machine learning operations; multiple data processing devices share the same control system or have their own control systems; multiple data processing devices share memory or have their own memory; the interconnection method of multiple data processing devices is any interconnection topology.

[0018] According to another aspect of the present disclosure, a combination processing device is provided, the combination processing device comprising:

[0019] Such as the aforementioned machine learning computing devices, universal interconnection interfaces and other processing devices;

[0020] The machine learning computing device interacts with the other processing devices to jointly complete the computing operations specified by the user.

[0021] Among them, the combined processing device also includes: a storage device, which is connected to the machine learning operation device and the other processing device respectively, and is used to store data of the machine learning operation device and the other processing device.

[0022] According to another aspect of the present disclosure, a chip is provided, comprising the above-mentioned combined processing device.

[0023] According to another aspect of the present disclosure, a board is provided, comprising: a memory device, an interface device, a control device, and the chip as described above;

[0024] Wherein, the data processing device is connected to the storage device, the control device and the interface device respectively;

[0025] The storage device is used to store data;

[0026] The interface device is used to realize data transmission between the data processing device and external equipment;

[0027] The control device is used to monitor the status of the data processing device,

[0028] Wherein, the memory device comprises: a plurality of groups of memory units, each group of the memory units is connected to the data processing device via a bus, and the memory units are: DDR SDRAM;

[0029] The data processing device includes: a DDR controller for controlling data transmission and data storage of each of the storage units;

[0030] The interface device is: a standard PCIE interface.

[0031] According to another aspect of the present disclosure, a data processing device is provided, comprising a processor and a memory, wherein a computer program is stored in the memory, and when the processor executes the computer program, the above-mentioned data processing method is implemented.

[0032] According to another aspect of the present disclosure, a non-volatile computer-readable storage medium is provided, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the above-mentioned data processing method is implemented.

[0033] The data processing method, device and storage medium provided by the embodiments of the present disclosure include: obtaining first data and label information of the first data, the label information including dynamic label information, the dynamic label information including a split index and a target storage space; splitting the first data into multiple second data according to the split index; storing the multiple second data in corresponding target storage spaces according to the identification information of the target storage space, wherein the dynamic label information is used to characterize the information associated with the first data and the multi-core processor. After determining the first data and its dynamic label, the method of the present disclosure can split and layout the first data based on the split index in the dynamic label information and the identification information of the target storage space, so that the second data can adapt to the multiple memory channels of the multi-core processor, so as to utilize the multiple computing cores in the multi-core processor to perform computing operations, thereby improving the processing efficiency and speed of neural network operations.

[0034] Further features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0036] Figure 1a A schematic diagram showing a framework of a computer device according to an embodiment of the present disclosure is shown.

[0037] Figure 1b 、 Figure 1c A schematic diagram of a multi-core processor architecture according to an embodiment of the present disclosure is shown.

[0038] Figure 1d 、 Figure 1e A schematic diagram of the architecture of a computing core cluster according to an embodiment of the present disclosure is shown.

[0039] Figure 2 A flowchart of a data processing method according to an embodiment of the present disclosure is shown.

[0040] Figure 3 A schematic diagram illustrating a first data packet according to an embodiment of the present disclosure is shown.

[0041] Figure 4 A flow chart of a data processing method according to an embodiment of the present disclosure is shown.

[0042] Figure 5 FIG. 1 is a schematic diagram illustrating the architecture of a multi-core processor 1 according to an embodiment of the present disclosure.

[0043] Figure 6a A schematic diagram illustrating the allocation of computing tasks for a multi-core processor 1 executing a computing instruction A according to an embodiment of the present disclosure is shown.

[0044] Figure 6b 、 6c A schematic diagram illustrating a process of executing an operation instruction A by a multi-core processor 1 according to an embodiment of the present disclosure is shown.

[0045] Figure 7 A block diagram of a data processing device according to an embodiment of the present disclosure is shown.

[0046] Figure 8 1 is a structural diagram illustrating a combined processing device 1200 according to an embodiment of the present disclosure.

[0047] Figure 9 FIG. 1 is a schematic diagram showing the structure of a board 1300 according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0048] Various exemplary embodiments, features, and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. The same reference numerals in the accompanying drawings represent elements with the same or similar functions. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0049] The word “exemplary” is used exclusively herein to mean “serving as an example, example, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0050] In addition, numerous specific details are provided in the following detailed description to better illustrate the present disclosure. Those skilled in the art will appreciate that the present disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art are not described in detail in order to highlight the main points of the present disclosure.

[0051] The data processing method of the present invention can be applied to Figure 1a In the computer device shown, the computer device may include a host 101, a device 102, a host memory 103, and a device memory 104. Host 101 may be a general-purpose processor, and device 103 may be a neural network accelerator, but the present invention is not limited to the types of host 101 and device 103. In this data processing method, the data flow is as follows: host 101 moves input data from host memory 103 to device memory 104; device 102 reads the input data from device memory 104 and performs calculations according to the instructions; device 102 writes the calculation results back to device memory 104; and host 101 moves output data from device memory 104 to host memory 103.

[0052] With the development of computer technology and big data, multi-core processors have gradually become mainstream. Device 102 in this embodiment may be a multi-core processor, which may have different architectures depending on usage needs. For example, a multi-core processor may include multiple computing core clusters, each of which may include at least one computing core, and each computing core cluster may be provided with designated memory. Figure 1b 、 Figure 1c A schematic diagram of a multi-core processor architecture according to an embodiment of the present disclosure is shown. Figure 1d 、 Figure 1e The multi-core processor may be a symmetric multi-processor (SMP) architecture, such as Figure 1b As shown in the figure, it is assumed that the symmetric multiprocessor includes four computing core clusters and four memories (off-chip device memories). The computing cores in the computing core cluster can access the memories through the routing node R. Among them, the four memories are the "local memories" of the corresponding four computing core clusters, but due to its symmetrical setting, the computing cores in each computing core cluster need to pass through two routing nodes R when accessing the four memories. In the absence of congestion, the access rate of any memory is the same. For example, Figure 1bThe "local memory" of compute cluster x is memory a. During data access, data corresponding to compute cluster x is preferentially stored in the "local memory." A corresponding memory channel is set up between the compute cluster and its corresponding "local memory," allowing the compute cluster to access its own "local memory" through this memory channel. This reduces the chance that cores from different compute clusters will access the same memory.

[0053] Multi-core processors can also be non-uniform memory access (NUMA) architecture, such as Figure 1c As shown in FIG, a multi-core processor with non-uniform symmetric memory access is assumed to include four computing core clusters and four memories. The computing cores in the computing core clusters can access the memories through the routing node R. The four memories are the "local memories" of the corresponding four computing core clusters. However, due to their asymmetric settings, when no congestion occurs, the computing cores in each computing core cluster can access their corresponding "local memories" (such as Figure 1c When a computing core in computing core cluster n accesses memory s), it only needs to pass through one routing node R. For example, when a computing core in computing core cluster n accesses memory s, it only needs to pass through one routing node R, and the access rate is the fastest. When a computing core in each computing core cluster accesses other non-"local memories", it needs to pass through at least two routing nodes R, and the access rate is slow.

[0054] Optionally, when a computing core cluster is configured with multiple computing cores, the organizational structure in the computing core cluster can also be configured as needed. The architecture of the computing core cluster can be a bus competition type, such as Figure 1d As shown, it is assumed that the computing core cluster includes 4 computing cores, and each computing core can access the memory through the routing node R. The architecture of the computing core cluster can also be a shared cache type, such as Figure 1e As shown, assuming that a computing core cluster includes four computing cores and an off-core cache corresponding to the computing core cluster is set, the four computing cores in the computing core cluster share the off-core cache. Each computing core in the computing core cluster can directly access the off-core cache and can access the memory through the routing node R.

[0055] To accelerate large-scale data tasks, such as neural network computations, multi-core processors typically employ data parallelism, model parallelism, and hybrid parallelism. Data parallelism involves different compute cores processing different input data for the same neural network, equivalent to computing multiple batches of input data for the same neural network in parallel. Model parallelism involves different compute cores processing different parts of the same input data for the same neural network. This involves breaking down the operators and data in the neural network, with each compute core processing a portion of the data, equivalent to the entire accelerator processing one copy of the input data in parallel. Hybrid parallelism combines data parallelism with model parallelism, such as using model parallelism within a compute core cluster and data parallelism between compute core clusters. However, when multi-core processors utilize these three approaches to execute computational tasks, the technical challenges of splitting operators and data and planning data storage locations to ensure efficient execution of computational tasks remain pressing.

[0056] The present disclosure provides a data processing method, before actually executing a neural network computing task, the host can pre-acquire the first data and the dynamic label information of the first data, and then split the first data into multiple second data according to the split index in the dynamic label information, and store the multiple second data in the corresponding target storage space according to the identification information of the target storage space in the dynamic label information, thereby realizing the layout storage of the first data, so that the multi-core processor can directly obtain the second data for related operations when executing the computing task, thereby improving the processing efficiency and speed of the computing task. The data processing method of the present disclosure can be specifically described below. Optionally, the compiler running in the host can implement the above-mentioned data processing method.

[0057] Figure 2 FIG. 1 is a flow chart showing a data processing method according to an embodiment of the present disclosure. Figure 2 As shown, the method is applied to a multi-core processor, the multi-core processor includes multiple computing core clusters, each computing core cluster includes multiple computing cores, and the method includes "label use steps" from step S11 to step S13.

[0058] In step S11, first data and tag information of the first data are acquired, where the tag information includes dynamic tag information, and the dynamic tag information includes identification information of a split index and a target storage space.

[0059] Optionally, the method disclosed herein may first traverse the computational graph of a neural network, which may include at least one data node (i.e., first data), and respectively determine the label information of each first data in the neural network, wherein the label information of the first data may include dynamic label information and static label information, and bind the label information of the first data to the corresponding first data. Furthermore, the method disclosed herein may process the above-mentioned neural network according to the label information of the first data. For example, a hardware instruction that can be executed by a multi-core processor is generated based on the label information of the first data, so that the multi-core processor performs corresponding processing on the neural network according to the hardware instruction.

[0060] Among them, the static label information can be used to characterize the information associated with the first data participating in the neural network operation, which may include at least one of the following: data category, static data type, static data dimension, static data dimension order and dimension value corresponding to each static data dimension and other information. The dynamic label information is used to characterize the information associated with the first data and the multi-core processor, which can be specifically determined according to the architecture of the multi-core processor. The dynamic label information may include at least one of the following: dynamic data type, dynamic data dimension order, sharding parameters, padding parameters and data size, split index, identification of the target storage space and target exchange level and other information. The specific process of determining the static label information and dynamic label information can be found in the description below and will not be repeated here.

[0061] Specifically, the first data may be data of various data categories involved in neural network operations, such as: input neurons (Input Neuron), output neurons (Output Neuron), hidden neurons (Hidden Neuron), constant neurons (Constant Neuron), input weights (Input Weight), output weights (Output Weight), constant weights (Constant Weight) and auxiliary data (Auxiliary). The first data may also include instructions corresponding to neural network operations, which may be hardware instructions that can be directly executed on a multi-core processor after compilation. In the method disclosed herein, each first data can be identified by the data category in the static tag information.

[0062] In this embodiment, the split index in the dynamic tag information can be used to indicate the implementation scheme that the first data needs to be split into multiple second data when the first data of a specified data category participates in the neural network operation on the current multi-core processor. Among them, the neural network operation refers to the computing node in the neural network calculation graph, which may include convolution operations, full connection operations, pooling operations, scaling operations and other operations, which are not limited in this disclosure. In the neural network operation, one or more input data are usually processed to obtain the operation result. The first data can be input data (including but not limited to input neurons and input weights) and operation results (including but not limited to output neurons), which are not limited in this disclosure.

[0063] In this embodiment, the identification information of the target storage space can be used to indicate where each second data needs to be stored in the multi-core processor (that is, to which specific storage space). As described above in the multi-core processor architecture, the storage space of the multi-core processor may include a local memory, or it may also be an off-core cache and a local memory. The identification information of the target storage space may be a number, name, etc. corresponding to the memory (or off-core cache) storing each second data, which can distinguish the different identities between the memory and other memories, or it may be a category of the memory or off-core cache, that is, a category identifier of the memory or a category identifier of the off-core cache.

[0064] For example, when the identification information of the target storage space in the dynamic tag information is the category identification of the memory (assuming that the target storage space is a memory), it indicates that multiple second data are stored in multiple memories in sequence. When the identification information of the target storage space in the dynamic tag information is the identity identification of each memory (assuming that the target storage space is a memory), it indicates that multiple second data are stored in sequence in the memory corresponding to each identity identification. Those skilled in the art can set the identification information of the target storage space stored in the dynamic tag information according to actual needs, and the present disclosure does not limit this.

[0065] In step S12, the first data is split into multiple second data according to the split index.

[0066] In step S13, the plurality of second data are stored in corresponding target storage spaces according to the identification information of the target storage spaces, so that each computing core can obtain the second data from the corresponding target storage space for computing and executing corresponding computing tasks.

[0067] Optionally, in the data processing method disclosed herein, the host may pre-acquire the first data and its corresponding dynamic tag information during compilation, and generate corresponding instructions based on the dynamic tag information, split the first data into multiple second data according to the instructions during runtime, and store the second data obtained after splitting into the corresponding target storage space. Optionally, the data processing method disclosed herein may also pass in the dynamic tag information of the first data during runtime, split the first data into multiple second data according to the dynamic tag information, and store the second data after splitting into the corresponding target storage space. It should be clear that the compiling time here refers to the stage of compiling the neural network calculation graph to generate instructions; the runtime refers to the operating environment of the program. Optionally, the above data processing method can be implemented by a compiler.

[0068] The data processing method provided by the embodiment of the present disclosure can, after determining the first data and its dynamic label information, split and layout the first data based on the split index in the dynamic label information and the identification information of the target storage space, so that the second data can adapt to the multiple memory channels of the multi-core processor, so as to utilize the multiple computing cores in the multi-core processor to perform computing operations, thereby improving the processing efficiency and speed of neural network operations.

[0069] In one possible implementation, the dynamic tag information also includes a target data exchange level. The "tag use step" of the method may further include: generating a first instruction for neural network operation corresponding to the first data based on the parallel computing mode of the multi-core processor, the identification information of the target storage space, and the target data exchange level, so that each computing core performs a corresponding computing task according to the first instruction. The first instruction may include at least one of the following: a data access instruction and a data operation instruction.

[0070] In this implementation, the host can generate the above-mentioned first instruction during the compilation stage. The method of the present disclosure generates a first instruction according to the dynamic tag information during compilation, so that the computing task required to be performed by each computing core can be sent to the corresponding computing core through the first instruction, so that the computing core can perform its corresponding computing task for the first data under the control of the received first instruction, and the present disclosure does not limit this. Among them, the data access instruction can be used to instruct the computing core to perform storage and / or reading for the second data (that is, the data after the first data is split). In this embodiment, different data access instructions are generated by the target storage space identification information and the target data exchange level in the dynamic tag information, so as to realize the exchange of data between different computing cores. The data operation instruction is used to indicate the detailed operation performed by the computing core on the second data, such as obtaining the operation result after the arithmetic operation corresponding to the second data.

[0071] Optionally, the first instruction may also include a data access instruction, a data exchange instruction, and a data operation instruction, wherein the data exchange instruction is used to indicate the exchange level of the second data and how to perform the data exchange when the data is actually exchanged. The data access instruction is used to instruct the storage and / or reading of data, and the data operation instruction is used by the computing core to perform operations.

[0072] Among them, the target data exchange level can be used to indicate whether the second data needs to be exchanged between cores. The exchange refers to whether the second data stored in the off-core cache or memory will be used by other computing cores in the same computing core cluster or computing cores in other computing core clusters (as data to be calculated or as the result of the operation) in addition to being used by the computing core that calculates the second data (as data to be calculated or as the result of the operation). The data exchange represented by the target data exchange level may include: no exchange, inter-cluster data exchange, inter-core data exchange, and inter-memory data exchange. Among them, "no exchange" may mean that the data will not be used by other computing cores, "inter-cluster data exchange" may mean that the data will be used by computing cores in other computing core clusters, "inter-core data exchange" may mean that the data will be used by computing cores in the same computing core cluster, and "inter-memory data exchange" may mean that the data will be used by computing cores in different computing core clusters. The embodiment of the present application can generate a corresponding first instruction according to the target data exchange level and target storage space in the dynamic tag information during compilation, and in combination with the architecture of the multi-core processor, so that each computing core of the multi-core processor can perform the corresponding task according to the first instruction.

[0073] In one possible implementation, the dynamic tag information may also include a target data exchange level, and the method may further include: determining the computing tasks that each computing core needs to perform based on a second instruction corresponding to the first data, the parallel computing method of the multi-core processor, the identification information of the target storage space, and the target data exchange level.

[0074] In this implementation, the second instruction is used to instruct the computing core on what kind of computing task needs to be performed on the first data, including how to obtain the first data, the dynamic label information of the first data, what kind of operation of the neural network is involved in the first data, which operators need to be called, how to store the obtained operation results, and other information related to the actual process of executing the computing task.

[0075] Optionally, when the neural network operations, target storage spaces, parallel computing methods of the multi-core processor, and target data exchange levels involved in the first data are different, the computing tasks performed by the computing cores are not exactly the same. For example, in Example 1, for a fully connected MLP operator operation, the first data includes input weights, input neurons, and output neurons. When the computing task is executed in a data-parallel manner, data exchange occurs between the input weights, while data exchange does not occur between the output neurons and the input neurons. Specifically, when the computing core cluster architecture is a bus-competitive type, data exchange occurs between the input weights and the memory. When the computing core cluster architecture is a shared cache type, data exchange occurs between the input weights and the cluster. Example 2: For a fully connected MLP operator operation, the first data includes input weights, input neurons, and output neurons. When the computing task is executed in a model-parallel manner, data exchange occurs between the output neurons, while data exchange does not occur between the input neurons and the input weights. Specifically, when the computing core cluster architecture is a bus-competitive type, data exchange occurs between the output neurons and the cluster. In Example 3, for a fully connected MLP operator, the first data includes input weights, input neurons, and output neurons. When executing the operation task in a hybrid parallel manner, data exchange occurs between the input neurons and the output neurons, but no data exchange occurs between the input weights. When the computing core cluster architecture is a shared cache type, data exchange occurs between cores and clusters for the output neurons, and data exchange occurs between clusters for the input neurons.

[0076] To facilitate understanding of the computational tasks performed by the computational core, the following describes the computational tasks performed by the computational core when the first data includes input neurons, input weights, and output neurons, and the data to be exchanged is determined based on dynamic label information. The process by which the computational core performs its corresponding computational tasks is described in the examples provided in the "Application Examples" section below.

[0077] In one possible implementation, when the first data includes input neurons, input weights, and output neurons, and data exchange for the output neurons is determined based on dynamic label information of the first data, the computing tasks performed by the computing core may include:

[0078] Each computing core obtains first target data from a plurality of second data of input neurons and second target data from a plurality of second data of input weights, calculates the first target data and the second target data to obtain a first intermediate result, and stores the first intermediate result in a storage space corresponding to the computing core;

[0079] A first computing core among the multiple computing cores obtains at least two first intermediate results, performs computation on the at least two first intermediate results to obtain a second intermediate result, and stores the second intermediate result in a storage space corresponding to the first computing core;

[0080] A second computing core among the multiple computing cores obtains at least two second intermediate results, performs operations on the at least two second intermediate results to obtain operation results, and stores the operation results as the output neuron in the target storage space.

[0081] In one possible implementation, when the first data includes input neurons, input weights, and output neurons, and data exchange of the input weights is determined based on dynamic tag information of the first data, the computing tasks performed by the computing core may include:

[0082] Each computing core is used to obtain first target data from a plurality of second data of input neurons and second target data from a plurality of second data of input weights, perform operations on the first target data and the second target data to obtain a first intermediate result, and store the first intermediate result in a corresponding target storage space;

[0083] Each computing core is used to obtain first target data from a plurality of second data of input neurons and third target data different from the second target data from a plurality of second data of input weights, and to store a second first intermediate result obtained after operating the first target data and the third target data in a corresponding target storage space;

[0084] A first computing core among the multiple computing cores obtains at least two first intermediate results, performs computation on the at least two first intermediate results to obtain a second intermediate result, and stores the second intermediate result in a corresponding target storage space, wherein the first intermediate results include the first type of first intermediate results and the second type of first intermediate results;

[0085] The second computing core among the multiple computing cores obtains at least two second intermediate results, performs operations on the at least two second intermediate results to obtain operation results, and stores the operation results as the output neuron in the target storage space.

[0086] In one possible implementation, when the first data includes an input neuron, an input weight, and an output neuron, and data exchange between the input neuron and the output neuron is determined based on dynamic label information of the first data, the computing tasks performed by the computing core may include:

[0087] Each computing core is used to obtain first target data from a plurality of second data of input neurons and second target data from a plurality of second data of input weights, and to obtain a first intermediate result after performing an operation on the first target data and the second target data, and to store the first intermediate result in a storage space corresponding to the computing core;

[0088] Each computing core is configured to obtain fourth target data and the second target data different from the first target data from the plurality of second data input to the neuron, perform operations on the fourth target data and the second target data to obtain a second first intermediate result, and store the second first intermediate result in a storage space corresponding to the computing core;

[0089] A first computing core among the multiple computing cores obtains at least two first intermediate results, performs computation on the at least two first intermediate results to obtain a second intermediate result, and stores the second intermediate result in a storage space corresponding to the first computing core, where the first intermediate results include the first type of first intermediate results and the second type of first intermediate results;

[0090] The second computing core among the multiple computing cores obtains at least two second intermediate results, performs operations on the at least two second intermediate results to obtain operation results, and stores the operation results as the output neuron in the target storage space.

[0091] In a possible implementation, the dynamic tag information further includes a dynamic data type, a dynamic data dimension order, a sharding parameter, and a padding parameter. The split index (the method for determining the split index is described below) includes: a target split dimension, a starting split position and an ending split position of each second data on the target split dimension of the first data. Step S12 may include:

[0092] When it is determined that the current data state of the first data is inconsistent with the dynamic tag information, the first data is processed according to the dynamic tag information to obtain processed first data; and on the target splitting dimension, the processed first data is split into a plurality of second data based on the starting split position and the ending split position of each second data on the target splitting dimension of the first data. The data state includes the data type, the order of the data dimensions, and the dimension values.

[0093] In this implementation, the dynamic label information is determined after determining the processor running the neural network, based on the static label information (described below), the algorithmic characteristics of the neural network, the computing power and performance of the processor, etc., so that the first data with dynamic label information can be applied to the processor's operation. When the neural network uses different processors for operation, the dynamic label information of the first data may be different. When the performance, computing power and other parameters of the two processors are the same, the dynamic label information of the first data may be the same.

[0094] In this implementation, the dynamic data type can be determined based on the type of data that can be processed by the processor running the neural network, the computing power, etc. For example, if a processor can process 16-bit floating point numbers, then when the neural network is run using this processor, the dynamic data type of the data to be processed is a 16-bit floating point number. The order of dynamic data dimensions can be determined based on the needs of the processor running the neural network to read or store data. The slicing parameter can be determined based on the computing power of the processor running the neural network. For example, if a processor can perform operations on 8 numbers at a time, the slicing parameter can be set to 8. The padding parameter can be determined based on the dimension value of the static data dimension of the data to be processed and the slicing parameter. The padding parameter may include the length of the data to be padded in different dimensions of the data and / or the required padding value. Data size, also known as the size or amount of data, is the product of the dimensions of the data in the actual operation and the data bit width, determined by the dimension values of the static data dimensions, the slicing parameters, and the padding parameters. For example, if the data is a matrix, and the dimensions of the two dimensions in the operation are 4 and 8 respectively, and the data bit width is 4, then the data size of the data is 4×8×4=128 bytes.

[0095] In a possible implementation, the dynamic tag information of the first data may be expressed as:

[0096] dynamic:type2,DIM_B1…Bn,tiling,padding,size,split x[(1_0,1_n-1)…(i_i×n,i_(i+1)n-1)],store,swap

[0097] Among them, dynamic indicates that the tag information is dynamic tag information. type2 indicates the dynamic data type. DIM_B1…Bn indicates that the dynamic data dimension order is B1…Bn. Tiling is the sharding parameter. Padding is the padding parameter, and size is the data size, which indicates the size of the storage space occupied by the data after dimension conversion, tiling, or padding. split x[(1_0, 1_n-1)…(i_i×n, i_(i+1)n-1)] represents the split index, where x represents the target split dimension and the split length is n. (1_0, 1_n-1) indicates that the starting split position of the first second data is 0 and the ending split position is n-1; (i_i×n, i_(i+1)n-1) indicates that the starting split position of the i-th second data is i×n and the ending split position is (i+1)n-1. store indicates the identification information of the target storage space. swap indicates the target data swap level. “,”, “[],” and “()” are only used to separate different parameters in the dynamic tag information in this disclosure, and are not essential content of the dynamic tag information. In actual applications, “,” and may not exist or may be replaced by other identifiers, and this disclosure does not impose any restrictions on this.

[0098] In one possible implementation, when it is determined that the current data state of the first data is consistent with the dynamic label information, the processed first data can be split into multiple second data directly on the target splitting dimension, with the starting splitting position and ending splitting position of each second data on the target splitting dimension of the first data as a reference.

[0099] In one possible implementation, the tag information further includes static tag information, which is used to represent information associated with the neural network operation in which the first data participates. The static tag information includes at least one of the following: a static data type, a static data dimension, a static data dimension order, and a dimension value corresponding to each static data dimension. When it is determined that the current data state of the first data is inconsistent with the dynamic tag information, the first data is processed according to the dynamic tag information to obtain processed first data, including at least one of the following:

[0100] Converting the data type of the first data from the static data type to the dynamic data type;

[0101] Adjusting the order of data dimensions of the first data from a static data dimension order to a dynamic data dimension order;

[0102] Filling the first data according to the filling parameter;

[0103] The first data is segmented according to the segmentation parameters.

[0104] In this implementation, the static label information may include information such as the data type, dimension, dimension value, etc. that describes the nature of the first data itself, and also includes information related to the neural network operation in which the first data participates. Therefore, the static label information of the same first data may be different in different neural networks. The static label information can be determined after the neural network is established. The static label information of the first data can be applicable to any processor that runs the neural network, that is, the static label information of the first data is unchanged in different processors. The static label information of the first data can be automatically detected and determined by the processor in the process of obtaining the first data (the process of the user inputting the first data), or it can be determined based on the information input by the user. This disclosure does not limit this.

[0105] In a possible implementation, the static label information may also include data categories. The data categories include any of the following: instructions, input neurons, output neurons, hidden neurons, constant neurons, input weights, output weights, constant weights, and auxiliary data. The data category represents the category of the first data in the neural network, which is determined based on information such as whether it is visible to the user and the operations involved in the neural network. The static data type represents the type and number of bits of the first data, such as a static data type can be a 32-bit floating point number or an 8-bit fixed point number. The static data dimension can be one-dimensional, two-dimensional, multi-dimensional, etc., and the static data dimension order can represent the dimensional order of storage and / or reading of the first data.

[0106] Optionally, the static data dimensions may include but are not limited to at least one of the following: channel dimension C, height dimension H, width dimension W, number dimension N, depth dimension D (used in three-dimensional convolution operations) and time dimension T (used in RNN network operations such as LSTM). The order of recording or characterizing the static data dimensions can be achieved by using the first 6 letters or other arrangement orders corresponding to the identifiers of each static data dimension. The static data dimension that comes first or on the left in the arrangement precedes the static data dimension that comes later or on the right. Alternatively, it can be assumed that the static data dimension that comes first or on the left in the arrangement is higher than the static data dimension that comes later or on the right. For example, if the static data dimension order of the first data is NCHW, it means that the first data is a four-dimensional tensor, and its corresponding static data dimension order is number dimension N, channel dimension C, height dimension H and width dimension W, with the highest dimension being number dimension N and the lowest dimension being width dimension W. The static data dimension order of the first data is TNHWC, which means that the first data is a five-dimensional tensor, and the corresponding static data dimension order is time dimension T, number dimension N, height dimension H, width dimension W and channel dimension C, with the highest dimension being time dimension T and the lowest dimension being channel dimension C. When the actual user inputs or the multi-core processor obtains from the physical memory, the first data will be mapped into a one-dimensional array according to the determined static data dimension order and stored in the physical memory. It may not be easy to determine which dimension a one-dimensional tensor (vector) belongs to. This situation can be determined based on the algorithm definition of the operator. For example, the bias data bias in the two-dimensional convolution is one-dimensional. In the algorithm definition, the bias needs to be superimposed on the output feature map, and each output channel is superimposed with a number. The superimposed numbers of different channels are different, so the dimension of the one-dimensional bias can be regarded as the channel dimension C.

[0107] In this implementation, the dimension value corresponding to each static data dimension represents the length or size of the corresponding static data dimension. For example, if the first data is a matrix, the static data dimensions include rows and columns, and the static data dimension order is row-first, the dimension value of the row is 10 and the dimension value of the column is 4, which means that the length of the row is 10 and the length of the column is 4.

[0108] In a possible implementation, the static tag information of the first data may be expressed as:

[0109] Static:classification,type1,DIM_A1…An,{x1…xn}

[0110] Among them, static is an identifier indicating that the label information is static label information. classification indicates the data category, and type1 indicates the static data type. The n in DIM_A1…An indicates the static data dimension, and A1…An indicates that the static data dimension order is A1…An. The dimension value of A1 is x1…The dimension value of An is xn. "," and "{}" are only used to separate different parameters in the static label information in this disclosure, and are not essential content of the static label information. In actual applications, "," and "{}" may not exist, and may also be replaced by other identifiers. This disclosure does not impose any restrictions on this.

[0111] It should be understood that those skilled in the art can set the static tag information, the identifier of the data category, and the position of each parameter in the static tag information according to actual needs, and the present disclosure does not limit this.

[0112] In one possible implementation, the "label use step" of the method may further include a constant data packaging step, which includes: when the first data includes multiple constant data, packaging multiple second data obtained by splitting each constant data according to the total number of computing cores in the multi-core processor to form multiple first data packets corresponding to each computing core and then storing them, so that each computing core performs a corresponding operation based on the loaded first data packets. The number of first data packets may be the same as the total number of computing cores.

[0113] The first data packet may include a constant data area and a tag area. The constant data area may include one of the multiple second data obtained by splitting each constant data. The tag area may include at least one of the following: a tag for the total constant data amount, a tag for the total hidden layer data amount of the hidden layer in the neural network operation in which the first data participates, and a tag for the input and output addresses in the neural network operation. In the embodiment of the present application, by packaging the constant data, the constant data can be transferred to the corresponding computing core of the multi-core processor at one time during the operation, without the need for repeated transfer, thereby improving the operation efficiency.

[0114] In this implementation, the "constant data packaging step" can be performed during the compilation phase of the neural network. During the compilation phase, the constant data corresponding to the neural network can be obtained based on the static tag information of the first data (such as the data category in the static tag information), and at least one constant data can be split and packaged into multiple first data packets, wherein the number of first data packets can be equal to the number of computing cores in the multi-core processor. Moreover, before the computing core executes the assigned computing task, the host can pre-send each first data packet to the "local memory" or "off-core cache" corresponding to the computing core, and the computing core can load the first data packet into the local memory to facilitate the execution of subsequent computing tasks. In this way, the computing core can obtain the constant data required to execute the computing task in advance, which simplifies the process of the computing core executing the computing task, and because the constant data is obtained in advance, the speed of the computing core executing the computing task can also be increased, thereby achieving a speed increase for the first data operation.

[0115] In this implementation, constant data may refer to data that does not change (or does not change frequently) after the architecture and neural network of the multi-core processor are determined and during the execution of the computing task. Since the model parameters of the trained neural network basically do not change, the constant data may include weight parameters, offset parameters, scaling parameters, beta parameters, etc. in the first data. The first instruction obtained after compilation will not change during the calculation process, so the constant data may also include the above-mentioned first instruction. Of course, the constant data may also include the third data required to perform the computing task.

[0116] Some constant data can be split into multiple second data based on their split indexes for use by different computational cores, such as first data, convolution filter parameters (weight parameters), offset parameters, scaling parameters, and beta parameters. Some constant data may not need to be split. The required third data can be determined based on the computational task to be performed by the computational core.

[0117] For the convenience of description, each second data obtained after the constant data is split according to the corresponding split index is also referred to as a constant data block in this document.

[0118] In this implementation, the constant total data amount mark is used to record the total data amount of all constant data blocks in the first data packet. The constant total data amount mark can also record the total data amount of all constant data blocks in the first data packet and the data amount of each constant data block. The total hidden layer data amount of the hidden layer in the neural network operation is used to record the total data amount of the hidden layer data in the neural network. The total hidden layer data amount can also indicate the size of each hidden layer data and the total data amount of the hidden layer data in the neural network. The sum of the data amount of all hidden layer data is the total hidden layer data amount. The input and output addresses in the neural network refer to the addresses of the input data and the addresses of the output data. The input data can be the data to be calculated that the computing core needs to obtain each time it performs a calculation task, and the output data can be the result obtained after the data to be calculated is calculated.

[0119] In one possible implementation, the constant data, hidden layer data, and input and output addresses in the first data packet can be arranged in a specific order to form different data segments. The above-mentioned "constant data packing step" also includes calculating the intra-segment offset of each data segment. The above-mentioned "constant data packing step" can also include at least one of the following operations: determining the first intra-segment offset, determining the second intra-segment offset, and determining the third intra-segment offset. The method disclosed herein does not specifically limit the execution order of the above-mentioned operations, and they can be executed sequentially in a specific order or in parallel.

[0120] in,

[0121] "Determine the offset within the first segment": Based on the total constant data size of each first data packet and the size of each second data item contained therein, determine and record the offset within the first segment of the constant data segment of the corresponding first data packet. This allows the computing core to read the corresponding constant data block from the constant data segment according to the first segment offset of each constant data block. The constant data segment is the data segment in the first data packet that records the constant data blocks.

[0122] "Determining the offset within the second segment": Based on the total amount of input and output address data in each first data packet, the amount of data contained in each input address, and the amount of data contained in each output address, the offset within the second segment of the address data segment of each input and output address is determined and recorded. The address data segment is used to record input addresses and output data segments. This allows the computing core to obtain each input address and / or output address based on the offset within the second segment, further obtain input data, and store computation results.

[0123] "Determine the offset within the third segment": Based on the total amount of hidden layer data in each first data packet and the amount of each hidden layer data item contained therein, determine and record the offset within the third segment of the hidden layer data segment of the corresponding first data packet. The hidden layer data segment is used to record the amount (i.e., size) of each hidden layer data item. This allows the computing core to determine the amount of each hidden layer data item from the total amount of hidden layer data based on the offset within the third segment, improving the speed and efficiency of the packaging process.

[0124] Figure 3 A schematic diagram of a first data packet according to an embodiment of the present disclosure is shown. For example, in the "constant data packing step", multiple constant data that need to be split and packed are first determined, such as Figure 3 As shown, it is assumed that the constant data includes the following: instruction 1 (also known as the first instruction) and instruction 2 (also known as the first instruction), and convolution filters. And these constant data will be allocated to computing cores 1 and 2 for use. Then, according to the label information of instruction 1, instruction 2, and convolution filters, it can be determined that instruction 1 and instruction 2 are the instructions to be executed by computing cores 1 and 2 respectively, and the convolution filter needs to be split into convolution filter data block 1 and convolution filter data block 2 according to the split index, which are used by computing cores 1 and 2 respectively. According to the input address and output address, it is determined that the input address 1 (the address for obtaining all the data to be calculated) and output address 1 (the address for storing the result of the calculation) required by computing core 1 are required, and the input address 2 (the address for obtaining all the data to be calculated) and output address 2 (the address for storing the result of the calculation) required by computing core 2 are required. Then, instruction 1, instruction 2, convolution filter data block 1, convolution filter data block 2, input address 1, input address 2, output address 1, and output address 2 are reordered according to the usage of the computing core, and packaged into the first data packet 1 required by computing core 1 and the first data packet 2 required by computing core 2, and the constant total data amount mark is recorded in the first data packet 1 and the first data packet 2.

[0125] Taking the first data packet 1 as an example, it is also necessary to calculate the second-segment offset of input address 1 and output address 2 in the address data segment. Since the data volume of input address 1 and output address 1 is 8 respectively, the second-segment offset of input address 1 is "0", and the second-segment offset of output address 1 is "8". Calculate the first-segment offset of instruction 1 and convolution filter data block 1. Since the data volume of instruction 1 is 2048 and convolution filter data block 1 is 1024, the first-segment offset of instruction 1 is "0", and the first-segment offset of convolution filter data block 1 is "2048". The constant total data volume mark in the first data packet 1 is "3072". Finally, before the computing core executes the assigned computing task, the host can send the first data packet 1 and the first data packet 2 to computing core 1 and computing core 2 respectively, or send them to the target storage space accessed by computing core 1 and computing core 2 respectively.

[0126] In one possible implementation, before executing step S11, the host may also pre-execute a "label generation step" to generate dynamic label information and static label information of the first data, wherein the dynamic label information may include the split index, target storage space and target data exchange level of the first data.

[0127] Figure 4 FIG. 1 is a flow chart showing a data processing method according to an embodiment of the present disclosure. In one possible implementation, as shown in FIG. Figure 4 As shown, the "label generation step" may include steps S14 to S16.

[0128] In step S14, first data and label information of the first data are obtained, where the first data is used to participate in neural network operations, and the label information includes static label information (as described above) and dynamic label information (excluding the split index, target storage space, and target data exchange level, but including the other information described above).

[0129] In step S15, a splitting index required to split the first data into multiple second data is determined based on the parameters of the operator corresponding to the operation in which the first data participates, the number of memory channels in the multi-core processor and the tag information.

[0130] In this embodiment, the parameters of the operator are used to represent or describe the type of operation that the operator needs to perform and the parameters required to implement its corresponding operation, such as the parameters of operators such as convolution operations and pooling operations.

[0131] In a possible implementation, step S15 may include:

[0132] Determining a splitting strategy corresponding to the first data from a splitting strategy database according to the determined parameters of the operator corresponding to the operation in which the first data participates and the label information;

[0133] A splitting index required to split the first data into a plurality of second data is determined according to the splitting strategy, the number of memory channels in the multi-core processor, and the tag information.

[0134] The splitting strategy includes at least one splittable dimension of the first data and a priority level corresponding to each splittable dimension. The target splitting dimension in the splitting index is a dimension selected from the at least one splittable dimension.

[0135] In this implementation, the splitting strategy can indicate the optional splitting methods corresponding to different data categories in different multi-core processors, different types of neural network operations, and operations, so that the data can be further split into multiple data in different ways. The target splitting dimension in the splitting index is determined from the multiple splittable dimensions of the splitting strategy, and then the starting splitting position and the ending splitting position of each second data on the target splitting dimension of the first data are further determined according to the target splitting dimension, and finally the splitting index is obtained. The splitting strategy can be preset, and the predetermined splitting strategy can be stored in the memory in the form of a splitting strategy database. Of course, in other embodiments, the splitting strategy can also be actually determined by the data processing device according to the operation in which the first data participates and the characteristics of the operator of the multi-core processor. Among them, the predetermined splitting strategy is recorded in the splitting strategy database, and the numbers of different data categories are set with corresponding splitting strategies in different operators.

[0136] For example, when the first data (such as input neurons, input weights, etc.) participates in the operation as "input", the split index can be used to split the first data into multiple second data to achieve the operation. When the first data (such as output neurons, etc.) participates in the operation as "output", the split index can be used to indicate or predict that the final output neuron (that is, the final operation result) obtained after the split operation of the "input" will be obtained by performing operations on several intermediate results. What it actually indicates is the split relationship between the intermediate results and the output neurons; or due to the size limit of the output neuron data, it may not be possible to split, that is, it has no corresponding split index. In actual operation tasks, one or more data to be operated are usually operated and processed to obtain the operation result. The determined split index can be any one of the one or more data to be operated and the operation result. The present disclosure does not limit this.

[0137] In step S16, the split index is added to the dynamic tag information so that the multi-core processor can perform the neural network operation on the first data based on the tag information.

[0138] In this embodiment, after the split index is added to the dynamic tag information, when the multi-core processor uses the first data (the first data is the data to be calculated) to perform a calculation task, it can split the first data into multiple second data according to the split index in the dynamic tag and then perform the calculation task (i.e., execute the above-mentioned step S12); it can also determine how to perform the relevant calculation process according to the split index during the execution of the calculation task (such as when the first data is the calculation result). In this way, with the help of the tag information, the multi-core processor can simplify the splitting and layout process of the data involved in the calculation task, thereby improving the calculation speed of the calculation task.

[0139] In one possible implementation, before executing step S14, the dynamic label information required for executing steps S14 to S16 can be obtained in advance through the "step of determining dynamic label information" (that is, obtaining dynamic label information that does not contain the split index, target storage space, and target data exchange level, but includes the other information described above). The step of determining the dynamic label information includes: obtaining information about the target processor (that is, the multi-core processor mentioned above) that runs the neural network. The information of the target processor may include the data type of the data that the target processor can process, the dimensional order of the target processor in reading and storing data, the number of data bits processed by the target processor each time (or the number of processed numbers), and other information related to the computing power and performance of the target quantity. Furthermore, the data processing device can determine the dynamic label information of the first data through at least one of the following operations based on the information of the target processor and the static label information of the first data:

[0140] Determine the dynamic data type according to the data type that the target processor can process;

[0141] Determine the dynamic data dimension order according to the dimension order of reading and storing data of the target processor;

[0142] Determine the sharding parameters based on the number of data bits processed each time by the target processor;

[0143] Determine the filling parameters based on the sharding parameters and the dimension values of the static data dimensions;

[0144] The data size is determined based on the dimension values of the static data dimensions, the sharding parameters, and the padding parameters.

[0145] In a possible implementation, the device may determine the data category of the first data based on the out-degree and in-degree of the neural network corresponding to the first data and the operations in the neural network in which the first data participates.

[0146] In this implementation, the in-degree represents the number of predecessor operation nodes in which the first data node participates as a data node (the first data node is the output of the predecessor operation node), and the out-degree represents the number of subsequent operation nodes in which the first data node participates as a data node (the first data node is the input of the subsequent operation node). For example, if a first data node cc can be the output of one predecessor operation node and the input of three subsequent operation nodes, the out-degree of the first data node cc is 3 and the in-degree is 1. Different codes can be set for different data categories to distinguish them. Table 1 below describes the characteristics of data in different data categories and their corresponding identifiers.

[0147] Table 1 Data categories, corresponding identifiers and data characteristics

[0148]

[0149] The out-degree and in-degree of the instruction are zero, triggering the neural network to execute the computation on the data and / or computational kernel. Input neurons, constant neurons, input weights, constant weights, and auxiliary data have an out-degree greater than 1 and an in-degree of 0. Output neurons and output weights have an out-degree of 0 and an in-degree greater than or equal to 1. Hidden neurons have both an out-degree and in-degree greater than or equal to 1.

[0150] In one possible implementation, determining the splitting strategy corresponding to the first data from a splitting strategy database based on the determined parameters of the operator corresponding to the operation in which the first data participates and the label information may include:

[0151] Obtaining a computation graph corresponding to the neural network, the computation graph including operation nodes, data nodes, and connection relationships between data nodes and operation nodes; wherein the data nodes may include label information of the first data, and the label information of the first data includes static label information and dynamic label information;

[0152] Obtain information of a target operation node connected to the data node where the first data is located in the computation graph, where the information of the target operation node includes parameters of an operator corresponding to an operation that implements the target operation node;

[0153] A splitting strategy corresponding to the first data is determined from a splitting strategy database according to the parameters of the operator and the static label information of the first data.

[0154] In this implementation, static label information and part of dynamic label information (excluding split index, target storage space, and target data exchange level) can be first determined based on the computational graph of the neural network, and the determined label information can be bound and stored with the corresponding data nodes.

[0155] In this implementation, the static label information may also include a data category. Furthermore, the splitting strategy corresponding to the first data may be determined from the splitting strategy database based on the parameters of the operator and the data category of the first data. For example, referring to Table 2 below, assuming that the operator corresponding to the operation in which the first data is involved is determined to be a two-dimensional convolution Conv and its data category is input weights based on the above steps, then its corresponding splitting strategy is "the splittable dimension is N, the storage space to be selected is Cluster, and the data exchange level to be selected is No." Assuming that the operator corresponding to the operation in which the first data is involved is determined to be a two-dimensional convolution Conv and its data category is input neurons based on the above steps, then its corresponding splitting strategy is "the splittable dimensions are N, H, and W (with decreasing priority), when the splittable dimension is N, the storage space to be selected is Mem, and the data exchange level to be selected is No; when the splittable dimension is H or W, the storage space to be selected is Cluster, and the data exchange level to be selected is Cluster."

[0156] In one possible implementation, determining, based on a splitting strategy corresponding to the first data, the number of memory channels in the multi-core processor, and the tag information, a splitting index for splitting the first data into a plurality of second data may include:

[0157] Determining a target splitting dimension from the at least one splittable dimension according to the number of memory channels and the operation dimension value of each dimension of the first data in the neural network operation process determined according to the label information, and determining a splitting length corresponding to the target splitting dimension, where the splitting length is the length of the second data in the direction of the target splitting dimension;

[0158] A split index for splitting the first data into a plurality of second data is determined according to the number of memory channels, an operation dimension value of the first data on the target split dimension, and the split length.

[0159] In this implementation, the operation dimension value refers to the dimension value of each dimension during the actual operation of the first data.

[0160] In this embodiment, since the purpose of splitting the first data is to utilize the multi-core processor to achieve parallel processing as much as possible. Therefore, before determining the split length, the target number of the second data can be determined first, and then the split length can be determined based on the dimension value and target number of the target split dimension. The size relationship between the operation dimension value of the target split dimension and the total number of computing cores of the multi-core processor (that is, the number of computing cores contained in the multi-core processor) and the number of memory channels can be judged first, and then the split length can be further determined in a corresponding manner based on the size relationship, that is, the following method one, method two, and method three.

[0161] Method 1: When the operational dimension value of the target split dimension is greater than or equal to the total number of computing cores, the target number of the second data is determined to be consistent with the total number of computing cores, and the split length is the ratio of the operational dimension value of the first data on the target split dimension to the total number of computing cores, and when the ratio is not an integer, a preset rounding function (as described below) can be used for rounding to obtain the split length. Among them, the rounding function can include a floor function (such as a floor function, that is, a Floor function, which takes the largest integer not greater than the ratio), an upward rounding function (such as a Ceil function, which takes the smallest integer greater than or equal to the ratio), a rounding function (such as a rounding function, that is, a Round function, which rounds the ratio to a specified number of decimal places to obtain an integer), and other rounding functions. In this way, it can be ensured that each computing core participates in the actual calculation process, reducing the idle computing power of the multi-core processor and improving the efficiency and speed of the calculation.

[0162] Method 2: When the operation dimension value of the target splitting dimension is less than the total number of computing cores and greater than or equal to the number of memory channels, the number of memory channels is determined as the target number of the second data, and the splitting length is the ratio of the operation dimension value of the first data on the target splitting dimension to the number of memory channels. When the ratio is not an integer, a preset rounding function can be used for rounding to obtain the splitting length.

[0163] Method three: when the operation dimension value of the target split dimension is less than the number of memory channels, the operation dimension value of the target split dimension is determined as the target number of the second data, and the split length is the unit length of the operation dimension value of the target split dimension.

[0164] By determining the split length using the above methods 1, 2, and 3, it is possible to ensure that all computing cores in the multi-core processor participate in the computing task, thereby ensuring efficient and high-speed execution of the computing task.

[0165] In one possible implementation, the static tag information may include: a static data dimension and a dimension value corresponding to each static data dimension; the dynamic tag information may include a dynamic data type, a padding parameter, and a data size; wherein, based on the splitting strategy, the number of memory channels in the multi-core processor, and the tag information, determining a split index required to split the first data into multiple second data may further include:

[0166] Based on the dimension value of each static data dimension of the first data and the padding parameter, a computational dimension value for each dimension of the first data during participation in the neural network computation is determined. The computational dimension value can be determined as the sum of the dimension value of each static data dimension and the length of padding data corresponding to the static data dimension in the padding parameter.

[0167] In this implementation, the operation dimension value may also be calculated using other methods based on the existing static label information and dynamic label information of the first data, and this disclosure does not impose any restrictions on this.

[0168] In one possible implementation, the operation dimension value can be pre-calculated and stored in the dynamic tag information. This allows the operation dimension value to be directly obtained from the dynamic tag information only for determining the split length and split index, simplifying the split index determination process and improving efficiency.

[0169] In one possible implementation, determining a target split dimension from the at least one splittable dimension and determining a split length corresponding to the target split dimension based on the number of memory channels and the operation dimension value of each dimension of the first data in the process of participating in the neural network operation may include:

[0170] When there are multiple splittable dimensions, the splittable dimensions are judged in descending order of priority to see whether they meet the splitting condition. When it is determined that the current splittable dimension meets the splitting condition, the current splittable dimension is determined as the target splitting dimension.

[0171] The splitting condition includes: the operation dimension value of the first data on the current splittable dimension is greater than or equal to the number of memory channels.

[0172] For example, assuming the first data has three dimensions "w1, w2, w3", and the operational dimension values of each dimension are w1 = 2, w2 = 32, and w3 = 64, the corresponding splitting strategy has splittable dimensions w1 and w3, and w1 has a higher priority than w3. If the number of channels of the multi-core processor is 4, first determine whether the first data's highest priority "splittable dimension w1" meets the splitting condition. Since w1's operational dimension value of 2 is less than the "number of channels 4", the splitting condition is not met. Then, determine whether the next "splittable dimension w3" meets the splitting condition. Since w3's operational dimension value of 32 meets the splitting condition, w3 of the first data is used as the target splitting dimension.

[0173] In one possible implementation, when all splittable dimensions do not meet the splitting condition, that is, the operation dimension value of each splittable dimension is less than the number of memory channels, the operation dimension value of the splittable dimension with the largest operation dimension value can be determined as the target splitting dimension. In this way, it is possible to ensure that more computing cores in the multi-core processor are used to perform the computing task for the first data.

[0174] For example:

[0175] Example 1, assuming that the multi-core processor includes 2 memory channels, 2 computing core clusters, and each computing core cluster includes 2 computing cores. If a first data includes three dimensions a, b, and c, and the dimension values of each dimension are a=1, b=4, and c=2. If its splittable dimensions are a and b, and a has a higher priority than b. Then, first determine the splittable dimension a. Since a=1 is less than the number of memory channels 2 (i.e., the splitting condition is not met), a cannot be used as the target splitting dimension. Continue to determine the splittable dimension b. Since b=4 is greater than the number of memory channels, the splittable dimension b is determined as the target splitting dimension. Furthermore, since b=4 is equal to the total number of computing cores 4, the target number of the second data can be determined to be the same as the total number of computing cores 4, and the splitting length = the dimension value of the target splitting dimension b 4 ÷ the total number of computing cores 4 = 1.

[0176] Example 2, assuming that the multi-core processor includes 2 memory channels, 2 computing core clusters, and each computing core cluster includes 2 computing cores. If a first data includes three dimensions a, b, and c, and the dimension values of each dimension are a=1, b=4, and c=2. If its splittable dimensions are a and c, and a has a higher priority than c. Then, first determine the splittable dimension a. Since a=1 is less than the number of memory channels 2 (i.e., the splitting condition is not met), a cannot be used as the target splitting dimension. Continue to determine the splittable dimension c. Since c=2 is less than the total number of computing cores and equal to the number of memory channels, the splittable dimension c can be determined as the target splitting dimension. Furthermore, since c=2 is less than the total number of computing cores 4 and equal to the number of memory channels, the target number of the second data can be determined to be the same as the number of memory channels 2, and the split length = the dimension value of the target splitting dimension c 2 ÷ the number of memory channels 2 = 1.

[0177] Example 2, assuming that the multi-core processor includes 4 memory channels, 2 computing core clusters, and each computing core cluster includes 2 computing cores. If a first data includes three dimensions a, b, and c, and the dimension values of each dimension are a=1, b=2, and c=2. If its splittable dimensions are a and c, and a has a higher priority than c. Then, first determine the splittable dimension a. Since a=1 is less than the number of memory channels 4 (i.e., the splitting condition is not met), a cannot be used as the target splitting dimension. Continue to determine the splittable dimension c. Since c=2 is still less than the number of memory channels 4 (i.e., the splitting condition is not met). At this time, since c=2>a=1, the splittable dimension c is determined as the target splitting dimension. Further, since c=2 is less than the number of memory channels 4, the target number of the second data can be determined as the dimension value 2 of the target splitting dimension C, and the splitting length = the dimension value 2 of the target splitting dimension c.

[0178] It should be noted that, in the actual operation process, the operation task is mostly to perform an arithmetic operation between at least two data to be operated to obtain an operation result. In this case, the data to be operated and the operation result can be used as the above-mentioned first data to determine the splitting index.

[0179] In this embodiment, when the first data participates in the calculation task, due to the differences in operators, target splitting dimensions, and multi-core processor architectures, in order to facilitate the use of the first data by different calculation cores, it is also necessary to set the target storage space of the second data obtained after splitting the first data to ensure that the calculation core that actually uses the second data to perform the corresponding calculation task can read and write conveniently and quickly.

[0180] In one possible implementation, step S15 may include: determining at least one splittable dimension corresponding to the first data and the priority level corresponding to each splittable dimension based on the parameters of the operator corresponding to the operation in which the first data participates, the characteristics of the operator of the multi-core processor and the label information (including dynamic data types and data categories).

[0181] In this implementation, the characteristics of the multi-core processor's arithmetic unit may include: the dimensions along which different data categories can be split when executing different operators, whether the different splitting dimensions match the multi-core processor's hardware settings or the multi-core processor's user-defined processing capabilities, and the impact of different splitting dimensions on computational efficiency, among other characteristics related to the processor's hardware settings and user-defined settings. This ensures that the splitting strategy can be determined while meeting computational efficiency and speed requirements.

[0182] In this implementation method, a strategy model for determining the splitting strategy can be trained in advance based on the parameters of the existing operators, the characteristics of the arithmetic unit of the multi-core processor, and the label information; or a correspondence between the parameters of the operators, the characteristics of the arithmetic unit of the multi-core processor, the label information and the splitting strategy can be established to determine the splitting strategy of the first data in real time.

[0183] In a possible implementation, the multi-core processor is provided with multiple computing core clusters, each computing core cluster includes multiple computing cores, and the “label generation step” may further include:

[0184] Determining a candidate storage space corresponding to each divisible dimension based on the determined parameters of the operator corresponding to the operation in which the first data participates and the storage space set in the multi-core processor;

[0185] According to the target splitting dimension, a target storage space corresponding to the first data is determined from the candidate storage spaces, and identification information of the target storage space is added to the dynamic tag information.

[0186] Wherein, the storage space includes multiple memories (such as Figure 1d As shown, the multi-core processor does not have an off-core cache for the computing core cluster); or the storage space includes multiple memories, multiple off-core caches (such as Figure 1e As shown, the multi-core processor is provided with an off-core cache of a computing core cluster), each computing core can access any one of the multiple memories, and the multiple computing cores in each computing core cluster share a corresponding off-core cache.

[0187] In this implementation, a model for determining the storage space to be selected can be trained in advance based on the parameters of the existing operator and the storage space settings set in the multi-core processor; or a correspondence between the parameters of the operator, the storage space set by the multi-core processor and the storage space to be selected can be established, and then the storage space to be selected for the first data can be determined in real time.

[0188] In this implementation, the multi-core processor is provided with multiple memories, and each computing core cluster can access the corresponding "local memory" through a channel, and can also access other memories through the channel and the routing node. Due to different architectures, the off-core cache in the multi-core processor can be set or not. The candidate storage space corresponding to each divisible dimension can be determined in real time based on the parameters of the operator and the storage space set in the multi-core processor. The difference in operators will affect the selection of the candidate storage space, and whether the storage space set in the multi-core processor contains an off-core cache provides an optional target for the operator.

[0189] In this implementation, there may be one or more storage spaces to be selected. In the process of determining the storage spaces to be selected, the divisible dimensions corresponding to each storage space to be selected may also be determined. Each storage space to be selected corresponds to one or more divisible dimensions. Different divisible dimensions may correspond to the same storage space to be selected. One divisible dimension corresponds to only one storage space to be selected (that is, one divisible dimension cannot correspond to two different storage spaces to be selected). The corresponding divisible dimension in the storage space to be selected includes one of the target divisible dimensions and is determined as the target storage space.

[0190] For example, Figure 5 A schematic diagram of the architecture of a multi-core processor 1 according to an embodiment of the present disclosure is shown as follows: Figure 5 As shown, the multi-core processor 1 includes memory 1 and memory 2, computing core cluster 1 (including computing core 1 and computing core 2) and its corresponding off-core cache 1, computing core cluster 2 (including computing core 3 and computing core 4) and its corresponding off-core cache 2, and the computing core accesses the memory through the routing node R. Among them, the category identifier of the memory is mem, the category identifier of the off-core cache is cluster, the identification information of memory 1 and memory 2 are mem1 and mem2 respectively, and the identification information of off-core cache 1 and off-core cache 2 are cluster1 and cluster2 respectively. Assuming that the first data a is an input neuron, it will be split into two second data a1 and a2, and need to be stored in the memory. The dynamic tag information can be stored in the identification information "mem" representing the storage space category of the memory (a1 and a2 can be stored in mem1 and mem2 respectively), or it can be the identification information "mem1" and "mem2" of the memory 1 and memory 2 themselves.

[0191] In a possible implementation, the splitting strategy further includes a candidate storage space, and each splittable dimension is provided with a corresponding candidate storage space. The "label generation step" may further include: determining a target storage space from the candidate storage spaces according to the target splitting dimension, and adding identification information of the target storage space to the dynamic label information.

[0192] The storage space includes multiple memories; or the storage space includes multiple memories and multiple off-core caches, each computing core can access any one of the multiple memories, and multiple computing cores in each computing core cluster share a corresponding off-core cache.

[0193] In this implementation, the conditions of the candidate storage spaces for data can be determined in advance and stored in the splitting strategy database to simplify the process of determining the target storage space and improve the speed and efficiency of data processing.

[0194] In a possible implementation, the “label generation step” may further include:

[0195] Determining a candidate data exchange level corresponding to each divisible dimension based on parameters of an operator corresponding to the determined operation in which the first data participates, characteristics of an operator of the multi-core processor, and the label information;

[0196] According to the target splitting dimension, a target data exchange level corresponding to the first data is determined from the candidate data exchange levels, and the target data exchange level is added to the dynamic tag information.

[0197] In this implementation, a model for determining the candidate data exchange level can be trained based on the operator parameters, the characteristics of the arithmetic unit of the multi-core processor, and the label information; or a correspondence between the operator parameters, the characteristics of the arithmetic unit of the multi-core processor, the label information and the candidate data exchange level can be established to determine the candidate data exchange level of the first data in real time.

[0198] In this implementation, there may be one or more data exchange levels to be selected. In the process of determining the data exchange levels to be selected, the splittable dimensions corresponding to each data exchange level to be selected may also be determined. Each data exchange level to be selected corresponds to one or more splittable dimensions. Different splittable dimensions may correspond to the same data exchange level to be selected. One splittable dimension corresponds to only one data exchange level to be selected (i.e., one splittable dimension cannot correspond to two different data exchange levels to be selected). The corresponding splittable dimensions in the data exchange level to be selected include one of the target splitting dimensions and are determined as the target data exchange level.

[0199] In a possible implementation, the splitting strategy further includes a candidate data exchange level corresponding to each splittable dimension, and the “label generation step” further includes:

[0200] A candidate data exchange level corresponding to the target splitting dimension in at least one candidate data exchange level is determined as a target data exchange level corresponding to the first data, and the target data exchange level is added to the dynamic tag information.

[0201] In this implementation, candidate data exchange levels for data can be determined in advance and stored in a splitting strategy database to simplify the process of determining the target data exchange level and improve the speed and efficiency of data processing.

[0202] In this embodiment, the splitting strategy for the first data can be set in advance according to the above-mentioned splitting strategy. Figure 5Taking the architecture of the multi-core processor shown in the figure and the first data being image data as an example, the following Table 2 provides an example of a splitting strategy for the first data in an embodiment of the present disclosure.

[0203] Table 2 Split strategy examples

[0204]

[0205] Among them, the splittable dimension N represents the number dimension, the splittable dimension H represents the height dimension, the splittable dimension W represents the width dimension, and the splittable dimension C represents the channel dimension.

[0206] In the candidate storage space, "Mem" is the memory category identifier, and "Cluster" is the identifier of the off-core cache.

[0207] In the data exchange level, "No" indicates no exchange, "Cluster" indicates inter-cluster data exchange, and "Core" indicates inter-core data exchange. Within the same data, earlier splittable dimensions take precedence over later ones. For example, in the input neuron of "2D Convolution," the splittable dimensions are N, H, and W, with the priorities being N, H, and W, from highest to lowest.

[0208] In this embodiment, a real-time splitting strategy determination model can be specified in advance based on the correspondence between the reference information related to the splitting strategy (including the splittable dimensions, the storage space to be selected, and the data exchange dimension to be selected) and the splitting strategy as described above, and then the splittable dimensions, the storage space to be selected, and the data exchange dimension to be selected of the first data can be determined in real time according to the model, and then the splitting index, the identification information of the target storage space, and the target data exchange level can be added to the dynamic tag information of the first data. A splitting strategy database can also be determined in advance based on the reference information, in which various required splitting strategies are recorded, and this disclosure does not impose any restrictions on this.

[0209] Application Examples

[0210] The following uses "processing operation instruction A" as an exemplary application scenario to provide an application example according to an embodiment of the present disclosure to facilitate understanding of the flow of the data processing method. Those skilled in the art should understand that the following application example is merely for the purpose of facilitating understanding of the embodiments of the present disclosure and should not be regarded as limiting the embodiments of the present disclosure.

[0211] Example 1

[0212] Assume that the data involved in processing the operation instruction A includes input neuron I, input weight W and output neuron O, and the multi-core processor that executes the operation instruction A is Figure 5The multi-core processor 1 shown here uses a fully connected MLP operation, employing model parallelism for data operations. The input neuron I, input weight W, and output neuron O are 1×1024, 1024×4, and 1×4 data, respectively. The specific operation is I×W=O. The input neuron I, input weight W, and output neuron O can then be grouped as "first data," and their corresponding split index, target storage space, and target data exchange level can be determined.

[0213] Input neuron I's label information: Static: IN, float32, DIM_NC, {1 1024} dynamic: float16, DIM_NC, C = 256, C = 0, 2KB. That is, I's data type is input neuron, the static data type is float32, the static data dimensions are N and C, the dimension value of dimension N is 1, the dimension value of dimension C is 1024, and the static data dimension order is NC. The dynamic data type is float16, the dynamic data dimension order is NC, the slicing parameter is 256-bit slicing along dimension C, the padding parameter is padding along dimension C with "0" as the padding value, and the data size is 2KB.

[0214] The label information for the input weight W is as follows: Static: IW, float32, DIM_CN, {1000 4} Dynamic: float16, DIM_NC, C = 512, C = 24, 8000 bytes. That is, the data type of W is input weight, the static data type is float32, the static data dimensions are N and C, the dimension value of dimension N is 4, the dimension value of dimension C is 1000, and the static data dimension order is CN. The dynamic data type is float16, the dynamic data dimension order is NC, the slicing parameter is 512-bit slicing along dimension C, the padding parameter is 24-bit padding along dimension C, and the data size is 8000 bytes.

[0215] Output neuron O's label information: Static: ON, float32, DIM_NC, {1 4} dynamic: float16, DIM_NC, C = 4, C = 0, 8KB. That is, O's data type is output neuron, the static data type is float32, the static data dimensions are N and C, with dimension N being 1 and dimension C being 4, and the static data dimension order is NC. The dynamic data type is float16, the dynamic data dimension order is NC, the slicing parameter is slicing with a length of 4 in the direction of dimension C, the padding parameter is padding with "0" in the direction of dimension C, and the data size is 8KB.

[0216] In the Label Generation Step:

[0217] For input neuron I: Assume that, according to a pre-determined splitting strategy database, its splittable dimensions include N and C (N takes precedence over C). Since input neuron I is 1×1024, multi-core processor 1 has two channels. First, the splittable dimension N is determined. If the number of channels 2 is greater than the operational dimension of input neuron I on dimension N (see above for the determination method), then dimension N cannot be used as the target splitting dimension. Then, the splittable dimension C is determined. If the number of channels 2 is less than the operational dimension of input neuron I on dimension C, then dimension C is determined as the target splitting dimension. Furthermore, the split length is determined to be L = 1024 ÷ 4 (total number of computing cores) = 512. Therefore, the split index for input neuron I is C[(0, 255), (256, 511), (512, 767), (768, 1023)]. Continuing with the pre-determined split strategy database based on the target split dimension C, we know that the target storage space for input neuron I is "Mem" (i.e., memory), and the target data exchange level is "NO," meaning no exchange. The label information for input neuron I is then increased to: Static: IN, float32, DIM_NC, {1 1024} dynamic: float16, DIM_NC, C = 256, C = 0, 2KB, C [(0, 255), (256, 511), (512, 767), (768, 1023)], Mem, NO.

[0218] Based on the same process as the input neuron I, we can determine that the label information of the input weight W after addition is: Static:IW,float32,DIM_CN,{1000 4}dynamic:float16,DIM_NC,C=512,C=24,8000 bytes,N[(0,255),(256,511),(512,767),(768,1023)],Mem,NO. The label information of the output neuron O after addition is: Static:ON,float32,DIM_NC,{1 4}dynamic:float16,DIM_NC,C=4,C=0,8KB,C[(0,3)],Cluster,Core.

[0219] In the "Tag Usage Steps":

[0220] Based on the label information of the input neuron I, input weight W, and output neuron O, when the multi-core processor 1 executes the operation instruction A, Figure 6a FIG. 1 shows a schematic diagram of computing task allocation for a multi-core processor 1 executing a computing instruction A according to an embodiment of the present disclosure. Figure 6b、 6c A schematic diagram showing a process of executing an operation instruction A by a multi-core processor 1 according to an embodiment of the present disclosure is shown. Figure 6a 、 Figure 6b The specific process is as follows:

[0221] The multi-core processor 1 or the processor that assigns tasks to the multi-core processor 1 first determines whether the data state of the current input neuron I and input weight W is consistent with the corresponding dynamic label information based on the label information of the input neuron I and the input weight W. If it is inconsistent, it needs to be processed so that the data obtained after processing is consistent with the corresponding dynamic label information. Among them, taking the input weight W as an example, the processing process is shown in FIG. Figure 6a First, convert the data type of the input weight W from a 32-bit floating point number to a 16-bit floating point number. Then, transpose the input weight W so that its data dimension order matches "DIM_NC." Based on the slicing parameter "512," split the input weight W into two data slices. Then, using the padding parameter "24," fill any data slices whose sizes don't match the slicing parameter, for example, with zeros. Finally, the processed input weight W is obtained, i.e., a 4×1024 input weight W.

[0222] Then, according to the split index, the input neuron I and the input weight W are split as follows Figure 6a The split shown. Split the input neurons into i1, i2, i3, i4, and split the input weight W into w1, w2, w3, w4. And follow the Figure 6b As shown, i1, i2, w1, and w2 are stored in their corresponding target storage space memory 1, and i3, i4, w3, and w4 are stored in their corresponding target storage space memory 2.

[0223] Then, the computing tasks to be performed by each computing core in the specific computing process of the computing instruction A are:

[0224] Computing core 1 obtains i1 and w1 from memory 1 and calculates to obtain the first intermediate result o1, and then stores it in its corresponding local memory NB; computing core 2 obtains i2 and w2 from memory 1 and calculates to obtain the first intermediate result o2, and stores the first intermediate result o2 in the off-core cache 1; computing core 3 obtains i3 and w3 from memory 2 and calculates to obtain the first intermediate result o3, and then stores it in its corresponding local memory NB; computing core 4 obtains i4 and w4 from memory 2 and calculates to obtain the first intermediate result o4, and stores the first intermediate result o4 in the off-core cache 2.

[0225] Next, computing core 1 obtains o2 from off-core cache 1, adds o2 and o1 to obtain the second intermediate result o5, and then stores it in its corresponding local memory NB; computing core 3 obtains o4 from off-core cache 2, adds o4 and o3 to obtain the second intermediate result o6, and stores the second intermediate result o6 in off-core cache 2.

[0226] Afterwards, computing core 1 obtains o6 from the off-core cache 2, adds o5 and o6 to obtain the calculation result o7 (that is, output neuron O), and stores o7 into memory 1 to complete the calculation task.

[0227] Among them, since the target storage space of output neuron O is the off-core cache Cluster and the target data exchange level is the inter-core data exchange Core, computing cores 2 and 4 will store their calculated results o2 and o4 in the corresponding off-core caches, and computing core 3 will store its calculated results o6 in off-core cache 2. In this way, computing cores 1 and 3 can obtain the required first intermediate result or second intermediate result from the off-core cache.

[0228] Example 2

[0229] The difference between Example 2 and Example 1 is that the structure of the multi-core processor has changed, and the multi-core processor 2 in Example 2 does not have an off-core cache.

[0230] In the Label Generation Step:

[0231] Based on the same process as Example 1, combined with the splitting strategy database (not shown in this disclosure) corresponding to multi-core processor 2, it can be determined that only the target storage space and target data exchange level in the label information of output neuron O have changed, namely, Static:ON,float32,DIM_NC,{1 4}dynamic:float16,DIM_NC,C=4,C=0,8KB,C[(0,3)],Mem,Cluster. The difference from Example 1 is that the target storage space and target data exchange level of output neuron O have changed.

[0232] In the "Tag Usage Steps":

[0233] Combine Figure 6a 、 Figure 6c It can be seen that the specific process is different from Example 1 in that:

[0234] Computing core 1 obtains i1 and w1 from memory 1 and calculates to obtain the first intermediate result o1, and then stores it in its corresponding local memory NB; computing core 2 obtains i2 and w2 from memory 1 and calculates to obtain the first intermediate result o2, and stores the first intermediate result o2 in memory 1; computing core 3 obtains i3 and w3 from memory 2 and calculates to obtain the first intermediate result o3, and then stores it in its corresponding local memory NB; computing core 4 obtains i4 and w4 from memory 2 and calculates to obtain the first intermediate result o4, and stores the first intermediate result o4 in memory 2.

[0235] Next, computing core 1 obtains o2 from memory 1, adds o2 and o1 to obtain the second intermediate result o5, and then stores it in its corresponding local memory NB; computing core 3 obtains o4 from memory 2, adds o4 and o3 to obtain the second intermediate result o6, and stores the second intermediate result o6 in memory 2.

[0236] Afterwards, computing core 1 obtains o6 from memory 2, adds o5 and o6 to obtain the operation result o7 (that is, output neuron O), and stores o7 in memory 1 to complete the operation task.

[0237] Among them, since the target storage space of output neuron O is memory Mem and the target data exchange level is inter-cluster data exchange Cluster, computing cores 2 and 4 will store their calculated results o2 and o4 in corresponding memories 1 and 2 respectively, and computing core 3 will store its calculated results o6 in memory 2. In this way, computing cores 1 and 3 can obtain the required first intermediate result or second intermediate result from the memory.

[0238] It should be noted that although the data processing method is described above using the above embodiments as examples, those skilled in the art will appreciate that the present disclosure is not limited thereto. In fact, users can flexibly set the various steps and modules according to their personal preferences and / or actual application scenarios, as long as they comply with the technical solutions of the present disclosure.

[0239] Figure 7 FIG. 1 is a block diagram of a data processing device according to an embodiment of the present disclosure. Figure 7 As shown, the device is applied to a multi-core processor, the multi-core processor includes multiple computing core clusters, each computing core cluster includes multiple computing cores, and the device includes: an information acquisition module 51, a data splitting module 52 and a data storage module 53.

[0240] The information acquisition module 51 acquires first data and tag information of the first data, wherein the tag information includes dynamic tag information, and the dynamic tag information includes identification information of a split index and a target storage space.

[0241] The data splitting module 52 splits the first data into multiple second data according to the splitting index.

[0242] The data storage module 53 stores the plurality of second data in the corresponding target storage space according to the identification information of the target storage space.

[0243] The dynamic tag information is used to represent information associated with the first data and the multi-core processor.

[0244] In a possible implementation, the dynamic tag information further includes a target data exchange level, and the apparatus may further include:

[0245] An instruction generation module generates a first instruction for neural network operation corresponding to the first data based on the parallel computing mode of the multi-core processor, the identification information of the target storage space, and the target data exchange level, so that each computing core performs a corresponding computing task according to the first instruction; wherein the first instruction includes at least one of the following: a data access instruction and a data operation instruction.

[0246] In a possible implementation, the dynamic tag information further includes a target data exchange level, and the apparatus may further include:

[0247] The computing task determination module determines the computing task that each computing core needs to perform based on the second instruction corresponding to the first data, the parallel computing mode of the multi-core processor, the identification information of the target storage space, and the target data exchange level.

[0248] In one possible implementation, when the first data includes input neurons, input weights, and output neurons, and data exchange for the output neurons is determined based on dynamic label information of the first data, the computing tasks performed by the computing core may include:

[0249] Each computing core is used to obtain first target data from a plurality of second data of input neurons and second target data from a plurality of second data of input weights, perform operations on the first target data and the second target data to obtain a first intermediate result, and store the first intermediate result in a storage space corresponding to the computing core;

[0250] A first computing core among the multiple computing cores obtains at least two first intermediate results, performs computation on the at least two first intermediate results to obtain a second intermediate result, and stores the second intermediate result in a storage space corresponding to the first computing core;

[0251] A second computing core among the multiple computing cores obtains at least two second intermediate results, performs operations on the at least two second intermediate results to obtain operation results, and stores the operation results as the output neuron in the target storage space.

[0252] In one possible implementation, when the first data includes input neurons, input weights, and output neurons, and data exchange of the input weights is determined based on dynamic tag information of the first data, the computing tasks performed by the computing core may include:

[0253] Each computing core is used to obtain first target data from a plurality of second data of input neurons and second target data from a plurality of second data of input weights, perform operations on the first target data and the second target data to obtain a first intermediate result, and store the first intermediate result in a corresponding target storage space;

[0254] Each computing core is used to obtain first target data from a plurality of second data of input neurons and third target data different from the second target data from a plurality of second data of input weights, and to store a second first intermediate result obtained after operating the first target data and the third target data in a corresponding target storage space;

[0255] A first computing core among the multiple computing cores obtains at least two first intermediate results, performs computation on the at least two first intermediate results to obtain a second intermediate result, and stores the second intermediate result in a corresponding target storage space, wherein the first intermediate results include the first type of first intermediate results and the second type of first intermediate results;

[0256] The second computing core among the multiple computing cores obtains at least two second intermediate results, performs operations on the at least two second intermediate results to obtain operation results, and stores the operation results as the output neuron in the target storage space.

[0257] In one possible implementation, when the first data includes an input neuron, an input weight, and an output neuron, and data exchange between the input neuron and the output neuron is determined based on dynamic label information of the first data, the computing tasks performed by the computing core may include:

[0258] Each computing core is used to obtain first target data from a plurality of second data of input neurons and second target data from a plurality of second data of input weights, and to obtain a first intermediate result after performing an operation on the first target data and the second target data, and to store the first intermediate result in a storage space corresponding to the computing core;

[0259] Each computing core is configured to obtain fourth target data and the second target data different from the first target data from the plurality of second data input to the neuron, perform operations on the fourth target data and the second target data to obtain a second first intermediate result, and store the second first intermediate result in a storage space corresponding to the computing core;

[0260] A first computing core among the multiple computing cores obtains at least two first intermediate results, performs computation on the at least two first intermediate results to obtain a second intermediate result, and stores the second intermediate result in a storage space corresponding to the first computing core, where the first intermediate results include the first type of first intermediate results and the second type of first intermediate results;

[0261] The second computing core among the multiple computing cores obtains at least two second intermediate results, performs operations on the at least two second intermediate results to obtain operation results, and stores the operation results as the output neuron in the target storage space.

[0262] In a possible implementation, the dynamic tag information further includes a dynamic data type, a dynamic data dimension order, a sharding parameter, and a padding parameter. The split index includes a target split dimension, a starting split position and an ending split position of each second data on the target split dimension of the first data. The data splitting module 52 may include:

[0263] a data processing submodule, which, when determining that the current data state of the first data is inconsistent with the dynamic tag information, processes the first data according to the dynamic tag information to obtain processed first data;

[0264] a splitting submodule, which splits the processed first data into a plurality of second data on the target splitting dimension, based on the starting splitting position and the ending splitting position of each second data on the target splitting dimension of the first data,

[0265] The data state includes the data type, the order of data dimensions and the dimension values.

[0266] In a possible implementation, the label information may further include static label information, where the static label information is used to represent information associated with the neural network operation in which the first data participates. The static label information may include at least one of the following: a static data type, a static data dimension, a static data dimension order, and a dimension value corresponding to each static data dimension.

[0267] The processing performed by the data processing submodule may include at least one of the following:

[0268] Converting the data type of the first data from the static data type to the dynamic data type;

[0269] Adjusting the order of data dimensions of the first data from a static data dimension order to a dynamic data dimension order;

[0270] Filling the first data according to the filling parameter;

[0271] The first data is segmented according to the segmentation parameters.

[0272] In a possible implementation manner, when the first data includes a plurality of constant data, the apparatus further includes:

[0273] a data packaging module, which packages the plurality of second data obtained by splitting each constant data according to the total number of computing cores in the multi-core processor, forms a plurality of first data packets corresponding to each computing core, and stores the first data packets therein, so that each computing core performs a corresponding operation according to the loaded first data packets; the number of the first data packets is the same as the total number of computing cores;

[0274] Among them, the first data packet includes one of the multiple second data obtained by splitting each constant data, and the first data packet also includes at least one of the following items: a constant total data amount mark, a hidden layer total data amount mark of the hidden layer in the neural network operation in which the first data participates, and an input and output address mark in the neural network operation.

[0275] In a possible implementation, the data packaging module is further configured to perform at least one of the following operations:

[0276] Determine, based on the constant total data volume of each first data packet and the data volume of each second data contained therein, the offset of each second data within the first segment of the constant data segment of the corresponding first data packet and record the offset;

[0277] Determine and record the offset of each input address and each output address within the second segment of the address data segment of the corresponding first data packet based on the total data volume of the input and output addresses of each first data packet, the data volume of each input address, and the data volume of each output address contained therein;

[0278] According to the total amount of hidden layer data in each first data packet and the amount of each hidden layer data contained therein, the offset of each hidden layer data in the third segment of the hidden layer data segment of the corresponding first data packet is determined and recorded.

[0279] In a possible implementation, the apparatus further includes:

[0280] The label determination module determines a splitting index, a target storage space, and a target data exchange level of the first data before splitting the first data.

[0281] The device provided by the embodiment of the present disclosure can, after determining the first data and its dynamic label, split and layout the first data based on the split index in the dynamic label information and the identification information of the target storage space, so that the second data can adapt to multiple memory channels of the multi-core processor, so as to utilize the multiple computing cores in the multi-core processor to perform computing operations, thereby improving the processing efficiency and speed of neural network operations.

[0282] An embodiment of the present disclosure further provides a data processing device, which includes a processor and a memory, wherein a computer program is stored in the memory, and when the processor executes the computer program, the data processing method as described above is implemented.

[0283] The embodiment of the present disclosure further provides a non-volatile computer-readable storage medium having computer program instructions stored thereon, wherein the computer program instructions implement the above-mentioned data processing method when executed by a processor.

[0284] The present disclosure provides a machine learning computing device, which may include one or more of the above-mentioned data processing devices, for obtaining data to be calculated and control information from other processing devices, and performing specified machine learning operations. The machine learning computing device can obtain neural network computing macro instructions or neural network computing instructions to be executed from other machine learning computing devices or non-machine learning computing devices, and pass the execution results to peripheral devices (also referred to as other processing devices) through an I / O interface. Peripheral devices include cameras, displays, mice, keyboards, network cards, wifi interfaces, and servers. When more than one data processing device is included, the data processing devices can be linked and data can be transmitted through a specific structure, for example, interconnected and data can be transmitted through a PCIE bus to support larger-scale neural network operations. At this time, the same control system can be shared, or each independent control system can be provided; memory can be shared, or each accelerator can have its own memory. In addition, the interconnection method can be any interconnection topology.

[0285] The machine learning computing device has high compatibility and can be connected to various types of servers through the PCIE interface.

[0286] Figure 8 FIG. 1 is a structural diagram showing a combined processing device 1200 according to an embodiment of the present disclosure. Figure 8As shown in , the combined processing device 1200 includes a computing device 1202, an interface device 1204, other processing devices 1206, and a storage device 1208. Depending on different application scenarios, the computing device may include one or more computing devices 1210. The computing device 1202 may be the aforementioned machine learning computing device or the aforementioned data processing device.

[0287] In various embodiments, the computing and processing device of the present disclosure may be configured to execute user-specified operations. In exemplary applications, the computing and processing device may be implemented as a multi-core artificial intelligence processor. Similarly, one or more computing devices included in the computing and processing device may be implemented as an artificial intelligence computing core (i.e., the computing core described above) or as part of the hardware structure of an artificial intelligence computing core.

[0288] In exemplary operation, the computing processing device of the present invention can interact with other processing devices through an interface device to jointly complete the operation specified by the user. Depending on the implementation, other processing devices of the present invention may include one or more types of processors in general and / or special processors such as a central processing unit (CPU), a graphics processing unit (GPU), an artificial intelligence processor, etc. These processors may include but are not limited to a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As previously mentioned, only with respect to the computing processing device of the present invention, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing processing device and other processing devices are considered together, the two can be regarded as forming a heterogeneous multi-core structure.

[0289] In one or more embodiments, the other processing device may serve as an interface between the computing device of the present disclosure (which may be embodied as an artificial intelligence computing device such as a neural network computing device) and external data and control, performing basic control including but not limited to data transfer, starting and / or stopping the computing device, and so on. In other embodiments, the other processing device may also collaborate with the computing device to jointly complete computing tasks.

[0290] In one or more embodiments, the interface device can be used to transmit data and control instructions between the computing and processing device and other processing devices. For example, the computing and processing device can obtain input data from other processing devices via the interface device and write it to the storage device (or memory) on the computing and processing device chip. Furthermore, the computing and processing device can obtain control instructions from other processing devices via the interface device and write them to the control cache on the computing and processing device chip. Alternatively or optionally, the interface device can also read data from the storage device of the computing and processing device and transmit it to other processing devices.

[0291] Additionally or optionally, the combined processing device of the present disclosure may further include a storage device. As shown in the figure, the storage device is connected to the computing processing device and the other processing device, respectively. In one or more embodiments, the storage device may be used to store data of the computing processing device and / or the other processing device. For example, the data may be data that cannot be fully stored in the internal or on-chip storage device of the computing processing device or other processing device.

[0292] In some embodiments, the present disclosure further discloses a chip (e.g. Figure 9 In one implementation, the chip is a system on chip (SoC) and integrates one or more components such as Figure 8 The chip can be connected to the external interface device (such as Figure 9 The external interface device 1306 shown in the figure is connected to other related components. The related components can be, for example, a camera, a display, a mouse, a keyboard, a network card or a wifi interface. In some application scenarios, other processing units (such as video codecs) and / or interface modules (such as DRAM interfaces) can be integrated on the chip. In some embodiments, the present disclosure also discloses a chip packaging structure, which includes the above-mentioned chip. In some embodiments, the present disclosure also discloses a board card, which includes the above-mentioned chip packaging structure. The following will be combined with Figure 9 The board is described in detail.

[0293] Figure 9 FIG. 1 is a schematic diagram showing the structure of a board 1300 according to an embodiment of the present disclosure. Figure 9As shown in , the board includes a storage device 1304 for storing data, which includes one or more storage units 1310. The storage device can be connected and data can be transmitted with the control device 1308 and the chip 1302 described above by means of, for example, a bus. Furthermore, the board also includes an external interface device 1306, which is configured for data relay or transfer function between the chip (or the chip in the chip packaging structure) and the external device 1312 (such as a server or computer, etc.). For example, the data to be processed can be passed from the external device to the chip through the external interface device. For another example, the calculation result of the chip can be transmitted back to the external device via the external interface device. According to different application scenarios, the external interface device can have different interface forms, for example, it can adopt a standard PCIE interface, etc.

[0294] In one or more embodiments, the control device in the disclosed board can be configured to regulate the state of the chip. To this end, in one application scenario, the control device can include a microcontroller unit (MCU) for regulating the working state of the chip.

[0295] According to the above combination Figure 8 and Figure 9 Based on the description, those skilled in the art can understand that the present disclosure also discloses an electronic device or apparatus, which may include one or more of the above-mentioned boards, one or more of the above-mentioned chips and / or one or more of the above-mentioned combined processing devices.

[0296] According to different application scenarios, the electronic equipment or devices disclosed herein may include servers, cloud servers, server clusters, data processing devices, robots, computers, printers, scanners, tablet computers, smart terminals, PC devices, Internet of Things terminals, mobile terminals, mobile phones, driving recorders, navigators, sensors, cameras, cameras, video cameras, projectors, watches, headphones, mobile storage, wearable devices, visual terminals, automatic driving terminals, vehicles, household appliances, and / or medical equipment. The vehicles include airplanes, ships and / or vehicles; the household appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, electric lights, gas stoves, and range hoods; the medical equipment includes magnetic resonance imaging (MRI), ultrasound machines and / or electrocardiographs. The electronic equipment or devices disclosed herein may also be applied to the Internet, Internet of Things, data centers, energy, transportation, public administration, manufacturing, education, power grids, telecommunications, finance, retail, construction sites, medical care and other fields. Furthermore, the electronic equipment or devices disclosed herein may also be used in application scenarios related to artificial intelligence, big data and / or cloud computing, such as the cloud, edge, and terminal. In one or more embodiments, electronic devices or apparatuses with high computing power according to the disclosed solution can be applied to cloud devices (such as cloud servers), while electronic devices or apparatuses with low power consumption can be applied to terminal devices and / or edge devices (such as smartphones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0297] It should be noted that, for the purpose of simplicity, the present disclosure describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will understand that the scheme of the present disclosure is not limited by the order of the actions described. Therefore, based on the disclosure or teachings of the present disclosure, those skilled in the art will understand that some of the steps therein can be performed in other orders or simultaneously. Further, those skilled in the art will understand that the embodiments described in the present disclosure can be regarded as optional embodiments, that is, the actions or modules involved therein are not necessarily necessary for the implementation of one or more schemes of the present disclosure. In addition, depending on the different schemes, the present disclosure also has different emphases on the description of some embodiments. In view of this, those skilled in the art will understand that the parts that are not described in detail in a certain embodiment of the present disclosure may also refer to the relevant descriptions of other embodiments.

[0298] In terms of specific implementation, based on the disclosure and teachings of this disclosure, those skilled in the art can understand that several embodiments disclosed in this disclosure can also be implemented in other ways not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this document divides them based on the consideration of logical functions, and there may be other ways of division in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in a unit or component can be selectively disabled. With respect to the connection relationship between different units or components, the connection discussed above in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0299] In the present disclosure, the units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units. The aforementioned components or units may be located in the same location or distributed across multiple network elements. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the solutions described in the embodiments of the present disclosure. In addition, in some scenarios, multiple units in the embodiments of the present disclosure may be integrated into one unit or each unit may exist physically separately.

[0300] In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the solution of the present disclosure is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present disclosure. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0301] In some other implementation scenarios, the above-mentioned integrated unit can also be implemented in the form of hardware, that is, a specific hardware circuit, which may include digital circuits and / or analog circuits, etc. The physical implementation of the hardware structure of the circuit may include but is not limited to physical devices, and the physical devices may include but are not limited to devices such as transistors or memristors. In view of this, the various devices described herein (such as computing devices or other processing devices) can be implemented by appropriate hardware processors, such as CPUs, GPUs, FPGAs, DSPs, and ASICs. Furthermore, the aforementioned storage unit or storage device can be any appropriate storage medium (including magnetic storage media or magneto-optical storage media, etc.), which can be, for example, resistive random access memory (RRAM), dynamic random access memory (DRAM), static random access memory (SRAM), enhanced dynamic random access memory (EDRAM), high bandwidth memory (HBM), hybrid memory cube (HMC), ROM and RAM, etc.

[0302] While various embodiments of the present disclosure have been described above, the foregoing description is intended to be illustrative, non-exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or technical improvements to existing technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A data processing method, characterized in that: Applied to a multi-core processor, the multi-core processor includes multiple computing core clusters, each computing core cluster includes multiple computing cores, the method includes: Acquire first data and tag information of the first data, wherein the tag information includes dynamic tag information, and the dynamic tag information includes identification information of a split index and a target storage space; Splitting the first data into a plurality of second data according to the splitting index; According to the identification information of the target storage space, the plurality of second data are stored in the corresponding target storage space respectively, Among them, the dynamic tag information is used to characterize the information associated with the first data and the multi-core processor, and the split index is determined based on the parameters of the operator corresponding to the operation in which the first data participates, the number of memory channels in the multi-core processor, static tag information, dynamic data type, dynamic data dimension order, sharding parameters and filling parameters. The static tag information includes at least one of the following: static data type, static data dimension, static data dimension order and dimension value corresponding to each static data dimension.

2. The method according to claim 1, characterized in that The dynamic tag information also includes a target data exchange level, and the method further includes: generating, based on the parallel computing mode of the multi-core processor, the identification information of the target storage space, and the target data exchange level, a first instruction for neural network computing corresponding to the first data, so that each computing core performs a corresponding computing task according to the first instruction; The first instruction includes at least one of the following: a data access instruction and a data operation instruction.

3. The method according to claim 1, characterized in that The dynamic tag information also includes a target data exchange level, and the method further includes: The computing task that each computing core needs to perform is determined based on the second instruction corresponding to the first data, the parallel computing mode of the multi-core processor, the identification information of the target storage space, and the target data exchange level.

4. The method according to claim 2 or 3, characterized in that When the first data includes input neurons, input weights, and output neurons, and data exchange for the output neurons is determined based on dynamic label information of the first data, the computing tasks performed by the computing core include: Each computing core is used to obtain first target data from a plurality of second data of input neurons and second target data from a plurality of second data of input weights, perform operations on the first target data and the second target data to obtain a first intermediate result, and store the first intermediate result in a storage space corresponding to the computing core; A first computing core among the multiple computing cores obtains at least two first intermediate results, performs computation on the at least two first intermediate results to obtain a second intermediate result, and stores the second intermediate result in a storage space corresponding to the first computing core; A second computing core among the multiple computing cores obtains at least two second intermediate results, performs operations on the at least two second intermediate results to obtain operation results, and stores the operation results as the output neuron in the target storage space.

5. The method according to claim 2 or 3, characterized in that When the first data includes input neurons, input weights, and output neurons, and data exchange for the input weights is determined based on dynamic label information of the first data, the computing tasks performed by the computing core include: Each computing core is used to obtain first target data from a plurality of second data of input neurons and second target data from a plurality of second data of input weights, perform operations on the first target data and the second target data to obtain a first intermediate result, and store the first intermediate result in a corresponding target storage space; Each computing core is used to obtain first target data from a plurality of second data of input neurons and third target data different from the second target data from a plurality of second data of input weights, and to store a second first intermediate result obtained after operating the first target data and the third target data in a corresponding target storage space; A first computing core among the multiple computing cores obtains at least two first intermediate results, performs computation on the at least two first intermediate results to obtain a second intermediate result, and stores the second intermediate result in a corresponding target storage space, wherein the first intermediate results include the first type of first intermediate results and the second type of first intermediate results; A second computing core among the multiple computing cores obtains at least two second intermediate results, performs operations on the at least two second intermediate results to obtain operation results, and stores the operation results as the output neuron in the target storage space.

6. The method according to claim 2 or 3, characterized in that When the first data includes an input neuron, an input weight, and an output neuron, and data exchange between the input neuron and the output neuron is determined based on dynamic label information of the first data, the computing tasks performed by the computing core include: Each computing core is used to obtain first target data from a plurality of second data of input neurons and second target data from a plurality of second data of input weights, and to obtain a first intermediate result after performing an operation on the first target data and the second target data, and to store the first intermediate result in a storage space corresponding to the computing core; Each computing core is configured to obtain fourth target data and the second target data different from the first target data from the plurality of second data input to the neuron, perform operations on the fourth target data and the second target data to obtain a second first intermediate result, and store the second first intermediate result in a storage space corresponding to the computing core; A first computing core among the multiple computing cores obtains at least two first intermediate results, performs computation on the at least two first intermediate results to obtain a second intermediate result, and stores the second intermediate result in a storage space corresponding to the first computing core, where the first intermediate results include the first type of first intermediate results and the second type of first intermediate results; A second computing core among the multiple computing cores obtains at least two second intermediate results, performs operations on the at least two second intermediate results to obtain operation results, and stores the operation results as the output neuron in the target storage space.

7. The method according to claim 1, characterized in that The dynamic tag information also includes dynamic data type, dynamic data dimension order, sharding parameters, and padding parameters. The split index includes: target split dimension, the starting split position and the ending split position of each second data on the target split dimension of the first data. The step of splitting the first data into a plurality of second data according to the split index includes: When it is determined that the current data state of the first data is inconsistent with the dynamic tag information, processing the first data according to the dynamic tag information to obtain processed first data; On the target splitting dimension, the processed first data is split into a plurality of second data based on the starting splitting position and the ending splitting position of each second data on the target splitting dimension of the first data, The data state includes the data type, the order of data dimensions and the dimension value.

8. The method according to claim 7, characterized in that The label information also includes static label information, and the static label information is used to represent information associated with the neural network operation in which the first data participates. When it is determined that the current data state of the first data is inconsistent with the dynamic tag information, the first data is processed according to the dynamic tag information to obtain processed first data, including at least one of the following: Converting the data type of the first data from the static data type to the dynamic data type; Adjusting the order of data dimensions of the first data from a static data dimension order to a dynamic data dimension order; Filling the first data according to the filling parameter; The first data is segmented according to the segmentation parameters.

9. The method according to claim 1, characterized in that When the first data includes a plurality of constant data, the method further includes: According to the total number of computing cores in the multi-core processor, the plurality of second data obtained by splitting each constant data is packaged to form a plurality of first data packets corresponding to each computing core and then stored, so that each computing core performs a corresponding operation according to the loaded first data packets; the number of the first data packets is the same as the total number of computing cores; Among them, the first data packet includes one of the multiple second data obtained by splitting each constant data, and the first data packet also includes at least one of the following items: a constant total data amount mark, a hidden layer total data amount mark of the hidden layer in the neural network operation in which the first data participates, and an input and output address mark in the neural network operation.

10. The method according to claim 9, characterized in that The method further includes at least one of the following operations: Determine, based on the constant total data volume of each first data packet and the data volume of each second data contained therein, the offset of each second data within the first segment of the constant data segment of the corresponding first data packet and record the offset; Determine and record the offset of each input address and each output address within the second segment of the address data segment of the corresponding first data packet based on the total data volume of the input and output addresses of each first data packet, the data volume of each input address, and the data volume of each output address contained therein; According to the total amount of hidden layer data in each first data packet and the amount of each hidden layer data contained therein, the offset of each hidden layer data in the third segment of the hidden layer data segment of the corresponding first data packet is determined and recorded.

11. The method according to claim 1, wherein The method further comprises: Before splitting the first data, a splitting index, a target storage space, and a target data exchange level of the first data are determined.

12. A non-volatile computer-readable storage medium, characterized in that: Computer program instructions are stored thereon, and it is characterized in that when the computer program instructions are executed by a processor, the data processing method according to any one of claims 1 to 11 is implemented.

13. A data processing device, characterized in that: The device includes a processor and a memory, wherein a computer program is stored in the memory, and when the processor executes the computer program, the method according to any one of claims 1 to 11 is implemented.

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