Fine-tuning of programming of analog neural memories in deep learning artificial neural networks

Abstract

The present disclosure relates to the precise tuning of programming of analog neural memories in deep learning artificial neural networks. The present disclosure relates to a method of reading a selected non-volatile memory cell storing one of N possible values. The invention discloses multiple embodiments of precise tuning algorithms and apparatus for precisely and rapidly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-matrix multiplication (VMM) array in an artificial neural network. Thus, the selected cell can be programmed with extreme precision to hold one of N different values.

Description

[0001] This application is a divisional application of a patent application with an international application date of July 25, 2019, an international application number of PCT / US2019 / 043524, a Chinese national application date of July 25, 2019, an application number of 201980068251.4, and an invention name of “Precise tuning of programming of analog neural memories in deep learning artificial neural networks”.

[0002] Priority Declaration

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 746,470, filed on October 16, 2018, entitled “Precision Tuning For the Programming Of Analog Neural Memory In A Deep Learning Artificial Neural Network,” and U.S. Patent Application No. 16 / 231,231, filed on December 21, 2018, entitled “Precision Tuning For the Programming Of Analog Neural Memory In A Deep Learning Artificial Neural Network.” Technical Field

[0004] The present invention discloses various embodiments of precision-tuned algorithms and apparatus for accurately and rapidly depositing the correct amount of charge on the floating gates of nonvolatile memory cells within vector-matrix multiplication (VMM) arrays in artificial neural networks. Background Art

[0005] Artificial neural networks simulate biological neural networks (the central nervous system of animals, especially the brain) and are used to estimate or approximate functions that may depend on a large number of inputs and are generally unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0006] Figure 1 An artificial neural network is shown, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the input and learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on the data received from the synapses, either individually or collectively.

[0007] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, that is, very high computational parallelism. In principle, such complexity can be achieved using digital supercomputers or clusters of dedicated graphics processing units. However, in addition to being high-cost, these approaches are also mediocre in energy efficiency compared to biological networks, which consume less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used in artificial neural networks, but given the large number of neurons and synapses, the synapses of most CMOS implementations are too large.

[0008] Applicant previously disclosed an artificial (simulated) neural network utilizing one or more nonvolatile memory arrays as synapses in U.S. patent application Ser. No. 15 / 594,439, which is incorporated herein by reference. The nonvolatile memory array operates as a simulated neuromorphic memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a source region and a drain region spaced apart formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed over and insulated from a first portion of the channel region; and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells is configured to multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs.

[0009] Each nonvolatile memory cell used in an analog neuromorphic memory system must be erased and programmed to maintain a very specific and precise amount of charge (i.e., number of electrons) in the floating gate. For example, each floating gate must maintain one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0010] One challenge in a VMM system is being able to program a selected cell with the precision and granularity required for different values ​​of N. For example, if a selected cell can contain one of 64 different values, extreme precision is required in the programming operation.

[0011] What are needed are improved programming systems and methods suitable for use with a VMM in an emulated neuromorphic memory system. Summary of the Invention

[0012] The present invention discloses various embodiments of a precision-tuned algorithm and apparatus for accurately and rapidly depositing the correct amount of charge on the floating gates of nonvolatile memory cells within a vector-matrix multiplication (VMM) array in an artificial neural network. Thus, a selected cell can be very accurately programmed to hold one of N different values. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram showing an artificial neural network.

[0014] Figure 2 A prior art split-gate flash memory cell is shown.

[0015] Figure 3 Another prior art split-gate flash memory cell is shown.

[0016] Figure 4 Another prior art split-gate flash memory cell is shown.

[0017] Figure 5 Another prior art split-gate flash memory cell is shown.

[0018] Figure 6 A schematic diagram illustrating different stages of an exemplary artificial neural network utilizing one or more non-volatile memory arrays.

[0019] Figure 7 is a block diagram showing a vector-matrix multiplication system.

[0020] Figure 8 is a block diagram illustrating an exemplary artificial neural network utilizing one or more vector-matrix multiplication systems.

[0021] Figure 9 Another embodiment of a vector-matrix multiplication system is shown.

[0022] Figure 10 Another embodiment of a vector-matrix multiplication system is shown.

[0023] Figure 11 Another embodiment of a vector-matrix multiplication system is shown.

[0024] Figure 12 Another embodiment of a vector-matrix multiplication system is shown.

[0025] Figure 13 Another embodiment of a vector-matrix multiplication system is shown.

[0026] Figure 14 A prior art long short-term memory system is shown.

[0027] Figure 15An exemplary cell for use in a long short-term memory system is shown.

[0028] Figure 16 Shown Figure 15 An embodiment of an exemplary unit of .

[0029] Figure 17 Shown Figure 15 Another embodiment of an exemplary unit of .

[0030] Figure 18 A prior art gate-controlled recursive cell system is shown.

[0031] Figure 19 An exemplary cell for use in a gate-controlled recursive cell system is shown.

[0032] Figure 20 Shown Figure 19 An embodiment of an exemplary unit of .

[0033] Figure 21 Shown Figure 19 Another embodiment of an exemplary unit of .

[0034] Figure 22A An embodiment of a method of programming a non-volatile memory cell is shown.

[0035] Figure 22B Another embodiment of a method of programming a non-volatile memory cell is shown.

[0036] Figure 23 One embodiment of a coarse programming method is shown.

[0037] Figure 24 Exemplary pulses used in programming of nonvolatile memory cells are shown.

[0038] Figure 25 Exemplary pulses used in programming of nonvolatile memory cells are shown.

[0039] Figure 26 A calibration algorithm for programming a non-volatile memory cell is shown that adjusts programming parameters based on the slope characteristics of the cell.

[0040] Figure 27 Shown in Figure 26 The circuit used in the calibration algorithm.

[0041] Figure 28 A calibration algorithm for programming non-volatile memory cells is shown.

[0042] Figure 29 Shown in Figure 28 The circuit used in the calibration algorithm.

[0043] Figure 30 An exemplary progression of voltages applied to the control gates of nonvolatile memory cells during a programming operation is shown.

[0044] Figure 31 An exemplary progression of voltages applied to the control gates of nonvolatile memory cells during a programming operation is shown.

[0045] Figure 32 A system for applying programming voltages during programming of non-volatile memory cells within a vector-multiplication matrix system is shown.

[0046] Figure 33 A charge summer circuit is shown.

[0047] Figure 34 A current summer circuit is shown.

[0048] Figure 35 A digital summer circuit is shown.

[0049] Figure 36A One implementation of an integrating analog-to-digital converter for neuron output is shown.

[0050] Figure 36B Shown Shown Figure 36A A graph showing the voltage output of an integrating analog-to-digital converter changing with time.

[0051] Figure 36C Another embodiment of an integrating analog-to-digital converter for neuron output is shown.

[0052] Figure 36D Shown Shown Figure 36C A graph showing the voltage output of an integrating analog-to-digital converter changing with time.

[0053] Figure 36E Another embodiment of an integrating analog-to-digital converter for neuron output is shown.

[0054] Figure 36F Another embodiment of an integrating analog-to-digital converter for neuron output is shown.

[0055] Figure 37A and 37B A successive approximation analog-to-digital converter of the neuron output is shown.

[0056] Figure 38 One embodiment of a Σ-Δ type analog-to-digital converter is shown. DETAILED DESCRIPTION

[0057] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays.

[0058] Non-volatile memory cells

[0059] Digital non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​("the '130 patent"), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which is a type of flash memory cell. Such a memory cell 210 is Figure 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls its electrical conductivity), and is formed over a portion of the source region 14. A wordline terminal 22 (which is typically coupled to a wordline) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls its electrical conductivity), and a second portion extending upward and over the floating gate 20. The floating gate 20 and wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0060] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on wordline terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim tunneling from floating gate 20 to wordline terminal 22.

[0061] Memory cell 210 is programmed by placing a positive voltage on wordline terminal 22 and a positive voltage on source region 14 (where electrons are placed on the floating gate). Electron current will flow from source region 14 to drain region 16. When the electrons reach the gap between wordline terminal 22 and floating gate 20, they will accelerate and become heated. Due to the electrostatic attraction from floating gate 20, some of the heated electrons will be injected through the gate oxide onto floating gate 20.

[0062] Memory cell 210 is read by placing a positive read voltage across drain region 16 and wordline terminal 22 (which turns on the portion of channel region 18 below the wordline terminal). If floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below floating gate 20 is also turned on, and current will flow through channel region 18, which is sensed as an erased state or a "1" state. If floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below floating gate 20 is mostly or completely turned off, and no current (or very little current) will flow through channel region 18, which is sensed as a programmed state or a "0" state.

[0063] Table 1 shows typical voltage ranges that may be applied to the terminals of the memory cell 110 for performing read, erase, and program operations:

[0064] Table 1: Figure 3 Operation of the flash memory unit 210

[0065] WL BL SL Read 2-3V 0.6-2V 0V Erase About 11-13V 0V 0V programming 1-2V 1-3μA 9-10V

[0066] Other split gate memory cell configurations are known as other types of flash memory cells. For example, Figure 3 A quad-gate memory cell 310 is shown, comprising a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating, meaning they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0067] Table 2 shows typical voltage ranges that may be applied to the terminals of the memory cell 310 for performing read, erase, and program operations:

[0068] Table 2: Figure 3 Operation of the flash memory unit 310

[0069] WL / SG BL CG EG SL Read 1.0-2V 0.6-2V 0-2.6V 0-2.6V 0V Erase -0.5V / 0V 0V 0V / -8V 8-12V 0V programming 1V 1μA 8-11V 4.5-9V 4.5-5V

[0070] Figure 4 A tri-gate memory cell 410 is shown, which is another type of flash memory cell. Figure 3 The memory cell 310 is identical to the memory cell 410, except that the memory cell 410 does not have a separate control gate. Except that no control gate bias is applied, the erase operation (thus erasing by using the erase gate) and the read operation are similar to Figure 3 The programming operation is also completed without control gate bias, and as a result, a higher voltage must be applied on the source line during the programming operation to compensate for the lack of control gate bias.

[0071] Table 3 shows typical voltage ranges that may be applied to the terminals of the memory cell 410 for performing read, erase, and program operations:

[0072] Table 3: Figure 4 Operation of the flash memory unit 410

[0073] WL / SG BL EG SL Read 0.7-2.2V 0.6-2V 0-2.6V 0V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 2-3μA 4.5V 7-9V

[0074] Figure 5 5 shows a stacked gate memory cell 510, which is another type of flash memory cell. The memory cell 510 is similar to Figure 2 Memory cell 210 is shown, except that floating gate 20 extends over the entire channel region 18, and control gate 22 (which here will be connected to the word line) extends over floating gate 20, separated by an insulating layer (not shown). Erase, program, and read operations operate in a similar manner as previously described for memory cell 210.

[0075] Table 4 shows typical voltage ranges that may be applied to the terminals of the memory cell 510 and substrate 12 for performing read, erase, and program operations:

[0076] Table 4: Figure 5 Operation of the flash memory unit 510

[0077] CG BL SL substrate Read 2-5V 0.6–2V 0V 0V Erase -8 to -10V / 0V FLT FLT 8-10V / 15-20V programming 8-12V 3-5V 0V 0V

[0078] In order to utilize a memory array comprising one of the above-described types of nonvolatile memory cells in an artificial neural network, two modifications were made. First, the circuitry was configured so that each memory cell could be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as explained further below. Second, continuous (analog) programming of the memory cells was provided.

[0079] Specifically, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage device is analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all cells in the memory array, and makes the memory array ideal for storing and fine-tuning the synaptic weights of neural networks.

[0080] Neural Networks Using Nonvolatile Memory Cell Arrays

[0081] Figure 6 A non-limiting example of a neural network utilizing a non-volatile memory array according to the present embodiment is conceptually illustrated. This example uses the non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a non-volatile memory array-based neural network.

[0082] For this example, S0 is the input layer, which is a 32×32 pixel RGB image with 5 bits of precision (i.e., three 32×32 pixel arrays, one for each color R, G, and B, with 5 bits of precision per pixel). Synapse CB1 from input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in other cases, and scans the input image with a 3×3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, the values ​​of 9 pixels in the 3×3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights, and after summing the outputs of this multiplication, a single output value is determined and provided by the first synapse of CB1 for use in generating a feature map for one of the pixels of layer C1. The 3×3 filter is then shifted one pixel to the right within the input layer S0 (i.e., a column of three pixels on the right is added and a column of three pixels on the left is released), whereby the nine pixel values ​​in this newly positioned filter are provided to the synapse CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3×3 filter has scanned all three colors and all bits (precision values) across the entire 32×32 pixel image of the input layer S0. This process is then repeated using different sets of weights to generate different feature maps for C1 until all feature maps for layer C1 are calculated.

[0083] At layer C1, in this example, there are 16 feature maps, each with 30×30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, layer C1 is composed of a two-dimensional array of 16 layers (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships, that is, arrays do not have to be oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as edge recognition. For example, a first map (generated using a first set of weights, shared for all scans used to generate the first map) can identify circular edges, a second map (generated using a second set of weights different from the first) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0084] Before passing from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2×2 regions in each feature map. The purpose of the pooling function is to average the values ​​of adjacent positions (or a max function can also be used) to, for example, reduce dependencies on edge positions and reduce the size of the data before entering the next stage. At layer S1, there are 16 15×15 feature maps (i.e., sixteen different arrays of 15×15 pixels each). The synapse CB2 from layer S1 to layer C2 scans the map in S1 using a 4×4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12×12 feature maps. Before passing from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2×2 regions in each feature map. At layer S2, there are 22 6×6 feature maps. An activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each map in layer S2 via a corresponding synapse on CB3. At layer C3, there are 64 neurons. Synapse CB4 from layer C3 to output layer S3 completely connects C3 to S3, that is, every neuron in layer C3 is connected to every neuron in layer S3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. For example, this output can indicate the recognition or classification of the content of the original image.

[0085] The synapses at each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0086] Figure 7 A block diagram of an array that can be used for this purpose is shown in FIG. The vector-matrix multiplication (VMM) array 32 includes non-volatile memory cells and serves as a synapse between one layer and the next (such as Figure 6 CB1, CB2, CB3, and CB4 in FIG. 1 ). Specifically, the VMM array 32 includes a nonvolatile memory cell array 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the corresponding inputs of the nonvolatile memory cell array 33. The inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the nonvolatile memory cell array 33.

[0087] The non-volatile memory cell array 33 serves two purposes. First, it stores weights to be used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33, and each output line (source line or bit line) adds them together to produce an output, which will serve as the input to the next layer or the final layer. By performing multiplication and addition functions, the non-volatile memory cell array 33 eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient due to its in-situ memory calculations.

[0088] The output of the non-volatile memory cell array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform the summation of positive and negative weights.

[0089] The output values ​​of the difference summer 38 are then summed and provided to the activation function circuit 39, which corrects the output. The activation function circuit 39 can provide a sigmoid, tanh or ReLU function. The corrected output value of the activation function circuit 39 becomes the next layer (for example, Figure 6 The elements of the feature map of layer C1 in the image processing apparatus are then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the difference summer 38 and the activation function circuit 39 constitute a plurality of neurons.

[0090] Figure 7 The inputs to the VMM array 32 (WLx, EGx, CGx, and optionally BLx and SLx) can be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0091] Figure 8 FIG. 1 is a block diagram illustrating the use of multiple layers of VMM arrays 32 (labeled here as VMM arrays 32a, 32b, 32c, 32d, and 32e). Figure 8As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM array 32a. The converted analog input can be a voltage or a current. The first level of input D / A conversion can be accomplished by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog levels of the matrix multiplier of the input VMM array 32a. Input conversion can also be accomplished by an analog-to-analog (A / A) converter to convert the external analog input into a mapped analog input for the input VMM array 32a.

[0092] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which in turn generates an output that is provided as input to the next VMM array (hidden level 2) 32c, and so on. The layers of VMM array 32 serve as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a separate physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. Figure 8 The example shown includes five layers (VMM arrays 32a, 32b, 32c, 32d, 32e): one input layer (VMM array 32a), two hidden layers (VMM arrays 32b, 32c), and two fully connected layers (VMM arrays 32d, 32e). Those skilled in the art will appreciate that this is merely exemplary and that, on the contrary, the system may include more than two hidden layers and more than two fully connected layers.

[0093] Vector-Matrix Multiplication (VMM) Array

[0094] Figure 9 A neuron VMM array 900 is shown, which is particularly suitable for Figure 3 The memory cells 310 shown are used as synapses and components for neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of nonvolatile memory cells and a reference array 902 of nonvolatile reference memory cells (at the top of the array). Alternatively, another reference array can be placed at the bottom.

[0095] In VMM array 900, control gate lines (such as control gate line 903) extend in the vertical direction (thus, reference array 902 is orthogonal to control gate line 903 in the row direction), and erase gate lines (such as erase gate line 904) extend in the horizontal direction. Here, the inputs of VMM array 900 are provided on the control gate lines (CG0, CG1, CG2, CG3), and the outputs of VMM array 900 appear on the source lines (SL0, SL1). In one embodiment, only even-numbered rows are used, and in another embodiment, only odd-numbered rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summation function of all the currents from the memory cells connected to that particular source line.

[0096] As described herein for neural networks, the non-volatile memory cells of VMM array 900 (ie, the flash memory of VMM array 900) are preferably configured to operate in the sub-threshold region.

[0097] Biasing the nonvolatile reference memory cell and the nonvolatile memory cell described herein in weak inversion:

[0098] Ids=Io*e (Vg-Vth) / kVt =w*Io*e (Vg) / kVt ,

[0099] where w = e (-Vth) / kVt

[0100] For an I-to-V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert the input current to an input voltage:

[0101] Vg=k*Vt*log[Ids / wp*Io]

[0102] Here, wp is w of a reference memory cell or a peripheral memory cell.

[0103] For a memory array used as a vector matrix multiplier VMM array, the output current is:

[0104] Iout=wa*Io*e (Vg) / kVt ,Right now

[0105] Iout=(wa / wp)*Iin=W*Iin

[0106] W=e (Vthp-Vtha) / kVt

[0107] Here, wa = w for each memory cell in the memory array.

[0108] The word line or control gate may be used as the input to the memory cell for the input voltage.

[0109] Alternatively, the flash memory cells of the VMM array described herein may be configured to operate in the linear region:

[0110] Ids=β*(Vgs-Vth)*Vds;β=u*Cox*W / L

[0111] W=α(Vgs-Vth)

[0112] The word line or control gate or bit line or source line may serve as the input of the memory cell operating in the linear region.

[0113] For an IV linear converter, a memory cell (eg, a reference memory cell or a peripheral memory cell) or a transistor operating in a linear region may be used to linearly convert an input / output current into an input / output voltage.

[0114] U.S. Patent Application No. 15 / 826,345 describes Figure 7 Other embodiments of the VMM array 32 of FIGURE 1 are incorporated herein by reference. As described herein, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0115] Figure 10 A neuron VMM array 1000 is shown, which is particularly suitable for Figure 2 Memory cell 210 is shown and serves as a synapse between the input layer and the next layer. VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. Reference arrays 1001 and 1002, arranged along the columns of the array, are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs on word lines WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected via a multiplexer 1014 (only partially shown), with the current input flowing therein. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0116] The memory array 1003 serves two purposes. First, it stores the weights that the VMM array 1000 will use on its corresponding memory cells. Second, the memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided in terminals BLR0, BLR1, BLR2, and BLR3, which are converted by reference arrays 1001 and 1002 into input voltages to be provided to word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1003, and then adds all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0-BLN), which will be the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient. Here, the voltage inputs are provided on the word lines (WL0, WL1, WL2, and WL3), and the outputs appear on the corresponding bit lines (BL0-BLN) during a read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all of the nonvolatile memory cells connected to that particular bit line.

[0117] Table 5 shows the operating voltages for VMM array 1000. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0118] Table 5: Figure 10 Operation of the VMM array 1000

[0119] WL WL-Not selected BL BL-Not selected SL SL-Not selected Read 1-3.5V -0.5V / 0V 0.6-2V(Ineuron) 0.6V-2V / 0V 0V 0V Erase About 5-13V 0V 0V 0V 0V 0V programming 1-2V -0.5V / 0V 0.1-3uA Vinh about 2.5V 4-10V 0-1V / FLT

[0120] Figure 11 A neuron VMM array 1100 is shown, which is particularly suitable for Figure 2 Memory cell 210 is shown and serves as a synapse and component for neurons between the input layer and the next layer. VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. Reference arrays 1101 and 1102 extend in the row direction of VMM array 1100. The VMM array is similar to VMM 1000, except that in VMM array 1100, the word lines extend in the vertical direction. Here, inputs are provided on word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all currents from the memory cells connected to that particular source line.

[0121] Table 6 shows the operating voltages for the VMM array 1100. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0122] Table 6: Figure 11 Operation of the VMM array 1100

[0123]

[0124]

[0125] Figure 12 A neuron VMM array 1200 is shown, which is particularly suitable for Figure 3 Memory cell 310 is shown and serves as a synapse and component of neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs on control gate lines CG0, CG1, CG2, and CG3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected via a multiplexer 1212 (only partially shown), with current inputs flowing into them through BLR0, BLR1, BLR2, and BLR3. Multiplexers 1212 each include a respective multiplexer 1205 and a cascode transistor 1204 to ensure a constant voltage on a bit line (such as BLR0) of each of the first and second nonvolatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0126] Memory array 1203 serves two purposes. First, it stores weights to be used by VMM array 1200. Second, memory array 1203 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1201 and 1202 convert into input voltages to be provided to control gate lines CG0, CG1, CG2, and CG3) by the weights stored in the memory array, and then adds all the results (cell currents) to produce an output, which appears at BL0-BLN and will be the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current placed on each bit line performs a summing function of all the currents from the memory cells connected to that particular bit line.

[0127] VMM array 1200 realizes unidirectional tuning for the non-volatile memory cells in memory array 1203. That is to say, each non-volatile memory cell is erased and then partially programmed until the required charge on the floating gate is reached. This can be performed, for example, using the novel precision programming technology described below. If too much charge is placed on the floating gate (so that the wrong value is stored in the cell), the cell must be erased and the sequence of the partial programming operation must be restarted. As shown in the figure, two rows sharing the same erase gate line (such as EG0 or EG1) need to be erased together (which is called page erase), and thereafter, each cell is partially programmed until the required charge on the floating gate is reached.

[0128] Table 7 shows the operating voltages for the VMM array 1200. The columns in the table indicate the voltages applied to the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector from the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0129] Table 7: Figure 12 Operation of the VMM array 1200

[0130]

[0131] Figure 13 A neuron VMM array 1300 is shown, which is particularly suitable for Figure 3Memory cells 310 are shown and serve as synapses and components of neurons between the input layer and the next layer. VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. Erase gate lines EGR0, EG0, EG1, and EGR1 extend vertically, while control gate lines CG0, CG1, CG2, and CG3 and word lines WL0, WL1, WL2, and WL3 extend horizontally. VMM array 1300 is similar to VMM array 1400, except that VMM array 1300 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve a desired charge on the floating gate due to the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into voltages to be applied to control gate lines CG0, CG1, CG2, and CG3 of the memory cells in the row direction (through the action of the reference cells connected via the diodes of multiplexer 1314). The current outputs (neurons) are in bit lines BL0-BLN, where each bit line sums all currents from the nonvolatile memory cells connected to that particular bit line.

[0132] Table 8 shows the operating voltages for the VMM array 1300. The columns in the table indicate the voltages applied to the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector from the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0133] Table 8: Figure 13 Operation of the VMM array 1300

[0134]

[0135] Long Short-Term Memory

[0136] Prior art includes a concept known as long short-term memory (LSTM). LSTM cells are commonly used in neural networks. LSTM allows neural networks to remember information for a predetermined, arbitrary time interval and use that information in subsequent operations. A typical LSTM cell consists of a cell, an input gate, an output gate, and a forget gate. These three gates regulate the flow of information into and out of the cell, as well as the time interval over which information is remembered within the LSTM. VMMs are particularly useful in LSTM cells.

[0137] Figure 14An exemplary LSTM 1400 is shown. In this example, LSTM 1400 includes units 1401, 1402, 1403, and 1404. Unit 1401 receives an input vector x0 and generates an output vector h0 and a unit state vector c0. Unit 1402 receives an input vector x1, an output vector (hidden state) h0 from unit 1401, and a unit state c0 from unit 1401, and generates an output vector h1 and a unit state vector c1. Unit 1403 receives an input vector x2, an output vector (hidden state) h1 from unit 1402, and a unit state c1 from unit 1402, and generates an output vector h2 and a unit state vector c2. Unit 1404 receives an input vector x3, an output vector (hidden state) h2 from unit 1403, and a unit state c2 from unit 1403, and generates an output vector h3. Additional units may be used, and an LSTM with four units is merely an example.

[0138] Figure 15 Shows the available Figure 14 FIG1 is an exemplary implementation of an LSTM unit 1500 for units 1401, 1402, 1403, and 1404 in FIG1. ​​LSTM unit 1500 receives an input vector x(t), a cell state vector c(t-1) from the previous unit, and an output vector h(t-1) from the previous unit, and generates a cell state vector c(t) and an output vector h(t).

[0139] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control how much of each component in the input vector is allowed to pass through to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors together, and an addition device 1509 for adding two vectors together. The output vector h(t) can be provided to the next LSTM cell in the system, or it can be accessed for other purposes.

[0140] Figure 16 LSTM unit 1600 is shown, which is an example of a specific implementation of LSTM unit 1500. For the convenience of the reader, the same numbering is used in LSTM unit 1600 as in LSTM unit 1500. Sigmoid function devices 1501, 1502, and 1503, and tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. Therefore, it can be seen that VMM arrays are particularly useful in LSTM units used in certain neural network systems.

[0141] An alternative form of LSTM cell 1600 (and another example of a specific implementation of LSTM cell 1500) is Figure 17 As shown in Figure 17 In the embodiment, the sigmoid function devices 1501, 1502, and 1503 and the tanh device 1504 share the same physical hardware (the VMM array 1701 and the activation function block 1702) in a time-division multiplexed manner. The LSTM unit 1700 further includes a multiplier device 1703 for multiplying two vectors together, an addition device 1708 for adding two vectors together, a tanh device 1505 (which includes the activation circuit block 1702), a register 1707 for storing the value i(t) when the value i(t) is output from the sigmoid function block 1702, and a register 1707 for storing the value f(t)*c(t-1) when the value f(t)*c(t-1) is output from the multiplier device 1703 via a multiplexer 1710. 03 is output from the multiplier device 1703, a register 1704 stores the value f(t)*c(t-1), when the value i(t)*u(t) is output from the multiplier device 1703 through the multiplexer 1710, a register 1706 stores the value o(t)*c~(t) when the value o(t)*c~(t) is output from the multiplier device 1703 through the multiplexer 1710, and a multiplexer 1709.

[0142] LSTM unit 1600 includes multiple sets of VMM arrays 1601 and corresponding activation function blocks 1602, while LSTM unit 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the implementation of LSTM unit 1700. LSTM unit 1700 will require less space than LSTM 1600 because LSTM unit 1700 only requires 1 / 4 of its space for VMM and activation function blocks compared to LSTM unit 1600.

[0143] It will also be appreciated that an LSTM cell will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as summer and activation circuit blocks, as well as high-voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0144] Gate-controlled recursive unit

[0145] The simulated VMM implementation can be used for a Gated Recurrent Unit (GRU) system. A GRU is a gate-controlled mechanism in recurrent neural networks. A GRU is similar to an LSTM, except that a GRU cell typically contains fewer components than an LSTM cell.

[0146] Figure 18 An exemplary GRU 1800 is shown. The GRU 1800 in this example includes units 1801, 1802, 1803, and 1804. Unit 1801 receives an input vector x0 and generates an output vector h0. Unit 1802 receives an input vector x1, the output vector h0 from unit 1801, and generates an output vector h1. Unit 1803 receives an input vector x2 and the output vector (hidden state) h1 from unit 1802, and generates an output vector h2. Unit 1804 receives an input vector x3 and the output vector (hidden state) h2 from unit 1803, and generates an output vector h3. Additional units may be used, and a GRU with four units is merely an example.

[0147] Figure 19 Shows the available Figure 18 1 , and 1804. The GRU unit 1900 receives an input vector x(t) and an output vector h(t-1) from a previous GRU unit and generates an output vector h(t). The GRU unit 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). The GRU unit 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, a plurality of multiplier devices 1904, 1905, and 1906 for multiplying two vectors together, an addition device 1907 for adding two vectors together, and a complement device 1908 for subtracting the input from 1 to generate an output.

[0148] Figure 20 1 shows a GRU unit 2000, which is an example of a specific implementation of the GRU unit 1900. For the convenience of the reader, the same numbering is used in the GRU unit 2000 as in the GRU unit 1900. Figure 20 As can be seen in FIG, sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that the VMM array is particularly useful in the GRU unit used in some neural network systems.

[0149] An alternative form of GRU unit 2000 (and another example of a specific implementation of GRU unit 1900) is Figure 21 In Figure 21In

[0045] , the GRU unit 2100 utilizes a VMM array 2101 and an activation function block 2102 which, when configured as a sigmoid function, applies a number between 0 and 1 to control how much of each component in the input vector is allowed to pass through to the output vector. Figure 21 In the example, sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-division multiplexing manner. The GRU unit 2100 also includes a multiplier device 2103 that multiplies two vectors together, an addition device 2105 that adds two vectors together, a complement device 2109 that subtracts the input from 1 to generate an output, a multiplexer 2104, a register 2106 that holds the value h(t-1)*r(t) when the value h(t-1)*r(t) is output from the multiplier device 2103 through the multiplexer 2104, a register 2107 that holds the value h(t-1)*z(t) when the value h(t-1)*z(t) is output from the multiplier device 2103 through the multiplexer 2104, and a register 2108 that holds the value h^(t)*(1-z(t)) when the value h^(t)*(1-z(t)) is output from the multiplier device 2103 through the multiplexer 2104.

[0150] The GRU unit 2000 includes multiple sets of VMM arrays 2001 and activation function blocks 2002, while the GRU unit 2100 includes only one set of VMM arrays 2101 and activation function blocks 2102, which are used to represent multiple layers in the implementation of the GRU unit 2100. The GRU unit 2100 will require less space than the GRU unit 2000 because the GRU unit 2100 only requires 1 / 3 of its space for VMM and activation function blocks compared to the GRU unit 2000.

[0151] It will also be appreciated that a GRU system will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks outside the VMM array (such as summer and activation circuit blocks, as well as high-voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiments described below attempt to minimize the circuitry required outside the VMM array itself.

[0152] The inputs to the VMM array can be analog levels, binary levels, or digital bits (in which case a DAC is required to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, or digital bits (in which case an output ADC is required to convert the output analog levels to digital bits).

[0153] For each memory cell in the VMM array, each weight w can be implemented by a single memory cell, a differential cell, or two hybrid memory cells (the average of the two cells). In the case of a differential cell, two memory cells are required to implement the weight w as a differential weight (w = w + – w -). In the case of two hybrid memory cells, two memory cells are required to implement the weight w as the average of the two cells.

[0154] Implementation for accurate programming of cells in a VMM

[0155] Figure 22A A programming method 2200 is shown. First, the method begins (step 2201), which typically occurs in response to receiving a program command. Next, a bulk programming operation programs all cells to a "0" state (step 2202). Then, a soft erase operation erases all cells to an intermediate weak erase level so that each cell will consume approximately 3μA-5μA of current during a read operation (step 2203). This is in contrast to the deep erase level, where each cell will consume approximately 20μA-30μA of current during a read operation. Then, hard programming is performed on all unselected cells to a very deep programmed state to add electrons to the floating gate of the cell (step 2204) to ensure that those cells are truly "off," meaning that those cells will consume a negligible amount of current during a read operation.

[0156] A coarse programming method is then performed on the selected cells (step 2205), followed by a fine programming method (step 2206) to program the precise value desired for each selected cell.

[0157] Figure 22B Another programming method 2210 is shown that is similar to the programming method 2200. However, instead of Figure 22A After the method starts (step 2201), all cells are erased to the "1" state using an erase operation (step 2212). Then all cells are programmed to an intermediate state (level) using a soft programming operation (step 2213) so that each cell will consume approximately 3uA-5uA of current during a read operation. Thereafter, the rough and fine programming methods will be as follows Figure 22A shown. Figure 22B A variation of the embodiment would remove the soft programming method (step 2213) entirely.

[0158] Figure 23A first embodiment of the coarse programming method 2205 is shown, which is a search and execute method 2300. First, a lookup table search is performed to determine a coarse target current value (I CT ) (step 2301). Assume that the selected cell can be programmed to store one of N possible values ​​(e.g., 128, 64, 32, etc.). Each of the N values ​​will correspond to a different expected current value (I D In one embodiment, the lookup table may contain M possible current values ​​to be used as a rough target current value I for the selected cell during the search and execution of method 2300. CT , where M is an integer less than N. For example, if N is 8, then M can be 4, which means that there are 8 possible values ​​that the selected cell can store, and one of the 4 coarse target current values ​​will be selected as the coarse target for the search and execution method 2300. That is, the search and execution method 2300 (which is also an embodiment of the coarse programming method 2205) is intended to quickly program the selected cell to a value that is close to the desired value (I D ) value (I CT ), then the precision programming method 2206 aims to program the selected cells more precisely to be very close to the desired value (I D ).

[0159] For a simple example of N=8 and M=4, examples of cell values, desired current values, and rough target current values ​​are shown in Tables 9 and 10:

[0160] Table 9: Example of N expected current values ​​when N = 8

[0161] The value stored in the selected cell <![CDATA[Expected current value (I D )]]> 000 100pA 001 200pA 010 300pA 011 400pA 100 500pA 101 600pA 110 700pA 111 800pA

[0162] Table 10: Example of M target current values ​​when M = 4

[0163] <![CDATA[Rough target current value (I CT )]]> Associated cell value <![CDATA[200pA+I CTOFFSET1 ]]> 000,001 <![CDATA[400pA+I CTOFFSET2 ]]> 010,011 <![CDATA[600pA+I CTOFFSET3 ]]> 100,101 <![CDATA[800pA+I CTOFFSET4 ]]> 110,111

[0164] Offset value I CTOFFSETx Used to prevent the desired current value from being exceeded during coarse adjustment.

[0165] Once the rough target current value I is selected CT , the selected cell is programmed (step 2302) by applying a voltage v0 to the appropriate terminal of the selected cell based on the cell architecture type of the selected cell (e.g., memory cell 210, 310, 410, or 510). Figure 3 For a memory cell 310 of the type φ, the voltage v0 will be applied to the terminal of the control gate 28, and according to the rough target current value ICT , v0 can be 5V-7V. The value of V0 can optionally be obtained by storing a voltage lookup table of v0 and a rough target current value I CT Sure.

[0166] Next, by applying a voltage v i =v i-1 +v increment Program the selected cell, where i starts at 1 and increments each time the step is repeated, and v increment is a small voltage that will result in a degree of programming appropriate for the desired granularity of change (step 2303). Thus, the first time step 2303 is performed, i=1, and v1 will be v0+v increment。 A verification operation is then performed (step 2304), in which a read operation is performed on the selected cell and the current consumed by the selected cell (I cell ). If I cell Less than or equal to I CT (here the first threshold), the search and execution method 2300 is complete and the precise programming method 2206 can begin. cell Not less than or equal to I CT , then repeat step 2303, and i increases.

[0167] Therefore, at the moment when the coarse programming method 2205 ends and the fine programming method 2206 begins, the voltage v i will be the final voltage used to program the selected cell, and the selected cell will store the value of the rough target current I CT The purpose of the precise programming method 2206 is to program the selected cell to a value where it consumes current I during a read operation. D (plus or minus an acceptable deviation, such as 50 pA or less), the current I D is the desired current value associated with the value intended to be stored in the selected cell.

[0168] Figure 24 Examples of different voltage progressions that may be applied to the control gates of selected memory cells during the precision programming method 2206 are shown.

[0169] In the first method, increasing voltages are applied to the control gate in a stepwise manner to further program the selected memory cell. The starting point is v i , which is the final voltage applied during the coarse programming method 2205. The increment v p1 Add to v1, then use the voltage v1+v p1 The selected cell (indicated by the second pulse from the left in progressive 2401) is programmed.p1 is less than v increment (the voltage increments used during the coarse programming method 2205). After each programming voltage is applied, a verification step (similar to step 2304) is performed in which it is determined whether Icell is less than or equal to Icell. PT1 (which is the first precise target current value and here is the second threshold), where I PT1 =I D +I PT1OFFSET , where I PT1OFFSET is the offset value added to prevent programming overshoot. If not, another increment v p1 is added to the previously applied programming voltage and the process is repeated. cell Less than or equal to I PT1 , then that portion of the programming sequence stops. Optionally, if I PT1 Equal to I D or sufficiently accurately approximate to I D , the selected memory cell has been successfully programmed.

[0170] If I PT1 Not close enough D , then further programming of smaller granularity can be performed. Here, the step 2402 is now used. The starting point of the step 2402 is the final voltage used for programming under the step 2401. p2 (It is less than v p1 ) is added to this voltage, and the combined voltage is applied to program the selected memory cell. After each programming voltage is applied, a verification step (similar to step 2304) is performed, in which the I cell Is it less than or equal to I PT2 (which is the second precise target current value and here is the third threshold), where I PT2 =I D +I PT2OFFSET , where I PT2OFFSET is the offset value added to prevent programming overshoot. If not, another increment v p2 is added to the previously applied programming voltage and the process is repeated. cell Less than or equal to I PT2 , then that part of the programming sequence stops. Here, it is assumed that I PT2 Equal to I D or close enough to I D , so that programming can stop because the target value has been achieved with sufficient accuracy. It will be understood by those skilled in the art that additional progression can be applied by using smaller and smaller programming increments. For example, in Figure 25In , three progressions (2501, 2502 and 2503) are applied instead of only two.

[0171] The second method is shown in progress 2403. Here, instead of increasing the voltage applied during programming of the selected memory cell, the same voltage is applied for the duration of the increasing cycle. Instead of adding an incremental voltage such as v in progress 2401, p1 And add v in progress 2403 p2 , but the additional time increment t p1 added to the programming pulses so that each applied pulse is longer than the previously applied pulse by t p1 After each programming pulse is applied, the same verification steps as previously described for progression 2401 are performed. Optionally, additional progressions may be applied where the additional time increments added to the programming pulses are of shorter duration than the previously used schedule. Although only one time progression is shown, one of ordinary skill in the art will appreciate that any number of different time progressions may be applied.

[0172] Additional details for two additional implementations of the coarse programming method 2205 will now be provided.

[0173] Figure 26 A second embodiment of the coarse programming method 2205 is shown, which is an adaptive calibration method 2600. The method begins (step 2601). The cell is programmed with a default starting value v0 (step 2602). Unlike in the search and execute method 2300, v0 is not derived from a lookup table but can be a relatively small initial value. The control gate voltage of the cell is measured at a first current value IR1 (e.g., 100 nA) and a second current value IR2 (e.g., 10 nA), and the subthreshold slope is determined based on these measurements (e.g., 360 mV / dec) and stored (step 2603).

[0174] Determine the new desired voltage v i The first time this step is performed, i=1, and v1 is determined based on the stored subthreshold slope value and the current target and offset values ​​using a subthreshold formula, such as the following:

[0175] Vi=Vi-1+Vincrement,

[0176] Vincrement is proportional to the slope of Vg

[0177] Vg=k*Vt*log[Ids / wa*Io]

[0178] Here, wa is the w of the memory cell, and Ids is the current target value plus the offset value.

[0179] If the stored slope value is relatively steep, a relatively small current offset value can be used. If the stored slope value is relatively flat, a relatively high current offset value can be used. Thus, determining the slope information will allow the selection of a current offset value that is customized for the particular cell under consideration. This will ultimately make the programming process shorter. As this step is repeated, i is incremented, and v is incremented. i =v i-1 +v increment . Then use vi to program. increment Can be stored by v increment The value is determined by a lookup table with the target current value.

[0180] Then, a verification operation is performed, in which a read operation is performed on the selected cell and the current consumed by the selected cell (I cell )(Step 2605). If I cell Less than or equal to I CT (Here it is a rough target threshold), where I CT Set to =I D +I CTOFFSET , where I CTOFFSET If I is the offset value added to prevent programming overshoot, the adaptive calibration method 2600 is complete and the precise programming method 2206 can begin. cell Not less than or equal to I CT , then repeat steps 2604 to 2605, and i is incremented.

[0181] Figure 27 Aspects of the adaptive calibration method 2600 are shown. During step 2603, current source 2701 is used to apply exemplary current values ​​IR1 and IR2 to the selected cell (here, memory cell 2702), and then the voltage at the control gate of memory cell 2702 is measured (CGR1 for IR1 and CGR2 for IR2). The slope will be (CGR2-CGR1) / dec.

[0182] Figure 28A second embodiment of the coarse programming method 2205 is shown, which is an absolute calibration method 2800. The method begins (step 2801). A cell is programmed with a default starting value v0 (step 2802). The control gate voltage (VCGRx) of the cell is measured and stored at a current value Itarget (step 2803). A new desired voltage v1 is determined based on the stored control gate voltage, the current target value, and the offset value Ioffset+Itarget (step 2804). For example, the new desired voltage v1 can be calculated as follows: v1 = v0 + (VCGBIAS - stored VCGR), where VGBIAS is approximately equal to 1.5V, which is the default read control gate voltage at the maximum target current, and the stored VCGR is the read control gate voltage measured in step 2803.

[0183] Then use v i Program the cell. When i=1, use voltage v1 from step 2804. When i>=2, use voltage v i =v i-1 +V increment .v increment Available from storage v increment Then, a verification operation is performed in which a read operation is performed on the selected cell and the current consumed by the selected cell (I cell )(Step 2806). If I cell Less than or equal to I CT (where it is a threshold), then the absolute calibration method 2800 is complete and the precise programming method 2206 can begin. cell Not less than or equal to I CT , then repeat steps 2805 to 2806, and i increases.

[0184] Figure 29FIG. 2900 shows a circuit for implementing step 2803 of the absolute calibration method 2800. A voltage source (not shown) generates a VCGR that ramps up from an initial voltage. Here, n + 1 different current sources 2901 (2901-0, 2901-1, 2901-2, ..., 2901-n) generate different currents IO0, IO1, IO2, … IOn with increasing magnitudes. Each current source 2901 is connected to an inverter 2902 (2902-0, 2902-1, 2902-2, ..., 2902-n) and a memory cell 2903 (2903-0, 2903-1, 2903-2, ... 2903-n). As the VCGR ramps up, each memory cell 2903 consumes an increasing amount of current, and the input voltage to each inverter 2902 decreases. Since IO0 < IO1 < IO2 <... < IOn, the output of inverter 2902-0 will first switch from low to high as the VCGR increases. Next, the output of inverter 2902-1 will switch from low to high, then the output of inverter 2902-2 will switch, and so on, until the output of inverter 2902-n switches from low to high. Each inverter 2902 controls a switch 2904 (2904-0, 2904-1, 2904-2, ..., 2904-n) such that when the output of the inverter 2902 is high, the switch 2904 closes, which causes the VCGR to be sampled by a capacitor 2905 (2905-0, 2905-1, 2905-2, ..., 2905-n). Thus, the switches 2904 and the capacitors 2905 can form a sample-and-hold circuit. In Figure 28 the absolute calibration method 2800, the values of IO0, IO1, IO2, ..., IOn are used as possible values of Itarget, and the corresponding sampled voltages are used as the associated values VCGRx. Graph 2906 shows the VCGR ramping up over time, and the outputs of inverters 2902-0, 2902-1, and 2902-n switching from low to high at different times.

[0185] Figure 30 FIG. 3000 shows an exemplary progression for programming selected cells during the adaptive calibration method 2600 or the absolute calibration method 2800. In one embodiment, a voltage Vcgp is applied to the control gates of the memory cells in the selected row. The number of selected memory cells in the selected row is, for example, = 32 cells. Thus, up to 32 memory cells in the selected row can be programmed in parallel. Each memory cell is allowed to be coupled to a programming current Iprog through a bit line enable signal. If the bit line enable signal is inactive (meaning a positive voltage is applied to the selected bit line), the memory cell is inhibited (not programmed). As Figure 30As shown, the bit line enable signal En_blx (where x varies between 1 and n, where n is the number of bit lines) is enabled at different times to have the desired Vcgp voltage level for that bit line (and thus the selected memory cell on that bit line). In another embodiment, the enable signal on the bit line can be used to control the voltage applied to the control gate of the selected cell. Each bit line enable signal enables the desired voltage (such as Vcgp) corresponding to that bit line. Figure 28 (vi) as described above is applied as Vcgp. The bitline enable signal can also control the programming current flowing into the bitline. In this example, each subsequent control gate voltage, Vcgp, is higher than the previous voltage. Alternatively, each subsequent control gate voltage can be lower or higher than the previous voltage. Each subsequent increment of Vcgp can be equal to or different from the previous increment.

[0186] Figure 31 An exemplary progression 3100 for programming selected cells during the adaptive calibration method 2600 or the absolute calibration method 2800 is shown. In one embodiment, the bitline enable signal enables the selected bitline (meaning the selected memory cell in that bitline) to be programmed with a corresponding VCGP voltage level. In another embodiment, the bitline enable signal can be used to control the voltage applied to the incremental ramp control gates of the selected cells. Each bitline enable signal enables the desired voltage corresponding to that bitline (such as Figure 28 vi) described in is applied to the control gate voltage. In this example, each subsequent increment is equal to the previous increment.

[0187] Figure 32 A system for implementing input and output methods for reading or verifying using a VMM array is shown. Input function circuit 3201 receives digital bit values ​​and converts them into analog signals, which are then used to apply a voltage to the control gate of a selected cell in array 3204, as determined by control gate decoder 3202. Simultaneously, word line decoder 3203 is also used to select the row in which the selected cell resides. Output neuron circuit block 3205 performs output actions for each column (neuron) of cells in array 3204. Output neuron circuit block 3205 can be implemented using an integrating analog-to-digital converter (ADC), a successive approximation register (SAR) ADC, or a sigma-delta ADC.

[0188] In one embodiment, for example, the digital value provided to the input function circuit 3201 includes four bits (DIN3, DIN2, DIN1, and DIN0), and different bit values ​​correspond to different numbers of input pulses applied to the control gate. A larger number of pulses will result in a larger output value (current) for the cell. Examples of bit values ​​and pulse values ​​are shown in Table 11:

[0189] Table 11: Digital bit input and generated pulses

[0190] DIN3 DIN2 DIN1 DIN0 Generated pulse 0 0 0 0 0 0 0 0 1 1 0 0 1 0 2 0 0 1 1 3 0 1 0 0 4 0 1 0 1 5 0 1 1 0 6 0 1 1 1 7 1 0 0 0 8 1 0 0 1 9 1 0 1 0 10 1 0 1 1 11 1 1 0 0 12 1 1 0 1 13 1 1 1 0 14 1 1 1 1 15

[0191] In the above example, there are a maximum of 16 pulses for a 4-bit digital value to read out the cell value. Each pulse is equal to one unit of the cell value (current). For example, if Icell unit = 1 nA, then for DIN[3-0] = 0001, Icell = 1*1 nA = 1 nA; and for DIN[3-0] = 1111, Icell = 15*1 nA = 15 nA.

[0192] In another embodiment, the digital bit input uses digital bit position summation to read the cell value, as shown in Table 12. Here, only four pulses are required to evaluate the 4-bit digital value. For example, the first pulse is used to evaluate DIN0, the second pulse is used to evaluate DIN1, the third pulse is used to evaluate DIN2, and the fourth pulse is used to evaluate DIN3. The results from the four pulses are then summed according to the bit position. The implemented digital bit summation formula is as follows: Output = (2^0*DIN0+2^1*DIN1+2^2*DIN2+2^3*DIN3)*IcellUnits.

[0193] For example, if Icell unit=1 nA, then for DIN[3-0]=0001, Icell total=0+0+0+1*1 nA=1 nA; and for DIN[3-0]=1111, Icell total=8*1 nA+4*1 nA+2*1 nA+1*1 nA=15 nA.

[0194] Table 12: Digital bit input summation

[0195] <![CDATA[ 2^3*DIN3 ]]> <![CDATA[ 2^2*DIN2 ]]> <![CDATA[ 2^1*DIN1 ]]> <![CDATA[ 2^0*DIN0 ]]> <![CDATA[ Total value ]]> 0 0 0 0 0 0 0 0 1 1 0 0 2 0 2 0 0 2 1 3 0 4 0 0 4 0 4 0 1 5 0 4 2 0 6 0 4 2 1 7 8 0 0 0 8 8 0 0 1 9 8 0 2 0 10 8 0 2 1 11 8 4 0 0 12 8 4 0 1 13 8 4 2 0 14 8 4 2 1 15

[0196] Figure 33 An example of a charge summer 3300 is shown that can be used to sum the output of the VMM during a verify operation to obtain a single analog value that represents the output and can then optionally be converted to a digital bit value. The charge summer 3300 includes a current source 3301 and a sample-and-hold circuit that includes a switch 3302 and a sample-and-hold (S / H) capacitor 3303. As shown in the example for a 4-bit digital value, there are 4 S / H circuits to hold the values ​​from 4 evaluation pulses, where these values ​​are summed at the end of the process. The S / H capacitor 3303 is selected to have a ratio associated with the 2^n*DINn bit position of the S / H capacitor; for example, C_DIN3 = x8 Cu, C_DIN2 = x4 Cu, C_DIN1 = x2 Cu, DIN0 = x1 Cu. The current source 3301 is also scaled accordingly.

[0197] Figure 34 A current summator 3400 is shown that can be used to sum the output of the VMM during a verify operation. Current summator 3400 includes a current source 3401, a switch 3402, switches 3403 and 3404, and a switch 3405. As shown for the example of a 4-bit digital value, a current source circuit is present to maintain the values ​​from the 4 evaluation pulses, where these values ​​are summed at the end of the process. The current sources are scaled based on 2^n*DINn bit positions; for example, I_DIN3 = x8 Icell units, I_DIN2 = x4 Icell units, I_DIN1 = x2 Icell units, and I_DIN0 = x1 Icell unit.

[0198] Figure 35 A digital summer 3500 is shown, which receives multiple digital values, sums them, and generates an output, DOUT, representing the sum of the inputs. Digital summer 3500 can be used during a verification operation. As shown in the example for a 4-bit digital value, a digital output bit is present to hold the values ​​from the 4 evaluation pulses, where these values ​​are summed at the end of the process. The digital outputs are digitally scaled based on 2^n*DINn bit positions; for example, DOUT3 = x8 DOUT0, DOUT2 = x4 DOUT1, I_DOUT1 = x2 DOUT0, and I_DOUT0 = DOUT0.

[0199] Figure 36A FIG3 shows an integrating dual slope ADC 3600 applied to an output neuron to convert the cell current into a digital output bit. The integrator composed of an integrating operational amplifier 3601 and an integrating capacitor 3602 integrates the cell current ICELL and the reference current IREF. Figure 36B As shown, during a fixed time t1, the cell current is integrated up (Vout rises), and then down-integrated (Vout falls) with the reference current applied during time t2. Current Icell = t2 / t1*IREF. For example, for t1, for 10-bit digital resolution, 1024 cycles are used, and for t2, the number of cycles varies from 0 to 1024 cycles depending on the Icell value.

[0200] Figure 36C FIG3 shows an integrating single slope ADC 3660 applied to an output neuron to convert the cell current into a digital output bit. An integrator consisting of an integrating operational amplifier 3661 and an integrating capacitor 3662 integrates the cell current ICELL. Figure 36DAs shown, during time t1, the cell current is integrated up (Vout rises until it reaches Vref2), and during time t2, another cell current is integrated up. Cell current Icell = Cint*Vref2 / t. The pulse counter is used to count the number of pulses (digital output bits) during the integration time t. For example, as shown, the digital output bit at t1 is less than the digital output bit at t2, which means that the cell current during t1 is greater than the cell current during the integration period t2. An initial calibration is performed to calibrate the integrating capacitor value Cint = Tref*Iref / Vref2 using a reference current and a fixed time.

[0201] Figure 36E An integrating dual-slope ADC 3680 is shown applied to an output neuron to convert the cell current into a digital output bit. Integrating dual-slope ADC 3680 does not use an integrating operational amplifier. The cell current or reference current is integrated directly against capacitor 3682. A pulse counter is used to count pulses (digital output bits) during the integration time. Current Icell = t2 / t1*IREF.

[0202] Figure 36F An integrating single-slope ADC 3690 is shown applied to an output neuron to convert the cell current into a digital output bit. Integrating single-slope ADC 3680 does not use an integrating operational amplifier. The cell current is integrated directly onto capacitor 3692. A pulse counter is used to count pulses (digital output bits) during the integration time. Cell current Icell = Cint*Vref2 / t.

[0203] Figure 37A A SAR (Successive Approximation Register) ADC is shown applied to an output neuron to convert the cell current into a digital output bit. The cell current may drop across a resistor to be converted into VCELL. Alternatively, the cell current may charge an S / H capacitor to be converted into VCELL. A binary search is used to calculate the bit starting from the MSB bit (most significant bit). Based on the digital bit from SAR 3701, DAC 3702 is used to set the appropriate analog reference voltage to comparator 3703. The output of comparator 3703 is then fed back to SAR 3701 to select the next analog level. As shown in FIG. Figure 37B As shown, for the example of a 4-bit digital output bit, there are 4 evaluation cycles: the first pulse evaluates DOUT3 by setting the analog level in the middle, then the second pulse evaluates DOUT2 by setting the analog level in the middle of the upper half or the middle of the lower half, and so on.

[0204] Figure 38The Σ-Δ ADC 3800 is shown applied to an output neuron to convert the cell current into a digital output bit. An integrator consisting of an operational amplifier 3801 and a capacitor 3805 integrates the sum of the current from the selected cell and the reference current from a 1-bit current DAC 3804. A comparator 3802 compares the integrated output voltage to a reference voltage. A clocked DFF 3803 provides a digital output stream based on the output of comparator 3802. The digital output stream typically enters a digital filter before being output to a digital output bit.

[0205] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intervening material, element, or space disposed therebetween) and "indirectly on" (intervening material, element, or space disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (no intervening material, element, or space disposed therebetween) and "indirectly adjacent" (intervening material, element, or space disposed therebetween), "mounted to" includes "directly mounted to" (no intervening material, element, or space disposed therebetween) and "indirectly mounted to" (intervening material, element, or space disposed therebetween), and "electrically coupled to" includes "directly electrically coupled to" (no intervening material or element electrically connecting the elements together) and "indirectly electrically coupled to" (intervening material or element electrically connecting the elements together). For example, forming an element "above a substrate" may include forming the element directly on the substrate without an intervening material / element therebetween, as well as forming the element indirectly on the substrate with one or more intervening materials / elements therebetween.

Claims

1. A method of reading a selected non-volatile memory cell storing one of N possible values, wherein N is an integer greater than 2, the method comprising: Convert each digital bit into a series of input pulses; applying the series of input pulses to the selected nonvolatile memory cell; determining a value stored in the selected nonvolatile memory cell by summing weighted output currents received from the selected nonvolatile memory cell in response to the series of input pulses, wherein the weighted output current for each input pulse in the series of input pulses is equal to twice the output current received in response to the input pulse; n times, where n is the bit position of the digital bit in response to which the input pulse is generated. 2 . The method of claim 1 , comprising converting the result of the summation into digital bits indicative of the value stored in the non-volatile memory cell by an analog-to-digital converter. 3 . The method according to claim 2 , wherein the analog-to-digital converter comprises an integrating single-slope or dual-slope analog-to-digital converter. The method of claim 1 , wherein the output is an electric current. The method of claim 1 , wherein the output is an electrical charge. The method of claim 1 , wherein the output is a digital bit.

7. The method of claim 1, wherein the selected nonvolatile memory cell comprises a floating gate.

8. The method of claim 7, wherein the selected non-volatile memory cell is a split-gate flash memory cell.

9. The method of claim 1 , wherein the selected non-volatile memory cell is in a vector-matrix multiplication array in an analog memory deep neural network.

10. A method of reading a selected non-volatile memory cell storing one of N possible values, wherein N is an integer greater than 2, the method comprising: applying a series of inputs to the selected nonvolatile memory cell, wherein the series of inputs is a series of input pulses generated by converting a received digital bit, wherein different bit values ​​of the received digital bit correspond to different numbers of input pulses, and a larger number of input pulses will result in a larger output current of the selected nonvolatile memory cell; In response to the series of inputs, an analog-to-digital converter circuit is used to determine a value stored in the selected nonvolatile memory cell by summing the output currents of the selected nonvolatile memory cell.

11. The method of claim 10, wherein the determining step comprises receiving an output neuron in an integrating single-slope or dual-slope analog-to-digital converter and generating a digital bit indicative of the value stored in the non-volatile memory cell.

12. The method of claim 10, wherein the determining step comprises receiving an output neuron in a SAR analog-to-digital converter to generate a digital bit indicative of the value stored in the non-volatile memory cell.

13. The method of claim 10, wherein the determining step comprises receiving an output neuron in a sigma-delta analog-to-digital converter to generate a digital bit indicative of the value stored in the nonvolatile memory cell.

14. The method of claim 10, wherein the selected nonvolatile memory cell comprises a floating gate.

15. The method of claim 10, wherein the selected non-volatile memory cell is a split-gate flash memory cell.

16. The method of claim 10, wherein the selected non-volatile memory cell is in a vector-matrix multiplication array in an analog memory deep neural network.

17. The method of claim 10, wherein the selected nonvolatile memory cell operates in a subthreshold region.

18. The method of claim 10, wherein the selected nonvolatile memory cell operates in a linear region.

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