Isolation structure and method for manufacturing the same

Abstract

The present invention provides a trench isolation structure and a method for manufacturing the same. The method comprises: forming a trench on a surface of a substrate; forming a mask pattern having an opening connected to the trench on the substrate; filling the connected opening and the trench with a first isolation material layer, wherein a surface of the first isolation material layer defines a first recess; filling the first recess with a second isolation material layer; partially removing the first and second isolation material layers to form a second recess; performing a first oblique ion implantation process to form a first damage zone in at least the first isolation material layer; performing a second oblique ion implantation process to form a second damage zone in at least the first isolation material layer; performing a decoupling plasma treatment to convert a portion of the first and second damage zones into a protective layer having an etch selectivity relative to the damage zone; and removing the damage zone.

Description

Technical Field

[0001] The present invention relates to an isolation structure and a manufacturing method thereof, and particularly to a trench isolation structure and a manufacturing method thereof. Background Art

[0002] In a semiconductor wafer, an isolation structure is used to electrically and physically isolate active regions of a plurality of semiconductor devices. A trench isolation structure is a commonly used isolation structure at present. A method for forming a trench isolation structure includes forming a trench on a surface of a substrate, then filling an insulating material in the trench and adjusting a height of the insulating material so that a top surface of the insulating material is approximately flush with the surface of the substrate. Generally, the height of the insulating material is adjusted by an etching process. During this etching process, it is possible to damage the active regions of the semiconductor devices. As a result, the performance of the semiconductor devices is adversely affected. Summary of the Invention

[0003] The present disclosure provides an isolation structure and a manufacturing method thereof, which can avoid damage to an active region during the formation of the isolation structure.

[0004] In one aspect of the present disclosure, a method for manufacturing an isolation structure is provided, including: forming a trench on a surface of a substrate; forming a mask pattern on the substrate, where the mask pattern has an opening communicating with the trench; filling a first isolation material layer in the trench and the opening, where a surface of the first isolation material layer defines a first depression; filling a second isolation material layer in the first depression; removing a part of the second isolation material layer and a part of the first isolation material layer to form a second depression in the opening of the mask pattern; performing a first ion implantation process so that first ions obliquely enter the second depression from a first side of the second depression to form at least a first damaged region in the first isolation material layer; performing a second ion implantation process so that second ions obliquely enter the second depression from a second side of the second depression to form at least a second damaged region in the first isolation material layer, where the first side and the second side of the second depression are opposite to each other; performing a decoupled plasma process to transform a part of the first damaged region and a part of the second damaged region into a protection layer, where the protection layer has an etching selectivity with respect to the first damaged region and the second damaged region; and removing the first damaged region and the second damaged region, where the isolation structure at least includes the remaining first isolation material layer.

[0005] In another aspect of the present disclosure, a method for manufacturing an isolation structure is provided, including: forming a first trench and a second trench on a surface of a substrate, wherein a width of the second trench is greater than a width of the first trench; forming a mask pattern on the substrate, wherein the mask pattern has a first opening communicating with the first trench and a second opening communicating with the second trench; filling a first isolation material layer into the first trench and the first opening communicating with each other and the second trench and the second opening communicating with each other, wherein a surface of the first isolation material layer defines a first depression; filling a second isolation material layer into the first depression; removing a part of the second isolation material layer and a part of the first isolation material layer to form a third depression in the first opening and a fourth depression in the second opening; performing a first ion implantation process to make first ions obliquely incident on the third depression and the fourth depression from a first side of the third depression and the fourth depression to form at least a first damaged region in the first isolation material layer; performing a second ion implantation process to make second ions obliquely incident on the third depression and the fourth depression from a second side of the third depression and the fourth depression to form at least a second damaged region in the first isolation material layer, wherein the first side and the second side of each of the third depression and the fourth depression are opposite to each other; performing a decoupled plasma treatment to transform some parts of the first damaged region and the second damaged region into a protection layer, wherein the protection layer has an etching selectivity with respect to the first damaged region and the second damaged region; and removing the first damaged region and the second damaged region, wherein the isolation structure at least includes the remaining first isolation material layer.

[0006] In yet another aspect of the present disclosure, an isolation structure is provided, including: an isolation material layer filled in a trench of a substrate; and a protection layer having two parts covering edges of opposite sides of the isolation material layer, wherein the two parts of the protection layer are laterally separated from each other, and the protection layer has an etching selectivity with respect to the isolation material layer.

[0007] Based on the above, the present disclosure provides an isolation structure and a method for manufacturing the same. In particular, before the second etching process in the manufacturing process of the isolation structure, damaged regions having a higher etching rate compared to other parts of the isolation material layer are formed on the top of the isolation material layer by an oblique ion implantation process from left to right and from right to left. In addition, some parts of the damaged regions are transformed into a protection layer with a denser structure by a decoupled plasma treatment. The protection layer is located at the bottom of the damaged region and covers the top corners of the active regions. Based on the etching rate of the protection layer being lower than that of the damaged region, the protection layer can protect the top corners of the active regions when removing the damaged regions, thereby preventing the performance of electronic components subsequently formed on the active regions from being affected. Description of the Drawings

[0008] Figure 1 is a flowchart of a method for manufacturing an isolation structure according to some embodiments of the present disclosure.

[0009] Figures 2A to 2J is Figure 1 a cross-sectional schematic view of each stage during the manufacturing method of

[0010] Figure 3 is a plan view of an isolation structure and a mask pattern in a memory cell region illustrated according to some embodiments of the present disclosure.

[0011] Figure 4 is a cross-sectional schematic view of an isolation structure illustrated according to some embodiments of the present disclosure.

[0012] Figure 5A is a cross-sectional schematic view of a memory element formed in a memory cell region according to some embodiments of the present disclosure.

[0013] Figure 5B is a plan view of a memory element formed in a memory cell region according to some embodiments of the present disclosure. Detailed Description

[0014] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0015] Figure 1 is a flowchart of a method for manufacturing an isolation structure according to some embodiments of the present disclosure. Figures 2A to 2J is Figure 1 a cross-sectional schematic view of each stage during the manufacturing method of

[0016] Please refer to Figure 1 and Figure 2A, perform step S100 to provide a substrate 100. In some embodiments, the substrate 100 is a semiconductor wafer or a semiconductor-on-insulator (SOI) wafer. For example, the semiconductor material in the semiconductor wafer or SOI wafer can be an elemental semiconductor (such as Si), an alloy semiconductor (such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like), or a compound semiconductor (such as SiC, GaAs, GaP, InAs, InSb, or the like). In addition, the substrate 100 can be divided into a memory cell region CR and a peripheral circuit region PR. After a series of processes, a plurality of memory elements can be formed within the scope of the memory cell region CR, and a circuit for controlling these memory elements can be formed within the scope of the peripheral circuit region PR. Compared with the elements in the peripheral circuit region PR, the active regions of the plurality of memory elements located in the memory cell region CR are quite dense, and the spacing between them is quite small. Therefore, the width of the isolation structure used to isolate these memory elements is significantly smaller than the width of the isolation structure in the peripheral circuit region PR.

[0017] Perform step S102 to form trenches 102a in the memory cell region CR and trenches 102b in the peripheral circuit region PR. The trenches 102a are used to accommodate the isolation structure (such as the isolation structure 114a shown) formed in the memory cell region CR in subsequent steps, while the trenches 102b are used to accommodate the isolation structure (such as the isolation structure 114b shown) formed in the peripheral circuit region PR in subsequent steps. Thus, it can be seen that the trenches 102a can define the active region AA1 in the memory cell region CR, and the trenches 102b can define the active region AA2 in the peripheral circuit region PR. The width W of the trench 102a for accommodating the isolation structure in the memory cell region CR Figure 2J can be significantly smaller than the width W of the trench 102b for accommodating the isolation structure in the peripheral circuit region PR. Figure 2J For example, the ratio of the width W to the width W 102a can be in the range of 2.8 to 3.3. 102b . For example, the width W 102b to the width W 102a can be in the range of 2.8 to 3.3. Figure 2B The illustrated trench 102b can be part of a continuously extending trench or can be one of a plurality of separate trenches.

[0018] Please refer to Figure 1 and Figure 2B, perform step S104 to form a liner layer 104 on the substrate 100. The liner layer 104 completely and conformally covers the substrate 100. In other words, the topmost surface of the substrate 100 and the surfaces of the trenches 102a and 102b are all covered by the liner layer 104. The liner layer 104 may be composed of an insulating material (such as silicon oxide). In some embodiments, the surface layer portion of the substrate 100 can be oxidized through an oxidation process to form the liner layer 104. In alternative embodiments, the liner layer 104 can also be formed on the substrate 100 through a deposition process (such as a chemical vapor deposition (CVD) process).

[0019] Please refer to Figure 1 and Figure 2C , perform step S106 to form a mask pattern 106 on the topmost surface of the substrate 100. The main body portion of the mask pattern 106 is located outside the trenches 102a and 102b, and the mask pattern 106 has openings P1 and P2 that communicate with the trenches 102a and 102b respectively. In some embodiments, the width W of the opening P1 P1 is greater than the maximum value of the width W of the trench 102a 102a (as Figure 2B shown), and the width W of the opening P2 P2 is greater than the maximum value of the width W of the trench 102b 102b (as Figure 2B shown). In some embodiments, the material of the mask pattern 106 includes (but is not limited to) silicon nitride.

[0020] Please refer to Figure 1 and Figure 2D, perform step S108 to form a first isolation material layer 108a and a first isolation material layer 108b. The first isolation material layer 108a is disposed in the trench 102a and the opening P1, while the first isolation material layer 108b is disposed in the trench 102b and the opening P2. The first isolation material layer 108a only covers the sidewalls of the opening P1 without filling the opening P1, and the surface of the first isolation material layer 108a can define a depression RS1. The bottommost end of the depression RS1 can be slightly lower than, flush with, or slightly higher than the topmost surface of the substrate 100. Similarly, the first isolation material layer 108b also only covers the sidewalls of the opening P2 without filling the opening P2. In addition, since the width of the trench 102b is wider (compared to the trench 102a), the bottommost end of the depression RS2 defined by the first isolation material layer 108b can be significantly lower than the topmost surface of the substrate 100. In other words, the depth of the depression RS2 can be greater than the depth of the depression RS1. In addition, based on the widths of the trench 102b and the opening P2 being significantly greater than the widths of the trench 102a and the opening P1, the width of the depression RS2 can also be significantly greater than the width of the depression RS1. In some embodiments, the first isolation material layer 108a and the first isolation material layer 108b are composed of silicon oxide (such as enhanced high aspect ratio process (eHARP) oxide). In addition, in some embodiments, the first isolation material layer 108a and the first isolation material layer 108b can be formed by a deposition process and a planarization process. The deposition process for forming the first isolation material layer 108a and the first isolation material layer 108b can be a CVD process, such as the so-called enhanced high aspect ratio trench filling process.

[0021] Please refer to Figure 1 , Figure 2D and Figure 2E, perform step S110 to fill the second isolation material layers 110a and 110b into the recesses RS1 and RS2 defined by the first isolation material layer 108a and the first isolation material layer 108b, respectively. The second isolation material layer 110a can fill the recess RS1, and the second isolation material layer 110b can fill the recess RS2. In some embodiments, the second isolation material layer 110a and the second isolation material layer 110b can be composed of silicon oxide (such as spin-on glass (SOG)). In the embodiments where the second isolation material layer 110a and the second isolation material layer 110b are composed of SOG, the liquid silicon oxide material can be filled into the recesses RS1 and RS2 by a spin coating process, and the solvent in the liquid silicon oxide material can be removed by a curing process to transform it into a solid structure. Subsequently, the portion of this solid structure located above the top surface of the mask pattern 106 can be removed by a planarization process (such as a CMP process). The remaining portion of this solid structure located within the recess RS1 forms the second isolation material layer 110a, and the remaining portion of this solid structure located within the recess RS2 forms the second isolation material layer 110b. Based on the width of the recess RS1 being significantly smaller than the width of the recess RS2, it is more difficult to completely remove the solvent of the liquid silicon oxide material located within the recess RS1 during the curing process. In the subsequent etching process, the etchant can more easily enter the interface between the first isolation material layer 108a and the second isolation material layer 110a, resulting in the etching rate of the second isolation material layer 110a being slightly higher than the etching rate of the second isolation material layer 110b.

[0022] Please refer to Figure 1 and Figure 2F, perform step S112 to partially remove the first isolation material layer 108a and the second isolation material layer 110a, and partially remove the first isolation material layer 108b and the second isolation material layer 110b. In this way, a recess RS3 extending downward from the topmost surface of the first isolation material layer 108a and the top surface of the second isolation material layer 110a is formed, and a recess RS4 extending downward from the topmost surface of the first isolation material layer 108b and the top surface of the second isolation material layer 110b is formed. In other words, the upper portions of the first isolation material layer 108a and the second isolation material layer 110a are removed, and the upper portions of the first isolation material layer 108b and the second isolation material layer 110b are removed. The width of the recess RS3 is slightly smaller than the width of the opening P1 of the mask pattern 106, and a part of the first isolation material layer 108a still covers the sidewall of the mask pattern 106 and defines the sidewall of the recess RS3. Similarly, the width of the recess RS4 can be slightly smaller than the width of the opening P2 of the mask pattern 106, and a part of the first isolation material layer 108b still covers the sidewall of the mask pattern 106 and defines the sidewall of the recess RS4. On the other hand, the bottommost ends of the recess RS3 and the recess RS4 are higher than the topmost surface of the substrate 100 to avoid damaging the active regions AA1 and AA2 during the formation of the recess RS3 and the recess RS4. In some embodiments, the recesses RS3 and RS4 can be formed by an isotropic etching process (such as a wet etching process). Based on the etching rate of the second isolation material layer 110a being higher than the etching rate of the second isolation material layer 110b (as described with reference to Figure 2E ), the depth of the recess RS3 is greater than the depth of the recess RS4. In an embodiment where the first isolation material layer 108a and the first isolation material layer 108b are made of eHARP silicon oxide and the second isolation material layer 110a and the second isolation material layer 110b are made of SOG, the etching rates of the first isolation material layer 108a and the first isolation material layer 108b are slightly lower than the etching rates of the second isolation material layer 110a and the second isolation material layer 110b. In this way, the second isolation material layer 110a and the second isolation material layer 110b retain portions covering the sidewalls of the mask pattern 106.

[0023] Please refer to Figure 1 and Figure 2G, step S114 is performed to execute a first ion implantation process. During the first ion implantation process, ions I are obliquely incident, for example, from the left side. In this way, the first isolation material layer 108a and the second isolation material layer 110a exposed to the right half of the recess RS3 are ion implanted, while the first isolation material layer 108a and the second isolation material layer 110a exposed to the left half of the recess RS3 are not ion implanted because they are shielded by the mask pattern 106. The ion-implanted portions of the first isolation material layer 108a and the second isolation material layer 110a are ion damaged, and a first damaged region D1a with a higher etching rate (compared to the non-ion-damaged portions) is formed. Similarly, at the recess RS4, the unshielded portions of the first isolation material layer 108b and the second isolation material layer 110b are ion implanted to form a first damaged region D1b with a higher etching rate. Since the recess RS4 is wider than the recess RS3, the unshielded portion of the recess RS4 is larger than the unshielded portion of the recess RS3. Therefore, the range of the first damaged region D1b is larger than the range of the first damaged region D1a. In addition, by controlling the depth of ion implantation, the bottommost ends of the first damaged region D1a and the first damaged region D1b can be slightly higher than, flush with, or slightly lower than the topmost surface of the substrate 100. On the other hand, the surface layer portion of the mask pattern 106 is also ion implanted, so a damaged region 106' with a higher etching rate is also formed. In an embodiment where the first isolation material layer 108a, the first isolation material layer 108b, the second isolation material layer 110a, and the second isolation material layer 110b are made of silicon oxide and the semiconductor material of the substrate 100 is silicon, the atomic number of the element included in the ions I is greater than the atomic number of oxygen but less than the atomic number of silicon. In this way, the ions I can be implanted into the first isolation material layer and the second isolation material layer without damaging the active regions AA1 and AA2 of the substrate 100.

[0024] Please refer to Figure 1 and Figure 2H, step S116 is performed to execute a second ion implantation process. During the second ion implantation process, ions I are obliquely incident, for example, from the right side. In this way, the first isolation material layer 108a and the second isolation material layer 110a exposed to the left half of the recess RS3 are ion implanted to form a second damage region D2a having a higher etching rate (compared to the un-ion implanted portion). On the other hand, at the recess RS4, the portions of the first isolation material layer 108b and the second isolation material layer 110b not shielded by the mask pattern 106 are ion implanted to form a second damage region D2b having a higher etching rate. By, for example, controlling the depth of ion implantation, the bottommost ends of the second damage region D2a and the second damage region D2b can be slightly higher than, flush with, or slightly lower than the topmost surface of the substrate 100. The first damage region D1a formed during the first ion implantation process and the second damage region D2a formed during the second ion implantation process can be connected to each other to form a continuous damage region Da. Similarly, the first damage region D1b formed during the first ion implantation process and the second damage region D2b formed during the second ion implantation process can be connected to each other to form a continuous damage region Db. In addition, in an embodiment where the liner layer 104 is formed by an oxidation process, the liner layer 104 has a denser structure and is not damaged by ions during the first and second ion implantation processes, and can further protect the active regions AA1 and AA2. In some embodiments, the first and second ion implantation processes use the same ions. In addition, in the first and second ion processes, the angles between the incident directions of the ions I and the vertical direction can be in the range of 50° to 80° respectively.

[0025] Please refer to Figure 1 and Figure 2I , step S118 is performed to convert some portions of the damage region Da and the damage region Db into a protection layer 112a and a protection layer 112b. Compared with the damage region Da and the damage region Db, the protection layer 112a and the protection layer 112b are formed into a denser structure, and the composition is slightly different from that of the damage region Da and the damage region Db. Therefore, the protection layer 112a and the protection layer 112b have an etching selectivity with respect to the damage region Da and the damage region Db. The formation of the protection layer 112a and the protection layer 112b is from the ions implanted by the first ion implantation process and the second ion implantation process (i.e., Figure 2G and Figure 2HThe ions shown in I) are generated by the reaction of the implanted material layer (i.e., the first isolation material layer or the first and second isolation material layers). Therefore, the above reaction occurs at the location where the implanted ion concentration is relatively high. For the relatively narrow recess RS3, the locations with relatively high ion concentrations are on the left and right sides of the recess RS3. On the other hand, for the relatively wide recess RS4, the locations with relatively high ion concentrations are spread over the bottom of the recess RS4. In some embodiments, the reaction between the implanted ions and the implanted material layer is initiated by a decoupled plasma treatment. In these embodiments, the above reaction is likely to occur at the bottom of the implanted material layer rather than at the surface of the implanted material layer. For the recess RS3, the protective layer 112a is formed above the edge of the trench 102a and covers the portion of the active region AA1 located between the mask pattern 106 and the trench 102a. In this way, the protective layer 112a can protect the active region AA1 in the subsequent etching steps. In addition, the protective layer 112a can further extend above the trench 102a and cover a part of the first isolation material layer 108a. On the other hand, at the recess RS4, the protective layer 112b continuously extends above the trench 102b and extends above the edge of the trench 102b. In other words, the protective layer 112b covers the first isolation material layer 108b and the second isolation material layer 110b in the trench 102b and covers the portion of the active region AA2 located between the mask pattern 106 and the trench 102b. In this way, the protective layer 112b can protect the active region AA2 in the subsequent etching steps. In the embodiment where the implanted ion element is nitrogen, the protective layer 112a and the protective layer 112b can be formed by performing a decoupled plasma nitridation (DPN) treatment. When the materials of the first isolation material layer (the first isolation material layer 108a, the first isolation material layer 108b) and the second isolation material layer (the second isolation material layer 110a, the second isolation material layer 110b) are silicon oxide, the protective layer 112a and the protective layer 112b formed by the DPN treatment can include silicon oxynitride. On the other hand, the components of the remaining damaged regions Da and Db can mainly be silicon oxide and may or may not be doped with a trace amount of nitrogen element. In some embodiments, the temperature of the decoupled plasma treatment is in the range of about 550 °C to about 750 °C, and the time of the decoupled plasma treatment is in the range of about 0.5 minutes to about 1 minute.

[0026] Please refer to Figure 1 and Figure 2J, step S120 is performed to remove the damaged regions Da and Db. After removing the damaged regions Da and Db, the protective layers 112a, 112b and the first isolation material layer 108a that has not been damaged by ion implantation are exposed. The remaining portions of the protective layer 112a and the first isolation material layer 108a can jointly serve as the isolation structure 114a within the memory cell region CR. On the other hand, the remaining portions of the protective layer 112b and the first isolation material layer 108b can jointly serve as the isolation structure 114b within the peripheral circuit region PR. In some embodiments, the isolation structure 114a within the memory cell region CR may further include the remaining portion of the second isolation material layer 110a, and the isolation structure 114b within the peripheral circuit region PR may further include the remaining portion of the second isolation material layer 110b. The method of removing the damaged regions Da and Db may include performing an isotropic etching process (such as a wet etching process). As can be seen from the above, compared with the protective layers 112a and 112b, the damaged regions Da and Db are more easily etched due to the damaged structure. In addition, due to the decoupling plasma treatment, the compositions of the protective layers 112a and 112b are slightly different from those of the damaged regions Da and Db, so the etching selectivity of the protective layers 112a and 112b relative to the damaged regions Da and Db can be further increased. In this way, when removing the damaged regions Da and Db, the protective layers 112a and 112b can be at least partially retained and can protect the underlying layer 104 and the active regions AA1, AA2 covered by them. In certain cases, the protective layers 112a and 112b are also removed together with the damaged regions Da and Db. Nevertheless, the etching rate of the protective layers 112a and 112b can still be lower than that of the damaged regions Da and Db, and can protect the active regions AA1, AA2 during the etching process. On the other hand, the damaged region 106' of the mask pattern 106 will be removed during the removal of the damaged regions Da and Db. In addition, other portions of the mask pattern 106 can be retained because they are not damaged and have an etching selectivity ratio with respect to the first and second isolation material layers.

[0027] Figure 3 is a plan view of the isolation structure 114a and the mask pattern 106 within the memory cell region CR illustrated according to some embodiments of the present disclosure. It should be noted that Figure 3 the illustration of the second isolation material layer 110a in the isolation structure 114a is omitted. In addition, Figure 2J the cross-sectional view shown can be a cross-sectional view along Figure 3 line A-A' of

[0028] Please refer to Figure 2J and Figure 3, in an embodiment where the active region AA1 is elongated, the trench 102a for defining the active region AA1 is also elongated (or has an elongated portion), and the mask pattern 106 covering the active region AA1 is also elongated. In these embodiments, the protective layer 112a extending between the mask pattern 106 and the trench 102a presents an elongated top view pattern.

[0029] Figure 4 is a cross-sectional schematic view of the isolation structures 214a and 214b illustrated in accordance with some embodiments of the present disclosure. The isolation structures 214a and 214b are similar to Figure 2J the isolation structures 114a and 114b shown. Only the differences will be described below, and the same or similar parts will not be repeated. In addition, similar element symbols represent the same or similar components.

[0030] Please refer to Figure 4 , the isolation structure 214a includes a first isolation material layer 208a and a protective layer 212a, and the isolation structure 214b includes a first isolation material layer 208b and a protective layer 212b. In some embodiments, the isolation structure 214a further includes a second isolation material layer 210a, and the isolation structure 214b further includes a second isolation material layer 210b. The top surface of the first isolation material layer 208a (or the first isolation material layer 208a and the second isolation material layer 210a) is lower than the topmost surface of the substrate 100. On the other hand, the top surface of the first isolation material layer 208b (or the first isolation material layer 208b and the second isolation material layer 210b) is substantially flush with the topmost surface of the substrate 100. It can be seen that, in the steps as described with reference to Figure 2F , the second isolation material layer 210a in the memory cell region CR has a higher etching rate (compared to the second isolation material layer 210b in the peripheral circuit region PR), such that the bottommost end of the formed depression RS3 is lower to a greater extent than the bottommost end of the depression RS4. In this way, in the steps as described with reference to Figure 2G and Figure 2H , the bottommost surface of the formed damage region Da can be lower than the topmost surface of the substrate 100, and the bottommost surface of the damage region Db can be substantially flush with the topmost surface of the substrate 100. Subsequently, in the steps as described with reference to Figure 2I , the formed protective layer 212a can extend upward from the top surface of the first isolation material layer 208a along the sidewall of the trench 102a to the topmost surface of the substrate 100. On the other hand, the protective layer 212b covers the top surface of the first isolation material layer 208b (or the first isolation material layer 208b and the second isolation material layer 210b), and extends to the topmost surface of the substrate 100. In other words, Figure 2I , Figure 2JThe shown protective layer 112a only covers the top surface of the active region AA1 located between the edge of the trench 102a and the mask pattern 106 and does not extend to the sidewalls of the active region AA1. On the other hand, Figure 4 The shown protective layer 212a further extends to the sidewalls of the active region AA1 and completely covers the top corners of the active region AA1.

[0031] Figure 5A is a cross-sectional schematic view of a memory element MC formed in a memory cell region CR according to some embodiments of the present disclosure. Figure 5B is a plan schematic view of a memory element MC formed in a memory cell region CR according to some embodiments of the present disclosure. It should be noted that, Figure 5B the illustration of the second isolation material layer 110a as shown in Figure 2J is omitted. In addition, Figure 5A the shown cross-sectional schematic view can be a cross-sectional schematic view along the line B - B' of Figure 5B .

[0032] Please refer to Figure 5A and Figure 5B . After forming the isolation structure (such as the isolation structures 114a and 114b as shown in Figure 2J ), the mask pattern 106 can be removed, and a memory element MC (or memory cell) can be formed on the active region AA1. The memory element MC includes a gate structure. The gate structure can include a tunneling dielectric layer 116, a floating gate 118, an inter-gate dielectric layer 120, and a control gate 122. The method of forming the gate structure can include removing some portions of the liner layer 104 to expose a plurality of active regions AA1. Then, the tunneling dielectric layer 116 and the floating gate 118 are formed on these exposed active regions AA1. In subsequent steps, the inter-gate dielectric layer 120 and the control gate 122 can be formed. The control gate 122 and the inter-gate dielectric layer 120 thereunder can continuously extend along a direction intersecting the extending direction of the active region AA1. In other words, the inter-gate dielectric layer 120 and the control gate 122 can cover some portions of the isolation structure 114a. In some embodiments, after forming the memory element MC, the protective layer 112a can still be retained and partially covered by the inter-gate dielectric layer 120 and the control gate 122. In alternative embodiments, the protective layer 112a is removed during the formation of the memory element MC. On the other hand, the tunneling dielectric layer 116 and the floating gate 118 are located between the control gate 122 and the active region AA1 and do not cover the isolation structure 114a. In reference to Figure 5A and Figure 5BIn the described embodiments, the memory element MC (or memory cell) can be a flash memory element. Additionally, it can be formed into a NAND flash memory or a NOR flash memory by changing the configuration of the signal lines. In addition, Figure 5A the isolation structure 114a shown can also be replaced with, for example, Figure 4 the isolation structure 214a shown.

[0033] In summary, during the manufacturing process of the isolation structure, the height of the isolation material layer is adjusted through two etching processes to form the final trench isolation structure. In the first etching process, the isolation material layer is etched to a height slightly higher than the top surface of the substrate. Before the second etching process, a damaged area with a higher etching rate compared to other parts of the isolation material layer is formed at the top of the isolation material layer through a pair of left and right oblique ion implantation processes. Additionally, some parts of the damaged area are transformed into a more dense protective layer through decoupling plasma treatment. The protective layer is located at the bottom of the damaged area and covers the top corners of the active area. In addition, the etching rate of the protective layer can be lower than that of the damaged area. In the second etching process, the damaged area is removed to form the final isolation structure. Based on the fact that the etching rate of the protective layer is lower than that of the damaged area, the protective layer can protect the top corners of the active area when the damaged area is removed, preventing the etchant from invading the active area from these top corners. Therefore, it is possible to avoid affecting the performance of the electronic components subsequently formed on the active area.

[0034] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A manufacturing method of an isolation structure, characterized in that Comprising: Forming trenches on the surface of a substrate; Forming a mask pattern on the substrate, wherein the mask pattern has an opening communicating with the trench; Filling a first isolation material layer into the trench and the opening, wherein the surface of the first isolation material layer defines a first recess; Filling a second isolation material layer into the first recess; Removing a part of the second isolation material layer and a part of the first isolation material layer to form a second recess in the opening of the mask pattern; Performing a first ion implantation process to obliquely incident first ions into the second recess from a first side of the second recess to form at least a first damaged region in the first isolation material layer; Performing a second ion implantation process to obliquely incident second ions into the second recess from a second side of the second recess to form at least a second damaged region in the first isolation material layer, wherein the first side and the second side of the second recess are opposite to each other; Performing a decoupled plasma treatment to transform a part of the first damaged region and a part of the second damaged region into a protection layer, wherein the protection layer has an etching selectivity relative to the first damaged region and the second damaged region; And Removing the first damaged region and the second damaged region, wherein the isolation structure at least includes the remaining first isolation material layer.

2. The manufacturing method of the isolation structure according to claim 1, characterized in that, Filling the first isolation material layer by enhancing the high aspect ratio trench filling process, and wherein the method of filling the second isolation material layer into the first recess includes: Filling the first recess with a liquid insulating material by a spin coating process; and Solidifying the liquid insulating material to form the second isolation material layer.

3. The manufacturing method of the isolation structure according to claim 1, characterized in that The bottommost end of the second recess is higher than the topmost surface of the substrate, a part of the first isolation material layer defines the sidewall of the second recess, and the top surface of the second isolation material layer defines the bottom surface of the second recess.

4. The manufacturing method of the isolation structure according to claim 1, characterized in that, The first damaged region extends from below the second recess to the second side of the second recess, the second damaged region extends from below the second recess to the first side of the second recess, and the first damaged region and the second damaged region are connected to each other.

5. The manufacturing method of the isolation structure according to claim 1, characterized in that When performing the decoupled plasma treatment, the protection layer is formed at the bottoms of the first damaged region and the second damaged region.

6. The manufacturing method of the isolation structure according to claim 1, wherein, Two parts of the protection layer cover the edges on opposite sides of the trench and cover the part of the substrate located between the edge of the trench and the mask pattern, and the two parts of the protection layer are laterally separated from each other.

7. The manufacturing method of the isolation structure according to claim 1, characterized in that After removing the first damaged region and the second damaged region, at least part of the protection layer is retained, and the isolation structure further includes the protection layer.

8. A manufacturing method of an isolation structure, characterized in that Comprising: Forming a first trench and a second trench on the surface of a substrate, wherein the width of the second trench is greater than the width of the first trench; Forming a mask pattern on the substrate, wherein the mask pattern has a first opening communicating with the first trench and a second opening communicating with the second trench; Fill a first isolation material layer in the first trench and the first opening that communicate with each other, and in the second trench and the second opening that communicate with each other, wherein the surface of the first isolation material layer defines a first depression; Fill the second isolation material layer into the first depression; Remove a part of the second isolation material layer and a part of the first isolation material layer to form a third depression in the first opening and a fourth depression in the second opening; Perform a first ion implantation process to make the first ions obliquely incident on the third depression and the fourth depression from the first side of the third depression and the fourth depression, so as to form a first damaged region at least in the first isolation material layer; Perform a second ion implantation process to make the second ions obliquely incident on the third depression and the fourth depression from the second side of the third depression and the fourth depression, so as to form a second damaged region at least in the first isolation material layer, wherein the first side and the second side of each of the third depression and the fourth depression are opposite to each other; Perform a decoupled plasma treatment to transform some parts of the first damaged region and the second damaged region into a protection layer, wherein the protection layer has an etching selectivity with respect to the first damaged region and the second damaged region; And Remove the first damaged region and the second damaged region, wherein the isolation structure at least includes the remaining first isolation material layer.

9. The manufacturing method of the isolation structure according to claim 8, characterized in that, When performing the decoupled plasma treatment, the protection layer formed in the first opening includes two laterally separated parts, and the protection layer formed in the second opening continuously extends to cover the second trench.

10. A memory element, characterized in that, Comprising: An isolation structure, comprising: An isolation material layer filled in a trench of a substrate; and A protection layer having two parts covering the edges of opposite sides of the isolation material layer, wherein the two parts of the protection layer are laterally separated from each other and respectively extend on the topmost surface of the isolation material layer, and the protection layer has an etching selectivity with respect to the isolation material layer; and A floating gate located above the topmost surface of the substrate, wherein the protection layer is formed by causing implanted ions to react with the isolation material layer through a decoupled plasma treatment.

11. The memory element according to claim 10, wherein The protection layer further covers the topmost surface of the substrate.

12. The memory element according to claim 11, wherein The protection layer further covers the sidewall of the trench, and the top surface of the isolation material layer is lower than the topmost surface of the substrate, and the protection layer completely covers the top corner of the substrate located at the edge of the trench.

13. The memory element according to claim 10, wherein The isolation material layer includes a first isolation material layer and a second isolation material layer, the surface of the first isolation material layer has a depression, and the second isolation material layer fills the depression, and the protection layer covers a part of the first isolation material layer.

14. The memory element according to claim 13, wherein The first isolation material layer and the second isolation material layer are made of silicon oxide, and the protection layer is made of silicon oxynitride.

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