Implantable isolation for device integration on a generic substrate

Abstract

This application relates to implantable isolation for device integration on a generic substrate, and discloses a structure including a device, such as a transistor, integrated on a semiconductor substrate, and a method of forming a structure including a device, such as a transistor, integrated on a semiconductor substrate. A first transistor is formed in a first device region of the semiconductor substrate, and a second transistor is formed in a second device region of the semiconductor substrate. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer composed of a group III-V compound semiconductor material. A poly layer includes a segment in the semiconductor substrate below the first device region.

Description

Technical Field

[0001] The present invention relates to semiconductor device manufacturing and integrated circuits, and more particularly, to structures including devices (e.g., transistors) integrated on a semiconductor substrate and methods for forming such structures. Background Technology

[0002] High-voltage power electronic devices, such as high electron mobility transistors (HEP transistors), can be fabricated using III-V compound semiconductors to take advantage of their material properties, such as carrier mobilities greater than those of silicon. III-V compound semiconductors include group III elements (aluminum, gallium, indium) and group V elements (nitrogen, phosphorus, arsenic, antimony). HEP transistors can comprise heterojunctions between crystalline III-V compound semiconductor materials with different band gaps, such as a heterojunction between binary gallium nitride and ternary aluminum-gallium nitride. During operation, a two-dimensional electron gas forms near the interface of the heterojunction and defines the channel of the HEP transistor.

[0003] The integration of high electron mobility transistors (HEMTs) with field-effect transistors (FETs) or heterojunction bipolar transistors formed on the same chip via complementary metal-oxide-semiconductor (CMOS) processing has proven to be a complex process because, for example, electrical isolation between the different devices is required. Integration can be achieved through wafer bonding or by using engineered or hybrid substrates, which inherently introduces significant complexity to the process of integrating HEMTs with these other types of transistors.

[0004] The need is for improved structures, including devices integrated on semiconductor substrates, such as transistors, and methods for forming such structures. Summary of the Invention

[0005] In one embodiment of the invention, a structure includes a semiconductor substrate having first and second device regions, a first transistor in the first device region, and a second transistor in the second device region. The second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes layers made of a III-V compound semiconductor material. The structure also includes a polycrystalline layer having segments in the semiconductor substrate located below the first device region.

[0006] In one embodiment of the invention, a method includes forming a polycrystalline layer having a segment located below a first device region of a semiconductor substrate, forming a first transistor in the first device region of the semiconductor substrate, forming a layer stack comprising layers made of a III-V compound semiconductor material in a second device region of the semiconductor substrate, and using the layer stack to form a second transistor. Attached Figure Description

[0007] The accompanying drawings, which are included in and constitute a part of this specification, illustrate various embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, the same reference numerals denote the same features in different views.

[0008] Figures 1 to 3 This is a cross-sectional view of the structure in the continuous manufacturing stage of the processing method according to an embodiment of the present invention.

[0009] Figure 3A This is according to an embodiment of the present invention. Figure 3 An enlarged cross-sectional view of a portion of the image.

[0010] Figures 4 to 6 Is Figure 3 A cross-sectional view of the structure in the subsequent continuous manufacturing stage of the processing method.

[0011] Figure 6A This is according to an embodiment of the present invention. Figure 6 An enlarged cross-sectional view of a portion of the image.

[0012] Figures 7 to 8 Is Figure 6 A cross-sectional view of the structure in the subsequent continuous manufacturing stage of the processing method.

[0013] Figure 8A This is according to an embodiment of the present invention. Figure 8 An enlarged sectional view of a portion of the document.

[0014] Figure 9 and Figure 10 This is a cross-sectional view of the structure according to an alternative embodiment of the present invention. Detailed Implementation

[0015] refer to Figure 1According to embodiments of the present invention, a semiconductor substrate 10 comprising a single-crystal semiconductor material (e.g., single-crystal silicon) is provided. The semiconductor substrate 10 has a top surface 12, which may be planar. The semiconductor substrate 10 may be a bulk substrate comprising a single-crystal semiconductor material (e.g., single-crystal silicon). In one embodiment, the single-crystal semiconductor material of the semiconductor substrate 10 may have a diamond lattice structure having a structure specified by the Miller indices. <111> Crystal orientation. In one embodiment, the semiconductor substrate 10 may include a crystal orientation having <111> Single-crystal silicon with a diamond lattice structure and specific crystal orientation. For those with... <111> The semiconductor substrate 10 has a (111) crystal plane parallel to the top surface 12 of the semiconductor substrate 10, and the

[111] crystal orientation is perpendicular to the (111) plane. The (100) crystal axis is not located in the plane of the top surface 12. The semiconductor substrate 10 can be characterized as a non-silicon-on-insulator (SOI) substrate, which lacks the buried oxide layer characteristics of a silicon-on-insulator (SOI) substrate. In one embodiment, the semiconductor substrate 10 can be entirely composed of a

[111] crystal plane parallel to the top surface 12 of the semiconductor substrate 10, and the

[111] crystal orientation is perpendicular to the (111) plane. <111> Semiconductor materials with crystal orientation.

[0016] A shallow trench isolation region 14 is formed extending from the top surface 12 of the semiconductor substrate 10 into the semiconductor substrate 10. The shallow trench isolation region 14 may contain a dielectric material deposited by chemical vapor deposition into trenches etched, polished, and deglazed in the semiconductor substrate 10. The dielectric material contained in the shallow trench isolation region 14 may include silicon dioxide, silicon nitride, silicon carbide, silicon-rich silicon dioxide, or a combination of two or more of these materials. The shallow trench isolation region 14 may extend to a depth d1 in the semiconductor substrate 10 relative to the top surface 12. The shallow trench isolation region 14 surrounds and defines a plurality of device regions 16, 18, 20, and the shallow trench isolation region 14 is laterally located between different device regions 16, 18, 20. In one embodiment, the top surface 12 in device region 18 may be coplanar with the top surface 12 in device region 16 or coplanar with the top surface 12 in device region 20.

[0017] A solder pad layer 21, which may be made of silicon nitride, is located on the top surface 12 of all device regions 16, 18, and 20. The solder pad layer 21 may be a remnant of a hard mask used for patterning the trenches in which the shallow trench isolation regions 14 are formed. In a conventional process flow, the solder pad layer 21 is removed after the shallow trench isolation regions 14 are formed.

[0018] refer to Figure 2 The similar reference numerals in the attached figures refer to... Figure 1Similar features are formed in the semiconductor substrate 10 in the device region 18, and trenches 30 are formed in the subsequent manufacturing stages of the processing method. For this purpose, the pad layer 21 is patterned by photolithography and etching processes and removed from the device region 18 to define an opening that is normally located above the device region 18, thereby exposing the top surface 12 of the semiconductor substrate 10 in the device region 18.

[0019] A trench 30 is formed at an opening in the pad layer 21 of the semiconductor substrate 10 using an etching process, such as reactive ion etching. The trench 30 may extend to a trench bottom 32 that coexists with the surface of the semiconductor substrate 10 and may have side surfaces or sidewalls 29, 31. A portion of the semiconductor substrate 10 is disposed between the trench 30 and an adjacent shallow trench isolation region 14. The surface 32 of the trench bottom may be located in the semiconductor substrate 10 at a depth d2 relative to the top surface 12, said depth d2 being greater than the depth d1 of the shallow trench isolation region 14. The pad layer 21, optionally used as a photoresist for patterning the trench 30, protects the semiconductor substrate 10 in the device region 16 and device region 20 during the etching process. In one embodiment, the surface 32 of the trench bottom may be planar and without topography. In one embodiment, the top surface 12 may be planar, the surface 32 of the trench bottom may be planar, and the planes of the top surface 12 and surface 32 may be parallel.

[0020] Sidewall spacers 34 are formed adjacent to the sidewalls 29, 31 of the trench 30. The sidewall spacers 34 can extend from the top surface 12 of the semiconductor substrate 10 to the bottom surface 32 of the trench 30. The sidewall spacers 34 can be formed by depositing a pad layer made of a dielectric material (e.g., silicon nitride) and etching the deposited pad layer using an anisotropic etching process such as reactive ion etching.

[0021] refer to Figure 3 , Figure 3A The same reference numerals refer to Figure 2The same features are used in the process, and in a subsequent manufacturing stage, a layer stack 36 comprising one or more compound semiconductor layers is formed on the surface 32 of the semiconductor substrate 10 located inside the trench 30. In one embodiment, the layer stack 36 may include at least one crystalline layer made of a III-V compound semiconductor material. In one embodiment, the layer stack 36 may include at least one crystalline layer made of a binary III-V compound semiconductor material. In one embodiment, the layer stack 36 may include at least one crystalline layer made of a ternary III-V compound semiconductor material. In one embodiment, the layer stack 36 may include multiple crystalline layers made of different III-V compound semiconductor materials. In one embodiment, the layer stack 36 may include at least one crystalline layer made of a binary III-V compound semiconductor material and at least one crystalline layer made of a ternary III-V compound semiconductor material. In one embodiment, the layer stack 36 may include one or more crystalline layers comprising gallium and nitrogen. In one embodiment, the layer stack 36 may include one or more crystalline layers comprising gallium nitride or a gallium nitride-based ternary III-V compound semiconductor material (e.g., aluminum gallium nitride).

[0022] The layer stack 36 can be formed by an epitaxial growth process. Each individual layer of the layer stack 36 can have a single-crystal crystal structure, or alternatively, a substantially single-crystal crystal structure with different levels of crystallization defects. By comparing layers with... <100> A more closely aligned crystal lattice match between the substrate and the semiconductor material (e.g., single-crystal silicon) of the semiconductor substrate 10 results in a better lattice match. <111> Crystal orientation promotes the epitaxial growth of III-V compound semiconductor materials (e.g., gallium nitride) with low crystal defect density in a layer stack 36. Specifically, it has... <111> The atoms on the surface of the crystal-oriented semiconductor substrate 10 are arranged in a hexagonal shape, which can be lattically matched quite well with the crystal structure of one or more compound semiconductor materials in the layer stack 36 (e.g., a gallium wurtzite crystal structure based on a binary hexagonal close-packed crystal system).

[0023] In one embodiment, the layer stack 36 can be formed using a selective epitaxial growth process, wherein the semiconductor material is not formed on the dielectric surface, such as the hard mask 26 and sidewall spacers 34. In one embodiment, the layer stack 36 can be formed using a non-selective epitaxial growth process, wherein the semiconductor material is deposited and patterned using photolithography and etching processes. In one embodiment, the sidewalls 37 of the layer stack 36 can be located adjacent to and spaced apart from the trench sidewalls 29, 31, and in that case, the trench 30 can be substantially filled by the layer stack 36. In a representative embodiment, the layer stack 36 has sidewalls 37 that slope inward away from the trench sidewalls 29, 31 to define, for example, a trapezoidal shape and space the sidewalls 37 from the trench sidewalls 29, 31. The sidewalls 37 can converge at the top surface 35 of the layer stack 36. In one embodiment, the top surface 35 can be coplanar or substantially coplanar with the top surface 12 of the semiconductor substrate 10. An isolation region (not shown) can be formed on the top surface 35 of the layer stack 36 by means of a mask implanted with, for example, nitrogen or argon.

[0024] In one embodiment and as follows Figure 3A As best shown, the layer stack 36 may include a buffer layer 76, a channel layer 78, a spacer layer 80, and a barrier layer 82. Layers 76, 78, 80, and 82 may be formed sequentially using an epitaxial growth process such as metal-organic chemical vapor deposition. Layers 76, 78, 80, and 82 may each have a single-crystal crystal structure, or alternatively, a substantially single-crystal crystal structure with different levels of crystal defects. One or more layers of layers 76, 78, 80, and 82 may include multiple sublayers characterized by different compositions or doping. Buffer layer 76 may contain a III-V compound semiconductor material, such as gallium nitride, which is tailored in terms of material composition, doping, and / or layer thickness to accommodate lattice mismatch between the material of the semiconductor substrate 10 and the material of the channel layer 78. The channel layer 78 disposed above buffer layer 76 may contain a III-V compound semiconductor material, such as gallium nitride. A spacer layer 80 and a barrier layer 82 are disposed above the channel layer 78, with the spacer layer 80 positioned between the channel layer 78 and the barrier layer 82. The spacer layer 80, which may be thinner than the channel layer 78, may comprise a III-V compound semiconductor, such as aluminum nitride. The barrier layer 82 may comprise a III-V compound semiconductor, such as aluminum gallium nitride, aluminum nitride, or aluminum indium nitride, providing a heterogeneous interface with the channel layer 78 of a different composition. The spacer layer 80 and the barrier layer 82, together with the material properties of the channel layer 78, facilitate the generation of a two-dimensional electron gas at a heterogeneous interface filled with high mobility and abundant electrons during device operation.

[0025] refer to Figure 4 The same reference numerals refer to Figure 3The same features are used in the subsequent manufacturing stage of the process, and the pad layer 21 is removed from the device region 16 and device region 20 by patterning using photolithography and etching processes. A portion of the patterned pad layer 21 remains in the device region 18 on the top surface 12 between the sidewall 29 of the trench 30 and the adjacent shallow trench isolation region 14, and another portion of the patterned pad layer 21 remains in the device region 18 on the top surface 12 between the sidewall 31 of the trench 30 and the adjacent shallow trench isolation region 14.

[0026] An implantation mask 22 is laid in device area 18. The implantation mask 22 includes a portion located above the center of layer stack 36 and a portion filling the gap between layer stack 36 and the sidewalls 29, 31 of trench 30. The implantation mask 22 includes an opening that exposes the top surface of layer stack 36 and thereby defines the area available for implantation. An implantation mask 22 is not present in device areas 16 and 20. The implantation mask 22 may include being laid by spin coating, pre-baked, exposed to light projected through a photomask, post-exposure baked, and developed with a chemical developer to define the openings arranged in the areas to be implanted and the shapes in areas not to be implanted.

[0027] refer to Figure 5 The same reference numerals refer to Figure 4 With the same characteristics as in the process and in subsequent manufacturing stages, throughout device regions 16 and 20, an implantation layer 38 comprising damaged or amorphous semiconductor material is formed in the semiconductor substrate 10 below the top surface 12 of the semiconductor substrate 10. In device region 18, the implantation layer 38 is also formed in a portion of the semiconductor substrate 10 between the sidewalls 29, 31 of the trench 30 and their respective adjacent shallow trench isolation regions 14. An implantation region 40 is formed in the layer stack 36, its location defined by the implantation mask 22.

[0028] The implanted layer 38 and the implanted region 40 can be formed simultaneously by an ion implantation process that introduces high-energy ions with ion trajectories. These high-energy ions bombard the top surface 12 and travel along paths within the semiconductor substrate 10 and the layer stack 36. The high-energy ions lose energy along their paths through random scattering events with atomic nuclei and electrons in the semiconductor material they pass through, and eventually stop after their energy dissipation. The energy lost in the nuclear collisions removes target atoms from their original lattice positions in the semiconductor substrate 10 and the layer stack 36, thereby damaging their respective lattice structures. The lattice structure of the semiconductor substrate 10 is damaged or amorphized within the implanted layer 38 compared to the undamaged region 24 of the semiconductor material of the semiconductor substrate 10 located below the lower boundary 15 of the implanted layer 38 and the non-implanted layer of the layer stack 36. In one embodiment, the implanted layer 38 in the semiconductor substrate 10 can extend from the lower boundary 15 to the top surface 12. In one embodiment, the lower boundary 15 can be planar. In an alternative embodiment, the lower boundary 15 may be shallower below the pad layer 21, which serves to locally increase the material thickness during implantation and reduce the ion range in a portion of the semiconductor substrate 10 below the pad layer 21.

[0029] The implantation region 40 in the layer stack 36 extends to a shallow depth within the layer stack 36 and may be located adjacent to the sidewall 37. In one embodiment, the implantation region 40 extends through the interface between the channel layer 78 and the barrier layer 82 in the layer stack 36 to define the boundary of the region in the layer stack 36 for two-dimensional electronic gas during use.

[0030] Ions can be generated by a suitable source gas and implanted into the semiconductor substrate 10 and layer stack 36 under one or more implantation conditions using an ion implantation tool. Implantation conditions (e.g., ion type, dose, energy) for the ion implantation process can be selected to adjust the characteristics of the implantation layer 38 and implantation region 40. In one embodiment, ions can be generated by an inert gas, such as argon or xenon. In one embodiment, the dose of argon ions can be greater than or equal to 1 x 10⁻⁶. 14 ions / cm 2 In one embodiment, the dose range of argon ions can be from approximately 1 x 10⁻⁶. 14 ions / cm 2 Up to approximately 5x10 15 ions / cm 2 In one embodiment, the energy of the argon ions can range from approximately 30 keV to approximately 1000 keV. The dose and energy of other implanted inert gas ion species can be similar to or different from those of argon. Ion implantation conditions can include single implantation, multiple implantations performed at different energies, segmented implantation, etc.

[0031] refer to Figure 6 , Figure 6A The same reference numerals refer to Figure 5 The same features are used in the process, and in subsequent manufacturing stages, the remaining pad layer 21 and implantation mask 22 are removed. A dielectric layer 42 can be deposited and patterned to cover the layer stack 36 in device region 18. The dielectric layer 42 is removed from device regions 16 and 20 during patterning, such that the top surface 12 of the semiconductor substrate 10 is exposed in device regions 16 and 20. The dielectric layer 42 is made of a dielectric material, such as silicon dioxide.

[0032] By performing a heat treatment (i.e., an annealing process), the damaged semiconductor material in the implanted layer 38 is transformed into the polycrystalline layer 44 and polycrystalline region 46 in the semiconductor substrate 10. In one embodiment, the heat treatment for heat-treating the implanted layer 38 of the semiconductor substrate 10 and forming the polycrystalline layer 44 and polycrystalline region 46 can be rapid thermal annealing. In one embodiment, rapid thermal annealing can be performed using, for example, a flash lamp assembly that heats the semiconductor substrate 10 to a peak temperature in the range of 900°C to 1125°C, with a dwell time of 30 milliseconds to 5 seconds at the peak temperature, and in a particular embodiment, the peak temperature can be maintained at 1000°C for a dwell time of less than or equal to 1 second.

[0033] Polycrystalline layer 44 and polycrystalline region 46 contain grains of polycrystalline semiconductor material (e.g., polycrystalline silicon). In addition to polycrystalline grains, polycrystalline layer 44 and polycrystalline region 46 may also contain defects as residual damage, and these defects may contain trapped atoms of an implanted type (e.g., argon or xenon). In device regions 16 and 20, the heat treatment also recrystallizes the damaged semiconductor material of the implanted layer 38 between polycrystalline layer 44 and top surface 12 into layer 48 of the semiconductor substrate 10, which comprises recrystallized semiconductor material (e.g., recrystallized single-crystal silicon). In device region 16, the damaged semiconductor material of implanted layer 38 does not recrystallize due to the presence of dielectric layer 42, and after heat treatment, polycrystalline region 46 may extend to top surface 12. In contrast to polycrystalline layer 44 and polycrystalline region 46, the recrystallized single-crystal semiconductor material in layer 48 has no polycrystalline grains and defects, and may also lack implanted atoms.

[0034] Polycrystalline region 46 is adjacent to trench 30, and more specifically, to sidewalls 29, 31 of trench 30. Polycrystalline layer 44 includes segments in device region 16 and device region 20, but is not present in device region 18 below trench 30. The polycrystalline layer 44 segments in device region 16 extend below shallow trench isolation regions 14 between device regions 16 to connect to one of the polycrystalline regions 46 in device region 18. Similarly, the polycrystalline layer 44 segments in device region 20 extend below shallow trench isolation regions 14 between device regions 20 to connect to another polycrystalline region 46 in device region 18. In each case, the respective polycrystalline region 46 extends from top surface 12 to connect to one or the other of the segments of polycrystalline layer 44. In one embodiment, the segments of polycrystalline layer 44 may extend laterally relative to top surface 12 below the entirety of each of device regions 16 and 20. For example, segments of polycrystalline layer 44 in device region 16 may extend laterally relative to and contact the top surface 12 between shallow trench isolation regions 14 surrounding device region 16, and segments of polycrystalline layer 44 in device region 20 may extend laterally relative to and contact the top surface 12 between shallow trench isolation regions 14 surrounding device region 20.

[0035] The recrystallized single-crystal layer 48 is located between the upper boundary 43 of the polycrystalline layer 44 in device regions 16 and 20 and the top surface 12 of the semiconductor substrate 10. The semiconductor substrate 10 also includes single-crystal semiconductor material in an undamaged region 24 below the lower boundary 47 of the polycrystalline layer 44 and the polycrystalline region 46. As a result, the polycrystalline layer 44 is buried below the top surface 12 in device regions 16 and 20 and embedded in the single-crystal semiconductor material of the semiconductor substrate 10.

[0036] The polycrystalline layer 44 and the polycrystalline region 46 can be characterized as trap-rich materials having a resistivity greater than or equal to that of the single-crystal semiconductor material of the semiconductor substrate 10. In one embodiment, the polycrystalline layer 44 and the polycrystalline region 46 can have a resistivity greater than or equal to 1,000 ohm-cm. In another embodiment, the resistivity of the polycrystalline layer 44 and the resistivity of the polycrystalline region 46 can be in the range of about 10,000 ohm-cm to about 1,000,000 ohm-cm.

[0037] The polycrystalline region 46 in device region 18 provides enhanced electrical isolation between layer stack 36 and device region 16, and between layer stack 36 and device region 20. Polycrystalline region 46 may extend together with adjacent shallow trench isolation region 14.

[0038] In one embodiment, the implantation region 40 in the layer stack 36 can be recrystallized into an isolation region 41 by heat treatment. The isolation region 41 comprises a single-crystal or substantially single-crystal semiconductor material containing an atomic concentration of implanted ion species. The atomic concentration of implanted ion species transforms the semiconductor material of the layer stack 36 into an electrical insulator. The isolation region 40 can extend into the stack 36 at a depth shallower than that of the polycrystalline layer 44.

[0039] refer to Figure 7 The same reference numerals refer to Figure 6 The field-effect transistor 50, sharing the same features as those in the process, can be fabricated using complementary metal-oxide (CMOS) processing to form a device structure in the device region 16 of the semiconductor substrate 10. The field-effect transistor 50 may include a gate electrode 52, a gate dielectric 53, a source / drain region 54, and a channel region below the gate electrode 52. The gate electrode 52 and the gate dielectric 53 are formed on the top surface 12 of the semiconductor substrate 10. The source / drain region 54 and the channel region of the field-effect transistor 50 comprise respective portions of the single-crystal semiconductor material of the semiconductor substrate 10. The source / drain region 54 is at least partially located below the top surface 12, while the channel region is located below the top surface 12, typically between the source / drain regions 54.

[0040] The bipolar junction transistor 56 can be fabricated as a device structure in device region 20 of semiconductor substrate 10. The bipolar junction transistor 56 may include a plurality of terminals in the form of a collector 58, an emitter 60 defined in semiconductor substrate 10, and a base layer 62 disposed between the collector 58 and the emitter 60. The base layer 62 may comprise a single-crystal semiconductor material (e.g., silicon-germanium) epitaxially grown on the top surface 12 of semiconductor substrate 10. In one embodiment, the collector 58 and emitter 60 may comprise n-type semiconductor material, and the base layer 62 may comprise p-type semiconductor material to define an NPN bipolar junction transistor.

[0041] Field-effect transistor 50 and bipolar junction transistor 56 constitute different types or classifications of transistor structures. The difference between field-effect transistor 50 and bipolar junction transistor 56 is that only majority carriers flow in field-effect transistor 50, while both majority and minority carriers flow in bipolar junction transistor 56. Field-effect transistor 50 and bipolar junction transistor 56 do not include any silicon carbide layer in their respective constructions, and are therefore silicon carbide-free. Both field-effect transistor 50 and bipolar junction transistor 56 are formed on a semiconductor material, characterized by having the same semiconductor material as the semiconductor material used to form the layer stack 36. <111> Crystal orientation.

[0042] refer to Figure 8 , Figure 8A The same reference numerals refer to Figure 7The same features are used in the process, and in a subsequent manufacturing stage, the dielectric layer 42 is partially removed from the device region 18 by an etching process. A portion of the dielectric layer 42 remains within a trench 30 in the space between the sidewalls 37 and sidewall spacers 34 of the layer stack 36. One or more dielectric layers 65 are formed on all device regions 16, 18, and 20. The one or more dielectric layers 65 are patterned to define openings in the device region 18 that expose the layer stack 36.

[0043] Transistor 64 is formed as a device structure in device region 18 using layer stack 36. Transistor 64 includes a gate electrode 66, a source region 68, and a drain region 69, which can be formed in a dielectric layer disposed on the top surface of layer stack 36. Gate electrode 66, source region 68, and drain region 69 can be made of metal, such as metal nitride. Metal atoms from source region 68 and drain region 69 can diffuse into layer stack 36.

[0044] Transistor 64 is not formed using CMOS technology and can therefore be considered a non-CMOS transistor. In one embodiment, transistor 64 may be a high electron mobility transistor (HEMT). In another embodiment, transistor 64 may be a metal-insulator-semiconductor high electron mobility transistor (MISHEMT). In yet another embodiment, transistor 64 may be a metal-oxide-semiconductor high electron mobility transistor (MOSHEMT). In embodiments, device region 18 may further include deep trench isolation regions for electrical isolation and / or through-silicon vias for electrical connections.

[0045] Next, mid-stage and back-end processes are performed, including forming contacts, vias, and wiring for interconnect structures located above the semiconductor substrate 10 and above transistors 50, 56, and 64. Various metallization layers, such as a first metallization (M1) layer, can be formed to couple with the field-effect transistor 50, bipolar junction transistor 56, and transistor 64. For this purpose, before forming the metallization layers, openings in one or more dielectric layers 65 can be filled with a dielectric material.

[0046] Polycrystalline region 46 in device region 18 provides lateral electrical isolation between field-effect transistor 50 in device region 16 and transistor 64 in device region 18, and between bipolar junction transistor 56 in device region 20 and transistor 64 in device region 18. Polycrystalline layer 44 provides vertical electrical isolation between field-effect transistor 50 in device region 16 and bipolar junction transistor 56 in device region 20. The isolation provided by polycrystalline layer 44 and polycrystalline region 46 prevents crosstalk and improves radio frequency performance.

[0047] refer to Figure 9Furthermore, according to an alternative embodiment, the semiconductor substrate 10 may be a silicon-on-insulator substrate, which includes a buried oxide layer 84 and is characterized in that... <111> A crystal-oriented handle substrate 86. By controlling the implantation conditions of the implantation layer 38, the polycrystalline layer 44 formed by the thermal processing of the implantation layer 38 can be located below the buried oxide layer 84. A trench 30 extends through the buried oxide layer 84 to the handle substrate 86 in the device region 18, and a layer stack 36 is epitaxially grown on the handle substrate 86. The field-effect transistor 50 in the device region 16 and the bipolar junction transistor 56 in the device region 20 are formed using a device layer on a silicon-on-insulator substrate.

[0048] refer to Figure 10 According to an alternative embodiment, the polycrystalline layer 45 may be formed in the semiconductor substrate 10 around the periphery of the trench 30. More specifically, the polycrystalline layer 45 may be adjacent to the bottom of the trench located on surface 32 and adjacent to sidewalls 29, 31 in the semiconductor substrate 10. Prior to forming the layer stack 36, the polycrystalline layer 45 may be formed by an ion implantation process to create damaged semiconductor material in the implantation layer (similar to implantation layer 38) adjacent to the surface 32 and sidewalls 29, 31 of the trench 30. The implantation layer may be converted into the polycrystalline layer 45 by the same thermal treatment used to form the polycrystalline layer 44 and the polycrystalline region 46. A recrystallization layer 17 of single-crystal semiconductor material is located between the polycrystalline layer 45 and the surface 32 of the semiconductor substrate 10 at the bottom of the trench. During the implantation process, which is used as part of the process flow for forming the polycrystalline layer 45, device regions 16 and 20 may be masked by an implantation mask similar to implantation mask 22.

[0049] The method described above is used to manufacture integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of raw wafers (e.g., as a single wafer with multiple unpackaged chips), as bare dies, or in packages. In the latter case, the chips are mounted in a single-chip package (e.g., a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or a multi-chip package (e.g., a ceramic carrier with surface interconnects or buried interconnects, or both). In any case, the chips can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product.

[0050] References to terms modified by approximate language, such as “about,” “approximately,” and “substantially,” are not limited to specified exact values. Approximate language may correspond to the precision of the instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may represent + / - 10% of the value.

[0051] The use of terms such as “vertical” and “horizontal” in this document is illustrative rather than restrictive, serving to establish a framework for reference. As used herein, the term “horizontal” is defined as a plane parallel to the conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to directions perpendicular to the horizontal line, as just defined. The term “lateral” refers to a direction within the horizontal plane.

[0052] A feature that is "connected" or "coupled" to or "coupled" to another feature may be directly connected or coupled to or coupled to another feature, or alternatively, one or more intermediate features may exist. If no intermediate feature exists, the feature may be "directly connected" or "directly coupled" to or directly coupled to another feature. If at least one intermediate feature exists, the feature may be "indirectly connected" or "indirectly coupled" to another feature. A feature that is "on" or "in contact" with another feature may be directly on or directly in contact with another feature, or alternatively, one or more intermediate features may exist. If no intermediate feature exists, the feature may be "directly" on or "directly in contact" with another feature. If at least one intermediate feature exists, the feature may be "indirectly" on or "indirectly in contact" with another feature.

[0053] The description of various embodiments of the present invention is presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been chosen to best explain the principles of the embodiments, their practical application, or technical improvements to technologies found in the market, or to enable those skilled in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: A semiconductor substrate having a first device region and a second device region, wherein the semiconductor substrate has a first surface and a trench extending from the first surface into the semiconductor substrate; A first transistor is located in the first device region of the semiconductor substrate; A second transistor, in the second device region of the semiconductor substrate, the second transistor includes a layer stack on the semiconductor substrate, and the layer stack includes a layer made of a III-V compound semiconductor material; A polycrystalline layer, in the semiconductor substrate, the polycrystalline layer including a first segment in the semiconductor substrate located below the first device region; and A polycrystalline region, adjacent to the trench in the semiconductor substrate.

2. The semiconductor structure as described in claim 1, wherein, The layer stack is located on the semiconductor substrate within the trench.

3. The semiconductor structure as described in claim 2, wherein, The polycrystalline region extends from the first surface to the first segment of the polycrystalline layer.

4. The semiconductor structure as described in claim 3, further comprising: A shallow trench isolation region is located laterally between the first device region and the second device region in the semiconductor substrate. The first segment of the polycrystalline layer extends laterally to the polycrystalline region below the shallow trench isolation region.

5. The semiconductor structure as described in claim 2, wherein, The semiconductor substrate has a second surface at the bottom of the trench, the trench includes sidewalls extending from the first surface to the second surface, the layer stack is located on the second surface of the semiconductor substrate, and the polycrystalline region is located adjacent to the sidewalls of the trench.

6. The semiconductor structure of claim 5, further comprising: A shallow trench isolation region is located laterally between the first device region and the second device region in the semiconductor substrate. The polycrystalline region is laterally located between the sidewall of the trench and the shallow trench isolation region.

7. The semiconductor structure as claimed in claim 5, wherein, The polycrystalline layer includes a second segment of the semiconductor substrate located below the second surface of the semiconductor substrate at the bottom of the trench.

8. The semiconductor structure as claimed in claim 5, wherein, The polycrystalline layer is not present below the second surface of the semiconductor substrate at the bottom of the trench.

9. The semiconductor structure of claim 1, further comprising: The isolation zone is located within the layer stack.

10. The semiconductor structure as claimed in claim 9, wherein, The semiconductor substrate includes a top surface, the first segment of the polycrystalline layer is located at a first depth relative to the top surface of the semiconductor substrate, the layer stack includes a top surface, and the isolation region is located at a second depth relative to the top surface of the layer stack, wherein the second depth is less than the first depth.

11. The semiconductor structure as claimed in claim 1, wherein, The semiconductor substrate includes a buried oxide layer located in the first device region, and the buried oxide layer is located between the first segment of the polycrystalline layer and the first device region.

12. The semiconductor structure as claimed in claim 1, wherein, The semiconductor substrate has a top surface, and the first segment of the polycrystalline layer extends laterally relative to the top surface below the entire first device region.

13. The semiconductor structure of claim 12, wherein, The semiconductor substrate has a third device region and further includes: The third transistor is located in the third device region of the semiconductor substrate. The polycrystalline layer includes a second segment in the semiconductor substrate located below the second device region, and the first transistor and the second transistor are transistor structures of different types.

14. The semiconductor structure of claim 13, wherein, The second segment of the polycrystalline layer extends laterally relative to the top surface below the entire third device region.

15. The semiconductor structure as claimed in claim 13, wherein, The first transistor is a field-effect transistor including source / drain regions in the semiconductor substrate at least partially located below the top surface, and the third transistor is a bipolar junction transistor including terminals in the semiconductor substrate at least partially located below the top surface.

16. The semiconductor structure as claimed in claim 1, wherein, The semiconductor substrate is composed of a diamond lattice structure and <111> Composed of single-crystal semiconductor materials with crystal orientation.

17. The semiconductor structure of claim 16, wherein, The semiconductor substrate is a bulk substrate, the single-crystal semiconductor material includes single-crystal silicon, and the III-V compound semiconductor material includes gallium nitride having a substantially single-crystal crystal structure.

18. A method for forming a semiconductor structure, the method comprising: A polycrystalline layer is formed having a first segment located below a first device region of a semiconductor substrate, wherein the semiconductor substrate has a first surface and a trench extending from the first surface into the semiconductor substrate; A first transistor is formed in the first device region of the semiconductor substrate; A layer stack comprising layers made of III-V compound semiconductor material is formed in the second device region of the semiconductor substrate; The second transistor is formed using the layer stack; and A polycrystalline region adjacent to the trench is formed in the semiconductor substrate.

19. The method of claim 18, further comprising: An isolation region is formed in the layer stack while the polycrystalline layer is being formed.

20. The method of claim 18, further comprising: The trenches are formed in the semiconductor substrate. The layer stack is formed on the semiconductor substrate within the trench, and the polycrystalline layer includes a second segment formed in the semiconductor substrate adjacent to the trench.

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