High-speed DreaMOS device and manufacturing method thereof

Abstract

The present invention discloses a high-speed DreaMOS device and a method for manufacturing the same. The high-speed DreaMOS device includes a semiconductor structure layer and a gate oxide layer and a gate electrode matched with the semiconductor structure layer. The semiconductor structure layer includes an epitaxial layer and a well region, a well region contact region, a drain region extension region and a drain region formed in the epitaxial layer. A plurality of source regions and a plurality of channel doping regions are also formed in the epitaxial layer, wherein the plurality of channel doping regions are respectively formed in different depth regions of the epitaxial layer, wherein at least two source regions have different junction depths. The high-speed DreaMOS device provided by the embodiment of the present invention reduces the high-temperature annealing process of the well region, simplifies the device manufacturing process, and improves the device consistency.

Description

Technical Field

[0001] The present invention relates to a power semiconductor device, in particular to a high-speed DreaMOS device and a manufacturing method thereof, and belongs to the technical field of semiconductors. Background Art

[0002] Figure 1 The structure of an LDMOS device is shown, wherein the source region 13, the drain extension region 14 and the drain region 15 have the same conductivity type, the conductivity type of the channel region under the gate 11 is the same as that of the body region and opposite to that of the source region 13, and the drain extension region 14 increases the breakdown voltage of the LDMOS device, thereby increasing the output power of the device. In the manufacturing process of the LDMOS device, the ion implantation method is used to form Figure 1 The well region 17 in the device is annealed at a high temperature for a long time so that the body region diffuses laterally and contacts the drain extension region 14, thereby forming a channel of the device.

[0003] However, long-term high-temperature annealing increases the thermal process of the device, reduces the consistency of the device, and causes the junction depth of the device to become deeper, thereby increasing the device capacitance. Figure 1 The LDMOS device shown is prone to hot carrier injection effect in high voltage and high current scenarios. Carriers enter the gate oxide layer area, which will aggravate the changes in parameters such as device on-resistance, saturation current, threshold voltage and breakdown voltage, and reduce the service life of the device; and as the doping concentration of the drain extension region increases, the hot carrier effect is aggravated. In order to improve the efficiency of the device, those skilled in the art hope to increase the doping concentration of the drain extension region. Traditional LDMOS devices are trapped by the hot carrier injection effect and cannot reduce the on-resistance and improve device performance.

[0004] Figure 2 The structure of a DreaMOS device is shown, which breaks the reliability limit of the hot carrier injection effect. Compared with the traditional LDMOS device, the on-resistance of the DreaMOS device is reduced by 40%, and the current density is 2.1 times that of the traditional LDMOS device. However, compared with the traditional LDMOS device, the advantages of the DreaMOS device in performance such as cutoff frequency are not particularly obvious, and the current density cannot meet the needs of higher frequency applications.

[0005] In summary, existing devices still have defects such as many thermal processes in the processing technology, poor device consistency, difficult to control device junction depth and large capacitance, and existing devices are limited by the hot carrier injection effect and cannot reduce on-resistance and improve device efficiency and current density. Summary of the invention

[0006] The main purpose of the present invention is to provide a high-speed DreaMOS device and a manufacturing method thereof to overcome the deficiencies in the prior art.

[0007] In order to achieve the above-mentioned invention object, the technical solution adopted by the present invention includes:

[0008] An embodiment of the present invention provides a high-speed DreaMOS device, including a semiconductor structure layer and a gate oxide layer and a gate electrode matched with the semiconductor structure layer, wherein the semiconductor structure layer includes an epitaxial layer and a well region, a well region contact region, a drain region extension region and a drain region formed in the epitaxial layer, and a plurality of source regions and a plurality of channel doping regions are also formed in the epitaxial layer, wherein the plurality of channel doping regions are respectively formed in different depth regions of the epitaxial layer, wherein at least two source regions have different junction depths.

[0009] An embodiment of the present invention also provides a method for manufacturing the high-speed DreaMOS device, which includes: before forming a gate, using ion implantation to form a well region in the epitaxial layer, performing multiple ion implantations on the epitaxial layer to form multiple channel doping regions at different depths in the epitaxial layer, and, after forming the gate, using ion implantation to form multiple source regions in the epitaxial layer.

[0010] Compared with the prior art, the advantages of the present invention include:

[0011] 1) The high-speed DreaMOS device provided by the embodiment of the present invention reduces the high-temperature annealing process of the well region, simplifies the device manufacturing process, and improves the device consistency;

[0012] 2) The on-resistance of the high-speed DreaMOS device provided by the embodiment of the present invention is reduced by 40%, and the current density is 2.1 times that of the traditional LDMOS device; under the same breakdown voltage, the cutoff frequency of the high-speed DreaMOS device provided by the embodiment of the present invention is increased by 2.5 times, and the power density is increased by 60%. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a cross-sectional schematic diagram of an existing power LDMOS device provided by the inventor;

[0014] Figure 2 is a cross-sectional schematic diagram of a DreaMOS device provided by the inventor;

[0015] Figure 3 is a cross-sectional schematic diagram of a high-speed DreamOS device provided in a typical implementation case of the present invention;

[0016] Figure 4a- Figure f is a schematic diagram of a device structure formed after each process step in a method for manufacturing a high-speed DreaMOS device provided in a typical implementation case of the present invention;

[0017] Explanation of the accompanying drawings: 11-gate, 12-gate oxide layer, 13-source region, 14-drain region extension region, 15-drain region, 16-well region contact region, 17-well region, 18-epitaxial layer, 19-substrate, 21-gate, 22-gate oxide layer, 23-first source region, 24-second source region, 25-drain region extension region, 26-drain region, 27-well region contact region, 28-well region, 29-epitaxial layer, 210-substrate, 211-first channel doping region, 212-second channel doping region, 213-third channel doping region, 31-gate, 32-gate oxide layer, 33-source region, 34-drain region extension region, 35-drain region, 36-well region contact region, 37-well region, 38-epitaxial layer, 39-substrate, 310-channel doping region. DETAILED DESCRIPTION

[0018] In view of the deficiencies in the prior art, the inventor of this case has proposed the technical solution of the present invention after long-term research and extensive practice. The technical solution, its implementation process and principle will be further explained as follows.

[0019] LDMOS: Lateral Doublediffusion Metal Oxide Semiconductor, lateral double diffused metal oxide semiconductor;

[0020] DreaMOS: Drain Extended Advance Metal Oxide Semiconductor, drain extended advanced metal oxide semiconductor.

[0021] In order to address the problem of hot carrier injection effect constraining the reduction of device on-resistance and increase of current density faced by semiconductor metal oxide transistor devices with drain extension, a high-speed DreaMOS device provided in an embodiment of the present invention adopts a dual-channel design, which effectively suppresses the hot carrier injection effect, increases the doping concentration of the drain extension region, increases the current density of the device to 2.1 times that of traditional devices, and reduces the on-resistance by 40%.

[0022] A high-speed DreaMOS device provided by an embodiment of the present invention forms a well region by ion implantation, thereby reducing the heat process of processing, simplifying the manufacturing process, and improving the consistency of the device; and, a high-speed DreaMOS device provided by an embodiment of the present invention combines the shortening of the gate length and the setting of multiple source regions to improve the device cutoff frequency, and, before manufacturing the gate, a high-speed DreaMOS device provided by an embodiment of the present invention forms multiple channel doping regions by performing multiple channel doping, and the multiple channel doping regions are combined with the well region to suppress the hot carrier injection effect. Under the same hot carrier injection life condition, the current density of the high-speed DreaMOS device provided by an embodiment of the present invention is 2.5 times that of the DreaMOS device, and the current density is increased by 60%.

[0023] An embodiment of the present invention provides a high-speed DreaMOS device, including a semiconductor structure layer and a gate oxide layer and a gate electrode matched with the semiconductor structure layer, wherein the semiconductor structure layer includes an epitaxial layer and a well region, a well region contact region, a drain region extension region and a drain region formed in the epitaxial layer, and a plurality of source regions and a plurality of channel doping regions are also formed in the epitaxial layer, wherein the plurality of channel doping regions are respectively formed in different depth regions of the epitaxial layer, wherein at least two source regions have different junction depths.

[0024] Furthermore, the plurality of channel doping regions are stacked in sequence along the depth direction of the epitaxial layer, and the plurality of channel doping regions are staggered along their own length direction.

[0025] Furthermore, the length of the overlapping region between two adjacent channel doping regions is 1 / 3-1 / 6 of the length of the channel doping regions.

[0026] Furthermore, the channel doping region has a thickness of 0.4-1 μm and a length of 0.1-0.8 μm.

[0027] Furthermore, the multiple channel doping regions are located below the gate, and the multiple source regions are distributed in sequence between the well region contact region and the channel doping region along a specified direction, wherein at least one source region is connected to the well region contact region, and at least one source region is connected to the channel doping region, and at least the junction depth of the source region connected to the well region contact region is greater than the junction depth of the source region connected to the channel doping region.

[0028] Furthermore, the junction depths of the plurality of source regions decrease sequentially along a direction approaching or tending toward the channel doping region or the gate.

[0029] Furthermore, the multiple source regions are connected in sequence.

[0030] Furthermore, the thickness of the source region is 100-4000nm, and the length is 500-4000nm, wherein the junction depth difference between the two source regions is 50n-2000nm.

[0031] Furthermore, the channel doping region located at the topmost layer is connected to the source region, wherein the channel doping region, the source region, the drain region and the drain region extension region have the same conductivity type.

[0032] Furthermore, the well region is located below the multiple channel doping regions, and the well region is connected to the well region contact region and the drain region extension region respectively, wherein the well region, the well region contact region and the epitaxial layer have the same conductivity type.

[0033] Furthermore, when the gate voltage and the threshold voltage have a first voltage difference, the effective channel and carrier path of the device are both located inside the semiconductor structure layer, and when the gate voltage is greater than the threshold voltage and the gate voltage and the threshold voltage have a second voltage difference, the effective channel of the device is located on the surface of the semiconductor structure layer.

[0034] Furthermore, when the gate voltage is near the threshold voltage, the effective channel of the device is located between the multiple channel doping regions and the well region.

[0035] Furthermore, the epitaxial layer is arranged on a substrate, and the conductivity type of the substrate and the epitaxial layer is the same.

[0036] Furthermore, the length of the gate is 50-250 nm.

[0037] An embodiment of the present invention also provides a method for manufacturing the high-speed DreaMOS device, which includes: before forming a gate, using ion implantation to form a well region in the epitaxial layer, performing multiple ion implantations on the epitaxial layer to form multiple channel doping regions at different depths in the epitaxial layer, and, after forming the gate, using ion implantation to form multiple source regions in the epitaxial layer.

[0038] Furthermore, the production method specifically includes:

[0039] An epitaxial layer is provided, and a well region is formed in the epitaxial layer by ion implantation, wherein the energy of the ion implantation is 100-800 KEV and the concentration is 5E12-5E14 cm -2 ;

[0040] The epitaxial layer is implanted multiple times by ion implantation to form multiple channel doping regions, the energy of the ion implantation is 15-250KEV, and the concentration is 1E11-5E12 cm -2 ;

[0041] forming a gate oxide layer on the epitaxial layer and forming a gate on the gate oxide layer;

[0042] The drain extension region is formed in the epitaxial layer by ion implantation, the energy of the ion implantation is 50-600KEV, and the concentration range is 2E11-5E12cm -2 ;

[0043] Ion implantation is used to form multiple source regions in the epitaxial layer, the energy of the ion implantation is 10-100KEV, and the concentration is 5E13-1E16 cm -2 ;

[0044] The well region, contact region and drain region are formed in the epitaxial layer by ion implantation.

[0045] The technical solution, its implementation process and principle will be further explained below in conjunction with the accompanying drawings. Unless otherwise specified, the manufacturing process and detection process used in the embodiments of the present invention are known to those skilled in the art.

[0046] Example 1

[0047] See also Figure 3 A high-speed DreaMOS device includes a semiconductor structure layer and a gate oxide layer 22 and a gate 21 matched with the semiconductor structure layer, wherein the semiconductor structure layer includes a substrate 210, an epitaxial layer 29 disposed on the substrate, and a well region 28, a well region contact region 27, a first source region 23, a second source region 24, a drain region extension region 25, a drain region 26 and a plurality of channel doping regions formed in the epitaxial layer 19;

[0048] The multiple channel doping regions are located below the gate 21, the well region 28 is located below the multiple channel doping regions, and the well region 28 is connected to the well region contact region 27 and the drain region extension region 25 respectively, the multiple channel doping regions include a first channel doping region 211, a second channel doping region 212, and a third channel doping region 213 which are sequentially formed at different depths in the epitaxial layer 29 along the depth direction of the epitaxial layer 29, the first source region 23 is located on a side of the second source region 24 close to the gate 21, the first source region 23 is connected to the second source region 24 and the first channel doping region 211, and the junction depth of the second source region 24 is greater than the junction depth of the first source region 23;

[0049] Among them, the first channel doping region 211, the second channel doping region 212, the third channel doping region 213, the first source region 23, the second source region 24, the drain extension region 25, and the drain region 26 have the same conductivity type, and the well region 28, the well region contact region 27, the epitaxial layer 29 and the substrate 210 have the same conductivity type.

[0050] When the gate voltage is slightly higher than the threshold voltage, the effective channel of the high-speed DreaMOS device is located inside the semiconductor structure layer and away from the surface of the semiconductor structure layer, and the current path is also away from the surface of the semiconductor structure layer, which reduces the probability of hot carrier injection under the gate voltage condition where the hot carrier injection effect is most likely to occur;

[0051] When the gate voltage is further increased, the effective channel of the high-speed DreaMOS device is located on the surface of the semiconductor structure layer like the traditional LDMOS device, thus ensuring the transconductance and device performance of the high-speed DreaMOS device when the gate voltage is high.

[0052] Specifically, a high-speed DreaMOS device provided by the embodiment of the present invention is a dual-channel device structure. When the gate voltage is slightly greater than the threshold voltage, the potential difference between the gate and the channel is smaller than the potential difference between the gate and the channel of a traditional device, forming an electron barrier to prevent hot electrons from entering the oxide layer, thereby reducing the probability of hot carrier injection effect in the device and greatly improving the current density of the device.

[0053] See also Figure 3 and Figure 4a-4f , a method for manufacturing a high-speed DreamOS device, comprising the following steps:

[0054] 1) growing an epitaxial layer 29 on the substrate 210, wherein the thickness of the epitaxial layer 29 is set according to the device specification, and the thickness is generally between 2 μm and 50 μm;

[0055] 2) An ion implantation process is used to form a well region 28 in the epitaxial layer 29. The energy of the ion implantation is 100-800 KEV and the concentration is 5E12-5E14 cm -2 , wherein the conductivity type of the well region 28 is the same as that of the epitaxial layer 29;

[0056] 3) Through the ion implantation process, a multi-layer mask is used to perform multiple ion implantations to form multiple channel doping regions in the epitaxial layer 29. In the embodiment of the present invention, three layers of masks are used to perform three ion implantations to form a first channel doping region 211, a second channel doping region 212, and a third channel doping region 213 that are stacked and sequentially connected in the epitaxial layer 29. The thickness of each ion implantation is 0.4-1 μm, and the overlapping portion of each layer of mask is 1 / 3-1 / 6 of the length of the implantation region. The energy of the ion implantation is 15KEV-250KEV, and the concentration is 1E11-5E12 cm -2 , wherein the conductivity type of the first channel doping region 211 , the second channel doping region 212 , and the third channel doping region 213 is opposite to that of the epitaxial layer 28 ;

[0057] 4) depositing a gate oxide layer 22 on the top surface of the epitaxial layer 29, and depositing a polysilicon gate on the gate oxide layer 22, and etching to form a gate 21, wherein the thickness of the gate oxide layer 22 is 5-30 nm, and the length of the gate 21 is related to the device parameter conditions, for example, the length of the gate 21 is 0.05-4 μm, preferably 50-250 nm;

[0058] 5) An ion implantation process is used to form a drain extension region 25 in the epitaxial layer 29. The energy of the ion implantation is 50KEV-600KEV and the concentration is 2E11-5E12 cm -2 ;

[0059] 6) An ion implantation process is used to form a first source region 23 in the epitaxial layer 29, and the first source region 23 is connected to the first channel doping region 211, wherein the thickness of the first source region is 100-4000nm, the length is 500-4000nm, the energy of the ion implantation is 10KEV-100KEV, and the concentration is 5E13-1E16 cm -2 ;

[0060] Then, a side wall of a polysilicon gate is formed in the epitaxial layer 29, and ion implantation is performed with the aid of the side wall to form a second source region 24, and the second source region 24 is connected to the first source region 23 and the well contact region 27, the junction depth of the second source region 24 is greater than the junction depth of the first source region 23, wherein the thickness of the second source region is 100-4000nm, the length is 500-4000nm, the energy of the ion implantation is 10KEV-100KEV, and the concentration is 5E13-1E16 cm -2 , the junction depth difference between the second source region 24 and the first source region 23 is 50n-2000nm, and the conductivity type of the first source region 23 and the second source region 24 is opposite to that of the substrate;

[0061] 7) The well contact region 27 and drain region 26 of the device are formed by ion implantation process, wherein the conductivity type of the well contact region 27 is the same as that of the well region 28, and the conductivity type of the drain extension region 25, the drain region 26 and the first source region 23 and the second source region 24 are the same.

[0062] Specifically, when the difference between the gate voltage (or driving voltage, the same below) and the threshold voltage is less than one-third of the gate voltage, the effective channel of the device is located between multiple channel doping regions and the well region, and is mainly located below the multiple channel doping regions. At this time, the current path is located inside the semiconductor structure layer, and thus away from the surface of the semiconductor structure layer, especially away from the junction of the drain extension region and the well region where the hot carrier injection effect is most likely to occur; multiple channel doping regions keep the carrier path away from the surface of the semiconductor structure layer, thereby reducing the probability of hot carrier injection effect in the device; and when the difference between the gate voltage and the threshold voltage is greater than one-third of the gate voltage, the effective channel of the device is located on the surface of the semiconductor structure layer. Since the hot carrier injection effect is improved, a higher concentration of doping can be used for the drain extension region, thereby reducing the on-resistance of the device and increasing the current density.

[0063] By the high-speed DreaMOS device provided by the embodiment of the present invention and Figure 1 , Figure 2 The existing device is simulated and tested. According to the device simulation test results, under the same hot carrier effect life condition, the current density of the high-speed DreaMOS device provided by the embodiment of the present invention is higher than that of the conventional device. Figure 2 The DreaMOS device in the system has been improved by 60%.

[0064] In addition, the well region is directly formed by ion implantation. Compared with the long high-temperature annealing process after ion implantation in the traditional LDMOS device manufacturing process, the present invention reduces the thermal process in chip processing, improves the consistency of the device, and can better control the junction depth of the device. More importantly, the present invention is conducive to reducing the gate size by setting multiple source regions and multiple channel doping regions, thereby achieving the purpose of shortening the gate length. At the same time, the present invention also forms multiple source regions, wherein the shallow junction structure of the first source region connected to the channel doping region improves the cutoff frequency of the device. Test results show that the cutoff frequency of the high-speed DreaMOS device provided by the embodiment of the present invention is higher than that of the existing DreaMOS device (such as Figure 2 ) is 2.5 times.

[0065] Compared with the traditional LDMOS device, the high-speed DreaMOS device provided by the embodiment of the present invention reduces the high-temperature annealing process of the well region, simplifies the device manufacturing process, and improves the device consistency; compared with the traditional LDMOS device, the on-resistance of the high-speed DreaMOS device provided by the embodiment of the present invention is reduced by 40%, and the current density is 2.1 times that of the traditional LDMOS device; compared with the existing DreaMOS device, under the same breakdown voltage, the cutoff frequency of the high-speed DreaMOS device provided by the embodiment of the present invention is increased by 2.5 times, and the power density is increased by 60%.

[0066] It should be understood that the above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with the technology to understand the content of the present invention and implement it accordingly, and they cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A high-speed DreaMOS device, comprising a semiconductor structure layer, a gate oxide layer and a gate electrode matched with the semiconductor structure layer, wherein the semiconductor structure layer comprises an epitaxial layer and a well region, a well region contact region, a drain region extension region and a drain region formed in the epitaxial layer, characterized in that: A plurality of source regions and a plurality of channel doping regions are also formed in the epitaxial layer. The plurality of channel doping regions are stacked in sequence along the depth direction of the epitaxial layer, and the plurality of channel doping regions are staggered along their own length direction, wherein the plurality of channel doping regions are respectively formed in different depth regions of the epitaxial layer, wherein at least two source regions have different junction depths, and the plurality of channel doping regions, source regions, drain regions and drain region extension regions have the same conductivity type.

2. The high-speed DreaMOS device according to claim 1, characterized in that: The length of the overlapping region between two adjacent channel doping regions is 1 / 3-1 / 6 of the length of the channel doping regions.

3. The high-speed DreaMOS device according to claim 1 or 2, characterized in that: The channel doping region has a thickness of 0.4-1 μm and a length of 0.1-0.8 μm.

4. The high-speed DreaMOS device according to claim 1, characterized in that: The multiple channel doping regions are located below the gate, and the multiple source regions are distributed in sequence between the well region contact region and the channel doping region along a specified direction, wherein at least one source region is connected to the well region contact region, and at least one source region is connected to the channel doping region, and at least the junction depth of the source region connected to the well region contact region is greater than the junction depth of the source region connected to the channel doping region.

5. The high-speed DreaMOS device according to claim 4, characterized in that: The junction depths of the plurality of source regions decrease sequentially along a direction approaching the channel doping region.

6. The high-speed DreaMOS device according to claim 4, characterized in that: The channel doping region located at the topmost layer is connected to the source region.

7. The high-speed DreaMOS device according to claim 4, characterized in that: The well region is located below the multiple channel doping regions, and the well region is connected to the well region contact region and the drain region extension region respectively, wherein the well region, the well region contact region and the epitaxial layer have the same conductivity type.

8. The high-speed DreaMOS device according to claim 1, characterized in that: When the gate voltage has a first voltage difference with the threshold voltage, the effective channel and carrier path of the device are both located inside the semiconductor structure layer, and when the gate voltage is greater than the threshold voltage and the gate voltage has a second voltage difference with the threshold voltage, the effective channel of the device is located on the surface of the semiconductor structure layer.

9. The high-speed DreamOS device according to claim 1, characterized in that: The epitaxial layer is arranged on a substrate, and the conductivity type of the substrate is the same as that of the epitaxial layer.

10. The high-speed DreaMOS device according to claim 1, characterized in that: The length of the gate is 50-250 nm.

11. The method for manufacturing a high-speed DreamOS device according to any one of claims 1 to 10, characterized in that include: Before forming the gate, a well region is formed in the epitaxial layer by ion implantation, and the epitaxial layer is implanted with ions multiple times to form multiple channel doping regions at different depths in the epitaxial layer. After forming the gate, multiple source regions are formed in the epitaxial layer by ion implantation.

12. The method according to claim 11, characterized in that Specifically include: An epitaxial layer is provided, and a well region is formed in the epitaxial layer by ion implantation, wherein the energy of the ion implantation is 100-800 KEV and the concentration is 5E12-5E14 cm -2 ; The epitaxial layer is implanted multiple times by ion implantation to form multiple channel doping regions, the energy of the ion implantation is 15-250KEV, and the concentration is 1E11-5E12 cm -2 ; forming a gate oxide layer on the epitaxial layer and forming a gate on the gate oxide layer; The drain extension region is formed in the epitaxial layer by ion implantation, the energy of the ion implantation is 50-600KEV, and the concentration range is 2E11-5E12cm -2 ; Ion implantation is used to form multiple source regions in the epitaxial layer, the energy of the ion implantation is 10-100KEV, and the concentration is 5E13-1E16 cm -2 ; The well region, contact region and drain region are formed in the epitaxial layer by ion implantation.

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