SGT MOSFET Device and Manufacturing Method

Abstract

The present invention discloses an SGT MOSFET device. The gate structure adopts a left-right structure, and a second field plate conductive material layer with a depth deeper than that of the gate conductive material layer is further formed between the source conductive material layer and the gate conductive material layer. When the device is reverse-biased, the depletion ability of the drift region near the channel region is increased by utilizing the characteristic that the distance between the second field plate conductive material layer and the drift region is smaller than the distance between the source conductive material layer and the drift region. The present invention also discloses a manufacturing method of an SGT MOSFET device. The present invention can adopt a left-right structure and can improve the depletion ability of the shielding structure for the drift region near the channel region when the device is reverse-biased.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and particularly to a shield gate trench (SGT) MOSFET device; the present invention also relates to a manufacturing method of an SGT MOSFET device. Background Art

[0002] Compared with the traditional trench MOSFET, the SGT MOSFET inserts a longitudinal source field plate, i.e., source polysilicon, in the drift region. The source field plate and the drift region perform lateral depletion, so that the doping concentration of the drift region can be greatly increased without reducing the breakdown voltage, thereby reducing the specific on-resistance and obtaining better performance. Currently, there are two very common SGT MOSFET structures, which are introduced as follows:

[0003] As Figure 1 shown, it is a schematic structural diagram of the first existing SGT MOSFET device. The first existing SGT MOSFET device is an up-and-down structure SGT MOSFET; taking an N-type device as an example, the gate structure of the first existing SGT MOSFET device is formed in a gate trench.

[0004] The gate trench is formed in an N-type first epitaxial layer 2. The first epitaxial layer 2 is formed on an N-type heavily doped semiconductor substrate 1. The semiconductor substrate 1 is usually in a wafer structure.

[0005] Generally, the semiconductor substrate 1 is a heavily doped structure and is thinned on the back to serve as a drain region. In order to reduce the reverse diffusion of the semiconductor substrate 1, the semiconductor substrate 1 usually selects a substrate doped with arsenic (Arsenic). However, because the lowest resistivity that can be achieved in the current process of a substrate doped with phosphorus (Phosphorus) is lower than that of a substrate doped with Arsenic. Therefore, in the case where the substrate resistance accounts for a relatively high proportion, such as in low-voltage devices below 40V, a substrate doped with Phosphorus is also often used. The thinner the semiconductor substrate 1 is, the better the heat dissipation of the device is, and the more significantly the substrate resistance can be reduced.

[0006] Figure 1 The shown gate structure is an up-and-down structure gate structure. Source polysilicon 4 is formed at the bottom of the gate trench. A shielding dielectric layer 3 is isolated between the source polysilicon 4 and the gate trench. The shielding dielectric layer 3 needs to withstand the breakdown voltage of the device. Therefore, the higher the breakdown voltage required by the device is, the thicker the shielding dielectric layer 3 is.

[0007] A polysilicon gate 6 is formed on top of the gate trench, and a gate dielectric layer such as a gate oxide layer 5 is isolated between the polysilicon gate 6 and the gate trench. A polysilicon interlayer oxide layer is isolated between the polysilicon gate 6 and the source polysilicon 4.

[0008] A P-type doped channel region 7 is formed in the surface region of the first epitaxial layer 2. The junction depth of the channel region 7 is less than or equal to the depth of the first side surface of the polysilicon gate 6, and the surface of the channel region 7 covered by the first side surface of the polysilicon gate 6 is used to form a channel.

[0009] The first epitaxial layer 2 below the channel region 7 forms a drift region. The biggest difference between the SGT MOSFET and the traditional TrenchMOSFET is that a longitudinal source polysilicon 4 is inserted laterally in the drift region.

[0010] An N-type heavily doped source region 8 is formed on the surface of the channel region 7.

[0011] The N-type heavily doped drain region is composed of the thinned semiconductor substrate 1 or is composed of the thinned semiconductor substrate 1 stacked with an N-type heavily doped backside ion implantation region.

[0012] It further includes: an interlayer film 11, a contact hole (CT) 9 passing through the interlayer film 11. The bottom of the contact hole 9 corresponding to the top of the source region 8 also passes through the source region 8 to achieve simultaneous contact with the source region 8 and the channel region 7; the source electrode and the gate electrode are formed by patterning a front metal layer 10. The source electrode is simultaneously connected to the source region 8 and the channel region 7 through the corresponding contact hole 9 at the bottom; the source polysilicon 4 is also connected to the source electrode through the corresponding contact hole 9 at the top; the gate electrode is connected to the polysilicon gate 6 through the corresponding contact hole at the bottom.

[0013] As Figure 2 shown, it is a schematic diagram of the design structure of the existing second SGT MOSFET device. The existing second SGT MOSFET device is a left-right structure SGT MOSFET device; and Figure 1 the difference from the existing first SGT MOSFET device shown is that the existing second SGT MOSFET device has the characteristics:

[0014] The polysilicon gate 6a adopts a left-right structure. This left-right structure polysilicon gate 6a is formed after the source polysilicon 4 and the shielding dielectric layer 3 are formed. The shielding dielectric layer 3 is etched back, and then a gate dielectric layer 5a and a polysilicon gate 6a are filled in the region where the shielding dielectric layer 3 is removed.

[0015] As can be seen from the above, the biggest difference between the existing first and second SGT MOSFET devices is:

[0016] The position between the polysilicon gate and the source polysilicon Figure 1 In Figure 1 , the polysilicon gate 6 is located directly above the source polysilicon 4, which is called the up-down structure; Figure 2 In Figure 2 , the polysilicon gate 6a is located on the left and right sides of the source polysilicon 4, which is called the left-right structure.

[0017] The advantages and disadvantages of these two structures are as follows:

[0018] The process implementation of the up-down structure is more complex because the source polysilicon 4 is covered by the polysilicon gate 6 directly above it, making it impossible for the source polysilicon 4 to be directly connected to the contact via. Additional photomasks and process steps are required.

[0019] The process implementation of the left-right structure is simple and does not require particularly complex process steps. All structures such as the polysilicon gate 6a and the source polysilicon are on the surface of the chip, i.e., the surface of the first epitaxial layer 2, and can be conveniently connected directly. However, compared with the up-down structure, the contact area between the polysilicon gate and the source polysilicon in the left-right structure is larger, so its input capacitance will also be larger.

[0020] For Figure 2 the left-right structure shown in Figure 2 , usually the shielding dielectric layer 3 needs to be further improved so that the thickness of the shielding dielectric layer 3 has a gradually changing structure; as Figure 3 shown in Figure 3 , it is a schematic diagram of the design structure of the existing third SGT MOSFET device;

[0021] And Figure 2 the difference between the existing second SGT MOSFET device shown in Figure 2 is that the existing third SGT MOSFET device has the feature that the thickness of the shielding dielectric layer 3a gradually increases in the direction from the channel region 1 to the semiconductor substrate 1, which can increase the uniformity of the electric field strength in the drift region 2. The specific reason is:

[0022] This is because in the drift region 2, the voltage near the channel region 7 is close to the source voltage, i.e., 0V, and it gradually increases to the drain voltage in the body. And the voltage of the source polysilicon 4 is 0V. Thus, the voltage difference between the source polysilicon 4 and the drift region 2 gradually increases in the direction from the channel region 1 to the semiconductor substrate 1. The smaller the voltage difference between the source polysilicon 4 and the drift region 2, the weaker the depletion ability of the source polysilicon 4 on the drift region 2. Therefore, it is necessary to correspondingly reduce the thickness of the shielding dielectric layer 3a here to increase the depletion ability on the drift region 2. So, Figure 3 in Figure 3 , the thickness of the shielding dielectric layer 3a gradually increases in the direction from the channel region 1 to the semiconductor substrate 1, which can better deplete the drift region 2 and make the distribution of the electric field strength in the body more uniform.

[0023] However, Figure 3The structure of the shielding dielectric layer 3a with a gradually changing thickness as shown is very difficult to achieve in actual processes. Summary of the Invention

[0024] The technical problem to be solved by the present invention is to provide an SGT MOSFET device that can adopt a left - right structure and can improve the depletion ability of the shielding structure for the drift region near the channel region when the device is reverse - biased. For this purpose, the present invention also provides a manufacturing method for an SGT MOSFET device.

[0025] To solve the above - mentioned technical problem, the gate structure of the SGT MOSFET device provided by the present invention includes: a gate trench, a shielding dielectric layer, a source conductive material layer, a second field - plate conductive material layer, and a gate conductive material layer.

[0026] The shielding dielectric layer is formed on the inner surface of the gate trench, and the shielding dielectric layer encloses an intermediate trench in the gate trench; the source conductive material layer is filled in the intermediate trench.

[0027] The second field - plate conductive material layer is formed in the first top sub - trenches on both sides of the source conductive material layer, and the gate conductive material layer is formed in the second top sub - trenches on both sides of the source conductive material layer.

[0028] Both the first top sub - trench and the second top sub - trench are formed in the shielding dielectric layer.

[0029] The depth of the first top sub - trench is greater than the depth of the second top sub - trench, and in the transverse direction, the first top sub - trench is located between the source conductive material layer and the second top sub - trench.

[0030] The first side surface of the second top sub - trench is on the corresponding side surface of the gate trench, and there is a gate dielectric layer between the gate conductive material layer and the first side surface of the second top sub - trench.

[0031] The second field - plate conductive material layer completely fills the first top sub - trench.

[0032] The gate trench is formed in a first epitaxial layer of a first conductivity type, a channel region doped with a second conductivity type is formed in the surface region of the first epitaxial layer, and the second top trench passes through the channel region.

[0033] The first epitaxial layer at the bottom of the channel region constitutes a drift region, a source region heavily doped with the first conductivity type is formed on the surface of the channel region; a drain region heavily doped with the first conductivity type is formed on the back surface of the first epitaxial layer.

[0034] When the device is reverse-biased, in the longitudinal direction from the drain region to the bottom surface of the channel region, the voltage of the drift region gradually decreases, and the voltage difference between the source conductive material layer and the drift region gradually decreases. By utilizing the characteristic that the distance between the second field plate conductive material layer and the drift region is smaller than the distance between the source conductive material layer and the drift region, the depletion ability of the drift region near the channel region side is increased.

[0035] A further improvement is that both the source region and the source conductive material layer are connected to the source electrode composed of the front metal layer through corresponding contact holes.

[0036] The gate conductive material layer is connected to the gate electrode composed of the front metal layer through a corresponding contact hole.

[0037] The second field plate conductive material layer is connected to the source electrode through a corresponding contact hole.

[0038] A further improvement is that there is a gap between the first side surface of the first top sub-groove and the second side surface of the second top sub-groove, and there is a gap between the second side surface of the first top sub-groove and the side surface of the source conductive material layer or the second side surface of the first top sub-groove is located on the side surface of the source conductive material layer.

[0039] A further improvement is that both the source region and the source conductive material layer are connected to the source electrode composed of the front metal layer through corresponding contact holes.

[0040] The gate conductive material layer is connected to the gate electrode composed of the front metal layer through a corresponding contact hole.

[0041] The second field plate conductive material layer is connected to the gate electrode through a corresponding contact hole.

[0042] A further improvement is that there is a gap between the first side surface of the first top sub-groove and the second side surface of the second top sub-groove or the second side surface of the second top sub-groove is located on the first side surface of the first top sub-groove.

[0043] There is a gap between the second side surface of the first top sub-groove and the side surface of the source conductive material layer.

[0044] A further improvement is that the shielding dielectric layer is composed of a first shielding dielectric layer and a second shielding dielectric layer stacked together, and the etching rate of the second shielding dielectric layer is greater than that of the first shielding dielectric layer; the first top sub-groove is formed in the second shielding dielectric layer, and the second top sub-groove is formed in the first shielding dielectric layer.

[0045] A further improvement is that the etching rate ratio of the second shielding dielectric layer to the first shielding dielectric layer includes: 1.5:1, 2:1, 3:1.

[0046] A further improvement is that the first shielding dielectric layer is a thermal oxide layer, and the second shielding dielectric layer is formed by CVD deposition.

[0047] A further improvement is that the material of the source conductive material layer includes polysilicon, the material of the second field plate conductive material layer includes polysilicon, and the material of the gate conductive material layer includes polysilicon.

[0048] To solve the above technical problems, a manufacturing method of an SGT MOSFET device provided by the present invention is characterized by including the following steps:

[0049] Step 1, forming a gate trench of a gate structure in a first epitaxial layer of a first conduction type.

[0050] Step 2, forming a shielding dielectric layer on the inner side surface of the gate trench; the shielding dielectric layer encloses an intermediate trench in the gate trench.

[0051] Step 3, filling a source conductive material layer in the intermediate trench.

[0052] Step 4, forming a first top sub-trench and a second top sub-trench in the shielding dielectric layer on both sides of the source conductive material layer.

[0053] The depth of the first top sub-trench is greater than the depth of the second top sub-trench, and in the transverse direction, the first top sub-trench is located between the source conductive material layer and the second top sub-trench.

[0054] The first side surface of the second top sub-trench is on the corresponding side surface of the gate trench.

[0055] Step 5, forming a gate dielectric layer on the first side surface of the second top sub-trench.

[0056] Step 6, forming a second field plate conductive material layer in the first top sub-trench and forming a gate conductive material layer in the second top sub-trench where the gate dielectric layer is formed.

[0057] Step 7, forming a channel region doped with a second conduction type in the surface region of the first epitaxial layer, and the junction depth of the channel region is less than or equal to the depth of the second top trench.

[0058] The first epitaxial layer at the bottom of the channel region forms a drift region.

[0059] Step 8, forming a source region heavily doped with a first conduction type on the surface of the channel region.

[0060] Step Nine: Form a drain region doped heavily with a first conductive type on the back surface of the first epitaxial layer.

[0061] When the device is reverse-biased, in the longitudinal direction from the drain region to the bottom surface of the channel region, the voltage of the drift region gradually decreases, and the voltage difference between the source conductive material layer and the drift region gradually decreases. By virtue of the fact that the distance between the second field plate conductive material layer and the drift region is smaller than the distance between the source conductive material layer and the drift region, the depletion ability of the drift region closer to the channel region side is increased.

[0062] A further improvement is that after Step Eight is completed and before Step Nine, the following front-end process steps are further included:

[0063] Form an interlayer film, contact holes, and a front-end metal layer, pattern the front-end metal layer to form a source electrode and a gate electrode, and both the source region and the source conductive material layer are connected to the source electrode through corresponding contact holes.

[0064] The gate conductive material layer is connected to the gate electrode through a corresponding contact hole.

[0065] The second field plate conductive material layer is connected to the source electrode through a corresponding contact hole.

[0066] A further improvement is that there is a gap between the first side surface of the first top sub-groove and the second side surface of the second top sub-groove, and there is a gap between the second side surface of the first top sub-groove and the side surface of the source conductive material layer or the second side surface of the first top sub-groove is located on the side surface of the source conductive material layer.

[0067] A further improvement is that after Step Eight is completed and before Step Nine, the following front-end process steps are further included:

[0068] Form an interlayer film, contact holes, and a front-end metal layer, and pattern the front-end metal layer to form a source electrode and a gate electrode.

[0069] Both the source region and the source conductive material layer are connected to the source electrode composed of the front-end metal layer through corresponding contact holes.

[0070] The gate conductive material layer is connected to the gate electrode composed of the front-end metal layer through a corresponding contact hole.

[0071] The second field plate conductive material layer is connected to the gate electrode through a corresponding contact hole.

[0072] A further improvement is that there is a gap between the first side surface of the first top sub-groove and the second side surface of the second top sub-groove, and the second side surface of the second top sub-groove is located on the first side surface of the first top sub-groove;

[0073] There is a gap between the second side surface of the first top sub-groove and the side surface of the source conductive material layer.

[0074] A further improvement is that the shielding dielectric layer is formed by stacking a first shielding dielectric layer and a second shielding dielectric layer, and the etching rate of the second shielding dielectric layer is greater than that of the first shielding dielectric layer; the first top sub-groove is formed in the second shielding dielectric layer, and the second top sub-groove is formed in the first shielding dielectric layer.

[0075] A further improvement is that the ratio of the etching rate of the second shielding dielectric layer to that of the first shielding dielectric layer includes: 1.5:1, 2:1, 3:1.

[0076] A further improvement is that step two includes the following sub-steps:

[0077] A thermal oxidation process is used to form a thermal oxide layer on the inner side surface of the gate trench and the first shielding dielectric layer is composed of the thermal oxide layer.

[0078] A CVD deposition process is carried out to form the second shielding dielectric layer on the first shielding dielectric layer.

[0079] A further improvement is that step four includes the following sub-steps:

[0080] A lithography process is used to define the formation regions of the first top sub-groove and the second top sub-groove. The formation region of the first top sub-groove is located in the second shielding dielectric layer, and the formation region of the second top sub-groove is located in the first shielding dielectric layer.

[0081] Etching is carried out to form the first top sub-groove and the second top sub-groove simultaneously. By using the fact that the etching rate of the second shielding dielectric layer is greater than that of the first shielding dielectric layer, the depth of the first top sub-groove is greater than that of the second top sub-groove.

[0082] A further improvement is that the material of the source conductive material layer includes polysilicon, the material of the second field plate conductive material layer includes polysilicon, and the material of the gate conductive material layer includes polysilicon.

[0083] The gate structure of the SGT MOSFET device of the present invention still adopts a left-right structure. Based on the existing first left-right structure, the present invention adds a second field plate conductive material layer filled in the first top sub-groove between the source polysilicon and the polysilicon gate. The depth of the second field plate conductive material layer is greater than that of the polysilicon gate. In this way, the second field plate conductive material layer can laterally deplete the drift region near the channel region when the device is reverse-biased. At the same time, the interval between the second field plate conductive material layer and the drift region is smaller than the interval between the source conductive material layer and the drift region. Therefore, compared with the existing first left-right structure without the second field plate conductive material layer, the present invention can increase the depletion ability of the drift region on the side close to the channel region, so that the electric field intensity distribution in the drift region is more uniform, improving the breakdown voltage of the device and reducing the specific on-resistance of the device.

[0084] At the same time, compared with the existing third left-right structure, the present invention can achieve an increase in the depletion ability of the drift region on the side close to the channel region without setting the thickness of the shielding dielectric layer to a longitudinally graded structure. It can be achieved only by adding a second field plate conductive material layer filled in the first top sub-groove. That is, the second field plate conductive material layer of the present invention can be realized only by using a trench etching and filling process. Compared with the existing third structure, the present invention can reduce the process difficulty of the device.

[0085] At the same time, the shielding dielectric layer of the present invention can adopt a structure formed by stacking a first shielding dielectric layer and a second shielding dielectric layer, where the etching rate of the second shielding dielectric layer is greater than that of the first shielding dielectric layer. For example, the first shielding dielectric layer is formed by thermal oxidation and the second shielding dielectric layer is formed by CVD deposition. The first top sub-groove is formed in the second shielding dielectric layer and the second top sub-groove corresponding to the gate conductive material layer is formed in the first shielding dielectric layer. Utilizing the characteristic that the etching rate of the second shielding dielectric layer is greater than that of the first shielding dielectric layer, the first top sub-groove and the second top sub-groove can be formed simultaneously, and the second field plate conductive material layer and the gate conductive material layer can also be formed simultaneously. Therefore, the introduction of the second field plate conductive material layer of the present invention basically does not increase the process cost.

[0086] In addition, the second shielding dielectric layer of the present invention is formed by CVD deposition, such as an oxide layer or other insulating layer formed by CVD deposition. The CVD deposition process can also easily form bubbles in the second shielding dielectric layer. This can not only increase the etching rate of the second shielding dielectric layer, but also appropriately reduce the dielectric constant of the second shielding dielectric layer. The lower the dielectric constant of the second shielding dielectric layer, according to Gauss's theorem, at the same breakdown voltage, the thickness of the second shielding dielectric layer can be reduced, which can reduce the pitch of the device, reduce the specific on-resistance, and optimize the performance. Description of the Drawings

[0087] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments:

[0088] Figure 1 is a schematic structural diagram of the first existing SGT MOSFET device;

[0089] Figure 2 is a schematic structural diagram of the second existing SGT MOSFET device;

[0090] Figure 3 is a schematic design structural diagram of the third existing SGT MOSFET device;

[0091] Figure 4 is a schematic structural diagram of the SGT MOSFET device according to the first embodiment of the present invention;

[0092] Figures 5A - 5E is a schematic structural diagram of the device in each step of the manufacturing method of the SGT MOSFET device according to the first embodiment of the present invention;

[0093] Figures 6A - 6B is a schematic structural diagram of the device in step four of the manufacturing method of the SGT MOSFET device according to the second embodiment of the present invention. Specific Embodiments

[0094] The SGT MOSFET device according to the first embodiment of the present invention:

[0095] As Figure 4 shown, it is a schematic structural diagram of the SGT MOSFET device according to the first embodiment of the present invention; the gate structure of the SGT MOSFET device according to the first embodiment of the present invention includes: gate trench 301, shielding dielectric layer 103, source conductive material layer 104, second field plate conductive material layer 112, and gate conductive material layer 106.

[0096] The shielding dielectric layer 103 is formed on the inner surface of the gate trench 301, and the shielding dielectric layer 103 encloses an intermediate trench 302 in the gate trench 301; the source conductive material layer 104 is filled in the intermediate trench 302.

[0097] The second field plate conductive material layer 112 is formed in the first top sub-trenches 303 on both sides of the source conductive material layer 104, and the gate conductive material layer 106 is formed in the second top sub-trenches 304 on both sides of the source conductive material layer 104.

[0098] Both the first top sub-trench 303 and the second top sub-trench 304 are formed in the shielding dielectric layer 103.

[0099] The depth of the first top sub-groove 303 is greater than that of the second top sub-groove 304. Horizontally, the first top sub-groove 303 is located between the source conductive material layer 104 and the second top sub-groove 304.

[0100] The first side of the second top sub-groove 304 is on the corresponding side of the gate trench 301. There is a gate dielectric layer 105 between the gate conductive material layer 106 and the first side of the second top sub-groove 304. In the first embodiment of the present invention, the gate dielectric layer 105 is a gate oxide layer.

[0101] The second field plate conductive material layer 112 completely fills the first top sub-groove 303.

[0102] The gate trench 301 is formed in a first epitaxial layer 102 of a first conductivity type. The first epitaxial layer 102 is formed on a semiconductor substrate such as a silicon substrate 101. The semiconductor substrate 101 is a heavily doped structure of the first conductivity type.

[0103] A channel region 107 doped with a second conductivity type is formed in the surface region of the first epitaxial layer 102. The second top trench passes through the channel region 107.

[0104] The first epitaxial layer 102 at the bottom of the channel region 107 forms a drift region. A source region 108 doped heavily with the first conductivity type is formed on the surface of the channel region 107; a drain region doped heavily with the first conductivity type is formed on the back surface of the first epitaxial layer 102. In the first embodiment of the present invention, the drain region is composed of the thinned semiconductor substrate 101 or is formed by performing back surface first conductivity type heavy doping ion implantation on the basis of the thinned semiconductor substrate 101.

[0105] When the device is reverse-biased, in the longitudinal direction from the drain region to the bottom surface of the channel region 107, the voltage of the drift region gradually decreases, and the voltage difference between the source conductive material layer 104 and the drift region gradually decreases. By using the characteristic that the distance between the second field plate conductive material layer 112 and the drift region is less than the distance between the source conductive material layer 104 and the drift region, the depletion ability of the drift region near the channel region 107 is increased.

[0106] Both the source region 108 and the source conductive material layer 104 are connected to a source electrode composed of a front metal layer 110 through corresponding contact holes 109. The contact holes 109 pass through the interlayer film 111.

[0107] The gate conductive material layer 106 is connected to a gate electrode composed of the front metal layer 110 through a corresponding contact hole 109.

[0108] The second field plate conductive material layer 112 is connected to the source electrode through the corresponding contact hole 109.

[0109] In the first embodiment of the present invention, there is a gap between the first side surface of the first top sub-groove 303 and the second side surface of the second top sub-groove 304, and there is a gap between the second side surface of the first top sub-groove 303 and the side surface of the source conductive material layer 104. Since the second field plate conductive material layer 112 is also connected to the source electrode, it can also be that the second side surface of the first top sub-groove 303 is located on the side surface of the source conductive material layer 104, so that the second field plate conductive material layer 112 can be in direct contact with the source conductive material layer 104.

[0110] In the first embodiment of the present invention, the shielding dielectric layer 103 is formed by superimposing a first shielding dielectric layer 103a and a second shielding dielectric layer 103b. Please refer to the first shielding dielectric layer 103a and the second shielding dielectric layer 103b Figure 5B as shown. The etching rate of the second shielding dielectric layer 103b is greater than that of the first shielding dielectric layer 103a; preferably, the ratio of the etching rate of the second shielding dielectric layer 103b to that of the first shielding dielectric layer 103a includes: 1.5:1, 2:1, 3:1. The first top sub-groove 303 is formed in the second shielding dielectric layer 103b, and the second top sub-groove 304 is formed in the first shielding dielectric layer 103a.

[0111] In the first embodiment of the present invention, the first shielding dielectric layer 103a is a thermal oxide layer, and the second shielding dielectric layer 103b is formed by CVD deposition. For example, the second shielding dielectric layer 103b is an oxide layer formed by CVD deposition. The CVD deposition process can introduce bubbles into the second shielding dielectric layer 103b to increase the etching rate of the second shielding dielectric layer 103b and reduce the dielectric constant of the second shielding dielectric layer 103b, further improving the performance of the device.

[0112] In the first embodiment of the present invention, the material of the source conductive material layer 104 is polysilicon, the material of the second field plate conductive material layer 112 is polysilicon, and the material of the gate conductive material layer 106 is polysilicon. In other embodiments, the source conductive material layer 104, the second field plate conductive material layer 112, and the gate conductive material layer 106 can also use other conductive materials.

[0113] In the first embodiment of the present invention, the gate structure of the SGT MOSFET device still adopts a left - right structure. Based on the existing first left - right structure, in the first embodiment of the present invention, a second field - plate conductive material layer 112 filled in the first top sub - trench 303 is added between the source polysilicon and the polysilicon gate. The depth of the second field - plate conductive material layer 112 is greater than that of the polysilicon gate. In this way, the second field - plate conductive material layer 112 can laterally deplete the drift region near the channel region 107 when the device is reverse - biased. At the same time, the distance between the second field - plate conductive material layer 112 and the drift region is less than the distance between the source conductive material layer 104 and the drift region. Therefore, compared with the existing first left - right structure without the second field - plate conductive material layer 112, the first embodiment of the present invention can increase the depletion ability of the drift region on the side close to the channel region 107, so that the electric - field intensity distribution in the drift region is more uniform, and the breakdown voltage of the device can be improved and the specific on - resistance of the device can be reduced.

[0114] At the same time, compared with the existing third left - right structure, in the first embodiment of the present invention, it is not necessary to set the thickness of the shielding dielectric layer 103 as a longitudinally - graded structure to achieve an increase in the depletion ability of the drift region on the side close to the channel region 107. It can be achieved only by adding the second field - plate conductive material layer 112 filled in the first top sub - trench 303. That is, the second field - plate conductive material layer 112 in the first embodiment of the present invention can be realized only by using a trench etching and filling process. Compared with the existing third structure, the first embodiment of the present invention can reduce the process difficulty of the device.

[0115] At the same time, the shielding dielectric layer 103 in the first embodiment of the present invention adopts a structure formed by stacking a first shielding dielectric layer 103a and a second shielding dielectric layer 103b. The etching rate of the second shielding dielectric layer 103b is greater than that of the first shielding dielectric layer 103a. For example, the first shielding dielectric layer 103a is formed by thermal oxidation and the second shielding dielectric layer 103b is formed by CVD deposition. The first top sub - trench 303 is formed in the second shielding dielectric layer 103b and the second top sub - trench 304 corresponding to the gate conductive material layer 106 is formed in the first shielding dielectric layer 103a. Utilizing the characteristic that the etching rate of the second shielding dielectric layer 103b is greater than that of the first shielding dielectric layer 103a, the first top sub - trench 303 and the second top sub - trench 304 can be formed simultaneously, and the second field - plate conductive material layer 112 and the gate conductive material layer 106 can also be formed simultaneously. Therefore, the introduction of the second field - plate conductive material layer 112 in the first embodiment of the present invention basically does not increase the process cost.

[0116] In addition, the second shielding dielectric layer 103b of the first embodiment of the present invention is formed by CVD deposition, such as an oxide layer or other insulating layer formed by CVD deposition. The CVD deposition process can also easily form air bubbles in the second shielding dielectric layer 103b, which can not only increase the etching rate of the second shielding dielectric layer 103b, but also appropriately reduce the dielectric constant of the second shielding dielectric layer 103b. The lower the dielectric constant of the second shielding dielectric layer 103b, according to Gauss's theorem, at the same breakdown voltage, the thickness of the second shielding dielectric layer 103b can be reduced, which can reduce the pitch of the device, reduce the specific on-resistance, and optimize the performance.

[0117] The SGT MOSFET device of the second embodiment of the present invention:

[0118] The difference between the SGT MOSFET device of the second embodiment of the present invention and the SGT MOSFET of the first embodiment of the present invention is that the SGT MOSFET device of the first embodiment of the present invention has the following characteristics:

[0119] The second field plate conductive material layer 112 is connected to the gate through the corresponding contact hole 109.

[0120] Compared with connecting the second field plate conductive material layer 112 to the source in the first embodiment of the present invention, the structure of connecting the second field plate conductive material layer 112 to the gate in the second embodiment of the present invention can achieve better effects, which are described as follows:

[0121] When the device is reverse-biased, the voltage of the gate and the voltage of the source are basically the same. At this time, the depletion effect of the second field plate conductive material layer 112 on the drift region in the second embodiment of the present invention is basically the same as that in the first embodiment of the present invention.

[0122] Moreover, when the device is forward-conducting, the second field plate conductive material layer 112 in the second embodiment of the present invention will generate a carrier accumulation effect on the drift region covered on the side, which can reduce the on-resistance of the device.

[0123] However, connecting the second field plate conductive material layer 112 in the second embodiment of the present invention to the gate will increase the gate capacitance of the device and increase the loss in the switching process. Therefore, it is more applicable in occasions where the requirement for switching speed is not high.

[0124] As a further improvement of the first and second embodiments of the present invention, the second field plate conductive material layer 112 can be connected to other voltages different from the voltage of the source and the voltage of the gate as needed.

[0125] In the second embodiment of the present invention, since the second field plate conductive material layer 112 is connected to the gate, the second field plate conductive material layer 112 can be isolated from the gate conductive material layer 106. At this time, the structural diagram is also the same as Figure 4 In this case, there is a gap between the first side surface of the first top sub-groove 303 and the second side surface of the second top sub-groove 304. It can also be that the second field plate conductive material layer 112 is in contact with the gate conductive material layer 106. At this time, the second side surface of the second top sub-groove 304 is located on the first side surface of the first top sub-groove 303.

[0126] There is a gap between the second side surface of the first top sub-groove 303 and the side surface of the source conductive material layer 104.

[0127] Manufacturing method of the SGT MOSFET device according to the first embodiment of the present invention:

[0128] As Figure 5A to Figure 5E shown, it is a schematic diagram of the device structure in each step of the manufacturing method of the SGT MOSFET device according to the first embodiment of the present invention; the manufacturing method of the SGT MOSFET device according to the first embodiment of the present invention includes the following steps:

[0129] Step 1: As Figure 5A shown, a gate trench 301 of a gate structure is formed in a first epitaxial layer 102 of a first conductivity type.

[0130] In the method of the first embodiment of the present invention, the first epitaxial layer 102 is formed on a semiconductor substrate such as a silicon substrate 101, and the semiconductor substrate 101 is a heavily doped structure of the first conductivity type.

[0131] Step 2: As Figure 5B shown, a shielding dielectric layer 103 is formed on the inner side surface of the gate trench 301; the shielding dielectric layer 103 encloses an intermediate trench 302 in the gate trench 301.

[0132] The shielding dielectric layer 103 is formed by superimposing a first shielding dielectric layer 103a and a second shielding dielectric layer 103b, and the etching rate of the second shielding dielectric layer 103b is greater than that of the first shielding dielectric layer 103a. For example, the ratio of the etching rate of the second shielding dielectric layer 103b to the etching rate of the first shielding dielectric layer 103a includes: 1.5:1, 2:1, 3:1. The subsequent first top sub-groove 303 will be formed in the second shielding dielectric layer 103b, and the second top sub-groove 304 will be formed in the first shielding dielectric layer 103a.

[0133] Preferably, step 2 includes the following sub-steps:

[0134] A thermal oxidation process is used to form a thermal oxide layer on the inner side of the gate trench 301, and the first shielding dielectric layer 103a is composed of the thermal oxide layer.

[0135] A CVD deposition process is performed to form the second shielding dielectric layer 103b on the first shielding dielectric layer 103a. The material of the second shielding dielectric layer 103b includes an oxide layer, and air bubbles can be incorporated into the second shielding dielectric layer 103b to adjust the etching rate and dielectric constant of the second shielding dielectric layer 103b.

[0136] As Figure 5B shown, the first shielding dielectric layer 103a and the second shielding dielectric layer 103b also extend to the surface of the first epitaxial layer 102 outside the gate trench 301.

[0137] Step three: As Figure 5C shown, a source conductive material layer 104 is filled in the intermediate trench 302.

[0138] In the method of the first embodiment of the present invention, the source conductive material layer 104 is made of polysilicon and is formed by polysilicon deposition and back-etching.

[0139] After that, as Figure 5D shown, a back-etching or chemical mechanical polishing (CMP) process is performed to remove the first shielding dielectric layer 103a and the second shielding dielectric layer 103b outside the gate trench 301.

[0140] Step four: First top sub-trenches 303 and second top sub-trenches 304 are formed in the shielding dielectric layers 103 on both sides of the source conductive material layer 104.

[0141] The depth of the first top sub-trench 303 is greater than the depth of the second top sub-trench 304, and in the transverse direction, the first top sub-trench 303 is located between the source conductive material layer 104 and the second top sub-trench 304.

[0142] The first side surface of the second top sub-trench 304 is on the corresponding side surface of the gate trench 301.

[0143] As Figure 5E shown, a photoresist pattern 401 is formed by a photolithography process to define the formation regions of the first top sub-trenches 303 and the second top sub-trenches 304. The formation region of the first top sub-trenches 303 is located in the second shielding dielectric layer 103b, and the formation region of the second top sub-trenches 304 is located in the first shielding dielectric layer 103a.

[0144] As Figure 4As shown, while etching, the first top sub-groove 303 and the second top sub-groove 304 are formed simultaneously. By using the etching rate of the second shielding dielectric layer 103b being greater than that of the first shielding dielectric layer 103a, the depth of the first top sub-groove 303 is greater than the depth of the second top sub-groove 304.

[0145] For subsequent steps, please refer to Figure 4 as shown.

[0146] Step Five: Form a gate dielectric layer 105 on the first side surface of the second top sub-groove 304.

[0147] Step Six: Form a second field plate conductive material layer 112 in the first top sub-groove 303 and form a gate conductive material layer 106 in the second top sub-groove 304 where the gate dielectric layer 105 is formed.

[0148] In the method of the first embodiment of the present invention, the material of the second field plate conductive material layer 112 is polysilicon, and the material of the gate conductive material layer 106 is polysilicon. In Step Six, the second field plate conductive material layer 112 and the gate conductive material layer 106 are formed simultaneously by using a polysilicon filling and etch-back process.

[0149] Step Seven: Form a channel region 107 doped with a second conductive type in the surface region of the first epitaxial layer 102, and the junction depth of the channel region 107 is less than or equal to the depth of the second top groove.

[0150] The first epitaxial layer 102 at the bottom of the channel region 107 forms a drift region.

[0151] Step Eight: Form a source region 108 heavily doped with a first conductive type on the surface of the channel region 107.

[0152] Form an interlayer film 111, contact holes 109, and a front metal layer 110. Pattern the front metal layer 110 to form a source electrode and a gate electrode. Both the source region 108 and the source conductive material layer 104 are connected to the source electrode through the corresponding contact holes 109.

[0153] The gate conductive material layer 106 is connected to the gate electrode through the corresponding contact holes 109.

[0154] The second field plate conductive material layer 112 is connected to the source electrode through the corresponding contact hole 109, and at this time, the SGT MOSFET device of the first embodiment of the present invention described above is formed. It can also be: the second field plate conductive material layer 112 is connected to the gate electrode through the corresponding contact hole 109, and at this time, the SGT MOSFET device of the second embodiment of the present invention described above is formed. When the second field plate conductive material layer 112 is connected to other potentials through the corresponding contact hole 109, devices of other embodiments can be obtained.

[0155] In the device structure formed by the method of the first embodiment of the present invention, there is a gap between the first side surface of the first top sub-groove 303 and the second side surface of the second top sub-groove 304, and there is a gap between the second side surface of the first top sub-groove 303 and the side surface of the source conductive material layer 104. In the methods of other embodiments, the following structure can also be formed: the second side surface of the first top sub-groove 303 is located on the side surface of the source conductive material layer 104. At this time, only the SGT MOSFET device structure of the first embodiment of the present invention can be formed, that is, the second field plate conductive material layer 112 will be connected to the source electrode.

[0156] Step Nine: Form a drain region doped with a first conductive type with high doping on the back surface of the first epitaxial layer 102. The drain region is directly composed of the thinned semiconductor substrate 101 or is formed by the thinned semiconductor substrate 101 plus ion implantation of the first conductive type with high doping on the back surface.

[0157] After that, a drain electrode composed of a back metal layer is formed on the back surface of the drain region.

[0158] When the device is reverse-biased, in the longitudinal direction from the drain region to the bottom surface of the channel region 107, the voltage of the drift region gradually decreases, and the voltage difference between the source conductive material layer 104 and the drift region gradually decreases. By using the characteristic that the gap between the second field plate conductive material layer 112 and the drift region is smaller than the gap between the source conductive material layer 104 and the drift region, the depletion ability of the drift region near the side of the channel region 107 is increased.

[0159] Manufacturing method of the SGT MOSFET device of the second embodiment of the present invention:

[0160] Steps One to Three of the method of the second embodiment of the present invention are the same as those of the method of the first embodiment of the present invention. For the corresponding drawings of Steps One to Three of the method of the second embodiment of the present invention, please also refer to Figures 5A to 5D shown.

[0161] The difference between the manufacturing method of the SGT MOSFET device of the second embodiment of the present invention and the manufacturing method of the SGT MOSFET of the first embodiment of the present invention is only in Step Four, asFigures 6A to 6B This is a schematic diagram of the device structure in Step 4 of the manufacturing method of the SGT MOSFET device according to the second embodiment of the present invention. Step 4 in the manufacturing method of the SGT MOSFET device according to the first embodiment of the present invention has the following characteristics:

[0162] Step 4: As Figure 6A shown, a photoresist pattern 402 is formed by a photolithography process to define the formation regions of the first top sub-groove 303 and the second top sub-groove 304. The formation region of the first top sub-groove 303 is located in the second shielding dielectric layer 103b, and the formation region of the second top sub-groove 304 is located in the first shielding dielectric layer 103a. Figure 6A In

[0163] As Figure 6B shown, etching is performed to simultaneously form the first top sub-groove 303 and the second top sub-groove 304. By using the etching rate of the second shielding dielectric layer 103b being greater than that of the first shielding dielectric layer 103a, the depth of the first top sub-groove 303 is greater than the depth of the second top sub-groove 304.

[0164] From Figure 6B shown, the second side surface of the second top sub-groove 304 is located on the first side surface of the first top sub-groove 303, that is, the second top sub-groove 304 and the first top sub-groove 303 are connected together.

[0165] After the second field plate conductive material layer 112 and the gate conductive material layer 106 are formed in subsequent Step 6, the second field plate conductive material layer 112 and the gate conductive material layer 106 are in direct side contact. Therefore, the manufacturing method of the second embodiment of the present invention can only form the device of the second embodiment of the present invention described above, that is, the structure in which the second field plate conductive material layer 112 is connected to the gate.

[0166] Compared with the method of the first embodiment of the present invention, the opening of the photoresist pattern 402 of the first top sub-groove 303 and the second top sub-groove 304 in the method of the second embodiment of the present invention is larger, so the photolithography process is simpler, and the etching process after photolithography is also simpler.

[0167] An improved method of the method according to the second embodiment of the present invention is that the photolithography process corresponding to the photoresist pattern 402 can be omitted, and the first top sub-groove 303 and the second top sub-groove 304 can be etched directly under the self-alignment condition of the source conductive material layer 104 and the first epitaxial layer 102, so that one photomask can be saved and the cost can be further reduced. However, the disadvantage of this method is that the distance between the second field plate conductive material layer 112 and the source conductive material layer 104 will be reduced, and finally the gate capacitance will be increased.

[0168] Another improved method of the method according to the second embodiment of the present invention is that Figure 5D the steps of removing the first shielding dielectric layer 103a and the second shielding dielectric layer 103b outside the gate trench 301 by corresponding etch-back or chemical mechanical polishing (CMP) process can be omitted, and step four can be directly carried out Figure 5C on this basis, so that one process step can be saved and the cost can be saved.

[0169] The present invention has been described in detail through specific embodiments, but these do not constitute a limitation to the present invention. Without departing from the principle of the present invention, those skilled in the art can also make many deformations and improvements, which should also be regarded as the protection scope of the present invention.

Claims

1. A SGT MOSFET device, characterized in that, The gate structure includes: a gate trench, a shielding dielectric layer, a source conductive material layer, a second field plate conductive material layer, and a gate conductive material layer; The shielding dielectric layer is formed on the inner surface of the gate trench, and the shielding dielectric layer encloses an intermediate trench in the gate trench; the source conductive material layer is filled in the intermediate trench; The second field plate conductive material layer is formed in the first top sub-trenches on both sides of the source conductive material layer, and the gate conductive material layer is formed in the second top sub-trenches on both sides of the source conductive material layer; Both the first top sub-trenches and the second top sub-trenches are formed in the shielding dielectric layer; The depth of the first top sub-trenches is greater than the depth of the second top sub-trenches, and in the transverse direction, the first top sub-trenches are located between the source conductive material layer and the second top sub-trenches; The first side surface of the second top sub-trenches is on the corresponding side surface of the gate trench, and there is a gate dielectric layer between the gate conductive material layer and the first side surface of the second top sub-trenches; The second field plate conductive material layer completely fills the first top sub-trenches; The gate trench is formed in a first epitaxial layer of a first conductivity type, and a channel region doped with a second conductivity type is formed in the surface region of the first epitaxial layer, and the second top sub-trenches pass through the channel region; The first epitaxial layer at the bottom of the channel region forms a drift region, and a source region heavily doped with the first conductivity type is formed on the surface of the channel region; a drain region heavily doped with the first conductivity type is formed on the back surface of the first epitaxial layer; When the device is reverse-biased, in the longitudinal direction from the drain region to the bottom surface of the channel region, the voltage of the drift region gradually decreases, and the voltage difference between the source conductive material layer and the drift region gradually decreases. By using the characteristic that the distance between the second field plate conductive material layer and the drift region is less than the distance between the source conductive material layer and the drift region, the depletion ability of the drift region near the channel region side is increased.

2. The SGT MOSFET device according to claim 1, characterized in that: Both the source region and the source conductive material layer are connected to the source electrode composed of a front metal layer through corresponding contact holes; The gate conductive material layer is connected to the gate electrode composed of the front metal layer through a corresponding contact hole; The second field plate conductive material layer is connected to the source electrode through a corresponding contact hole.

3. The SGT MOSFET device according to claim 2, characterized in that: There is a gap between the first side surface of the first top sub-trenches and the second side surface of the second top sub-trenches, and there is a gap between the second side surface of the first top sub-trenches and the side surface of the source conductive material layer or the second side surface of the first top sub-trenches is located on the side surface of the source conductive material layer.

4. The SGT MOSFET device according to claim 1, characterized in that: Both the source region and the source conductive material layer are connected to the source electrode composed of a front metal layer through corresponding contact holes; The gate conductive material layer is connected to the gate electrode composed of the front metal layer through a corresponding contact hole; The second field plate conductive material layer is connected to the gate electrode through a corresponding contact hole.

5. The SGT MOSFET device according to claim 4, characterized in that: There is a gap between the first side surface of the first top sub-trenches and the second side surface of the second top sub-trenches or the second side surface of the second top sub-trenches is located on the first side surface of the first top sub-trenches; There is a gap between the second side surface of the first top sub-groove and the side surface of the source conductive material layer.

6. The SGT MOSFET device according to claim 1, characterized in that: The shielding dielectric layer is formed by stacking a first shielding dielectric layer and a second shielding dielectric layer, and the etching rate of the second shielding dielectric layer is greater than that of the first shielding dielectric layer; the first top sub-groove is formed in the second shielding dielectric layer, and the second top sub-groove is formed in the first shielding dielectric layer.

7. The SGT MOSFET device according to claim 6, characterized in that: The etching rate ratio of the second shielding dielectric layer to the first shielding dielectric layer includes: 1.5:1, 2:1, 3:

1.

8. The SGT MOSFET device according to claim 6, characterized in that: The first shielding dielectric layer is a thermal oxidation layer, and the second shielding dielectric layer is formed by CVD deposition.

9. The SGT MOSFET device according to claim 1, characterized in that: The material of the source conductive material layer includes polysilicon, the material of the second field plate conductive material layer includes polysilicon, and the material of the gate conductive material layer includes polysilicon.

10. A manufacturing method of a SGT MOSFET device, characterized in that, It includes the following steps: Step 1, forming a gate trench of a gate structure in a first epitaxial layer of a first conductivity type; Step 2, forming a shielding dielectric layer on the inner side surface of the gate trench; The shielding dielectric layer encloses an intermediate trench in the gate trench; Step 3, filling a source conductive material layer in the intermediate trench; Step 4, forming a first top sub-groove and a second top sub-groove in the shielding dielectric layer on both sides of the source conductive material layer; The depth of the first top sub-groove is greater than the depth of the second top sub-groove, and in the transverse direction, the first top sub-groove is located between the source conductive material layer and the second top sub-groove; The first side surface of the second top sub-groove is on the corresponding side surface of the gate trench; Step 5, forming a gate dielectric layer on the first side surface of the second top sub-groove; Step 6, forming a second field plate conductive material layer in the first top sub-groove and forming a gate conductive material layer in the second top sub-groove where the gate dielectric layer is formed; Step 7, forming a channel region doped with a second conductivity type in the surface region of the first epitaxial layer, and the junction depth of the channel region is less than or equal to the depth of the second top sub-groove; The first epitaxial layer at the bottom of the channel region forms a drift region; Step 8, forming a source region heavily doped with a first conductivity type on the surface of the channel region; Step 9, forming a drain region heavily doped with a first conductivity type on the back surface of the first epitaxial layer; When the device is reverse-biased, in the longitudinal direction from the drain region to the bottom surface of the channel region, the voltage of the drift region gradually decreases, and the voltage difference between the source conductive material layer and the drift region gradually decreases. By using the characteristic that the gap between the second field plate conductive material layer and the drift region is smaller than the gap between the source conductive material layer and the drift region, the depletion ability of the drift region near the channel region side is increased.

11. The manufacturing method of the SGT MOSFET device according to claim 10, characterized in that: After step 8 is completed and before step 9, the following front process steps are further included: Forming an interlayer film, contact holes and a front metal layer, patterning the front metal layer to form a source electrode and a gate electrode, and both the source region and the source conductive material layer are connected to the source electrode through corresponding contact holes; The gate conductive material layer is connected to the gate electrode through a corresponding contact hole; The second field plate conductive material layer is connected to the source electrode through a corresponding contact hole.

12. The manufacturing method of the SGT MOSFET device according to claim 10, characterized in that: There is a gap between the first side surface of the first top sub-groove and the second side surface of the second top sub-groove, and there is a gap between the second side surface of the first top sub-groove and the side surface of the source conductive material layer or the second side surface of the first top sub-groove is located on the side surface of the source conductive material layer.

13. The manufacturing method of the SGT MOSFET device according to claim 10, characterized in that After step eight and before step nine, the following front-end process steps are further included: Form an interlayer film, contact holes and a front-end metal layer, and pattern the front-end metal layer to form a source electrode and a gate electrode; Both the source region and the source conductive material layer are connected to the source electrode composed of the front-end metal layer through corresponding contact holes; The gate conductive material layer is connected to the gate electrode composed of the front-end metal layer through a corresponding contact hole; The second field plate conductive material layer is connected to the gate electrode through a corresponding contact hole.

14. The manufacturing method of the SGT MOSFET device according to claim 13, characterized in that: There is a gap between the first side surface of the first top sub-groove and the second side surface of the second top sub-groove, and the second side surface of the second top sub-groove is located on the first side surface of the first top sub-groove; There is a gap between the second side surface of the first top sub-groove and the side surface of the source conductive material layer.

15. The manufacturing method of the SGT MOSFET device according to claim 10, characterized in that: The shielding dielectric layer is formed by stacking a first shielding dielectric layer and a second shielding dielectric layer, and the etching rate of the second shielding dielectric layer is greater than that of the first shielding dielectric layer; the first top sub-groove is formed in the second shielding dielectric layer, and the second top sub-groove is formed in the first shielding dielectric layer.

16. The manufacturing method of the SGT MOSFET device according to claim 15, characterized in that: Step two includes the following sub-steps: Adopt a thermal oxidation process to form a thermal oxide layer on the inner side surface of the gate trench and form the first shielding dielectric layer by the thermal oxide layer; Perform a CVD deposition process to form the second shielding dielectric layer on the first shielding dielectric layer.

17. The manufacturing method of the SGT MOSFET device according to claim 16, characterized in that: Step four includes the following sub-steps: Adopt a photolithography process to define the formation regions of the first top sub-groove and the second top sub-groove. The formation region of the first top sub-groove is located in the second shielding dielectric layer, and the formation region of the second top sub-groove is located in the first shielding dielectric layer; Perform etching to simultaneously form the first top sub-groove and the second top sub-groove, and make the depth of the first top sub-groove greater than the depth of the second top sub-groove by using the etching rate of the second shielding dielectric layer being greater than that of the first shielding dielectric layer.

18. The manufacturing method of the SGT MOSFET device according to claim 10, characterized in that: The material of the source conductive material layer includes polysilicon, the material of the second field plate conductive material layer includes polysilicon, and the material of the gate conductive material layer includes polysilicon.

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